Capacitance detection circuit and method supporting self-capacitance and mutual-capacitance detection

Abstract

The invention discloses a capacitance detection circuit supporting self-capacitance and mutual-capacitance detection. The capacitance detection circuit comprises a first analog bus, a second analog bus and a plurality of multiplexer switch modules, wherein the first analog bus is electrically connected with the integrating capacitor and the input end of the delta-sigma modulator, the delta-sigma modulator supplements charges to the integrating capacitor through control and maintains the average voltage value of the first analog bus, the second analog bus is used for providing reference voltage, and the multiplexer switch modules are connected with channels to be detected in a one-to-one correspondence mode. Each multiplexer switch module comprises a first switch, a second switch and a third switch, first ends of the first switch, the second switch and the third switch are connected with one end of the channel to be detected, a second end of the first switch is grounded or a power supply, a second end of the second switch is connected to the first analog bus, and a second end of the third switch is connected to the second analog bus. The circuit supports self-capacitance detection and mutual capacitance detection at the same time on the premise that no extra switch is added, and is simple in structure and convenient to control.

Description

Technical Field

[0001] This invention relates to the field of capacitance detection technology, and in particular to a capacitance detection circuit and method that supports self-capacitance and mutual capacitance detection. Background Technology

[0002] Capacitance testing is a technique that measures capacitance and capacitance changes using dedicated circuits or equipment. It includes two main categories: self-capacitance testing and mutual capacitance testing. Self-capacitance testing is primarily used to measure changes in the capacitance of a conductor itself, while mutual capacitance testing is used to measure changes in coupling between conductors. Existing capacitance testing methods are mostly based on the principle of voltage comparison, for example, using a proportional capacitance-to-digital converter circuit.

[0003] Commonly used self-capacitance detection circuits include Figure 1 As shown, where C self For the self-capacitance to be detected, C INTA The capacitor is an integrating capacitor. SW1 and SW2 are channel capacitance switching switches. AMUXBUS is an analog bus shared by all self-capacitance detection channels. The ΔΣ modulator functions as a voltage comparator, charge compensation, and output code stream. Its principle is as follows: SW1 and SW2 are alternately turned on under the drive of the switches, causing C... self Periodically put C INTA The charge on the plate is released to ground. The ΔΣ modulator modulates the voltage on the AMUXBUS and the reference voltage V. ref Compare them, and based on the comparison results, submit to C. INTA Adding or removing charge to make the average voltage on the AMUXBUS approximate V. ref When C self When the capacitance value changes, the feedback from the ΔΣ loop compensates for the change in C. INTA The charge also changes, which eventually causes a change in the ratio of "0" and "1" in the output bitstream, thereby realizing the conversion of capacitance value to digital bitstream.

[0004] Active shielding technology is crucial for achieving waterproofing because it significantly reduces the impact of parasitic capacitance between different channels and between channels and the shielding electrodes on the detection results. Therefore, this feature is generally included in current self-capacitance detection circuits. When active shielding technology is introduced to suppress the influence of parasitic mutual capacitance, such as... Figure 1 The self-capacitance detection circuit shown needs to perform the following: Figure 2 The configuration shown is as follows. Pin 1 is the channel under test, pin 2 is the shielding electrode, and C... mp For parasitic mutual capacitance, C self1 C is the self-capacitance of the channel to be tested, input from pin 1. self2 To actively shield the self-capacitance of the channel, C INTAThe capacitor is an integrating capacitor; SW1 and SW2 are capacitor switching switches for the channel under test; AMUXBUS is an analog bus shared by all self-capacitance detection channels; the ΔΣ modulator functions as a voltage comparator, charge compensation, and output code stream; and the active shielding signal is a square wave signal that periodically switches between the power supply voltage and ground voltage. Furthermore, to achieve self-capacitance detection with active shielding, a similar [missing information - likely a specific type of capacitor] is typically used in each detection channel. Figure 3 The multiplexer shown in the dashed box. When the detection channel is configured in detection mode, switches SW1 and SW2 achieve self-capacitance detection through periodic switching, while switch SW3 is always open; when the detection channel is configured in active shielding mode, switches SW1 and SW2 are always off, while switch SW3 is always on, allowing the active shielding signal to be output from the detection channel.

[0005] Commonly used mutual capacitance detection circuits include Figure 4 As shown, where C mutual For the mutual capacitance to be detected, C self1 and C self2 C is the parasitic self-capacitance of the channel itself. INTA and C INTB SW1 and SW2 are integrating capacitors, SW1 and SW2 are integrating capacitor switching switches, AMUXBUS is an analog bus shared by all mutual capacitance detection channels, the ΔΣ modulator functions as voltage comparison, charge compensation, and output code stream, and the TX excitation signal is a square wave signal that periodically switches between the power supply voltage and ground voltage. Its principle is as follows: Before the input TX signal, C... INTA and C INTB The voltage will be reset to the reference voltage V. ref During the period when the TX excitation signal flips to a high level, SW1 is closed and SW2 is open, allowing the signal to pass through the mutual capacitance C. mutual To C INTA Charge is introduced into the AMUXBUS, causing the AMUXBUS voltage to rise. The ΔΣ modulator detects this rise in AMUXBUS voltage through a voltage comparison and then sends feedback from C... INTA The charge is drawn from the upper part, causing the AMUXBUS voltage to gradually decrease to V at a constant rate of change. ref Then it remains unchanged. Conversely, during the period when the TX excitation signal flips to a low level, SW2 is closed and SW1 is open, which will pass through the mutual capacitance C. mutual From C INTB Charge is drawn from the AMUXBUS, causing the AMUXBUS voltage to decrease. The ΔΣ modulator detects this decrease in AMUXBUS voltage through a voltage comparison and then sends feedback to C. INTB A charge is applied to the AMUXBUS, causing the voltage to gradually rise to Vref at a constant rate of change, and then remain constant. When C... mutual When the capacitance value changes, the TX signal changes, affecting C. INTA and CINTB The charging and discharging amplitude will also change, and then the ΔΣ modulator will perform constant-rate charge compensation, meaning the time required for charging or discharging will also change. This change in charge compensation time will directly alter the ratio of "0" and "1" in the output bitstream of the ΔΣ modulator. By then statistically analyzing the proportion of "1" in the bitstream, the conversion from capacitance value to digital result can be achieved.

[0006] As can be seen, in the existing technical solutions, self-capacitance detection only requires one fixed-connection integrating capacitor, and the corresponding switch of the detection channel needs to be periodically switched. Mutual capacitance detection, on the other hand, requires two periodically connected integrating capacitors. The TX channel needs to output a periodically switched square wave signal, while the RX channel does not need to be switched. Therefore, to add mutual capacitance detection functionality to the self-capacitance detection circuit, two additional periodically connected integrating capacitors are required. Since integrating capacitors are typically implemented using off-chip discrete components, the two integrating capacitors required for mutual capacitance detection increase capacitor complexity and cost. Furthermore, the charge compensation logic of the ΔΣ modulator for the integrating capacitors differs between self-capacitance and mutual capacitance detection modes, requiring an additional charge compensation circuit, which also increases control complexity. Summary of the Invention

[0007] To simplify the circuit structure, control, and logic while ensuring compatibility with both self-capacitance and mutual capacitance detection, the first aspect of this invention provides a capacitance detection circuit supporting both self-capacitance and mutual capacitance detection, comprising: The first analog bus is electrically connected to the input of an integrating capacitor and a ΔΣ modulator. The ΔΣ modulator replenishes the charging of the integrating capacitor by control to maintain the average voltage of the first analog bus. A second analog bus is used to provide a reference voltage; and Multiple multiplexer switch modules are provided, each connected to a channel to be tested. Each multiplexer switch module includes a first switch, a second switch, and a third switch. The first terminal of the first switch is connected to a pin of the channel to be tested, and the second terminal is grounded or powered. The first terminal of the second switch is connected to a pin of the channel to be tested, and the second terminal is connected to the first analog bus. The first terminal of the third switch is connected to a pin of the channel to be tested, and the second terminal is connected to the second analog bus.

[0008] Furthermore, the capacitance detection circuit also includes a mode control module, which is used to configure the operating mode of the multiplexer switch to achieve different capacitance detection functions.

[0009] Furthermore, the operating mode includes: Self-capacitance detection mode, which is used for self-capacitance detection of the corresponding channel to be tested in the multi-channel selection switch module; Mutual capacitance RX mode and mutual capacitance TX mode are used to detect the mutual capacitance between the channels to be tested corresponding to two multiplexer modules; and The active shielding mode is used to reduce the impact of parasitic coupling capacitance between the shielding electrode and the channel under test on the self-capacitance detection results.

[0010] Furthermore, the capacitance detection circuit also includes a clock module, which provides a switching clock signal. Based on the switching clock signal, the multiplexer module controls the closing and opening of each switch according to the configured operating mode.

[0011] Furthermore, the capacitance detection circuit also includes a voltage buffer, whose input is connected to a reference voltage and whose output is connected to the second analog bus to drive the second analog bus.

[0012] Furthermore, the integrating capacitor is an off-chip discrete device.

[0013] Furthermore, the integrating capacitor is integrated on-chip.

[0014] Based on the capacitance detection circuit described above, a second aspect of the present invention provides a capacitance detection method, comprising: Configure the operating mode of the multi-channel selection switch module according to the required detection functions; and Based on the switching clock signal, the closing and opening of each switch are controlled according to the operating mode.

[0015] Furthermore, depending on the required detection functions, the operating modes of the multiplexer module can be configured as follows: If self-capacitance testing is required, configure the multiplexer module corresponding to the pin of the channel to be tested to self-capacitance testing mode. If self-capacitance testing with active shielding is required, configure the multiplexer module corresponding to the pin of the channel to be tested for self-capacitance testing, and simultaneously configure the multiplexer corresponding to the actively shielded channel for active shielding mode; and If mutual capacitance detection is required, the multiplexer modules corresponding to the two pins that generate mutual capacitance should be configured as mutual capacitance RX mode and mutual capacitance TX mode, respectively.

[0016] Furthermore, based on the switching clock signal, controlling the closing and opening of each switch according to the operating mode includes: In self-capacitance detection mode, when the switching clock signal is low, only the first switch is closed, so that the pin of the channel to be detected is connected to ground; when the switching clock signal is high, only the second switch is closed, so that the pin of the channel to be detected is connected to the first analog bus. In the mutual capacitance RX mode, when the switching clock signal is low, only the third switch is closed, so that the pin of the channel to be tested is connected to the second analog bus; when the switching clock signal is high, only the second switch is closed, so that the pin of the channel to be tested is connected to the first analog bus. In mutual capacitance TX mode, when the switching clock signal is low, only the third switch is closed, connecting the pin of the channel under test to the second analog bus; when the switching clock signal is high, only the first switch is closed, connecting the pin of the channel under test to ground. In active shielding mode, when the switching clock signal is low, closing only the first switch will connect the corresponding electrode to ground; when the switching clock signal is high, closing only the third switch will connect the shielding electrode to the second analog bus.

[0017] This invention provides a capacitance detection circuit and method supporting self-capacitance and mutual capacitance detection. It simultaneously achieves self-capacitance and mutual capacitance detection without adding additional switches and supports active shielding. Using this capacitance detection circuit, both self-capacitance and mutual capacitance detection require only a single fixed-connection integrating capacitor, reducing circuit complexity and control difficulty. Furthermore, the charge compensation logic for the integrating capacitor in the ΔΣ modulator is completely consistent, further simplifying the design of the charge compensation circuit, reducing control logic complexity, and thus effectively reducing module area. Attached Figure Description

[0018] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0019] Figure 1 This diagram illustrates the structure of a self-capacitance detection circuit in the prior art. Figure 2 A schematic diagram of a self-capacitance detection circuit with active shielding function in the prior art is shown. Figure 3 This diagram illustrates the structure of a multiplexer switch in the prior art. Figure 4 This diagram shows a schematic of the structure of a mutual capacitance detection circuit in the prior art; Figure 5 This diagram illustrates a capacitance detection circuit supporting self-capacitance and mutual capacitance detection according to an embodiment of the present invention. Figure 6 This diagram illustrates a structural schematic of a capacitance detection circuit supporting self-capacitance and mutual capacitance detection according to another embodiment of the present invention; and Figure 7 The diagram shows a flowchart of a capacitance detection method according to an embodiment of the present invention. Detailed Implementation

[0020] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or in conjunction with other alternatives and / or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0021] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0022] Existing self-capacitance and mutual capacitance detection circuits differ in structure and control logic. Adding mutual capacitance detection directly to a self-capacitance detection circuit requires both an additional integrating capacitor and an additional charge compensation circuit. To address these issues, this invention proposes a proportional capacitor-to-digital converter circuit based on voltage comparison principles. In both self-capacitance and mutual capacitance detection modes, the charge compensation logic for the integrating capacitor by the ΔΣ modulator remains identical, simplifying the design of the charge compensation circuit and reducing the complexity of the control logic. Furthermore, both self-capacitance and mutual capacitance detection require only a single, fixedly connected integrating capacitor.

[0023] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments. Figure 5 This diagram illustrates a capacitance detection circuit supporting self-capacitance and mutual capacitance detection according to an embodiment of the present invention. Figure 5 As shown, a capacitance detection circuit supporting self-capacitance and mutual capacitance detection includes two analog buses and several multiplexer modules 503, wherein the first analog bus 501 is connected to the integrating capacitor C. INTA 504 also serves as the input signal for the ΔΣ modulator 505. The second analog bus 502 is used to provide the reference voltage V. refThe capacitor to be tested is connected to the detection channel, and the capacitance detection circuit is connected to the detection channel via pin 001, thereby enabling the capacitance detection circuit to detect it. As shown in the figure, pin 001 is connected one-to-one with the multiplexer module 503, and is connected to the first analog bus 501 and the second analog bus 502 via the multiplexer module 503.

[0024] In one embodiment of the present invention, the capacitance detection circuit further includes a mode control module and a clock module (not shown in the figure), wherein the mode control module is used to output a mode control signal, and the clock module is used to output a switching clock signal. Figure 5 As shown, the mode control signal and the switching clock signal are used as input signals for each multiplexer module 503 to control the multiplexer module 503. The mode control signal input for each multiplexer module 503 is independently controlled, while the switching clock signal is a shared input.

[0025] like Figure 5 As shown, in one embodiment of the present invention, each multiplexer module 503 includes a first switch SW1, a second switch SW2, and a third switch SW3. The first terminal of the first switch is connected to a pin of the channel to be detected, and the second terminal is grounded. The first terminal of the second switch is connected to a pin of the channel to be detected, and the second terminal is connected to the first analog bus. The first terminal of the third switch is connected to a pin of the channel to be detected, and the second terminal is connected to the second analog bus. By controlling the on / off state of each switch, different capacitance detection functions can be achieved, as shown in Table 1.

[0026] Table 1 As shown in Table 1, if self-capacitance testing is required, the multiplexer corresponding to the pin of the channel to be tested should be configured to self-capacitance testing mode. The self-capacitance on the pin of the channel to be tested is then used to detect the capacitance from the integrating capacitor C. INTA The function of extracting charge. If self-capacitance detection with active shielding is required, configure the multiplexer corresponding to the pin of the shielding electrode to active shielding mode, so that the voltage waveform on the corresponding shielding electrode is basically consistent with the waveform on the pin of the self-capacitance detection channel, which greatly reduces the parasitic coupling capacitance between the corresponding shielding electrode and the pins of other self-capacitance detection channels from the integrating capacitor C. INTA Extracting charge from or to the integrating capacitor C INTAThe amplitude of the injected charge is reduced, thereby decreasing the impact of the parasitic coupling capacitance on the self-capacitance detection result. If mutual capacitance detection is required, the multiplexers corresponding to the pins of the two channels to be tested that generate mutual capacitance are configured to mutual capacitance RX mode and mutual capacitance TX mode, respectively. The mutual capacitance between the pins of the two channels to be tested is then used to calculate the self-capacitance detection result from the integrating capacitor C. INTA The function of extracting charge.

[0027] As shown in Table 1, in self-capacitance detection mode, when the switching clock signal is low, only the first switch is closed, connecting the pin of the channel under test to ground; when the switching clock signal is high, only the second switch is closed, connecting the pin of the channel under test to the first analog bus. In mutual capacitance (RX) mode, when the switching clock signal is low, only the third switch is closed, connecting the pin of the channel under test to the second analog bus; when the switching clock signal is high, only the second switch is closed, connecting the pin of the channel under test to the first analog bus. In mutual capacitance (TX) mode, when the switching clock signal is low, only the third switch is closed, connecting the pin of the channel under test to the second analog bus; when the switching clock signal is high, only the first switch is closed, connecting the pin of the channel under test to ground. In active shielding mode, when the switching clock signal is low, only the first switch is closed, connecting the pin of the shielding electrode to ground; when the switching clock signal is high, only the third switch is closed, connecting the pin of the channel under test to the second analog bus.

[0028] As mentioned above, in the embodiments of the present invention, the capacitance detection circuit includes only one set of charge compensation circuit and control logic. Specifically, the charge compensation circuit includes an integrating capacitor C. INTA and the ΔΣ modulator, wherein the integrating capacitor C INTA One end of the ΔΣ modulator is connected to the first analog bus, and the other end is grounded. The first input terminal of the ΔΣ modulator is connected to the first analog bus, and the second input terminal is connected to the reference voltage V. ref ,like Figure 5 As shown. Based on this circuit structure, in one embodiment of the present invention, the ΔΣ modulator takes the voltage of the first analog bus as the input signal and modulates the signal according to the reference voltage V. ref The input signal is quantized. Simultaneously, based on the quantization result, the flow rate to the integrating capacitor C is controlled. INTA The magnitude of the compensation charge is adjusted so that the average voltage on the first analog bus is maintained at V via feedback. ref Nearby. Specifically, within each unit of time, when the ΔΣ modulator detects via voltage comparison that the voltage of the first analog bus is lower than the reference voltage V... ref Then, to the integrating capacitor C INTAA certain amount of charge is compensated to increase the voltage of the first analog bus; and when the ΔΣ modulator detects through voltage comparison that the voltage of the first analog bus is higher than the reference voltage V... ref Then reduce the integrator capacitor C INTA Compensated charge, or stop compensating charge, or from the integrating capacitor C INTA A certain amount of charge is removed, causing the voltage of the first analog bus to rise less or fall less. It can be seen that, regardless of whether it is in self-capacitance detection mode or mutual capacitance detection mode, the capacitor under test serves to discharge the integrating circuit, while the ΔΣ modulator replenishes the charge of the integrating capacitor under feedback. Therefore, the charge compensation logic of the ΔΣ modulator for the integrating capacitor is exactly the same in both self-capacitance and mutual capacitance detection modes, reducing the complexity of circuit design and control. The integrating capacitor can be an off-chip discrete component or an on-chip integrated component.

[0029] like Figure 5 As shown, in one embodiment of the present invention, the capacitance detection circuit may further include a voltage buffer 506, the second analog bus 502 being driven by the voltage buffer 506, and the input and output voltages of the voltage buffer 506 being a reference voltage V. ref It should be understood that in some other embodiments of the present invention, a voltage buffer may not be required, as long as the reference voltage V driving the second analog bus is guaranteed. ref Sufficient driving capability is sufficient.

[0030] In one embodiment of the present invention, the first switch can also charge the pin of the corresponding channel to be detected from the power supply, such as... Figure 6 As shown. Figure 6 The structure of the embodiment shown is similar to Figure 5 The circuit structures shown are basically the same, the only difference being that the second terminal of the first switch is not grounded, but connected to the power supply V. dd Connection. Based on Figure 6 The circuit structure shown has control logic and Figure 5 The embodiments shown are basically the same, except that the voltage connected when the first switch is turned on is different, as shown in Table 2.

[0031] Table 2 Similarly, Figure 6 The voltage buffer in the circuit structure can also be omitted, as long as the reference voltage V driving the second analog bus is guaranteed. ref Sufficient driving capability is sufficient.

[0032] Furthermore, in the capacitance detection circuit, the structures of each multiplexer module can be the same or different. For example, the second terminals of each first switch in the capacitance detection circuit can be all grounded, all connected to the power supply, or partially grounded and partially connected to the power supply. In addition, the multiplexer module can also adopt other designs, as long as they can satisfy the control logic described in Tables 1 and 2.

[0033] Based on the capacitance detection circuit described above Figure 7 This diagram illustrates a flow chart of a capacitance detection method according to an embodiment of the present invention. Figure 7 As shown, a capacitance detection method includes: First, in step 701, configure the operating mode. Configure the operating mode of the multiplexer switch according to the required detection function. Specifically, if self-capacitance detection is required, configure the multiplexer switch corresponding to the pin of the channel to be tested in self-capacitance detection mode; if self-capacitance detection with active shielding is required, configure the multiplexer switch corresponding to the pin of the shielding electrode in active shielding mode; if mutual capacitance detection is required, configure the multiplexers corresponding to the pins of the two chips that generate mutual capacitance in mutual capacitance RX mode and mutual capacitance TX mode, respectively; and Finally, in step 702, the control switch is closed or opened to obtain the capacitance detection result. Based on the switching clock signal, the closing and opening of each switch is controlled according to the operating mode, and the capacitance detection result is obtained through the ΔΣ modulator. Specifically, in self-capacitance detection mode, when the switching clock signal is low, only the first switch is closed, connecting the pin of the channel to be detected to ground or power supply; when the switching clock signal is high, only the second switch is closed, connecting the pin of the channel to be detected to the first analog bus. In mutual capacitance RX mode, when the switching clock signal is low, only the third switch is closed, connecting the pin of the channel to be detected to the second analog bus; when the switching clock signal is high, only the second switch is closed, connecting the pin of the channel to be detected to the first analog bus. In mutual capacitance TX mode, when the switching clock signal is low, only the third switch is closed, connecting the pin of the channel to be detected to the second analog bus; when the switching clock signal is high, only the first switch is closed, connecting the pin of the channel to be detected to ground or power supply. In active shielding mode, when the switching clock signal is low, only the first switch is closed, connecting the shielding electrode pin to ground or power. When the switching clock signal is high, only the third switch is closed, connecting the shielding electrode pin to the second analog bus. During this process, the capacitance detection result is obtained through the ΔΣ modulator.

[0034] It should be understood that in some other embodiments of the present invention, the phase of the clock signal can also be reversed. That is, in self-capacitance detection mode, when the switching clock signal is high, only the first switch is closed, connecting the pin of the channel under test to ground or power supply; when the switching clock signal is low, only the second switch is closed, connecting the pin of the channel under test to the first analog bus. In mutual capacitance RX mode, when the switching clock signal is high, only the third switch is closed, connecting the pin of the channel under test to the second analog bus; when the switching clock signal is low, only the second switch is closed, connecting the pin of the channel under test to the first analog bus. In mutual capacitance TX mode, when the switching clock signal is high, only the third switch is closed, connecting the pin of the channel under test to the second analog bus; when the switching clock signal is low, only the first switch is closed, connecting the pin of the channel under test to ground or power supply. In active shielding mode, when the switching clock signal is high, closing only the first switch will connect the pin of the shielding electrode to ground or power supply. When the switching clock signal is low, closing only the third switch will connect the pin of the shielding electrode to the second analog bus.

[0035] The capacitance detection circuit provided by this invention simultaneously achieves self-capacitance detection and mutual capacitance detection with active shielding function without adding additional switches. This solves the problem in voltage comparison-based proportional capacitor-to-digital converter circuits that require additional switches and integrating capacitors to accommodate both self-capacitance and mutual capacitance detection, thereby reducing material costs in applications. Furthermore, in both self-capacitance and mutual capacitance detection modes, the capacitance detection circuit differs only in the switching logic of the multiplexer; the charge compensation logic of the ΔΣ modulator for the integrating capacitor remains completely consistent. This simplifies the design of the charge compensation circuit, reduces the complexity of the control logic, and helps to reduce module area, thus lowering manufacturing costs.

[0036] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A capacitance detection circuit supporting self-capacitance and mutual capacitance detection, characterized in that, include: A first analog bus is electrically connected to the input of an integrating capacitor and a ΔΣ modulator, the ΔΣ modulator being configured to replenish charge to the integrating capacitor by control to maintain the average voltage of the first analog bus; The second analog bus is configured to provide a reference voltage; as well as Multiple multiplexer switch modules are provided, each connected to a channel to be tested. Each multiplexer switch module includes a first switch, a second switch, and a third switch. The first terminal of the first switch is connected to a pin of the channel to be tested, and the second terminal is grounded or powered. The first terminal of the second switch is connected to a pin of the channel to be tested, and the second terminal is connected to the first analog bus. The first terminal of the third switch is connected to a pin of the channel to be tested, and the second terminal is connected to the second analog bus.

2. The capacitance detection circuit as described in claim 1, characterized in that, It also includes a mode control module, which is configured to configure the operating mode of the multiplexer module to achieve different capacitance detection functions.

3. The capacitance detection circuit as described in claim 2, characterized in that, The working modes include: Self-capacitance detection mode, which is used for self-capacitance detection of the corresponding channel to be tested in the multi-channel selection switch module; Mutual capacitance RX mode and mutual capacitance TX mode are used to detect the mutual capacitance between the channels to be tested corresponding to two multiplexer modules; and Active shielding mode is used to reduce the impact of parasitic coupling capacitance between the shielding electrode and the current detection channel on the self-capacitance detection results.

4. The capacitance detection circuit as described in claim 2, characterized in that, It also includes a clock module configured to provide a switching clock signal, and the multiplexer module controls the closing and opening of each switch based on the switching clock signal and according to the configured operating mode.

5. The capacitance detection circuit as described in claim 1, characterized in that, It also includes a voltage buffer, whose input is connected to a reference voltage and whose output is connected to the second analog bus to drive the second analog bus.

6. The capacitance detection circuit as described in claim 1, characterized in that, The integrating capacitor is an off-chip discrete device.

7. The capacitance detection circuit as described in claim 1, characterized in that, The integrating capacitor is integrated on-chip.

8. A capacitance detection method, characterized in that, The capacitance detection method, employing the capacitance detection circuit as described in any one of claims 1 to 7, comprises: Configure the operating mode of the multi-channel selection switch module according to the required detection functions; and Based on the switching clock signal, the closing and opening of each switch are controlled according to the operating mode.

9. The capacitance detection method as described in claim 8, characterized in that, Depending on the required detection functions, the operating modes of the multi-channel selection switch module can be configured as follows: If self-capacitance testing is required, configure the multiplexer module corresponding to the pin of the channel to be tested to self-capacitance testing mode. If self-capacitance testing with active shielding is required, configure the multiplexer module corresponding to the pin of the channel to be tested for self-capacitance testing, and configure the multiplexer corresponding to the actively shielded channel for active shielding mode; and If mutual capacitance detection is required, the multiplexer modules corresponding to the two pins that generate mutual capacitance should be configured as mutual capacitance RX mode and mutual capacitance TX mode, respectively.

10. The capacitance detection method as described in claim 8, characterized in that, Based on the switching clock signal, controlling the closing and opening of each switch according to the operating mode includes: In self-capacitance detection mode, when the switching clock signal is low, only the first switch is closed, so that the pin of the channel to be detected is connected to ground; when the switching clock signal is high, only the second switch is closed, so that the pin of the channel to be detected is connected to the first analog bus. In the mutual capacitance RX mode, when the switching clock signal is low, only the third switch is closed, so that the pin of the channel to be tested is connected to the second analog bus; when the switching clock signal is high, only the second switch is closed, so that the pin of the channel to be tested is connected to the first analog bus. In mutual capacitance TX mode, when the switching clock signal is low, only the third switch is closed, connecting the pin of the channel under test to the second analog bus; when the switching clock signal is high, only the first switch is closed, connecting the pin of the channel under test to ground. In active shielding mode, when the switching clock signal is low, closing only the first switch will connect the corresponding electrode to ground; when the switching clock signal is high, closing only the third switch will connect the shielding electrode to the second analog bus.

Images