Chip test system and test method

Abstract

The invention discloses a chip test system and a test method. The chip test system comprises a controller; the test assembly comprises a test base and a test carrier plate, the test base is detachably installed on the test carrier plate, the test base is used for installing a to-be-tested chip, the test carrier plate is provided with a clock module and a power supply module, the clock module and the power supply module are electrically connected with the controller, and the power supply module is electrically connected with the controller. The clock module and the power supply module are adjustable; the display assembly comprises a plurality of groups of display lamps; and a power assembly. According to the chip test system, the controller can be connected with other electronic equipment through the interface, so that different programs can be conveniently debugged according to different specifications of chips to be tested; the clock module and the power supply module prestore some parameters for different chips to be tested to use. A plurality of groups of display lamps are arranged, so that the expansibility of the chip test system is improved, and one or more groups of display lamps can be called to work every time.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip testing technical field, and particularly to a chip testing system and a testing method. BACKGROUND

[0002] With the development of the times, there are more and more types of chips, and the requirements for aging testing of the chips are also increasing. Different voltage requirements, current requirements, and signal requirements are various. Each type of chip product needs to be customized with a corresponding aging testing system for aging testing. When the aging testing demand of the same type of chip product ends, the corresponding aging testing system is directly scrapped, and when another type of chip product needs to be tested, the aging testing system needs to be re-built. When multiple specifications of chip products need to be tested, the traditional method not only wastes resources, but also greatly affects the testing efficiency. SUMMARY

[0003] To solve the above technical problems, the present application provides a chip testing system and a testing method.

[0004] In a first aspect, the present application provides a chip testing system, comprising: a controller; a testing assembly comprising a testing base and a testing board, the testing base being detachably mounted on the testing board, the testing base being used for mounting a chip to be tested, the testing board being provided with a clock module and a power supply module, the clock module and the power supply module both being electrically connected with the controller, the clock module and the power supply module both being adjustable; a display assembly comprising a plurality of display lights, all the display lights being electrically connected with the controller; a power supply assembly for supplying power to the testing assembly, the controller and the display assembly.

[0005] Optionally, the testing base and the testing board are hard connected through a board-to-board connector, and the power supply assembly and the testing board are connected through a cable.

[0006] Optionally, the testing board adopts an interface design defined by a general PIN.

[0007] Optionally, the display assembly is mounted on a case, and the power supply assembly and the case are hard connected through a board-to-board connector.

[0008] Optionally, a plurality of the display lights are arranged on the case.

[0009] Optionally, the display lights have at least two colors to distinguish pass signals and fail signals. Alternatively, The display lamp distinguishes the pass signal and the fail signal by light and dark.

[0010] Optionally, the power supply component comprises a power supply carrier plate, and a power supply protection chip is arranged on the power supply carrier plate and used for providing power supply protection.

[0011] Optionally, the power supply component comprises a power supply carrier plate, and a pair of power management chips are arranged on the power supply carrier plate, one of the power management chips is used for generating a system positive voltage by step-down, and the other power management chip is used for generating a system negative voltage by step-down.

[0012] Optionally, the power supply component comprises a power supply carrier plate, and the controller is a CPLD device arranged on the power supply carrier plate and used for controlling timing, providing a control signal and system monitoring.

[0013] Optionally, a FAN-OUT chip is arranged on the test carrier plate, and the FAN-OUT chip is used for fan-out clock to form an adjustable clock module for multiple stations.

[0014] Optionally, a pair of low-dropout linear voltage stabilizers are arranged on the test carrier plate, one of the low-dropout linear voltage stabilizers is used for providing adjustable positive power supply for the chip to be tested, and the other low-dropout linear voltage stabilizer is used for providing adjustable negative power supply for the chip to be tested.

[0015] Optionally, an operational amplifier component is arranged on the test carrier plate and used for providing overcurrent protection.

[0016] Optionally, a monitoring unit is arranged on the test carrier plate and used for monitoring a feedback signal of the chip to be tested.

[0017] In a second aspect, the application provides a test method using the chip test system as described above, comprising the following steps: S1, according to the specification of the chip to be tested, a corresponding test base 21 is installed on the test carrier plate 22; S2, the chip to be tested is installed on the test base 21; S3, a start test button is triggered in software, and the software sends instructions to the CPLD device; S4, the CPLD device changes the parameters of the clock module, the power management chip and the low-dropout linear voltage stabilizer; S5, after a certain time is set, the display result of the display component 3 is observed and recorded; S6, the system power supply is turned off; S7, the test base 21 is disassembled, and the chip to be tested is disassembled from the test base 21; S8, steps S1-S7 are repeated.

[0018] The technical scheme provided by the embodiment of the application has the following advantages compared with the prior art. The chip testing system provided by the application, wherein the controller can be connected with other electronic devices through the interface, so that different programs can be debugged according to different specifications of the chip to be tested. The clock module and the power supply module prestore some parameters for different chips to be tested. A plurality of display lamps are arranged, so that the expansibility of the chip testing system is improved, and one or more groups of display lamps can be called to work each time. BRIEF DESCRIPTION OF DRAWINGS

[0019] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the application and, together with the specification, serve to explain the principles of the application.

[0020] In order to more clearly illustrate the technical scheme in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows, and obviously, other drawings can also be obtained by those skilled in the art without creative labor.

[0021] Figure 1 A schematic view of the power supply assembly connected with the testing assembly according to the embodiment of the application; Figure 2 A schematic view of the display assembly and the testing assembly connected with the controller according to the embodiment of the application; Figure 3 A structural schematic view of the display assembly according to the embodiment of the application; Figure 4 A flow chart of the testing method according to the embodiment of the application.

[0022] Explanation of reference signs 1, controller; 2, testing assembly; 21, testing base; 22, testing carrier plate; 23, clock module; 24, power supply module; 3, display assembly; 31, display lamp. DETAILED DESCRIPTION

[0023] In order to more clearly illustrate the above-mentioned purposes, features and advantages of the application, the scheme of the application will be further described below. It should be noted that the embodiments of the application and the features in the embodiments can be combined with each other without conflict.

[0024] In the following description, many specific details are set forth in order to provide a thorough understanding of the application, but the application can also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some of the embodiments of the application, not all the embodiments.

[0025] The embodiment provides a chip testing system and a testing method. The chip testing system and the testing method are described in detail through specific embodiments as follows. Referring to Figures 1 to 3 The chip testing system provided by the embodiment comprises a controller 1. The controller 1 can be connected with other electronic devices through an interface, so that different programs can be debugged according to different specifications of chips to be tested, and the controller 1 is responsible for testing logic scheduling, parameter configuration, state monitoring and data interaction.

[0026] It should be noted that the controller 1 can also be remotely connected through a wireless communication module such as 4G, 5G, WIFI or Bluetooth, so as to realize the work of remotely debugging programs. Technical personnel can also check the testing progress and download testing data through a cloud platform at different places. At the same time, the system can upload testing data (such as chip working voltage, current and temperature) to a cloud database at regular intervals (for example, every 5 minutes), so as to facilitate data analysis and tracing in the later period.

[0027] The testing assembly 2 comprises a testing base 21 and a testing board 22.

[0028] The testing base 21 is detachably installed on the testing board 22, and the testing base 21 is used for installing chips to be tested.

[0029] The testing board 22 serves as a connecting carrier of the testing base 21 and other modules of the system, and can be designed as a 4-layer PCB board (the top layer and the bottom layer are signal layers, and the middle two layers are power supply layers and ground planes), so as to reduce power supply noise and signal interference.

[0030] The testing board 22 is provided with a clock module 23 and a power supply module 24, and the clock module 23 and the power supply module 24 are electrically connected with the controller 1. The clock module 23 and the power supply module 24 can be adjusted. It should be understood that the clock module 23 and the power supply module 24 prestore some parameters for use of different chips to be tested.

[0031] The display assembly 3 comprises a plurality of display lamps 31, and all the display lamps 31 are electrically connected with the controller 1. The plurality of display lamps 31 are arranged, so that the expandability of the chip testing system is improved, and one or more groups of display lamps 31 can be called for work each time. The display assembly 3 is used for intuitively feeding back the states of all testing stations.

[0032] A power supply assembly is used for supplying power for the testing assembly 2, the controller 1 and the display assembly 3.

[0033] In some embodiments, the test base 21 and the test board 22 are hard connected through a board-to-board connector; the power supply assembly and the test board 22 are connected through a cable. Specifically, the power supply assembly and the test board 22 can adopt a 100PIN high-speed cable interface and are connected through a 100PIN high-speed cable, wherein the pin definition is standardized (including power pin, clock pin, control pin, and state feedback pin), ensuring that test boards 22 of multiple specifications can be used.

[0034] Further, the cable can be a shielded FFC cable (the shielding layer is composed of aluminum foil and woven mesh, and has strong anti-interference ability), and the specific length of the cable can meet the flexible arrangement requirements of the test board 22 in the aging oven; the power supply assembly and the case are hard connected through a board-to-board connector, and the connector has an anti-reverse insertion design to avoid circuit damage caused by installation errors.

[0035] In some embodiments, the test board 22 adopts a universal PIN defined interface design, thereby supporting direct plug-in of test bases 21 of different specifications.

[0036] It should be noted that the test base 21, as an “adapting interface” of the chip to be tested, adopts a modular design and is customized according to the chip packaging type to correspond to the base structure.

[0037] Further, the test base 21 can be made of high-temperature-resistant engineering plastic by injection molding, and the base is internally integrated with elastic probes to ensure reliable contact between the chip and the base, while avoiding pin wear caused by frequent plugging and unplugging.

[0038] The pin arrangement of the test base 21 is completely matched with the board-to-board connector of the test board, without the need for additional welding or jumper wiring, thereby realizing “plug and play”; for high-power chips, the bottom of the test base 21 is designed with heat dissipation holes, which can be used in combination with a cooling fan or a cooling fin to reduce the temperature rise of the chip to be tested during testing.

[0039] In some embodiments, chips of the same packaging type can share the same test base 21, for example, MCUs, operational amplifiers, and comparators in SOP8 packaging can use the same SOP8 test base 21, and only need to configure different test parameters through software.

[0040] In some embodiments, the display assembly 3 is installed on the case, and the power supply assembly and the case are hard connected through a board-to-board connector. It should be noted that the case serves as a bracket to provide mounting stations for the display assembly 3 and the power supply assembly and the like.

[0041] Further, the power supply assembly can be connected to the case through buckles, bolts, or the like, thereby facilitating disassembly and assembly of the power supply assembly and the case and improving the convenience of later maintenance.

[0042] Continuing to refer toFigure 3 As shown, multiple groups of display lamps 31 are arranged on the cabinet, that is, multiple groups of display lamps 31 can be arranged on the outer surface of one side or multiple sides of the cabinet, and each group of display lamps 31 can correspond to a test station of a chip to be tested, and then the color and on-off state of each group of display lamps 31 can be used to determine whether the test station is working normally.

[0043] In further embodiments, the display lamp 31 has at least two colors to distinguish pass signals and fail signals.

[0044] In some embodiments, the display lamp 31 is composed of green and red LED lamps. When the green LED lamp is always on, it means that the aging test of the chip to be tested corresponding to the test station is normal, and the voltage, current and signal interaction all meet the requirements, that is, a pass signal is obtained. When the green LED lamp flashes, it means that the test station is in a standby state (the parameter configuration has been completed, and the chip is waiting to be installed). When the red LED lamp is always on, it means that the aging test of the chip to be tested corresponding to the test station is abnormal (such as overcurrent, overvoltage or signal interruption), that is, a fail signal is obtained. When the red LED lamp flashes, it means that the chip to be tested corresponding to the test station is not correctly installed or has poor contact.

[0045] Alternatively, the display lamp 31 distinguishes pass signals and fail signals by on-off. It should be understood that the display lamp 31 distinguishes pass signals and fail signals by on-off includes three cases of always on, always off or flashing, so as to correspond to three cases of obtaining a pass signal, obtaining a fail signal and the chip to be tested not being correctly installed or having poor contact.

[0046] In some embodiments, the power supply assembly includes a power supply carrier plate, which is the "power supply and control center" of the chip test system and integrates multiple special chips. In further embodiments, the power supply carrier plate can be designed as a multi-layer PCB plate, specifically a four-layer PCB plate, in which the power supply layer and the ground plane are independently layered to reduce interference.

[0047] In some embodiments, the power supply assembly is the energy supply center of the system and is responsible for providing stable power supply for the controller, the test assembly and the display assembly. Specifically, the power supply assembly can adopt a power supply carrier plate + redundancy design architecture.

[0048] Further, for the key power supply circuit (such as controller power supply, test carrier board main power supply), a dual power supply parallel design can be adopted, two same specification power management chips work simultaneously, when one chip fails, the other chip can automatically switch and bear all the load, ensuring that the system does not interrupt the test; at the same time, a backup battery interface is provided on the power supply carrier board, when the external power supply is interrupted, the backup battery can maintain the controller 1 and the display assembly 3 to work for a set time (which can be designed according to the needs, such as 5-10 minutes), ensuring that the test data is not lost.

[0049] In some embodiments, a power protection chip is provided on the power supply carrier board and is used to provide power protection. The power protection chip can monitor the output current and voltage in real time, and when overcurrent (exceeding the configured threshold), overvoltage or undervoltage is detected, the power supply circuit is immediately cut off to protect the chip to be tested and the subsequent circuit.

[0050] Specifically, the model of the power protection chip can be TPS259570DSGR, the working voltage is 2.7V-18V, the maximum current limiting value is configurable (0.1A-5A), and the response time is <1μs.

[0051] It should be understood that the power protection chip can realize the following protection functions: the current limiting value of the circuit current is adjustable between 0.1A-5A, the response time is <1μs, when the output current exceeds the threshold, the power supply circuit is immediately cut off; the overvoltage threshold is 1.2 times the rated voltage, and the undervoltage threshold is 0.8 times the rated voltage, which protects the power management chip and the subsequent circuit; when the chip temperature exceeds 150℃, the output power is automatically reduced, and when the temperature drops below 120℃, the normal work is restored.

[0052] In some embodiments, the power supply assembly includes a power supply carrier board, and a pair of power management chips are provided on the power supply carrier board, one of which is used to generate a system positive voltage by step-down, and the other is used to generate a system negative voltage by step-down.

[0053] Among them, the pair of power management chips are a first power management chip and a second power management chip; the first power management chip steps down the voltage input from the outside to the positive voltage required by the system (such as 3.3V, 5V), and supplies power to the test carrier board 22 and the system control circuit; the second power management chip generates the negative voltage required by the system (such as -5V, -12V), to meet the special chip test requirements of double power supply.

[0054] Furthermore, the first power management chip is a TPS54335 DC / DC chip with an input voltage of 4.5V~17V, an output voltage of 0.8V~12V, and an output current of 3A; the second power management chip is an LMZ34002RKGR DC / DC chip with an input voltage of 4.5V~20V, an output voltage of -0.8V~-12V, and an output current of 2A.

[0055] Continue to refer to Figure 2 As shown, the power supply assembly includes a power supply carrier board, and the controller 1 is a CPLD device mounted on the power supply carrier board, which is used to control timing, provide control signals, and monitor the system.

[0056] Among them, the CPLD device can generate clock signals (configurable from 1MHz to 100MHz) and control signals (such as reset signals and enable signals); the CPLD device can also receive the status signals of the chip under test fed back by the test carrier board 22, process them and send them to the chassis control and display component 3 for display; the CPLD device can also monitor the working status of each chip on the power supply carrier board and record fault information.

[0057] Regarding power supply components, a "zonal layout" design can be adopted, separating the power supply circuit (DC / DC chip, power protection chip) from the control circuit (CPLD device) to reduce the impact of interference signals in the power supply circuit on the control signal; critical power supply lines adopt a copper-plated thickened design to reduce line impedance and ensure the stability of high current power supply.

[0058] Continue to refer to Figure 1 As shown, the test carrier board 22 is equipped with a FAN-OUT chip, which is used to fan out the clock to form an adjustable clock module 23 for use by multiple workstations.

[0059] Specifically, the FAN-OUT chip can amplify the clock signal and control signal sent by the power supply carrier board and fan them out to multiple test bases 21 to ensure signal consistency at each station.

[0060] The FAN-OUT chip is model 74AVC1T1022DPJ; its operating voltage is 1.65V~3.6V, and its maximum fan-out number is 8, which means it can fan out to 1~8 test base 21 stations.

[0061] In some embodiments, the test carrier 22 is provided with a pair of low dropout linear regulators, one of which is used to provide an adjustable positive power supply to the chip under test, and the other is used to provide an adjustable negative power supply to the chip under test.

[0062] Specifically, the low-dropout linear regulator that provides an adjustable positive power supply to the chip under test is the first low-dropout linear regulator, and the low-dropout linear regulator that provides an adjustable negative power supply to the chip under test is the second low-dropout linear regulator.

[0063] The first low-dropout linear regulator provides a positive voltage supply to the chip under test (DUT). The output voltage can be adjusted via an external resistor to suit the positive voltage requirements of different DUTs (e.g., 1.8V, 3.3V). The first low-dropout linear regulator can be a TPS7A9101DSK, with an input voltage of 2.5V~18V, an output voltage of 0.8V~16V, an output current of 1A, and a voltage accuracy of ±1%.

[0064] The second low-dropout linear regulator provides a negative voltage supply to the chip under test (DUT). The output voltage can be adjusted via an external resistor to accommodate DUTs requiring negative voltages (such as operational amplifier components). The second low-dropout linear regulator can be model LT3093EDD#TRPBF, with an input voltage of -2.5V to -18V, an output voltage of -0.8V to -16V, and an output current of 300mA.

[0065] In some further embodiments, the test carrier 22 is also provided with a backup low-dropout linear regulator. The backup low-dropout linear regulator provides a positive voltage power supply to the chip under test. As a backup low-dropout linear regulator that provides a positive voltage, it is used in conjunction with the first low-dropout linear regulator to meet the power supply requirements of the low-current chip under test, or to provide redundant power supply when the first low-dropout linear regulator fails.

[0066] In some embodiments, the test carrier 22 is provided with an operational amplifier assembly and is used to provide overcurrent protection.

[0067] In some further embodiments, the operational amplifier components include TLV274CPWR and LM339PWR, where TLV274CPWR is a four-channel operational amplifier with an operating voltage of 2.7V~12V; and LM339PWR is a four-channel voltage comparator with an operating voltage of 2V~36V. Together, they form a current detection circuit: TLV274CPWR converts the operating current of the chip under test into a voltage signal, and LM339PWR compares this voltage signal with a preset threshold. If the threshold is exceeded, overcurrent protection is triggered, and a signal is sent to the power supply carrier to cut off the power supply.

[0068] In some embodiments, the test carrier board 22 is provided with a monitoring unit for monitoring the feedback signal of the chip under test.

[0069] Furthermore, the monitoring unit receives status signals (such as data output and ready signals) from the chip under test, shapes unstable signals into standard pulse signals, and sends them to the CPLD device on the power supply board for processing to ensure the accuracy of signal detection. Specifically, the monitoring unit can be a monostable multivibrator of model 74LVC1G123DCURG4, with an operating voltage of 1.65V~5.5V and configurable output pulse width.

[0070] Continue to refer to Figures 1 to 4 As shown, in a second aspect, this application provides a testing method using the chip testing system described above, comprising the following steps: S1. Install the corresponding test base 21 onto the test carrier board 22 according to the specifications of the chip to be tested; S2. Install the chip to be tested onto the test base 21; S3. Trigger the start test button in the software, and the software will send instructions to the CPLD device; S4, CPLD devices change the parameters of the clock module, power management chip, and low dropout linear regulator; S5. After setting a time, observe and record the display results of display component 3. S6. Disconnect the system power; S7. Remove the test base 21 and remove the chip to be tested from the test base 21; S8. Repeat steps S1-S7.

[0071] Furthermore, step S21 is included between steps S2 and S3: placing the test substrate 22 and the test chip into an aging furnace, which has set environmental characteristics, such as set environmental parameters such as temperature and humidity.

[0072] Further, step S4 specifically includes: the CPLD device controlling the clock module 23 to work according to the debugged clock signal, the CPLD device controlling the power management chip to input the positive voltage required by the test system, and the CPLD device controlling the low dropout linear regulator to input the debugged set voltage.

[0073] Further, step S5 specifically includes: the indicator light 31 can be composed of green and red LEDs. When the green LED is constantly lit, it indicates that the aging test of the chip under test at the corresponding station is normal, and the voltage, current, and signal interaction all meet the requirements, i.e., a pass signal is obtained; when the red LED is constantly lit, it indicates that the aging test of the chip under test at the corresponding station is abnormal (such as overcurrent, overvoltage, or signal interruption), i.e., a fail signal is obtained; when the red LED flashes, it indicates that the chip under test at the corresponding station is not installed correctly or has poor contact. When the red LED is lit, it indicates that a fault has occurred at the corresponding station, and the fault time is recorded.

[0074] In some embodiments, step S6 specifically includes: when the test duration reaches a preset value, the controller 1 automatically sends a "test completed" signal to the host computer, the software pops up a test completed prompt, and generates a preliminary test report (including the number of normal workstations, the number of faulty workstations, and the statistics of fault types); if the test is conducted in an aging furnace, the heating function of the aging furnace is turned off first, and a cooling program is started, such as natural cooling or forced air cooling, and the power supply of the test system is disconnected after the temperature inside the furnace drops to room temperature; if the test is conducted in a room temperature environment, the power supply of the system is directly disconnected.

[0075] It should be noted that after all the chips to be tested have completed the test, step S9 can be executed to end the test.

[0076] After completing the aging test of all the chips to be tested, the complete test data can be exported from the host computer software, including the real-time voltage / current / temperature curves of each station and snapshot data when the fault occurs (such as the current fluctuation at a set time before the fault). For the chips that pass the test, their test data are compiled as a basis for chip reliability assessment. For example, if the voltage drift is less than ±0.02V after a set aging period, it is considered qualified. For the chip under test that shows "Fail", analyze the cause of the failure: if it is an overcurrent fault, check if there is a short circuit in the chip; if it is a signal abnormality, check if the test base probes are worn or if the chip pins are oxidized; if it is an over-temperature fault, check if the temperature control of the aging furnace is normal.

[0077] The above-mentioned data collection and analysis can be performed separately after each chip under test has completed the test, or the data can be analyzed uniformly after all chips under test have completed the test.

[0078] It should be understood that system initialization and parameter configuration must be completed before formal testing, specifically including system hardware checks and test parameter configuration.

[0079] The system hardware check includes checking whether the connection between the power supply component and the chassis and test carrier board 22 is reliable, ensuring that the board-to-board connectors are not loose and the cables are not damaged; turning on the system power and observing whether all the display lights 31 in the display component 3 can be lit. If any LED is not lit, check the power supply circuit or controller connection of the corresponding workstation; the system hardware check also includes connecting to the controller 1 through the host computer software to read the system hardware information (such as CPLD model, power management chip status, temperature sensor calibration value) to confirm that each module is working normally.

[0080] The specific implementation method and principle are the same as those in the above embodiments, and can bring the same or similar technical effects. They will not be repeated here. For details, please refer to the description of the above chip testing system embodiments.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip testing system, characterized in that, include: Controller; The test assembly includes a test base and a test carrier board. The test base is detachably mounted on the test carrier board and is used to mount the chip to be tested. The test carrier board is provided with a clock module and a power supply module. Both the clock module and the power supply module are electrically connected to the controller, and both the clock module and the power supply module are adjustable. The display component includes multiple sets of indicator lights, all of which are electrically connected to the controller; A power supply assembly for supplying power to the test assembly, the controller, and the display assembly.

2. The chip testing system according to claim 1, characterized in that, The test base and the test carrier board are rigidly connected via a board-to-board connector; the power supply assembly is connected to the test carrier board via a cable.

3. The chip testing system according to claim 1, characterized in that, The test carrier board adopts a universal PIN-defined interface design.

4. The chip testing system according to claim 1, characterized in that, The display component is mounted on the chassis, and the power supply component is hard-connected to the chassis via a board-to-board connector.

5. The chip testing system according to claim 4, characterized in that, Multiple sets of the aforementioned indicator lights are arranged on the chassis.

6. The chip testing system according to claim 1, characterized in that, The indicator light has at least two colors to distinguish between pass and fail signals; or, The indicator light distinguishes between pass and fail signals by turning on and off.

7. The chip testing system according to claim 1, characterized in that, The power supply assembly includes a power carrier board, on which a power protection chip is provided to provide power protection.

8. The chip testing system according to claim 1, characterized in that, The power supply assembly includes a power carrier board, on which a pair of power management chips are provided. One of the power management chips is used to step down and generate a positive voltage for the system, and the other power management chip is used to step down and generate a negative voltage for the system.

9. The chip testing system according to claim 1, characterized in that, The controller is a CPLD device mounted on the power supply board and is used to control timing, provide control signals, and monitor the system.

10. The chip testing system according to any one of claims 1-9, characterized in that, The test carrier board is equipped with a FAN-OUT chip, which is used to fan out a clock to form an adjustable clock module for use by multiple workstations.

11. The chip testing system according to any one of claims 1-9, characterized in that, The test carrier board is equipped with a pair of low dropout linear regulators, one of which is used to provide an adjustable positive power supply to the chip under test, and the other is used to provide an adjustable negative power supply to the chip under test.

12. A testing method using the chip testing system as described in any one of claims 1-11, characterized in that, Includes the following steps: S1. Install the corresponding test base 21 onto the test carrier board 22 according to the specifications of the chip to be tested; S2. Install the chip to be tested onto the test base 21; S3. Trigger the start test button in the software, and the software will send instructions to the CPLD device; S4, CPLD devices change the parameters of the clock module, power management chip, and low dropout linear regulator; S5. After setting a time, observe and record the display results of display component 3. S6. Disconnect the system power; S7. Remove the test base 21 and remove the chip to be tested from the test base 21; S8. Repeat steps S1-S7.

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