Testing system for testing integrated circuit packaging finished product

Abstract

The invention discloses a test system for testing an integrated circuit packaging finished product, and belongs to the technical field of chip integrated packaging test, and the system is provided with a power conversion module, a main control module, a relay module, a test module and a tested chip. The test module comprises an open-short circuit test unit, a frequency test unit, a voltage test unit, a write-read data test unit and a power consumption test unit, and can effectively solve the problem that analog voltage provided by a test machine is not accurate to an ADC input channel of a tested chip in chip test production in a test production line. The chip to be tested is tested according to the test program setting condition, and the project for trimming the parameter deviation is set according to the program, so that the shipment chip parameters are ensured to be within the product specification, the shipment quality of the integrated circuit packaging product is guaranteed, the chip test convenience is improved, and the integrated circuit FT test cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit testing technology, and in particular relates to a testing system for testing packaged integrated circuit products. Background Technology

[0002] Currently, MCU chips undergo testing after packaging. The main content of the testing is the verification and adjustment of chip parameters after packaging (due to packaging stress, the parameters tested and adjusted during the wafer stage will have varying degrees of deviation after packaging). The parameters need to be corrected to the design specifications during FT (Final Test). The testing of finished integrated circuits after packaging is generally carried out using test machines. Test machines are the mainstream integrated circuit testing systems, especially at the wafer level, where general-purpose test machine systems are basically used for production testing. Moreover, wafer-level testing is carried out in professional testing plants. However, the testing of finished integrated circuits after packaging is more scattered. Some are sent to testing plants for testing after packaging, some are tested directly in the packaging plant after packaging, and some customers pack a few hundred chips themselves and test them on the application system to verify that the functions are normal before conducting batch testing.

[0003] The quality requirements for finished products necessitate comprehensive testing of all packaged integrated circuits before application. However, currently, due to various factors, comprehensive testing is not performed after packaging; instead, sampling inspection is conducted before shipment. The main factors include cost (due to limitations of robotic arms, the number of circuits tested simultaneously is typically only 2 or 4. This means that while the price of a testing machine is the same as that of a wafer-level testing machine, wafer-level testing can test 32 or 64 circuits simultaneously, making the cost per circuit tested significantly higher). Secondly, post-packaging testing and production face some challenges (currently, there are many large and small packaging plants in China; large, well-established packaging plants have multiple mainstream testing machine platforms to choose from and a large number of machines available for packaging). While post-packaging testing capacity can keep up with packaging demand, small-scale packaging plants have very limited types and quantities of testing equipment, or can only test open and short circuits. As a result, after integrated circuit packaging, it needs to be transported to a testing plant for testing and production (low failure rate, and requires finding a factory with production capacity for testing). Thirdly, the price of finished integrated circuits is low and they are cost-sensitive. Testing and production on a testing platform requires testing expenses, which increases the product cost. Under this comparison between price and cost, some customers voluntarily give up testing of the finished packaged product and only perform simple open and short circuit tests at the packaging plant, resulting in a relatively high shipping risk (the quality of the shipped product depends entirely on the control of the packaging process).

[0004] Therefore, there is an urgent need to provide a testing system for testing finished integrated circuit packages in order to solve the aforementioned technical problems. Summary of the Invention

[0005] In view of this, the present invention provides a testing system for testing finished integrated circuit packages. The system can test the chip according to the conditions set in the testing program and adjust the parameter deviations according to the program settings to ensure that the parameters of the shipped chips are within the product specifications, thus ensuring the quality of the shipped integrated circuit packages. This improves the convenience of chip testing and reduces the cost of integrated circuit FT testing. The specific technical solution adopted is as follows.

[0006] This invention provides a testing system for testing packaged integrated circuit products. The testing system includes a power conversion module, a main control module, a relay module, a testing module, and a chip under test (DUT). The power conversion module, the testing module, and the relay module are all connected to the main control module. The power conversion module and the DUT are all connected to the relay module. The DUT is also connected to the testing module. The relay module includes multiple analog switch groups. The testing module includes an open / short circuit testing unit, a frequency testing unit, a voltage testing unit, a write / read data testing unit, and a power consumption testing unit. The open / short circuit test unit is used to close the IO pin of the chip under test with the first test switch of the main control module to obtain the open / short circuit test result of whether the GND voltage of the chip under test meets the open / short circuit range. After the open / short circuit test result is passed, the main control module sends a first control command of the first level to the input terminal of the first analog switch group to connect the VCC pin of the chip under test. The frequency testing unit is used to receive a second control command of the first level sent by the main control module to the second analog switch group. The second analog switch group between the main control module and the frequency pin of the chip under test is closed to test and adjust the frequency, and to obtain a frequency test result to determine whether it conforms to the frequency range. The voltage testing unit is used to close the third analog switch group between the main control module and the voltage output pin of the chip under test after the frequency test result passes, so as to test the adjustment voltage and obtain the voltage test result to determine whether it meets the voltage range. The write-read data test unit is used to send clock data of the first level to the power switch after the voltage test result is passed. The data pin and clock pin of the chip under test are respectively connected to the main control module, and write-read data operations are performed on the storage unit of the chip under test to obtain the write-read data test result. The power consumption test unit is used to, after the write and read data test results pass, send a second level control to the fourth analog switch group to disconnect the connection between the VCC pin of the chip under test and the power conversion module. The main control module tests the output voltage of the current sensing amplifier connected to the fourth analog switch group and calculates the current corresponding to the output voltage to obtain the power consumption test results to determine whether it meets the voltage range. The main control module controls the first test switch to send a second level according to the power consumption test result to disconnect the second test switch between the power conversion module, the VCC pin of the chip under test and the main control module, and the VCC pin of the chip under test is powered off to end the test.

[0007] As a preferred embodiment of the above technical solution, the test system further includes a serial communication module and an auxiliary test module. The serial communication module is used to connect the data pin and clock pin of the chip under test to the main control module respectively. The main control module controls the data flow direction to transmit and receive data bit by bit according to the timing requirements of the received and output data of the chip under test. The auxiliary test module is used to control the connection between the auxiliary test of the chip under test and the main control module, and to control the direction of the auxiliary data flow.

[0008] As a preferred embodiment of the above technical solution, the power conversion module includes chip U2, chip U5, chip U7, capacitor C5, capacitor C6, capacitor C13, capacitor C16, and capacitor C17. One end of capacitor C5 is connected to chip U2, chip U5, and chip U7. One end of capacitor C6 is connected to chip U2, and the other end of capacitor C5 is grounded. The other end of capacitor C6 is grounded. One end of capacitor C13 is connected to chip U5, and the other end of capacitor C13 is grounded. One end of capacitor C16 is connected to chip U7, and the other end of capacitor C16 is grounded. One end of capacitor C17 is connected to chip U7, and the other end of capacitor C17 is grounded.

[0009] As a preferred embodiment of the above technical solution, the testing system further includes a data output display module and a test program storage module. Both the data output display module and the test program storage module are connected to the main control module. The data output display module is used to display test data, and the test program storage module is used to write user programs to the chip under test and store the user programs.

[0010] As a preferred embodiment of the above technical solution, the first analog switch group includes switch K2, switch SW4, switch SW5 and I_ADC module. The common terminal of switch SW4, the common terminal of switch SW5 and the control terminal of switch K2 are connected to the power conversion module. The control terminal of switch SW4, I_ADC module and normally open terminal of switch SW5 are connected to the normally open terminal of switch K2. The control terminal of switch SW5 is connected to the output terminal of the first test switch. The I_ADC module includes a chip U1, a capacitor C6, a resistor R3, a resistor R7, and a diode D6. The anode of the capacitor C6 and the diode D6, and one end of the resistor R3 are all connected to the chip U1. The cathode of the diode D6 is connected to the control terminal of the switch SW4 and one end of the resistor R7. The other end of the resistor R7 and the other end of the resistor R3 are connected to the chip U1. The normally open terminal of the switch SW4 is connected to the test switch of the main control module.

[0011] As a preferred embodiment of the above technical solution, the second analog switch group includes switch SW6, the normally open terminal of switch SW6 is connected to the output terminal of the power conversion module, the control terminal of switch SW6 is connected to the main control module, and the input terminal of switch SW6 is connected to the second test switch.

[0012] As a preferred embodiment of the above technical solution, the third analog switch group includes switch K3, capacitor C2, resistor R5, and voltage follower OP07. The common terminal of switch K3 is connected to the main control module. The normally open terminal of switch K3 is connected to one end of resistor R5 and the output terminal of voltage follower OP07. The control terminal of switch K3 is connected to the second test switch. The other end of resistor R5 is connected to the positive output terminal of voltage follower OP07. Capacitor C2 is connected in parallel between the positive input terminal and the negative output terminal of voltage follower OP07. The normally closed terminal of switch K3 is used to connect to the Tic terminal block. The Tic_GND pin of the Tic terminal block is used to measure the GND pin of the chip under test and to correct the reference voltage measurement value when testing the reference. The normally open terminal of switch K3 is connected to the Tic_MV pin of the Tic terminal block.

[0013] As a preferred embodiment of the above technical solution, the fourth analog switch group includes switch K4, switch SW7, capacitors C1, C3, C4, C7, C8, resistors R8, R9, R10, R11, and a current sensing amplifier. The input terminal of switch SW7 is connected to the second test switch, the normally closed terminal of switch SW7 is connected to the output terminal of the power conversion module, the control terminal of switch SW7 is connected to one end of capacitor C4, one end of capacitor C1, one end of resistor R8, and the current sensing amplifier, and the other end of resistor R8 is connected to the current sensing amplifier. One end of capacitor C3, the stationary contact of switch K4, and the current sensing amplifier are connected. The moving contact of switch K4 is connected to the chip under test. The control terminal of switch K4 is connected to the second test switch. The other end of capacitor C1 is connected to the other end of capacitor C3 and grounded. Resistor R9 and one end of capacitor C8 are connected to the current sensing amplifier. The other end of capacitor C8 is connected to the current sensing amplifier and grounded. One end of resistor R10 is connected to one end of resistor R10 and capacitor C7. The other end of resistor R11 is connected to the main control module. The other end of resistor R10 is connected to the current sensing amplifier.

[0014] As a preferred embodiment of the above technical solution, the SW7 switch includes a chip U47 with model number TS5A3160DBVR, and the current sensing amplifier includes a chip U49 with model number INA190A31DCKR.

[0015] As a preferred embodiment of the above technical solution, the testing system further includes multiple test power supplies and a robotic arm. The multiple test power supplies are connected to the power conversion module, and each test power supply includes a linear regulator of model SY6345AAC, multiple resistors, and multiple capacitors. The robotic arm is connected to the main control module. The robotic arm is used to receive the test results sent by the main control module. After receiving the test results, the robotic arm places the tested chip into the designated loading tube according to the result BIN signal and sends the next test instruction to the test system. The test results include at least one of the open / short circuit test results, the frequency test results, the voltage test results, the write / read data test results, or the power consumption test results.

[0016] This invention provides a testing system for testing finished integrated circuit packages. It comprises a power conversion module, a main control module, a relay module, a testing module, and a chip under test (DT). The testing module includes open / short circuit testing units, frequency testing units, voltage testing units, write / read data testing units, and power consumption testing units. In the testing production line, it effectively solves the problem of inaccurate analog voltage provided by the testing machine to the ADC input channel of the DT chip encountered during chip testing. The system tests the DT chip according to the conditions set in the testing program and adjusts parameter deviations according to the program settings, ensuring that the parameters of the shipped chips are within the product specifications. This guarantees the quality of shipped integrated circuit packages, improves the convenience of chip testing, and reduces the cost of FT testing for integrated circuits. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The structural block diagram of the testing system provided by the present invention; Figure 2 A schematic diagram illustrating the working principle of the testing system for testing finished integrated circuit packages provided by this invention; Figure 3 The circuit diagram of the open / short circuit test unit provided by the present invention; Figure 4A circuit diagram of the frequency testing unit provided by the present invention; Figure 5 A circuit diagram of the voltage testing unit provided by the present invention; Figure 6 A circuit diagram of the power consumption testing unit provided by the present invention; Figure 7 A circuit diagram of the power conversion unit provided by the present invention; Figure 8 A schematic diagram of the power conversion unit provided by the present invention; Figure 9 A schematic diagram of the current sensing amplifier provided for this invention; Figure 10 A schematic diagram of the test power supply provided for this invention; Figure 11 The execution flowchart of the test system provided by the present invention.

[0019] The symbols for the main components are explained below: 100 - Power conversion module; 110 - Main control module; 120 - Relay module; 121 - First analog switch group; 122 - Second analog switch group; 123 - Third analog switch group; 124 - Fourth analog switch group; 130 - Test module; 131 - Open / short circuit test unit; 132 - Frequency test unit; 133 - Voltage test unit; 134 - Write / read data test unit; 135 - Power consumption test unit; 140 - Chip under test. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] See Figure 1 , Figure 2 and Figure 11This invention provides a testing system for testing finished integrated circuit packages. The testing system includes a power conversion module 100, a main control module 110, a relay module 120, a testing module 130, and a chip under test (DUT) 140. The power conversion module 100, the testing module 130, and the relay module 120 are all connected to the main control module 110. The power conversion module 100 and the DUT 140 are all connected to the relay module 120. The DUT 140 is connected to the testing module 130. The relay module 120 includes multiple analog switch groups. The testing module 130 includes an open / short circuit testing unit 131, a frequency testing unit 132, a voltage testing unit 133, a write / read data testing unit 134, and a power consumption testing unit 135. The open / short circuit test unit 131 is used to close the IO pin of the chip under test 140 with the first test switch of the main control module 110 to obtain the open / short circuit test result of whether the GND voltage of the chip under test 140 meets the open / short circuit range. After the open / short circuit test result is passed, the main control module 110 sends a first control command of the first level to the input terminal of the first analog switch group 121 to connect the VCC pin of the chip under test 140. The frequency test unit 132 is used to receive a second control command of the first level sent by the main control module 110 to the second analog switch group 122. The second analog switch group 122 between the main control module 110 and the frequency pin of the chip under test 140 is closed to test and adjust the frequency, and to obtain the frequency test result to determine whether it conforms to the frequency range. The voltage test unit 133 is used to close the third analog switch group 123 between the main control module 110 and the voltage output pin of the chip under test 140 after the frequency test result is passed, so as to test the adjustment voltage and obtain the voltage test result to determine whether it meets the voltage range. The write-read data test unit 134 is used to send clock data of the first level to the second test switch connected to the power conversion module 100 after the voltage test result is passed. The data pin and clock pin of the chip under test 140 are respectively connected to the main control module 110, and write-read data operation is performed on the storage unit of the chip under test 140 to obtain the write-read data test result. The power consumption test unit 135 is used to, after the write and read data test results are passed, send a second level control to the fourth analog switch group 124 to disconnect the connection between the VCC pin of the chip under test 140 and the power conversion module 100. The main control module 110 tests the output voltage of the current sensing amplifier connected to the fourth analog switch group 124 and calculates the current corresponding to the output voltage to obtain the power consumption test result to determine whether it meets the voltage range. The main control module 110 controls the first test switch to send a second level according to the power consumption test result to disconnect the second test switch between the power conversion module 100, the VCC pin of the chip under test 140 and the main control module 110, and the VCC pin of the chip under test 140 is powered off to end the test.

[0022] In this embodiment, the test system further includes a serial communication module and an auxiliary test module. The serial communication module is used to connect the data pin and clock pin of the chip under test 140 to the main control module 110 respectively. The main control module 110 controls the data flow direction to transmit and receive bit by bit according to the timing requirements of the received and output data of the chip under test 140. The auxiliary test module is used to control the auxiliary test of the chip under test 140 to be connected to the main control module 110 and control the auxiliary data flow direction. The testing system also includes multiple test power supplies and a robotic arm. The multiple test power supplies are connected to the power conversion module 110. Each test power supply includes a SY6345AAC linear regulator, multiple resistors, and multiple capacitors. The robotic arm is connected to the main control module 110 and is used to receive test results sent by the main control module 110. After receiving the test results, the robotic arm places the chip under test 140 into designated loading tubes according to the result BIN signal and sends the next test command to the testing system. The test results include at least one of the open / short circuit test results, frequency test results, voltage test results, write / read data test results, or power consumption test results. The testing system also includes a data output display module and a test program storage module. Both the data output display module and the test program storage module are connected to the main control module 110. The data output display module displays test data, and the test program storage module writes user programs to the chip under test and stores the user programs. The first level is high, and the second level is low.

[0023] It should be noted that the integrated circuit package testing system consists of two parts: software and hardware. The hardware part includes a test power supply module (power conversion module), a main control module, a user program storage unit, a robotic arm communication module (not shown in the figure), and a test result display module (data output display module). The software part includes main control system library files and test device hardware library files (test timing protocol files, test hardware interface library files, voltage and frequency test module files, header files, power supply module files, test main program MAIN, test vector file TEST_PATTERN, and test project file PGM_PLAN). The operation of the integrated circuit package testing system in the FT test of integrated circuit packages is as follows: ① The test engineer writes test vectors according to the FT test conditions of the integrated circuit package and according to the hardware resource definition of this device (the vector functions use the functions in the TEST_PATTERN library file); ② Write the test PLAN (i.e., PGM_PLAN) according to the FT test conditions of the integrated circuit package; ③ Load the test PLAN and test vectors into the MAIN main program. Compile the program and download it to the main control module to execute the test. This test program needs to be developed based on the hardware resource allocation and within the framework of the software system. The integrated circuit package test system mainly includes the following modules: DC15V power supply, power conversion module, VCC power relay (relay module) and filter circuit, GND switch circuit and current sinking module, switch circuits for each IO pin, frequency measurement switch circuit, LDO / BG voltage measurement switch circuit and voltage follower circuit, VCC power consumption measurement switch circuit and current measurement module, data transmission & reception switch circuit, data clock switch circuit, test vector storage module, and test result processing & test START module.

[0024] The advantages of an integrated circuit package testing system should be understood as follows: ① As shown in the figure, the simplified testing machine has low cost. Production capacity only requires washing the board, installing components, loading software, and then loading the test program, which can greatly reduce the cost of FT testing for integrated circuits; ② This device tests the chip according to the test program settings and adjusts the parameters according to the program settings to ensure that the parameters of the shipped chips are within the product specifications, thus guaranteeing the quality of the shipped integrated circuit packages; ③ It is easy to expand production capacity. For example, if the testing capacity of factory A is insufficient, an integrated circuit package testing system can be added to increase production capacity. If production is transferred from packaging factory A to packaging factory B for packaging and testing, this testing device can be provided directly for production and testing without the need to develop and debug test programs; ④ The integrated circuit package testing system is easy to maintain and has low maintenance costs. By setting up a power conversion module, main control module, relay module, test module, and chip under test (DUT), the test module includes open / short circuit test units, frequency test units, voltage test units, write / read data test units, and power consumption test units. This effectively solves the problem of inaccurate analog voltage provided by the test machine to the ADC input channel of the chip under test encountered in chip testing production. The DUT is tested according to the conditions set in the test program, and parameter deviations are adjusted according to the program settings, ensuring that the parameters of the shipped chips are within the product specifications. This guarantees the quality of shipped integrated circuit packages, improves the convenience of chip testing, and reduces the cost of integrated circuit FT testing.

[0025] Optionally, the power conversion module includes chip U2, chip U5, chip U7, capacitor C5, capacitor C6, capacitor C13, capacitor C16, and capacitor C17. One end of capacitor C5 is connected to chip U2, chip U5, and chip U7; one end of capacitor C6 is connected to chip U2; the other end of capacitor C5 is grounded; the other end of capacitor C6 is grounded; one end of capacitor C13 is connected to chip U5; the other end of capacitor C13 is grounded; one end of capacitor C16 is connected to chip U7; the other end of capacitor C16 is grounded; one end of capacitor C17 is connected to chip U7; the other end of capacitor C17 is grounded. The main control module includes an STM32F105 processing chip.

[0026] In this embodiment, as Figure 3As shown, (1) The test principle is that the IO of the chip under test is pulled high. By adding 150UA current to the GND pin of the chip under test, the IO of the chip under test is pulled low one by one. At the same time, the voltage of the GND pin is between 0.4 and 0.9V, which means the open and short circuit test is passed; (2) Specific operation process: ① The main controller sends a control command through PE6~PE10 to make PWR_SW_595_Q3 (the first test switch) high (that is, ctrl_T_os is high), closes the relay switch of the test OS, connects the main controller PA5, I_ADC module and the GND of the chip under test, and at this time the current of I_ADC module is injected into the GND pin of the chip under test. ② The main controller PE11~15 controls CH_595(2~4)_Qx (the second test switch) to close the switch between 32F105_Px (Px) and CH_x (the IO of the chip under test). First, the main controller PE11~15 controls all CH_595(2~4)_Qx to the 1 state, that is, the CH_x of the chip under test (the IO of the chip under test) is connected to the main controller 32F105_Px (Px), and 32F105_Px outputs all 1s to pull all IOs high. ③ 32F105_Px is given a 0 state one by one (that is, the IO under test is pulled low), and at the same time the main controller PA5 tests the GND voltage (that is, the open and short circuit voltage of the IO).

[0027] Optionally, such as Figure 3 As shown, the power supply operation process of the chip under test is as follows: After the external 15V DC power supply enters the power conversion module, it outputs three voltages: 5V for the system's 5V devices, 5V for the chip under test, and 3.3V for the main control chip. The main control PE6~PE10 sends a control command to make PWR_SW_595_Q0 high (i.e., ctrl_vcc is high), closing the VCC power relay (first test switch) and sending DUT_5V to the VCC pin of the chip under test. The first analog switch group includes switch K2, switch SW4, switch SW5, and I_ADC module. The common terminal of switch SW4, the common terminal of switch SW5, and the control terminal of switch K2 are connected to the power conversion module. The control terminal of switch SW4, the I_ADC module, and the normally open terminal of switch SW5 are connected to the normally open terminal of switch K2. The control terminal of switch SW5 is connected to the output terminal of the first test switch. The I_ADC module includes a chip U1, a capacitor C6, a resistor R3, a resistor R7, and a diode D6. The anode of the capacitor C6 and the diode D6, and one end of the resistor R3 are all connected to the chip U1. The cathode of the diode D6 is connected to the control terminal of the switch SW4 and one end of the resistor R7. The other end of the resistor R7 and the other end of the resistor R3 are connected to the chip U1. The normally open terminal of the switch SW4 is connected to the test switch of the main control module.

[0028] In this embodiment, as Figure 4As shown, (1) The test principle is that the frequency of the chip under test is sent to the main control PA0. The main control PA0 is set to input capture and the frequency of the chip under test is tested using the cycle test method. The output frequency of the chip under test = IC_GetFreq / 1000. In the current ordinary MCU chip (the chip under test), the internal clock frequency HSI and LSI need to be tested and adjusted (the manufacturing process affects the actual frequency and the design frequency. It is necessary to adjust the frequency to the range required by the product specification by adjusting the register of the chip under test); (2) Frequency test operation process: The main control PE11~15 controls CH_595(1)_Q0 to close the switch between the main control PA0 and the frequency pin of the chip under test and connect the main control PA0 and the frequency pin of the chip under test. The frequency test adjustment can then be performed (the frequency adjustment rules are based on the chip under test specification. This test system will write the corresponding frequency test software program according to the chip under test specification). The second analog switch group includes switch SW6. The normally open terminal of switch SW6 is connected to the output terminal of the power conversion module, the control terminal of switch SW6 is connected to the main control module, and the input terminal of switch SW6 is connected to the second test switch.

[0029] Optionally, the third analog switch group includes switch K3, capacitor C2, resistor R5, and voltage follower OP07. The common terminal of switch K3 is connected to the main control module. The normally open terminal of switch K3 is connected to one end of resistor R5 and the output terminal of voltage follower OP07. The control terminal of switch K3 is connected to the second test switch. The other end of resistor R5 is connected to the positive output terminal of voltage follower OP07. Capacitor C2 is connected in parallel between the positive input terminal and the negative output terminal of voltage follower OP07. The normally closed terminal of switch K3 is used to connect to the Tic terminal block. The Tic_GND pin of the Tic terminal block is used to measure the GND pin of the chip under test and to correct the reference voltage measurement value when testing the reference. The normally open terminal of switch K3 is connected to the Tic_MV pin of the Tic terminal block.

[0030] In this embodiment, as Figure 5As shown, the fourth analog switch group includes switch K4, switch SW7, capacitors C1, C3, C4, C7, C8, resistors R8, R9, R10, R11, and a current sensing amplifier. The input terminal of switch SW7 is connected to the second test switch, the normally closed terminal of switch SW7 is connected to the output terminal of the power conversion module, the control terminal of switch SW7 is connected to one end of capacitor C4, one end of capacitor C1, one end of resistor R8, and the current sensing amplifier, and the other end of resistor R8 is connected to one end of capacitor C3. The circuit consists of a terminal, a stationary contact of switch K4, and a current sensing amplifier. The moving contact of switch K4 is connected to the chip under test. The control terminal of switch K4 is connected to the second test switch. The other end of capacitor C1 is connected to the other end of capacitor C3 and grounded. Resistor R9 and one end of capacitor C8 are connected to the current sensing amplifier. The other end of capacitor C8 is connected to the current sensing amplifier and grounded. One end of resistor R10 is connected to one end of resistor R10 and capacitor C7. The other end of resistor R11 is connected to the main control module. The other end of resistor R10 is connected to the current sensing amplifier. The SW7 switch includes a chip U47 of model TS5A3160DBVR, and the current sensing amplifier includes a chip U49 of model INA190A31DCKR.

[0031] It should be noted that (1) the test principle is that the output voltage of the chip under test is sent to the main control PA1. The main control PA1 is set to ADC input mode and the output voltage of the chip under test is measured by ADC sampling. The output voltage of the chip under test = ADC_GetValue(ADC_Ch1)*3.3 / 4096. In the current ordinary MCU chip (the chip under test) LDO / BG / VREF and other voltage modules, testing and adjustment are required (the manufacturing process affects the actual output voltage of each voltage module inside the chip under test, and the deviation from the design power supply is relatively large, so production testing is required to adjust it to the range required by the product specification); (2) voltage test operation process: the main control PE11~15 controls CH_595(1)_Q1 to close the switch between the main control PA1 and the voltage output pin of the chip under test, that is, to connect the main control PA1 and the voltage output pin of the chip under test, and then the voltage test adjustment can be performed (the voltage adjustment rules are based on the chip under test specification, and this test system will write the corresponding voltage test software program according to the chip under test specification).

[0032] like Figure 6As shown, in the power consumption test of the chip under test, (1) the test principle is that the VCC of the chip under test is connected to the power conversion module through the current test module (current sensing amplifier). The main controller PB0 is set to ADC input mode and the voltage of the output PIN of INA190A3IDCKR is measured by ADC sampling. The power consumption is calculated as (ADC_GetValue(ADC_Ch8)*3.3 / 4096) / 10 ohm resistor (resistance in series in VCC)*1000 (power consumption is converted to milliampere unit mA); (2) power consumption test operation process: ① The main controller PE11~15 controls CH_595(1)_Q5 to make the VCC voltage of the chip under test pass through the INA190A3IDCKR (IN+ and IN-, 10 ohm resistor is connected between IN+ and IN-) through the current test module to the voltage conversion module DUT_5V. ② The main controller PE6~PE10 sends a control command to make PWR_SW_595_Q0 low level (i.e., ctrl_vcc low level), and the VCC power relay (first test switch) is disconnected, so that the VCC voltage of the chip under test has only one path from the current test module switch through INA190A3IDCKR (IN+ and IN-, with a 10-ohm resistor connected between IN+ and IN-) to the voltage conversion module DUT_5V; ③ The main controller PB0 tests the voltage of the output PIN of INA190A3IDCKR and then calculates it into current (i.e., chip power consumption). The calculation formula is (ADC_GetValue(ADC_Ch8)*3.3 / 4096) / 10-ohm resistor (resistance in series with VCC)*1000 (power consumption converted to milliamperes mA).

[0033] like Figure 9As shown, switch K4 is switch U110. The power consumption test unit includes chip U47, chip U49, resistors R21, R22, R23, R24, R25, and R26, capacitors C50, C51, C52, C53, and C123, diode D6, and MOSFET Q4. Chip U47 corresponds to switch SW7. One end of capacitor C124 is connected to pin 5 of chip U47, and the other end of capacitor C124... Grounded, pin 1 of chip U47 is connected to the main control module (pin TEST_VCC), pin 6 of chip U47 is connected to the first test switch (PWR_M_UA), one end of capacitor C52 and resistor R21, and one end of capacitor C50 are connected to pin 4 (COM) of chip U47 and pin 4 (IN+) of chip U49, one end of resistor R23 is connected to pin 5 (DUT_5V) of chip U47, and the other end of resistor R23 is connected to one end of capacitor C53 and chip U49. Pin 3 (VS) of U49 is connected. The other end of capacitor C53 is connected to pins 1 (GND) and 2 (REF) of chip U49. One end of resistor R24 ​​is connected to pin 6 (OUT) of chip U49. The other end of resistor R24 ​​is connected to one end of capacitor C54 and one end of resistor R25. The other end of capacitor C54 is grounded. The other end of resistor R25 is connected to the second test switch (CH23). The other end of capacitor C50 is connected to one end of capacitor C51 and grounded. The other end of capacitor C51 is connected to the other end of resistor R21, pin 5 (IN-) of chip U49, and port 4 of switch U110. Resistor R22 is connected to port 1 of switch U110 and the cathode of diode D6. The anode of diode D6 is connected to port 2 of switch U110 and the drain of MOSFET Q4. The gate of MOSFET Q4 is connected to one end of resistor R26 and the first test switch (PWR_M_UA). The other end of resistor R26 is connected to the source of MOSFET Q4 and grounded.

[0034] Specifically, such as Figure 5 and Figure 10 As shown, the test power supply includes a voltage follower OP07CDR, capacitor C55, resistor R27, switch U51, resistor R28, diode D7, resistor R29, and MOSFET Q5. Switch K3 corresponds to switch U51. The positive input terminal of voltage follower OP07CDR is connected to one end of capacitor C55 and TIC_VREF, and the other end of capacitor C55 is grounded. Resistor R27 is connected to voltage follower OP07CDR and port 1 of switch 1C05. Resistor R28 is connected to port 4 of switch U51 and the cathode of diode D7. The anode of diode D7 is connected to pin 3 of switch U51 and the drain of MOSFET Q5. The gate of MOSFET Q5 is connected to one end of resistor R29, and the source of MOSFET Q5 is connected to the other end of resistor R29 and grounded.

[0035] Specifically, in the serial communication between the chip under test (DUT) and the main controller (module), the DUT's data pin (SDA) and clock pin (SCK) are connected to the main controller's PA2 (transmit data and receive data) and PA3 (transmit clock), respectively. The main controller's PA6 controls the data flow direction (PA6 is at level 0 when the main controller is transmitting data, and at level 1 when the main controller is receiving data). According to the timing requirements of the DUT's data reception and output, the main controller transmits and receives data bit by bit (i.e., transmits 1 bit at a time, and the data is synchronized with the clock). For the occurrence of the timing format is the data packet clock format); the main control PE11~15 controls the CH_595(1)_Q2 and CH_595(1)_Q3 switches to be turned on, so that the data pin (SDA) and clock pin (SCK) of the chip under test are connected to the main control PA2 (send data and receive data) and PA3 (send clock) respectively. The main control PA6 controls the direction of data flow (PA6 is at 0 level when the main control sends data, and at 1 level when the main control receives data), so as to realize the operation of the data clock pin of the chip under test and the main control.

[0036] The main controller sends commands and other operation data to the chip under test according to the timing requirements of the chip under test, and adjusts the data transmission and reception format of the test system. Auxiliary test circuit module (same as the serial port data transmission and reception format above): The auxiliary test adds auxiliary signal transmission and reception on the basis of the serial port data transmission and reception mode above. The operation mode is as follows: the main controller PE11~15 controls CH_595(1)_Q4 to close the auxiliary test switch, so that the auxiliary test PIN of the chip under test is connected to the main controller PA4 (PA4 is the auxiliary data transmission and reception). The main controller PA7 controls the direction of the auxiliary data flow (PA7 is at 0 level when the main controller sends data, and PA7 is at 1 level when the main controller receives data). If the timing requirements of the main controller PA2 (serial port data transmission and reception), PA3 (transmission clock), and PA4 (auxiliary data transmission and reception) are based on the requirements of the chip under test, then only the timing software program of this test system needs to be modified.

[0037] Specifically, the data output display module can be an LCD module. The LCD module in this system is used to display data during the testing process (such as test voltage, frequency, and adjustment values, which are displayed on the LCD for confirmation during debugging). The main controller operates the LCD according to the LCD signal protocol. The test program storage module mainly uses a W25X memory. The main controller's PD4~7 pins are connected to the W25X signal pins. The main controller writes to and reads from the W25X memory according to the W25X operation timing. This is mainly used when a user program needs to be written to the chip under test during testing. The test system stores the user program in the W25X. When a user program needs to be written, the main controller reads the program from the W25X and writes it to the chip under test's storage module via the serial port.

[0038] The test system involves sending test results to a robotic arm (sorter) after the test. Following the test, the main controller sends the results back to the robotic arm according to its timing format requirements. Upon receiving the results, the robotic arm sorts the tested chip into the designated loading tube based on the BIN signal and sends an instruction to the test system to test the next chip. The test system software operates based on a hardware module architecture and consists of: STM32F105 system library files (official ST32F105 library files), LCD library files, Keil v5.36 (required development environment), and the test system software program. The main test program serves as the entry point for the entire test system. It loads all library file names and various test subroutine modules, including: library files, main program entry point, module initialization functions, test program functions, and a test completion and BIN sorting function.

[0039] In one feasible implementation, the testing platforms currently available in small and medium-sized packaging plants are relatively basic and cannot meet the testing needs of customers' products. This necessitates outsourcing product testing to other testing plants after packaging, which impacts delivery time (poor real-time performance). Secondly, even when a required testing platform is available within the plant, factory engineers still need to develop test programs or transfer the testing platform. Misunderstandings of customer product information during this process can lead to product quality issues. Integrated circuit package testing systems can solve this production problem. Engineers from chip design companies can configure the test programs on this system and provide them to the packaging and testing plant. The plant only needs to connect this system to a robotic arm to begin production testing, eliminating the need for factory engineers to develop test programs. This solves the problem of insufficient or no testing platforms for finished integrated circuit packages.

[0040] For maintenance, this testing system can be easily sent from the packaging and testing plant to the chip design company's engineers for inspection. If a signal needs replacement, the chip design company's engineer can simply download the program for the product model to be manufactured into the system (or send the debugged program to the factory for the factory engineer to download), simplifying maintenance, repairs, and production model changes. Compared to factories lacking testing platforms and production capacity, which cannot perform packaged product testing before shipping, this testing system can test and adjust parameter deviations caused by packaging stress to bring the product within specifications, ensuring product quality.

[0041] In one feasible implementation, product testing and processing is also a significant expense for chip design companies. (Testing costs are typically calculated based on the hourly rate of the testing platform used. For example, a low-end S100 testing machine from Taiwan's Jiuyuan, with 128 test channels (suitable for packaged product testing), costs NT$50 per hour. If each chip is tested for 3 seconds, the hourly capacity is 1200 chips, resulting in a testing cost of approximately 4 cents per chip. This is a very high cost for currently mass-market consumer chips. If this testing system is used, the hourly rate is NT$20, and the same hourly capacity would only cost 1.6 cents per chip.) The hourly rate of testing machines mainly depends on the price of the testing platform. A low-end S100 testing machine from Taiwan's Jiuyuan costs approximately NT$200,000, while the hardware and software of this testing system cost only NT$1,000. This huge price difference is the key difference in hourly production costs. The advantage of the test machine platform lies in wafer-level testing, which can test multiple chips simultaneously (that is, multiple chips can be tested in parallel at one time, such as 32 or 64 chips at the same time. Although the machine is expensive, the high throughput due to the large number of chips tested can spread the cost).

[0042] In one feasible implementation, if production needs to increase capacity, simply provide the factory with a few more of this test system units for online testing and production. If the packaging and testing factory is changed, the test system can be retrieved and given to the packaging and testing factory that needs it. There is no need for repetitive work such as developing programs based on the factory's testing platform when changing factories, which increases capacity and the convenience of production transfer.

[0043] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.

[0044] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0045] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.

Claims

1. A test system for testing finished integrated circuit packages, characterized in that, The testing system includes a power conversion module, a main control module, a relay module, a test module, and a chip under test. The power conversion module, the test module, and the relay module are all connected to the main control module. The power conversion module and the chip under test are all connected to the relay module. The chip under test is connected to the test module. The relay module includes multiple analog switch groups. The test module includes an open / short circuit test unit, a frequency test unit, a voltage test unit, a write / read data test unit, and a power consumption test unit. The open / short circuit test unit is used to close the IO pin of the chip under test with the first test switch of the main control module to obtain the open / short circuit test result of whether the GND voltage of the chip under test meets the open / short circuit range. After the open / short circuit test result is passed, the main control module sends a first control command of the first level to the input terminal of the first analog switch group to connect the VCC pin of the chip under test. The frequency testing unit is used to receive a second control command of the first level sent by the main control module to the second analog switch group. The second analog switch group between the main control module and the frequency pin of the chip under test is closed to test and adjust the frequency, and to obtain a frequency test result to determine whether it conforms to the frequency range. The voltage testing unit is used to close the third analog switch group between the main control module and the voltage output pin of the chip under test after the frequency test result passes, so as to test the adjustment voltage and obtain the voltage test result to determine whether it meets the voltage range. The write-read data test unit is used to send clock data of the first level to the test module after the voltage test result is passed. The data pin and clock pin of the chip under test are respectively connected to the main control module, and write-read data operations are performed on the storage unit of the chip under test to obtain the write-read data test result. The power consumption test unit is used to, after the write and read data test results pass, send a second level control to the fourth analog switch group to disconnect the connection between the VCC pin of the chip under test and the power conversion module. The main control module tests the output voltage of the current sensing amplifier connected to the fourth analog switch group and calculates the current corresponding to the output voltage to obtain the power consumption test results to determine whether it meets the voltage range. The main control module controls the first test switch to send a second level according to the power consumption test result to disconnect the second test switch between the power conversion module, the VCC pin of the chip under test and the main control module, and the VCC pin of the chip under test is powered off to end the test.

2. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The test system also includes a serial communication module and an auxiliary test module. The serial communication module is used to connect the data pin and clock pin of the chip under test to the main control module respectively. The main control module controls the data flow direction to send and receive data bit by bit according to the timing requirements of the received and output data of the chip under test. The auxiliary test module is used to control the connection between the auxiliary test of the chip under test and the main control module, and to control the direction of the auxiliary data flow.

3. The test system for testing finished integrated circuit packages according to claim 2, characterized in that, The power conversion module includes chip U2, chip U5, chip U7, capacitor C5, capacitor C6, capacitor C13, capacitor C16, and capacitor C17. One end of capacitor C5 is connected to chip U2, chip U5, and chip U7. One end of capacitor C6 is connected to chip U2, and the other end of capacitor C5 is grounded. The other end of capacitor C6 is grounded. One end of capacitor C13 is connected to chip U5, and the other end of capacitor C13 is grounded. One end of capacitor C16 is connected to chip U7, and the other end of capacitor C16 is grounded. One end of capacitor C17 is connected to chip U7, and the other end of capacitor C17 is grounded.

4. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The testing system also includes a data output display module and a test program storage module. Both the data output display module and the test program storage module are connected to the main control module. The data output display module is used to display test data, and the test program storage module is used to write user programs to the chip under test and store the user programs.

5. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The first analog switch group includes switch K2, switch SW4, switch SW5 and I_ADC module. The common terminal of switch SW4, the common terminal of switch SW5 and the control terminal of switch K2 are connected to the power conversion module. The control terminal of switch SW4, I_ADC module and normally open terminal of switch SW5 are connected to the normally open terminal of switch K2. The control terminal of switch SW5 is connected to the output terminal of the first test switch. The I_ADC module includes a chip U1, a capacitor C6, a resistor R3, a resistor R7, and a diode D6. The anode of the capacitor C6 and the diode D6, and one end of the resistor R3 are all connected to the chip U1. The cathode of the diode D6 is connected to the control terminal of the switch SW4 and one end of the resistor R7. The other end of the resistor R7 and the other end of the resistor R3 are connected to the chip U1. The normally open terminal of the switch SW4 is connected to the test switch of the main control module.

6. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The second analog switch group includes switch SW6. The normally open terminal of switch SW6 is connected to the output terminal of the power conversion module, the control terminal of switch SW6 is connected to the main control module, and the input terminal of switch SW6 is connected to the second test switch.

7. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The third analog switch group includes switch K3, capacitor C2, resistor R5, and voltage follower OP07. The common terminal of switch K3 is connected to the main control module. The normally open terminal of switch K3 is connected to one end of resistor R5 and the output terminal of voltage follower OP07. The control terminal of switch K3 is connected to the second test switch. The other end of resistor R5 is connected to the positive output terminal of voltage follower OP07. Capacitor C2 is connected in parallel between the positive input terminal and the negative output terminal of voltage follower OP07. The normally closed terminal of switch K3 is used to connect to the Tic terminal block. The Tic_GND pin of the Tic terminal block is used to measure the GND pin of the chip under test and to correct the reference voltage measurement value when testing the reference. The normally open terminal of switch K3 is connected to the Tic_MV pin of the Tic terminal block.

8. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The fourth analog switch group includes switch K4, switch SW7, capacitors C1, C3, C4, C7, C8, resistors R8, R9, R10, R11, and a current sensing amplifier. The input terminal of switch SW7 is connected to the second test switch, the normally closed terminal of switch SW7 is connected to the output terminal of the power conversion module, the control terminal of switch SW7 is connected to one end of capacitor C4, one end of capacitor C1, one end of resistor R8, and the current sensing amplifier, the other end of resistor R8 is connected to one end of capacitor C3, the stationary contact of switch K4, and the current sensing amplifier, the moving contact of switch K4 is connected to the chip under test, the control terminal of switch K4 is connected to the second test switch, the other end of capacitor C1 is connected to the other end of capacitor C3 and grounded, one end of resistor R9 and one end of capacitor C8 are connected to the current sensing amplifier, the other end of capacitor C8 is connected to the current sensing amplifier and grounded, one end of resistor R10 is connected to one end of resistor R10 and one end of capacitor C7, the other end of resistor R11 is connected to the main control module, and the other end of resistor R10 is connected to the current sensing amplifier.

9. The test system for testing finished integrated circuit packages according to claim 8, characterized in that, The SW7 switch includes a chip U47 with model number TS5A3160DBVR, and the current sensing amplifier includes a chip U49 with model number INA190A31DCKR.

10. The test system for testing finished integrated circuit packages according to claim 1, characterized in that, The testing system also includes multiple test power supplies and a robotic arm. The multiple test power supplies are connected to the power conversion module. Each test power supply includes a linear regulator of model SY6345AAC, multiple resistors, and multiple capacitors. The robotic arm is connected to the main control module. The robotic arm is used to receive the test results sent by the main control module. After receiving the test results, the robotic arm places the tested chip into the designated loading tube according to the result BIN signal and sends the next test instruction to the test system. The test results include at least one of the open / short circuit test results, the frequency test results, the voltage test results, the write / read data test results, or the power consumption test results.

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