Battery unit voltage difference detection circuit and method for battery monitoring chip

Abstract

The invention provides a battery unit voltage difference detection circuit and method for a battery monitoring chip, which can be applied to the technical field of batteries. The detection circuit comprises a multiplexer which is used for outputting a voltage signal of a first battery unit in a battery unit module in a first half period of a first control clock signal and outputting a voltage signal of a second battery unit in the battery unit module in a second half period of the first control clock signal so as to output a voltage square wave signal; the level shifter is used for separating a differential mode voltage and a common mode voltage in the voltage square wave signal to suppress interference of the common mode voltage and outputting a differential mode voltage square wave signal; the voltage peak blocking unit is used for suppressing voltage peak interference and outputting effective square wave signals in the differential mode voltage square wave signals; and the square wave demodulation amplifier module is used for carrying out fully differential chopping demodulation processing on the effective square wave signal to obtain a detection signal for representing the voltage difference of the battery unit.

Description

Technical Field

[0001] This invention relates to the field of battery technology, and in particular to a battery cell voltage difference detection circuit and method for a battery monitoring chip. Background Technology

[0002] In battery management systems, if some battery cells in a series-connected battery pack are overcharged or over-discharged, it can severely reduce the overall capacity and lifespan of the battery pack, and may also lead to safety hazards such as thermal runaway, fire, and explosion. Therefore, accurate detection of battery cell voltage differences is a key prerequisite for ensuring the reliable operation of the battery management system and improving the safety and durability of the battery pack. This places higher performance requirements on the voltage detection analog front-end architecture of the battery monitoring chip.

[0003] However, the voltage detection analog front-end architecture of existing battery monitoring chips cannot simultaneously solve the following problems: occupying a large chip area, mismatch between different channels in the architecture, high voltage front-end requires front-end calibration and the calibration validity period limits safety, and voltage difference detection accuracy is limited. Summary of the Invention

[0004] In view of the above problems, the present invention provides a battery cell voltage difference detection circuit and method for battery monitoring chips.

[0005] According to a first aspect of the present invention, a battery cell voltage difference detection circuit for a battery monitoring chip is provided, comprising:

[0006] The square wave modulation module includes a multiplexer, a level shifter, and a voltage spike blocking unit;

[0007] The aforementioned multiplexer is used to output the voltage signal of the first battery cell in the battery cell module during the first half-cycle of the first control clock signal, and to output the voltage signal of the second battery cell in the battery cell module during the second half-cycle of the first control clock signal, so as to output a voltage square wave signal under the aforementioned first control clock signal.

[0008] The aforementioned level shifter is used to separate the differential-mode voltage and common-mode voltage in the aforementioned voltage square wave signal in order to suppress common-mode voltage interference and output a differential-mode voltage square wave signal.

[0009] The voltage spike blocking unit is used to suppress voltage spike interference in the differential mode voltage square wave signal based on the on / off state of the voltage spike blocking unit, so as to output an effective square wave signal in the differential mode voltage square wave signal.

[0010] The square wave demodulation amplifier module is used to perform full differential chopping demodulation processing on the effective square wave signal output by the square wave modulation module to obtain a detection signal that characterizes the voltage difference between the first battery cell and the second battery cell.

[0011] A second aspect of the present invention provides a method for detecting the voltage difference of battery cells in a battery monitoring chip, applied to the aforementioned detection circuit, the detection circuit including a multiplexer, a level shifter, a voltage spike blocking unit, and a square wave demodulation amplifier module, and the detection method including:

[0012] Using the aforementioned multiplexer, the voltage signal of the first battery cell in the battery cell module is output during the first half-cycle of the first control clock signal, and the voltage signal of the second battery cell in the battery cell module is output during the second half-cycle of the first control clock signal, so as to output a voltage square wave signal under the aforementioned first control clock signal.

[0013] Using the aforementioned level shifter, the differential-mode voltage and common-mode voltage in the aforementioned voltage square wave signal are separated to suppress common-mode voltage interference and output a differential-mode voltage square wave signal;

[0014] Using the voltage spike blocking unit described above, based on the on / off state of the voltage spike blocking unit, voltage spike interference in the differential mode voltage square wave signal is suppressed, so as to output an effective square wave signal in the differential mode voltage square wave signal.

[0015] Using the aforementioned square wave demodulation amplifier module, the effective square wave signal is subjected to fully differential chopping demodulation processing to obtain a detection signal used to characterize the voltage difference between the first battery cell and the second battery cell.

[0016] According to the battery cell voltage difference detection circuit for a battery monitoring chip provided by the present invention, since the multiplexer outputs both differential-mode voltage and common-mode voltage, and the output common-mode voltage can cause the square wave demodulation amplifier module to malfunction or experience significant accuracy degradation, a level shifter is introduced to suppress the common-mode voltage interference. However, when the common-mode voltage jump amplitude of the input level shifter is large, it can cause a significant voltage spike in the differential-mode voltage output by the level shifter. Furthermore, the larger the input common-mode voltage jump amplitude, the longer the duration of the voltage spike in the output differential-mode voltage. Therefore, a voltage spike blocking unit is introduced to suppress voltage spike interference and output the effective square wave signal in the differential-mode voltage square wave signal based on the on / off state of the voltage spike blocking unit. Based on this, the square wave demodulation amplifier module can be used to process the effective square wave signal to obtain a detection signal characterizing the voltage difference between two battery cells, thereby improving the detection accuracy of the battery cell voltage difference. Therefore, the battery cell voltage difference detection circuit used in battery monitoring chips directly detects and amplifies the voltage difference between two battery cells without acquiring and outputting the physical quantities related to the voltage of a single battery cell. This satisfies the application requirements for high-precision acquisition of battery cell voltage differences and also realizes a new analog front-end architecture for battery monitoring chips. Attached Figure Description

[0017] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0018] Figure 1 An application scenario diagram of a battery cell voltage difference detection circuit for a battery monitoring chip according to an embodiment of the present invention is shown.

[0019] Figure 2 A schematic diagram of a voltage spike blocking unit according to an embodiment of the present invention is shown;

[0020] Figure 3 A schematic diagram of a latching switch assembly according to an embodiment of the present invention is shown;

[0021] Figure 4 A schematic diagram of a second control clock signal and its inverted control clock signal according to an embodiment of the present invention is shown;

[0022] Figure 5 A schematic diagram of a latching switch assembly in an ON state according to an embodiment of the present invention is shown;

[0023] Figure 6 A schematic diagram of a latching switch assembly in the off state according to an embodiment of the present invention is shown;

[0024] Figure 7A schematic diagram of a multiplexer according to an embodiment of the present invention is shown;

[0025] Figure 8 A schematic diagram of a square wave modulation module according to an embodiment of the present invention is shown;

[0026] Figure 9 A schematic diagram of a first control clock signal, a second control clock signal, and a third control clock signal according to an embodiment of the present invention is shown;

[0027] Figure 10 A schematic diagram of a square wave demodulation amplifier module according to an embodiment of the present invention is shown;

[0028] Figure 11 This diagram illustrates the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period I, according to an embodiment of the present invention.

[0029] Figure 12 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period II is shown according to an embodiment of the present invention.

[0030] Figure 13 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period III is shown according to an embodiment of the present invention.

[0031] Figure 14 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period IV, according to an embodiment of the present invention, is shown.

[0032] Figure 15 A flowchart of a battery cell voltage difference detection method for a battery monitoring chip according to an embodiment of the present invention is shown. Detailed Implementation

[0033] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0035] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0036] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0037] In the process of developing this invention, it was discovered that, taking lithium-ion batteries, the mainstream power battery type for electric vehicles, as an example, to ensure the user experience of electric vehicle users, the power battery pack must undergo regular equalization maintenance. A well-maintained battery pack should not allow excessive voltage differences between battery cells; these differences are typically on the order of several millivolts, and rarely reach the order of tens of millivolts. Therefore, accurate detection of the voltage difference between battery cells to avoid excessive voltage differences is crucial for ensuring the reliable operation of the battery management system and improving battery pack safety.

[0038] Therefore, in order to manage such a large number of battery cells, the mainstream BMS (Battery Management System) used in electric vehicles is usually chip-based and adopts a master-slave architecture, that is, after the battery cells are grouped, they are monitored in real time by their respective corresponding battery monitor integrated chip (BMIC).

[0039] The simplest and most direct structure for the voltage detection analog front-end architecture of a battery monitoring chip is a parallel architecture where the voltage of each battery cell is detected independently; the most commonly used architecture is an analog-to-digital converter multiplexing architecture formed by cascading "high voltage front-end - analog-to-digital converter".

[0040] However, the multi-channel parallel sampling architecture requires multiple analog-to-digital converters, occupying a large chip area. Furthermore, due to the influence of chip manufacturing processes, the internal device parameters of the voltage detection circuits in each channel cannot be completely consistent, resulting in channel matching issues. The analog-to-digital converter multiplexing architecture requires front-end calibration of the high-voltage front end, and there is a calibration validity period, which limits system safety. The architecture using passive modules to process the voltage difference of battery cells is affected by the non-ideal effects of switching MOS (Metal-Oxide-Semiconductor) transistors (such as charge injection effect and leakage current effect). In addition, the analog-to-digital converter in the subsequent stage of this architecture requires additional driving circuits, but the driving circuits themselves introduce noise, which limits the detection accuracy.

[0041] It is evident that the existing voltage detection analog front-end architecture described above cannot simultaneously solve some key issues, thus limiting the accuracy of voltage difference detection.

[0042] Therefore, embodiments of the present invention provide a battery cell voltage difference detection circuit for a battery monitoring chip, which can take into account the requirements of small chip area, high channel matching, and high precision for long-term monitoring.

[0043] Figure 1 A schematic diagram of a battery cell voltage difference detection circuit for a battery monitoring chip according to an embodiment of the present invention is shown.

[0044] like Figure 1 As shown, the battery cell voltage difference detection circuit 100 for the battery monitoring chip includes a square wave modulation module 110 and a square wave demodulation amplifier module 120. The square wave modulation module 110 includes a multiplexer 111, a level shifter 112, and a voltage spike blocking unit 113.

[0045] In one embodiment, the battery cell voltage difference detection circuit 100 for the battery monitoring chip is disposed on the battery monitoring chip. The battery cell module 130 includes a plurality of battery cells connected in series, and the battery cell module 130 is electrically connected to the multiplexer 111. The battery cell voltage difference is used to characterize the difference in differential mode voltage between two battery cells, and the differential mode voltage is used to characterize the battery cell voltage, which refers to the voltage difference between the positive and negative terminals of the battery cell.

[0046] Based on this, the multiplexer 111 is used to select two battery cells from a plurality of battery cells in the battery cell module 130, so as to detect the battery cell voltage difference between the two battery cells by the battery cell voltage difference detection circuit 100 for the battery monitoring chip.

[0047] In one embodiment, the two selected battery cells in the battery cell module 130 can be a first battery cell and a second battery cell, wherein the first battery cell and the second battery cell are two different battery cells arbitrarily selected from the battery cell module 130.

[0048] Since the voltage difference of the battery cells needs to be detected, the multiplexer 111 can be used to output the voltage signal of the first battery cell in the battery cell module during the first half-cycle of the first control clock signal, and output the voltage signal of the second battery cell in the battery cell module during the second half-cycle of the first control clock signal, so as to output a voltage square wave signal under the first control clock signal.

[0049] In one embodiment, the multiplexer, as a selection device, has multiple parallel channels, and the first control clock signal is used to control the on and off of each channel in the multiplexer.

[0050] In one embodiment, since the multiplexer outputs the voltage signal of the first battery cell in the first half-cycle of the first control clock signal and outputs the voltage signal of the second battery cell in the battery cell module in the second half-cycle of the first control clock signal, the first half-cycle of one cycle of the voltage square wave signal is the voltage signal of the first battery cell and the second half-cycle is the voltage signal of the second battery cell.

[0051] In one embodiment, the spectrum of the voltage difference signal between the first battery cell and the second battery cell before the input multiplexer needs to be lower than half the frequency of the first control clock signal to ensure that there is no spectral aliasing.

[0052] In one embodiment, the battery cell module includes multiple battery cells connected in series. Since the battery cell voltage difference is detected, the total voltage of the battery cell module increases with the number of cells, that is, the battery cell module has voltage stacking characteristics. Therefore, the multiplexer 111 can be a high voltage multiplexer to reduce the interference of non-sampling channels on sampling accuracy and meet safety protection requirements.

[0053] According to an embodiment of the present invention, the output of the multiplexer 111 outputs not only the differential mode voltage of the battery cell but also the common mode voltage of the battery cell, and the output common mode voltage affects the operation of the square wave demodulation amplifier module 120.

[0054] For example, the battery cell module 130 can be composed of multiple battery cells connected in series. Each battery monitoring chip is responsible for detecting up to 12 battery cells in the battery cell module. Based on this, there may be a voltage difference of tens of volts between the two selected battery cells, which may cause the common-mode voltage jump of the multiplexer output to cause the square wave demodulation amplifier module to malfunction or significantly deteriorate in accuracy.

[0055] Therefore, the voltage signal of the first or second battery cell output by the multiplexer 111 includes two components: the differential-mode voltage and the common-mode voltage of the corresponding battery cell.

[0056] In one embodiment, both the differential-mode voltage and the common-mode voltage are output in square wave form, with the edges of the common-mode voltage square wave aligned with the edges of the differential-mode voltage square wave.

[0057] In this design, the differential-mode voltage square wave is the effective transmission component, while the common-mode voltage square wave is the interference component. The common-mode voltage is used to characterize the average voltage of the positive and negative electrodes of the battery cell.

[0058] Based on the above, the common-mode voltage in the voltage signal output by the multiplexer 111 will affect the square wave demodulation amplifier module 120. Therefore, the level shifter 112 set after the multiplexer 111 can be used to separate the differential-mode voltage and the common-mode voltage in the voltage signal output by the multiplexer 111 in order to suppress common-mode voltage interference and output a differential-mode voltage square wave signal.

[0059] Specifically, the common-mode voltage in the voltage signal input to the level shifter 112 will not be output from the level shifter 112, while the differential-mode voltage in the voltage signal will be output from the level shifter 112, so as to avoid the common-mode voltage square wave output by the multiplexer 111 from affecting the square wave demodulation amplifier module 120, thereby affecting the accuracy of the battery cell voltage difference detection.

[0060] In one embodiment, the first half of a cycle of the differential mode voltage square wave signal is the differential mode voltage of the first battery cell, and the second half of the cycle is the differential mode voltage of the second battery cell.

[0061] According to an embodiment of the present invention, when the common-mode voltage jump amplitude input to the level shifter 112 is large, obvious voltage spikes will be generated in the differential-mode voltage square wave signal output by the level shifter. Furthermore, the larger the input common-mode voltage jump amplitude, the longer the voltage spikes in the differential-mode voltage square wave signal output by the level shifter last.

[0062] In one embodiment, if the amplitude of the input common-mode voltage jump is greater than a preset amplitude, a voltage spike will appear in the differential-mode voltage square wave signal output by the level shifter. For example, the preset amplitude can be 10V.

[0063] Because the voltage spikes in the differential mode voltage square wave signal affect the square wave demodulation amplifier module 120, the accuracy of the battery cell voltage difference between the first battery cell and the second battery cell represented by the detection signal output by the square wave demodulation amplifier module 120 is poor.

[0064] Based on the above, the voltage spike blocking unit 113 provided after the level shifter 112 can be used to suppress voltage spike interference in the differential mode voltage square wave signal based on the on / off state of the voltage spike blocking unit 113, so as to output the effective square wave signal in the differential mode voltage square wave signal.

[0065] Specifically, the voltage spike blocking unit 113 can suppress voltage spike interference in the differential mode voltage square wave signal by blocking voltage spikes in the differential mode voltage square wave signal, and the voltage spike blocking unit 113 can output the effective square wave signal in the differential mode voltage square wave signal by allowing the effective square wave signal in the differential mode voltage square wave signal to pass through.

[0066] Among them, the effective square wave signal can characterize the signal in the differential mode voltage square wave signal except for the voltage spike portion.

[0067] Based on the above, the square wave modulation module 110 can be used to modulate the voltage signals of any two different battery cells in the battery cell module 130 to output the effective square wave signal in the differential mode voltage square wave signal.

[0068] In one embodiment, the differential mode voltage of the first half-cycle of an effective square wave signal is equal to the voltage of the first battery cell, and the differential mode voltage of the second half-cycle is equal to the voltage of the second battery cell. That is, the top and bottom of the effective square wave signal correspond to the voltages of the first and second battery cells, respectively. This effective square wave signal can be processed by the square wave demodulation amplifier module.

[0069] According to an embodiment of the present invention, the square wave demodulation amplifier module 120 can be used to perform fully differential chopping demodulation processing on the effective square wave signal output by the square wave modulation module 110 to obtain a detection signal for characterizing the voltage difference between the first battery cell and the second battery cell.

[0070] In one embodiment, the fully differential chopper demodulation process can specifically be characterized as differential amplification of adjacent signal portions located at the top and bottom of the effective square wave signal.

[0071] The voltage difference represented by the adjacent signal portions at the top and bottom of the effective square wave signal characterizes the voltage difference between the first and second battery cells. The voltage value represented by the detection signal is a preset multiple of the voltage difference between the first and second battery cells.

[0072] According to an embodiment of the present invention, since the multiplexer outputs both differential-mode and common-mode voltages, and the output common-mode voltage can cause the square wave demodulation amplifier module to malfunction or experience significant accuracy degradation, a level shifter is introduced to suppress the common-mode voltage interference. However, when the common-mode voltage jump amplitude of the input level shifter is large, it can cause a significant voltage spike in the differential-mode voltage output by the level shifter. Furthermore, the larger the input common-mode voltage jump amplitude, the longer the duration of the voltage spike in the output differential-mode voltage. Therefore, a voltage spike blocking unit is introduced to suppress voltage spike interference and output the effective square wave signal in the differential-mode voltage square wave signal based on the on / off state of the voltage spike blocking unit. Based on this, the square wave demodulation amplifier module can be used to process the effective square wave signal to obtain a detection signal characterizing the voltage difference between two battery cells, thereby improving the detection accuracy of the battery cell voltage difference. Therefore, the battery cell voltage difference detection circuit used in battery monitoring chips directly detects and amplifies the voltage difference between two battery cells without acquiring and outputting the physical quantities related to the voltage of a single battery cell. This satisfies the application requirements for high-precision acquisition of battery cell voltage differences and also realizes a new analog front-end architecture for battery monitoring chips.

[0073] According to an embodiment of the present invention, the voltage spike blocking unit includes: a plurality of latching switch assemblies connected in series to the positive output terminal of the level shifter, and a plurality of latching switch assemblies connected in series to the negative output terminal of the level shifter.

[0074] Figure 2 A schematic diagram of a voltage spike blocking unit according to an embodiment of the present invention is shown. Figure 2 As shown, the voltage spike blocking unit 113 may include multiple series-connected latching switch assemblies electrically connected to the positive output terminal of the level shifter 112, such as latching switch assembly 1, latching switch assembly 2, ..., latching switch assembly N connected in series to the positive output terminal "+" of the level shifter; the voltage spike blocking unit 113 may also include multiple series-connected latching switch assemblies electrically connected to the negative output terminal of the level shifter 112, such as latching switch assembly 1, latching switch assembly 2, ..., latching switch assembly N connected in series to the negative output terminal "-" of the level shifter. Wherein, N is an integer greater than 1.

[0075] In one embodiment, the voltage spike blocking unit 113 includes two parallel branches, each branch including a plurality of latching switch assemblies connected in series, and the number of latching switch assemblies connected in series in the two branches is the same.

[0076] In one embodiment, the on / off state of the voltage spike blocking unit is determined by the on / off state of the latching switch assembly. Specifically, the on / off states of each latching switch assembly in the voltage spike blocking unit remain consistent.

[0077] Specifically, when multiple latching switch components in the voltage spike blocking unit are in the on state, the voltage spike blocking unit is in the on state; when multiple latching switch components in the voltage spike blocking unit are in the off state, the voltage spike blocking unit is in the off state.

[0078] In one embodiment, the second control clock signal characterizes a control signal used to control the on / off state of each latching switch assembly in the voltage spike blocking unit.

[0079] Based on the above, the voltage spike blocking unit can be used to block voltage spikes in the differential voltage square wave signal and output an effective square wave signal based on the on / off state of each latching switch component under the second control clock signal.

[0080] Specifically, when all latching switch components are in the off state, during the period when voltage spikes occur in the differential mode voltage square wave signal input to the voltage spike blocking unit, the voltage spike blocking unit is in the off state to suppress voltage spike interference by blocking the voltage spikes in the differential mode voltage square wave signal, thus preventing voltage spikes from affecting the square wave demodulation amplifier module. When all latching switch components are in the on state, during the period when no voltage spikes occur in the differential mode voltage square wave signal input to the voltage spike blocking unit, the voltage spike blocking unit is in the on state to output the valid square wave signal in the differential mode voltage square wave signal to the square wave demodulation amplifier module, so that the square wave demodulation amplifier module can perform battery cell voltage difference detection based on the valid square wave signal.

[0081] According to an embodiment of the present invention, since the level shifter is provided with a positive output terminal and a negative output terminal, the voltage spike blocking unit is provided with latching switch components electrically connected to the positive output terminal of the level shifter and latching switch components electrically connected to the negative output terminal of the level shifter. Based on this, the two branches of the voltage spike blocking unit use multiple latching switch components connected in series to ensure that voltage spikes in the differential mode voltage square wave signal can be sufficiently blocked when the voltage spike blocking unit is in the off state, and cannot be input to the square wave demodulation amplifier module through the voltage spike blocking unit, thereby further improving the detection accuracy of the battery cell voltage difference.

[0082] According to an embodiment of the present invention, the level shifter has a certain current driving capability, and the voltage spike blocking unit can be a passive unit. Therefore, the circuit implementation of the voltage spike blocking unit can use capacitors and MOS switches.

[0083] Figure 3 A schematic diagram of a latching switch assembly according to an embodiment of the present invention is shown.

[0084] like Figure 3 As shown, for any latching switch assembly in the voltage spike blocking unit, the latching switch assembly includes a first transistor, a second transistor, and a third transistor.

[0085] In one embodiment, the first transistor, the second transistor, and the third transistor may be PMOS (P-channel Metal-Oxide-Semiconductor Field-Effect Transistor) or NMOS (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor). Figure 3 The diagram shows the connection relationship between the first transistor, the second transistor, and the third transistor in the latching switch assembly when the first transistor, the second transistor, and the third transistor are PMOS transistors.

[0086] exist Figure 3 In this configuration, the drain of the first transistor serves as the input terminal of the second control clock signal and is electrically connected to the gate of the second transistor. The source of the first transistor serves as the input terminal of the differential mode voltage square wave signal and is electrically connected to the source of the second transistor and the source of the third transistor. The gate of the first transistor is electrically connected to the drain of the second transistor.

[0087] The input terminal of the second control clock signal is... Figure 3 The port indicated by "ON" is the input terminal for the differential mode voltage square wave signal. Figure 3 The port indicated by "VIN" shown in the diagram.

[0088] exist Figure 3 In this configuration, the drain of the second transistor serves as the input terminal of the inverted control clock signal of the second control clock signal. Specifically, the input terminal of the inverted control clock signal of the second control clock signal is... Figure 3 The "OFF" symbol shown indicates the port.

[0089] exist Figure 3 In this configuration, the gate of the third transistor is electrically connected to the drain of the second transistor, and the drain of the third transistor serves as its output terminal. The output terminal of the third transistor is... Figure 3 The port indicated by "VOUT" shown in the diagram.

[0090] In one embodiment, the latching switch assembly may further include capacitors C1 and C2, wherein capacitor C1 is disposed between the drain of the first transistor and the input terminal of the second control clock signal, and capacitor C2 is disposed between the drain of the second transistor and the input terminal of the inverting control clock signal.

[0091] According to an embodiment of the present invention, capacitor C1 is used to couple a second control clock signal, and capacitor C2 is used to couple an inverting control clock signal.

[0092] The on / off states of the first transistor and the second transistor are jointly controlled by the second control clock signal and the inverting control clock signal. The on / off state of the third transistor is controlled by the on / off states of the first transistor and the second transistor. The on / off state of the latching switch assembly is controlled by the on / off state of the third transistor.

[0093] According to an embodiment of the present invention, since both the first transistor and the second transistor are PMOS transistors and the control clock signals received by the first transistor and the second transistor are at opposite levels, the first transistor and the second transistor are in different states. Specifically, when the first transistor is turned on, the second transistor is turned off; when the first transistor is turned off, the second transistor is turned on.

[0094] According to an embodiment of the present invention, the on / off state of each latching switch component in the voltage spike blocking unit is controlled by a second control clock signal and its inverting control clock signal. Therefore, by setting the second control clock signal, when the differential-mode voltage square wave signal is in the period of voltage spike occurrence, the voltage spike blocking unit can also be turned off based on the latching switch components being in the off state, thereby blocking the voltage spike from passing through and preventing the voltage spike from being input into the square wave demodulation amplifier module and affecting the detection accuracy.

[0095] Figure 4 A schematic diagram of a second control clock signal and its inverted control clock signal according to an embodiment of the present invention is shown.

[0096] like Figure 4 As shown, the second control clock signal and its inverting control clock signal are at opposite levels. Specifically, when the second control clock signal is at a high level, the inverting control clock signal is at a low level.

[0097] exist Figure 4 In this context, the first level is used to represent a high level, and the second level is used to represent a low level.

[0098] According to an embodiment of the present invention, a latching switch assembly is configured to control a first transistor to turn on and a second transistor to turn off when a second control clock signal is at a first level and an inverting control clock signal is at a second level, and further control a third transistor to turn on based on the gate input of the third transistor being at a second level and the source input of the third transistor being at a first level, so as to output an effective square wave signal in a differential mode voltage square wave signal.

[0099] The time period during which the second control clock signal is at the first level is used to characterize the time period during which voltage spikes do not exist in the differential mode voltage square wave signal.

[0100] Figure 5 A schematic diagram of a latching switch assembly in the ON state according to an embodiment of the present invention is shown.

[0101] like Figure 5 As shown, when the second control clock signal is at the first level (high level), the inverting control clock signal is at the second level (low level). Based on this, the gate input of the first transistor is at the second level, and the gate input of the second transistor is at the first level. Therefore, the first transistor is turned on, and the second transistor is turned off.

[0102] exist Figure 5 In the case where the first transistor is turned on and the second transistor is turned off, the gate input of the third transistor is at the second level and the source input of the third transistor is at the first level. That is, the gate of the third transistor generates a voltage drop relative to its source that is equal to the amplitude of the second control clock signal jump. This voltage drop controls the third transistor to turn on, thereby putting the latching switch assembly into the on state.

[0103] Based on this, the input and output terminals of the latching switch assembly are connected, enabling it to be used to output the effective square wave signal in the differential voltage square wave signal.

[0104] According to an embodiment of the present invention, under the control of the second control clock signal, the latching switch assembly can be in the conducting state when the differential mode voltage square wave signal is in a period without voltage spikes, thereby enabling the output of the effective square wave signal in the differential mode voltage square wave signal to the square wave demodulation amplifier module, so that the square wave demodulation amplifier module can perform battery cell voltage difference detection based on the effective square wave signal.

[0105] According to an embodiment of the present invention, the latching switch assembly is further configured to control the first transistor to turn off and control the second transistor to turn on when the second control clock signal is at the second level and the inverting control clock signal is at the first level, and then control the third transistor to turn off based on the gate input of the third transistor being at the first level and the source input of the third transistor being at the second level, so as to suppress voltage spike interference in the differential mode voltage square wave signal.

[0106] The time period during which the second control clock signal is at the second level is used to characterize the time period during which voltage spikes exist in the differential mode voltage square wave signal.

[0107] Figure 6 A schematic diagram of a latching switch assembly in the off state according to an embodiment of the present invention is shown.

[0108] like Figure 6 As shown, when the second control clock signal is at the second level (low level), the inverting control clock signal is at the first level (high level). Based on this, the gate input of the first transistor is at the first level, and the gate input of the second transistor is at the second level. Therefore, the first transistor is turned off, and the second transistor is turned on.

[0109] exist Figure 6 In the case where the first transistor is off and the second transistor is on, the gate input of the third transistor is at the first level and the source input of the third transistor is at the first level, that is, the gate voltage of the third transistor is equal to the source voltage, the third transistor is off, and thus the latching switch assembly is in the off state.

[0110] Based on this, the input and output terminals of the latching switch assembly are not connected, blocking voltage spikes in the differential-mode voltage square wave signal to suppress voltage spike interference in the differential-mode voltage square wave signal.

[0111] According to an embodiment of the present invention, under the control of the second control clock signal, the latching switch assembly can be in the off state when the differential mode voltage square wave signal is in a period of voltage spike, thereby blocking the voltage spike in the differential mode voltage square wave signal from being input to the square wave demodulation amplifier module, so as to suppress voltage spike interference and avoid the voltage spike from affecting the square wave demodulation amplifier module, thereby improving the detection accuracy of the battery cell voltage difference to a certain extent.

[0112] Based on the above, a latching switch assembly is constructed using PMOS transistors. The gates and drains of the first and second transistors in the latching switch assembly are cross-connected to form a latch structure. Specifically, the connection method is as follows: Figure 3 As shown in the diagram. When the second control clock signal jumps to the first level (high level) and the inverting control clock signal jumps to the second level (low level), the latching switch component switches from the off state to the on state. When the second control clock signal jumps to the second level (low level) and the inverting control clock signal jumps to the first level (high level), the latching switch component switches from the on state to the off state.

[0113] In one embodiment, since the voltages at both outputs of the level shifter have swings ranging from nearly 0V to nearly 5V, and to ensure that the voltage spike blocking unit can function properly under both positive and negative input conditions, a switch composed of a single low-voltage MOSFET does not meet the symmetry requirement. Furthermore, the charge injection effect of a switch composed of a power MOSFET and related control circuitry during turn-off would interfere with the subsequent input capacitor. Therefore, the switch of this invention is selected as a latch structure composed of low-voltage MOSFETs, so as to meet the signal swing requirement of 0V to 5V without generating a significant charge injection effect.

[0114] According to an embodiment of the present invention, the multiplexer includes: a plurality of positive input terminals, a plurality of negative input terminals, a plurality of switching components, a positive output terminal, and a negative output terminal.

[0115] Figure 7 A schematic diagram of a multiplexer according to an embodiment of the present invention is shown.

[0116] like Figure 7 As shown, the multiplexer has multiple channels, each channel is used to electrically connect to one battery cell in the battery cell module 130, and each channel is provided with a switch assembly, which is used to control the conduction and shutdown of the channel by the opening and closing state of the switch assembly.

[0117] Specifically, for any channel in the multiplexer, the positive input terminal of the multiplexer is electrically connected to the positive terminal of the battery cell in the battery cell module, and is electrically connected to the positive output terminal via a switching assembly; the negative input terminal of the multiplexer is electrically connected to the negative terminal of the battery cell in the battery cell module, and is electrically connected to the negative output terminal via a switching assembly.

[0118] According to an embodiment of the present invention, during the process of detecting the voltage difference between battery cells using the multiplexer 111, the multiplexer 111 selects any two different battery cells in the battery cell module 130. Specifically, it can be used to... Figure 7 The first and second battery cells in the battery cell module 130 shown are examples.

[0119] In one embodiment, the switching components of each channel in the multiplexer are controlled by a first control clock signal. Specifically, the switching components in the multiplexer corresponding to the two selected battery cells are controlled by the same first control clock signal.

[0120] Based on the above, a multiplexer can be used to provide channels for each of the multiple battery cells in a battery cell module, so as to enable the channel of the first battery cell in the multiplexer during the first half-cycle of the first control clock signal, and enable the channel of the second battery cell in the multiplexer during the second half-cycle of the first control clock signal.

[0121] The channel of the first battery cell in the multiplexer is turned on to indicate that the switching component in the channel of the first battery cell in the multiplexer is turned on; the channel of the second battery cell in the multiplexer is turned on to indicate that the switching component in the channel of the second battery cell in the multiplexer is turned on.

[0122] In one embodiment, during the first half-cycle of the first control clock signal, the multiplexer can select to turn on the channel of the first battery cell, while the channels of the second battery cell and other battery cells in the multiplexer are in the off state; during the second half-cycle of the first control clock signal, the multiplexer can select to turn on the channel of the second battery cell, while the channels of the first battery cell and other battery cells in the multiplexer are in the off state.

[0123] Therefore, it can be seen that the multiplexer operates in a dual-channel alternating manner under the action of the first control clock signal.

[0124] According to an embodiment of the present invention, the multiplexer is controlled by a first control clock signal. During the first half-cycle of the first control clock signal, the channel of the first battery cell is turned on to output the voltage signal of the first battery cell. During the second half-cycle of the first control clock signal, the channel of the second battery cell is turned on to output the voltage signal of the second battery cell. Based on this, the output of the multiplexer can form a voltage square wave signal, facilitating subsequent detection of the voltage difference between the battery cells.

[0125] Based on the above, taking electric vehicles as an example, the noise current of the electric vehicle motor inverter is converted into noise voltage through the internal resistance of the battery cell, and superimposed on the voltage of the battery cell, thus interfering with voltage detection. In related technologies, external RC filters (resistors in series and capacitors in parallel) mounted on the circuit board are typically used to filter out inverter noise, which brings greater difficulty in board-level design and development and higher board-level material costs.

[0126] In the technical solution of this invention, because the internal resistance of the battery cells is small and relatively close, the amplitude of the inverter noise voltage difference between each battery cell is very small. Therefore, the differential-mode square wave amplitude obtained by the multiplexer modulation of the inverter noise voltage difference is very small and will not interfere with the detection of useful signals. Thus, this invention can filter out inverter noise through the battery cell voltage difference detection circuit inside the battery monitoring chip, thereby obtaining a battery cell voltage difference that contains no inverter noise or only a small amount of inverter noise. Based on this, this invention can save the number of resistors and capacitors on the circuit board, thereby reducing the difficulty of board-level design and development and reducing board-level material costs.

[0127] According to an embodiment of the present invention, the positive input terminal of the level shifter is electrically connected to the negative output terminal of the multiplexer, and the negative input terminal of the level shifter is electrically connected to the positive output terminal of the multiplexer; the positive input terminal of the level shifter corresponds to the negative output terminal of the level shifter, and the negative input terminal of the level shifter corresponds to the positive output terminal of the level shifter.

[0128] Figure 8 A schematic diagram of a square wave modulation module according to an embodiment of the present invention is shown.

[0129] like Figure 8 As shown, the square wave modulation module includes a multiplexer 111, a level shifter 112, and a voltage spike blocking unit 113.

[0130] exist Figure 8 In this circuit, the positive input terminal of level shifter 112 is electrically connected to the negative output terminal of multiplexer 111, and the negative input terminal of level shifter 112 is electrically connected to the positive output terminal of multiplexer 111; the positive input terminal of level shifter 112 corresponds to the negative output terminal of level shifter 112, and the negative input terminal of level shifter 112 corresponds to the positive output terminal of level shifter 112.

[0131] According to an embodiment of the present invention, the level shifter 112 can be used to extract the differential mode voltage in the voltage square wave signal, reverse the polarity of the differential mode voltage, and then attach the polarity-reversed differential mode voltage to a preset output common mode voltage according to a fixed ratio, so as to provide a stable common mode reference for the differential mode voltage square wave signal.

[0132] According to an embodiment of the present invention, the differential-mode voltage output by the level shifter is the input differential-mode voltage multiplied by a fixed ratio, and the common-mode voltage output by the level shifter is fixed and independent of the input common-mode voltage. Thus, the level shifter can appropriately scale down the input differential-mode voltage before outputting it.

[0133] The preset output common-mode voltage is used to characterize the common-mode voltage output by the level shifter.

[0134] In one embodiment, the differential voltage extracted from the voltage square wave signal by the level shifter is actually obtained through circuit calculation.

[0135] In one embodiment, the fixed ratio should remain constant as the common-mode voltage of the input level shifter varies in the range of tens of volts.

[0136] According to an embodiment of the present invention, since the subsequent square wave demodulation amplifier module has strict common-mode voltage input range requirements, if the amplitude of the common-mode voltage square wave of the voltage signal output by the multiplexer is too large, even if the differential-mode voltage square wave signal is valid, it will cause the differential-mode voltage square wave signal to be distorted or unrecognizable, making the subsequent circuit unable to function properly. Furthermore, since the common-mode voltage and differential-mode voltage output by the multiplexer are square waves with the same shape and phase, if the input capacitors in the subsequent square wave demodulation amplifier module are mismatched, the common-mode voltage square wave will be converted into differential-mode square wave current interference, mixing with the square wave current converted from the valid square wave signal, thus introducing errors. Therefore, fixing the common-mode reference ensures the normal operation of the subsequent square wave demodulation amplifier module.

[0137] Based on the above, level shifters exhibit DC offset (no frequency characteristic), meaning there is a voltage-independent DC error between the output and input of the level shifter. When a multiplexer cycles through channel conduction, as long as the multiplexer's operating conditions are stable, the DC offset of the level shifter remains consistent for each channel. Therefore, the DC offset of the level shifter can be canceled out rather than modulated.

[0138] In one embodiment, the voltage spike blocking unit 113 can be as follows: Figure 8 As shown in the image. Figure 8 Taking the voltage spike blocking unit 113, which includes four latching switch assemblies, as an example, two latching switch assemblies are respectively provided on the two branches of the voltage spike blocking unit 113.

[0139] Specifically, Figure 8 The structure of any latching switch assembly 810 in the voltage spike blocking unit 113 shown can be specifically as follows: Figure 3 As shown.

[0140] In one embodiment, the second control clock signal can be used to control the on / off state of any latching switch component 810, that is, the second control clock signal can be used to control the on / off state of the first transistor, the second transistor and the third transistor.

[0141] exist Figure 8 In this circuit, capacitors are placed between each node and GND (Ground, ground plane), specifically capacitors C3, C4, C5, C6, C7, and C8. Capacitors C3 to C8, together with the equivalent resistance of the latching switch assembly in the off state, form an RC low-pass filter, effectively blocking voltage spikes to filter out noise. Each node represents the input and output nodes of the latching switch assembly.

[0142] According to an embodiment of the present invention, the multiplexer is controlled by a first control clock signal, the voltage spike blocking unit is controlled by a second control clock signal, and the square wave demodulation amplifier module is controlled by a third control clock signal.

[0143] Figure 9 A schematic diagram of a first control clock signal, a second control clock signal, and a third control clock signal according to an embodiment of the present invention is shown.

[0144] like Figure 9 As shown, the first control clock signal, the second control clock signal, and the third control clock signal are all generated from the same base clock signal.

[0145] According to an embodiment of the present invention, the first half-cycle and the second half-cycle of the first control clock signal have the same duration; the transition time of the first control clock signal is used to characterize the switching time between the first half-cycle and the second half-cycle of the first control clock signal or the switching time between the second half-cycle and the first half-cycle of the first control clock signal.

[0146] According to an embodiment of the present invention, the transition time of the first control clock signal can also be used to characterize the moment when the first control clock signal transitions from a low level to a high level or from a high level to a low level.

[0147] In one embodiment, such as Figure 9 As shown, the first half-cycle of the first control clock signal is high, and the second half-cycle is low; similarly, the first half-cycle of the first control clock signal can also be low. The second half-cycle of the first control clock signal is high. Therefore, the high and low levels of the first and second half-cycles of the first control clock signal can be interchanged.

[0148] In one embodiment, the multiplexer can be used to switch the conduction channel of the multiplexer at the transition time of the first control clock signal, so as to switch the channel conduction between the channel of the first battery cell and the channel of the second battery cell.

[0149] In one embodiment, taking the first half-cycle of the first control clock signal as high level and the second half-cycle as low level as an example, at the moment when the first control clock signal transitions from low level to high level, the multiplexer switches from the channel that enables the second battery cell to the channel that enables the first battery cell; at the moment when the first control clock signal transitions from high level to low level, the multiplexer switches from the channel that enables the first battery cell to the channel that enables the second battery cell.

[0150] According to an embodiment of the present invention, since the voltage difference between battery cells needs to be detected, the duration of the high level and the duration of the low level in the differential voltage square wave signal should be consistent to ensure that the acquisition duration corresponding to the differential mode voltage of the first battery cell and the differential mode voltage of the second battery cell are consistent. Thus, when detecting the voltage difference between the differential mode voltage of the first battery cell and the differential mode voltage of the second battery cell, the accuracy of the battery cell voltage difference detection is ensured because the differential mode voltage of the first battery cell and the differential mode voltage of the second battery cell are time-aligned.

[0151] According to an embodiment of the present invention, the transition time of the first control clock signal is located within the time period when the second control clock signal is at the second level, and the time period when the second control clock signal is at the first level is located within the time period between two adjacent transition times in the first control clock signal; the voltage spike blocking unit is used to block voltage spikes in the differential mode voltage square wave signal caused by the channel switching of the multiplexer when the multiplexer performs channel switching.

[0152] According to an embodiment of the present invention, the common-mode voltage jump amplitude of the multiplexer output when switching the conduction channel will be large, that is, the common-mode voltage jump amplitude input to the level shifter will be large when the multiplexer switches the conduction channel, which will cause voltage spikes in the differential-mode voltage output by the level shifter.

[0153] Based on this, a voltage spike blocking unit is set after the level shifter to block voltage spikes from passing through when voltage spikes exist in the differential mode voltage output by the level shifter, and to allow the differential mode voltage signal to pass through when there are no voltage spikes in the differential mode voltage output by the level shifter.

[0154] According to an embodiment of the present invention, since the voltage spike blocking unit is turned on when the second control clock signal is at the first level (high level) and turned off when the second control clock signal is at the second level (low level), when the multiplexer switches the conduction channel, that is, when the first control clock signal is at the moment of transition, the second control clock signal should be at the second level to control the voltage spike blocking unit to turn off and thus block the voltage spike from passing through; when the multiplexer has completed the channel conduction switching, that is, when the first control clock signal is at the moment of no transition, the second control clock signal should be at the first level to control the voltage spike blocking unit to turn on and thus allow the differential mode voltage square wave signal to pass through.

[0155] According to an embodiment of the present invention, by setting the transition time of the first control clock signal to be within the time period when the second control clock signal is at the second level, and the time period when the second control clock signal is at the first level to be within the time period between two adjacent transition times in the first control clock signal, the voltage spike blocking unit is turned off to block the voltage spike when the multiplexer performs channel switching, thereby avoiding the influence of the voltage spike on the battery cell voltage difference detection.

[0156] According to an embodiment of the present invention, the transition time from the second level to the first level in the second control clock signal is aligned with the transition time of the third control clock signal of the square wave demodulation amplifier module; the transition time from the second level to the first level in the second control clock signal is used to characterize the time when the voltage spike blocking unit starts to conduct; the transition time of the third control clock signal is used to characterize the state switching time of the chopper in the square wave demodulation amplifier module.

[0157] In one embodiment, a voltage spike blocking unit is used to output the effective square wave signal in the differential mode voltage square wave signal to the square wave demodulation amplifier module when the voltage spike blocking unit is turned on.

[0158] According to an embodiment of the present invention, the square wave demodulation amplifier module includes a chopper, which is controlled by a third control clock signal. The chopper is a circuit module composed of four switches, and has two input terminals and two output terminals. By controlling the states of the switches in pairs, the two input terminals are periodically and alternately connected to the two output terminals.

[0159] In this context, chopper state switching refers to the alternating connection of two input terminals to two output terminals. For example, if input terminal A is connected to output terminal B and input terminal C is connected to output terminal D, the chopper will switch states so that input terminal A is connected to output terminal D and input terminal C is connected to output terminal B.

[0160] Based on this, the voltage spike blocking unit needs to transmit the effective square wave signal to the square wave demodulation amplifier module. Therefore, the time period in a certain cycle of the second control clock signal that is at the first level should fall within half a cycle of a certain cycle of the third control clock signal. That is, the transition moment in the third control clock signal cannot fall within the time period in a certain cycle of the second control clock signal that is at the first level.

[0161] Therefore, the transition time from the second level to the first level in the second control clock signal is set to align with the transition time of the third control clock signal, ensuring that the effective square wave signal just output by the voltage spike blocking unit can be received immediately after the chopper in the square wave demodulation amplifier module completes its state switch. Specifically, as follows... Figure 9 As shown in the image.

[0162] In one embodiment, the presence of voltage spikes in the differential-mode square wave signal output by the level shifter may cause the square wave demodulation amplifier module to be interfered with by voltage spikes when the chopper has just completed its state switch, making it unable to acquire a valid square wave signal and thus affecting voltage detection. Therefore, a voltage spike blocking unit is set after the level shifter to suppress voltage spikes.

[0163] According to an embodiment of the present invention, by setting the transition time from the second level to the first level in the second control clock signal to be aligned with the transition time of the third control clock signal of the square wave demodulation amplifier module, it is ensured that the voltage spike blocking unit transmits the effective square wave signal to the square wave demodulation amplifier module, thereby performing battery cell voltage difference detection based on the effective square wave signal.

[0164] According to an embodiment of the present invention, a square wave demodulation amplifier module includes an input capacitor, a primary transconductance amplifier, an intermediate chopper, and a secondary transconductance amplifier, wherein the intermediate chopper is disposed between the primary transconductance amplifier and the secondary transconductance amplifier.

[0165] Figure 10 A schematic diagram of a square wave demodulation amplifier module according to an embodiment of the present invention is shown.

[0166] like Figure 10 As shown, the square wave demodulation amplifier module 120 includes an input capacitor C9, an input capacitor C10, a main stage transconductance amplifier, an intermediate stage chopper, and a secondary stage transconductance amplifier.

[0167] In one embodiment, such as Figure 10 As shown, the input capacitor is electrically connected to the output terminal of the voltage spike blocking unit 113. Specifically, the positive output terminal of the voltage spike blocking unit 113 is electrically connected to the input capacitor C9, and the negative output terminal of the voltage spike blocking unit 113 is electrically connected to the input capacitor C10. Thus, the input capacitor can be used to isolate the DC voltage in the effective square wave signal, so that the DC component in the effective square wave signal will not affect the output of the square wave demodulation amplifier module.

[0168] In one embodiment, such as Figure 10 As shown, the positive input terminal of the main stage transconductance amplifier is electrically connected to the input capacitor C9, and the negative input terminal of the main stage transconductance amplifier is electrically connected to the input capacitor C10. To ensure that the flicker noise of the input transistors of the main stage transconductance amplifier is filtered out, the frequency of the first control clock signal is set to be greater than the corner frequency of the main stage transconductance amplifier. Specifically, an intermediate-stage chopper is used to modulate the flicker noise of the input transistors of the main stage transconductance amplifier to filter out the flicker noise; the secondary-stage transconductance amplifier is used to filter out the modulated flicker noise to ensure that the flicker noise can be sufficiently filtered out.

[0169] Specifically, the first control clock signal causes the multiplexer to modulate the useful DC signal into a square wave shape. The spectrum of the useful signal is shifted from DC to near the clock frequency, while the spectrum of the flicker noise of the main stage transconductance amplifier is located near the low frequency close to DC. Thus, the frequencies of the signal and noise are separated, thereby achieving the filtering out of flicker noise.

[0170] The first control clock signal and the third control clock signal have the same frequency.

[0171] According to an embodiment of the present invention, the square wave demodulation amplifier module further includes a ripple suppression loop, a feedback chopper, and a feedback capacitor. The specific connections of the components in the square wave demodulation amplifier module can be as follows: Figure 10 As shown in the image.

[0172] According to an embodiment of the present invention, since the effective square wave signal contains a DC voltage component, and this DC component can affect the square wave demodulation amplifier module, an input capacitor is provided on the input side of the square wave demodulation amplifier module to isolate the DC voltage in the effective square wave signal. Furthermore, the input transistors of the main stage transconductance amplifier exhibit flicker noise. By setting the frequency of the first control clock signal to be greater than the turning frequency of the main stage transconductance amplifier, the flicker noise of the input transistors of the main stage transconductance amplifier can be sufficiently filtered out.

[0173] Based on the above content, based on such Figure 10 The square wave demodulation amplifier module 120 shown in the diagram has a ripple suppression loop that suppresses the output ripple voltage caused by the offset of the primary transconductance amplifier. The secondary transconductance amplifier can specifically consist of one or two sub-transconductance amplifiers. To ensure the loop stability of the instrumentation amplifier, Miller compensation is required for the secondary transconductance amplifier. The compensation circuit is considered an internal circuit of the secondary transconductance amplifier and therefore not separately included in the circuit. Figure 10 As shown in the image.

[0174] Furthermore, due to the primary and secondary transconductance amplifiers in the square wave demodulation amplifier module 120, the battery cell voltage difference detection module for the battery monitoring chip of the present invention is active. That is, the present invention achieves active operation through the primary and secondary transconductance amplifiers, avoiding the influence of non-ideal effects of the switching MOSFETs on passive modules used in existing technologies. Simultaneously, the battery cell voltage difference detection module for the battery monitoring chip of the present invention can provide the current drive required by the subsequent analog-to-digital converter while realizing the detection of battery cell voltage difference, ensuring detection accuracy.

[0175] Specifically, the key reason why the non-ideal effects of MOS switches in existing technologies affect passive battery voltage difference detection modules is that the modules do not contain active circuits capable of processing signals, and the charge and energy loss caused by the non-ideal effects cannot be offset. Therefore, using a transconductance amplifier as an active circuit to build the battery cell voltage difference detection circuit can avoid the loss of charge or energy related to the signal, thereby avoiding the limitation of detection accuracy by the non-ideal effects of MOS switches.

[0176] Based on such Figure 10 The square wave demodulation amplifier module 120 shown in the diagram has a primary transconductance amplifier and a secondary transconductance amplifier forming a negative feedback loop with a feedback capacitor. The closed-loop gain is determined by the ratio of the input capacitor value to the feedback capacitor value, and it can process the input AC differential-mode voltage square wave signal while shielding common-mode interference. The closed-loop gain characterizes the amplification factor of the effective square wave signal applied to the input capacitor.

[0177] Based on such Figure 10 The square wave demodulation amplifier module 120 shown, if no level shifter is set after the multiplexer to suppress common-mode voltage, the common-mode voltage square wave will be coupled to the input terminal of the main stage transconductance amplifier by the input capacitor in the square wave demodulation amplifier module. However, since the internal circuit components of the main stage transconductance amplifier use low-voltage devices, if the voltage difference between the top and bottom of the common-mode voltage square wave exceeds 5V, it will cause the device to overvoltage. The main stage transconductance amplifier is a differential pair structure, but there is a certain degree of mismatch in the actual circuit, which will cause the input common-mode voltage square wave to be converted into differential-mode output, thus affecting the accuracy of the output detection signal. Although the input capacitor has been matched, mismatch cannot be completely avoided, so that the input common-mode voltage square wave is converted into a differential-mode current square wave through the input capacitor. This current cannot be distinguished from the differential-mode current square wave converted from the input differential-mode voltage square wave through the input capacitor, which will seriously affect the reliability of the output detection signal.

[0178] Therefore, by setting a level shifter after the multiplexer to suppress the common-mode voltage, the common-mode voltage square wave cannot be transmitted to the square wave demodulation amplifier module, thus affecting the accuracy of the output detection signal.

[0179] based on Figure 10 The battery cell voltage difference detection circuit for battery monitoring chips of the present invention uses only one differential pair (main stage transconductance amplifier), and based on the phase settings of the first control clock signal, the second control clock signal and the third control clock signal, a level shifter is set after the multiplexer to suppress common-mode voltage, and a voltage spike blocking unit is set after the level shifter to suppress voltage spikes.

[0180] According to an embodiment of the present invention, the first control clock signal, the second control clock signal, and the third control clock signal can cause the switch in the battery cell voltage difference detection circuit to periodically turn on and off, so as to... Figure 9 Taking the control clock signal shown as an example, four representative time periods within one cycle of the first control clock signal are selected, namely time period I, time period II, time period III, and time period IV.

[0181] The following example uses time periods I, II, and III, which are located in the latter half of the cycle when the first control clock signal is at a high level.

[0182] Figure 11 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period I is shown according to an embodiment of the present invention.

[0183] like Figure 11 As shown, when the first control clock signal is in the state as Figure 9 During the time period I shown, the first control clock signal jumps, and the multiplexer 111 switches to the channel that turns on the second battery cell. The selected second battery cell charges the capacitor at the input of the level shifter 112 until the input voltage is equal to the positive and negative voltages of the second battery cell. The output of the level shifter 112 increases the current drive, but the voltage output by the level shifter 112 will have a short-term voltage spike before stabilizing.

[0184] Based on this, when the first control clock signal is in such a state Figure 9 During the time period I shown, when the second control clock signal is at the second level (low level), the voltage spike blocking unit 113 is in the off state to block voltage spikes. Furthermore, the third control clock signal is not at a transition moment.

[0185] Figure 12 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period II is shown according to an embodiment of the present invention.

[0186] like Figure 12 As shown, when the first control clock signal is in the state as Figure 9 During the time period II shown, the first control clock signal does not change, and the multiplexer 111 still conducts the channel of the second battery cell. However, during this time period II, the second control clock signal is at the first level (high level), and the voltage spike blocking unit 113 is in the conducting state.

[0187] Based on this, the output of the level shifter 112 provides current drive, and the input voltage of the square wave demodulation amplifier module 120 is charged until the input voltage is equal to the steady-state voltage of the output of the level shifter 112. Furthermore, the corresponding third control clock signal changes, the chopper within the square wave demodulation amplifier module 120 switches states, and the secondary transconductance amplifier charges the output capacitor and feedback capacitor until the corresponding nodes reach their steady-state voltage.

[0188] Figure 13 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period III is shown according to an embodiment of the present invention.

[0189] like Figure 13 As shown, when the first control clock signal is in the state as Figure 9 During time period III, the first control clock signal does not change, and the multiplexer 111 remains connected to the channel of the second battery cell. However, during this time period III, the second control clock signal changes from high to low, and the voltage spike blocking unit 113 is turned off. The third control clock signal does not change.

[0190] Based on this, the first control clock signal is in time period III, and the voltage spike blocking unit 113 is in the off state to prepare for the switching of the multiplexer channel in the next stage (time period IV).

[0191] Figure 14 A schematic diagram of the operation of a battery cell voltage difference detection circuit for a battery monitoring chip during time period IV, according to an embodiment of the present invention, is shown.

[0192] like Figure 14 As shown, when the first control clock signal is in the state as Figure 9 During the time period IV shown, the first control clock signal jumps, and the multiplexer switches the conduction path. Specifically, the multiplexer switches from the channel that conducts the second battery cell to the channel that conducts the first battery cell. The selected first battery cell charges the capacitor at the input of the level shifter 112 until the input voltage is equal to the positive and negative voltages of the first battery cell. The output of the level shifter 112 increases the current drive, but the voltage output by the level shifter 112 will have a short-term voltage spike before stabilizing.

[0193] Based on this, when the first control clock signal is in such a state Figure 9 During the time period IV shown, when the second control clock signal is at the second level (low level), the voltage spike blocking unit 113 is in the off state to block voltage spikes. Furthermore, the third control clock signal is not at a transition moment.

[0194] In the first control clock signal, time period IV and time period I are functionally identical. Subsequently, the circuit operation of the battery cell voltage difference detection circuit used for the battery monitoring chip will repeat cyclically in each time period.

[0195] based on Figure 9 The first control clock signal, the second control clock signal, and the third control clock signal shown in the figure can have their high and low levels interchanged. The high and low levels of the first control clock signal and the third control clock signal can also be interchanged.

[0196] exist Figure 9 In this configuration, the frequency of the first control clock signal is one-quarter of the base clock frequency, the frequency of the second control clock signal is one-half of the base clock frequency, and the frequency of the third control clock signal is one-quarter of the base clock frequency. The midpoint of the high level in the second control clock signal is aligned with the midpoint of the high / low level in the first control clock signal, and the duration of the high / low level in the second control clock signal is half the duration of the high / low level in the first control clock signal. Figure 9 The frequency correspondence of the various control clock signals shown is merely an exemplary embodiment.

[0197] Specifically, the high-level period in the second control clock signal only needs to be within the period when the first control clock signal is at a high or low level.

[0198] The three control clock signals of this invention are a first control clock signal for the multiplexer, a second control clock signal for the voltage spike blocking unit, and a third control clock signal for the square wave demodulation amplifier module. To address the problem of differential-mode voltage spikes within the circuit, the circuit of this invention shifts the phase of the third control clock signal of the square wave demodulation amplifier module backward relative to the phase of the first control clock signal of the square wave modulation module, and correspondingly sets the phase of the second control clock signal of the voltage spike blocking unit, thereby forming a phase-shifting chopping technique to prevent voltage spikes from interfering with the square wave demodulation amplifier module.

[0199] In existing technologies, the detection circuit converts each pair of differential-mode voltages into transconductance current, and then converts the transconductance current back into voltage. Through this conversion process, the output voltage of the detection circuit is conditioned to meet the requirements of subsequent circuits or signal processing. However, the conversion process during differential-mode voltage detection introduces random noise, and the random noise introduced by detecting two differential-mode voltages cannot cancel each other out. Therefore, this invention improves the detection accuracy of the battery cell voltage difference by directly detecting and amplifying it without acquiring and outputting the voltage of a single battery cell. Thus, the technical solution of this invention can effectively cancel out the random errors introduced during the detection process. Furthermore, this cancellation not only applies to the "internal errors" introduced by the chip's internal circuitry but also to the "external errors" introduced by the battery cell ports, primarily inverter noise.

[0200] Based on the above, the battery cell voltage difference detection circuit for battery monitoring chips of the present invention adopts a transconductance amplifier with a differential pair structure to ensure that the active circuit provides sufficient current drive to the capacitor during operation. Compared with the passive battery cell voltage difference detection module composed only of MOS switches and capacitors, it avoids the influence of charge injection effect and leakage current effect of MOS switches on signal accuracy, thereby achieving high-precision battery cell voltage difference detection, and also eliminates the need for additional back-end drive circuits. Using the battery cell voltage difference detection module, analog-to-digital converter, controller, and processor, an analog front-end architecture for battery monitoring chips based on battery cell voltage difference can be constructed. Compared with other existing technologies, this architecture can meet the requirements of smaller chip area, high channel matching, and high precision for long-term monitoring.

[0201] Based on the above, the battery cell voltage difference detection circuit for battery monitoring chips of the present invention adopts a transconductance amplifier with a differential pair structure to ensure that the active circuit provides sufficient current drive to the capacitor during operation. Compared with the passive battery cell voltage difference detection module composed only of MOS switches and capacitors, it avoids the influence of charge injection effect and leakage current effect of MOS switches on signal accuracy, thereby achieving high-precision battery cell voltage difference detection, and also eliminates the need for additional back-end drive circuits. Using the battery cell voltage difference detection module, analog-to-digital converter, controller, and processor, an analog front-end architecture for battery monitoring chips based on battery cell voltage difference can be constructed. Compared with other existing technologies, this architecture can meet the requirements of smaller chip area, high channel matching, and high precision for long-term monitoring.

[0202] Figure 15 A flowchart of a battery cell voltage difference detection method for a battery monitoring chip according to an embodiment of the present invention is shown.

[0203] like Figure 15As shown, the battery cell voltage difference detection method 1500 for battery monitoring chips includes operations S1510 to S1540.

[0204] In one embodiment, the battery cell voltage difference detection method 1500 for a battery monitoring chip can be applied to, for example... Figure 1 The battery cell voltage difference detection circuit 100 shown is used in this circuit.

[0205] In operation S1510, a multiplexer is used to output the voltage signal of the first battery cell in the battery cell module during the first half-cycle of the first control clock signal, and to output the voltage signal of the second battery cell in the battery cell module during the second half-cycle of the first control clock signal, so as to output a voltage square wave signal under the first control clock signal.

[0206] In operation of S1520, a level shifter is used to separate the differential-mode voltage and common-mode voltage in the voltage square wave signal to suppress common-mode voltage interference and output a differential-mode voltage square wave signal.

[0207] In operation S1530, the voltage spike blocking unit is used to suppress voltage spike interference in the differential mode voltage square wave signal based on the on / off state of the voltage spike blocking unit, so as to output the effective square wave signal in the differential mode voltage square wave signal.

[0208] In operation of S1540, the square wave demodulation amplifier module is used to perform fully differential chopping demodulation on the effective square wave signal to obtain a detection signal used to characterize the voltage difference between the first and second battery cells.

[0209] According to an embodiment of the present invention, since the multiplexer outputs both differential-mode and common-mode voltages, and the output common-mode voltage can cause the square wave demodulation amplifier module to malfunction or experience significant accuracy degradation, a level shifter is introduced to suppress the common-mode voltage interference. However, when the common-mode voltage jump amplitude of the input level shifter is large, it can cause a significant voltage spike in the differential-mode voltage output by the level shifter. Furthermore, the larger the input common-mode voltage jump amplitude, the longer the duration of the voltage spike in the output differential-mode voltage. Therefore, a voltage spike blocking unit is introduced to suppress voltage spike interference and output the effective square wave signal in the differential-mode voltage square wave signal based on the on / off state of the voltage spike blocking unit. Based on this, the square wave demodulation amplifier module can be used to process the effective square wave signal to obtain a detection signal characterizing the voltage difference between two battery cells, thereby improving the detection accuracy of the battery cell voltage difference. Therefore, the battery cell voltage difference detection circuit used in battery monitoring chips directly detects and amplifies the voltage difference between two battery cells without acquiring and outputting the physical quantities related to the voltage of a single battery cell. This satisfies the application requirements for high-precision acquisition of battery cell voltage differences and also realizes a new analog front-end architecture for battery monitoring chips.

[0210] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0211] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0212] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A battery cell voltage difference detection circuit for a battery monitor chip, characterized by, The method comprises the following steps: The square wave modulation module comprises a multiplexer, a level shifter and a voltage spike blocking unit; The multiplexer is configured to output a voltage signal of a first battery unit in the battery unit module in a first half cycle of a first control clock signal and output a differential voltage signal of a second battery unit in the battery unit module in a second half cycle of the first control clock signal, so as to output a voltage square wave signal under the first control clock signal; The level shifter is configured to separate a differential mode voltage and a common mode voltage in the voltage square wave signal, suppress common mode voltage interference, and output a differential mode voltage square wave signal; The voltage spike blocking unit is configured to suppress voltage spike interference in the differential mode voltage square wave signal based on an on-off state of the voltage spike blocking unit, so as to output an effective square wave signal in the differential mode voltage square wave signal; The square wave demodulation amplifier module is configured to perform full-differential chopping demodulation processing on the effective square wave signal output by the square wave modulation module, so as to obtain a detection signal for characterizing a battery unit voltage difference between the first battery unit and the second battery unit.

2. The detection circuit of claim 1, wherein The voltage spike blocking unit comprises a plurality of series-connected latch switch components connected to a positive output end of the level shifter and a plurality of series-connected latch switch components connected to a negative output end of the level shifter; The voltage spike blocking unit is configured to block voltage spikes in the differential mode voltage square wave signal and output an effective square wave signal under a second control clock signal based on an on-off state of each latch switch component; The on-off states of each latch switch component in the voltage spike blocking unit are consistent.

3. The detection circuit of claim 2, wherein, The latch switch component comprises: A first transistor, a drain of the first transistor serving as an input end of the second control clock signal and being electrically connected to a gate of a second transistor, a source of the first transistor serving as an input end of the differential mode voltage square wave signal and being electrically connected to a source of the second transistor and a source of a third transistor, and a gate of the first transistor being electrically connected to a drain of the second transistor; The second transistor, a drain of the second transistor serving as an input end of an inverted control clock signal of the second control clock signal; The third transistor, a gate of the third transistor being electrically connected to the drain of the second transistor, and a drain of the third transistor serving as an output end of the third transistor; The on-off states of the first transistor and the second transistor are controlled by the second control clock signal and the inverted control clock signal, the on-off state of the third transistor is controlled by the on-off states of the first transistor and the second transistor, and the on-off state of the latch switch component is controlled by the on-off state of the third transistor.

4. The detection circuit of claim 3, wherein The latch switch assembly is configured to control the first transistor to be turned on and the second transistor to be turned off when the second control clock signal is at the first level and the inverted control clock signal is at the second level, and then control the third transistor to be turned on based on the gate input of the third transistor being at the second level and the source input of the third transistor being at the first level, so as to output an effective square wave signal in the differential mode voltage square wave signal. The time period when the second control clock signal is at the first level is used to represent a time period when the voltage spike in the differential mode voltage square wave signal does not exist.

5. The detection circuit of claim 4, wherein the latch switch assembly is further configured to control the first transistor to be turned off and the second transistor to be turned on when the second control clock signal is at the second level and the inverted control clock signal is at the first level, and then control the third transistor to be turned off based on the gate input of the third transistor being at the first level and the source input of the third transistor being at the second level, so as to suppress the voltage spike in the differential mode voltage square wave signal. The time period when the second control clock signal is at the second level is used to represent a time period when the voltage spike in the differential mode voltage square wave signal exists. The multiplexer includes a plurality of positive input terminals, a plurality of negative input terminals, a plurality of switch assemblies, a positive output terminal, and a negative output terminal.

6. The detection circuit according to any one of claims 1 to 5, characterized in that, The positive input terminals are electrically connected to the positive poles of the battery cells in the battery cell module and are electrically connected to the positive output terminal via the switch assemblies. The negative input terminals are electrically connected to the negative poles of the battery cells in the battery cell module and are electrically connected to the negative output terminal via the switch assemblies. The multiplexer is configured to provide respective channels of the plurality of battery cells in the battery cell module, to turn on the channel of the first battery cell in the multiplexer in a first half cycle of the first control clock signal, and to turn on the channel of the second battery cell in the multiplexer in a second half cycle of the first control clock signal. Turning on the channel of the first battery cell in the multiplexer is used to represent that the switch assembly in the channel of the first battery cell in the multiplexer is turned on.

7. The detection circuit of claim 6, wherein the first half cycle of the first control clock signal is consistent in length with the second half cycle of the first control clock signal. The transition time of the first control clock signal is used to represent a switching time between the first half cycle and the second half cycle of the first control clock signal or a switching time between the second half cycle and the first half cycle of the first control clock signal. The multiplexer is configured to switch the on channel of the multiplexer at the transition time of the first control clock signal, so as to switch the on channel between the channel of the first battery cell and the channel of the second battery cell.

8. The detection circuit of claim 7, wherein ​ ​ The jump time of the first control clock signal is located in the time period when the second control clock signal is at the second level, and the time period when the second control clock signal is at the first level is located in the time period between two adjacent jump times of the first control clock signal; The voltage spike blocking unit is configured to block voltage spikes in the differential mode voltage square wave signal caused by channel switching of the multiplexer in the case of channel conduction switching of the multiplexer.

9. The detection circuit according to claim 8, characterized in that, The jump time of the second control clock signal from the second level to the first level is aligned with the jump time of the third control clock signal of the square wave demodulation amplifier module; The jump time of the second control clock signal from the second level to the first level is used to represent the conduction start time of the voltage spike blocking unit; The jump time of the third control clock signal is used to represent the state switching time of the chopper in the square wave demodulation amplifier module; The voltage spike blocking unit is configured to output the effective square wave signal in the differential mode voltage square wave signal to the square wave demodulation amplifier module in the case of conduction start of the voltage spike blocking unit.

10. The detection circuit of claim 1, wherein, The positive input end of the level shifter is electrically connected with the negative output end of the multiplexer, and the negative input end of the level shifter is electrically connected with the positive output end of the multiplexer; the positive input end of the level shifter corresponds to the negative output end of the level shifter, and the negative input end of the level shifter corresponds to the positive output end of the level shifter; The level shifter is configured to extract the differential mode voltage in the voltage square wave signal, polarity-invert the differential mode voltage, and then mount the polarity-inverted differential mode voltage to a preset output common mode voltage in a fixed proportion, so as to provide a stable common mode reference for the differential mode voltage square wave signal.

11. The detection circuit of claim 1, wherein, The square wave demodulation amplifier module comprises an input capacitor, a primary transconductance amplifier, an intermediate chopper and a secondary transconductance amplifier, wherein the intermediate chopper is arranged between the primary transconductance amplifier and the secondary transconductance amplifier; The input capacitor is configured to isolate the direct current voltage in the effective square wave signal; The frequency of the first control clock signal is greater than the corner frequency of the primary transconductance amplifier to ensure that the flicker noise of the input pair tube of the primary transconductance amplifier is filtered out, The intermediate chopper is configured to modulate the flicker noise of the input pair tube of the primary transconductance amplifier to be filtered out; The secondary transconductance amplifier is configured to filter out the modulated flicker noise.

12. A battery cell voltage difference detection method for a battery monitoring chip, applied to the detection circuit according to any one of claims 1-11, characterized in that, The detection circuit comprises a multiplexer, a level shifter, a voltage spike blocking unit and a square wave demodulation amplifier module, and the detection method comprises: The multiplexer is configured to output the voltage signal of a first battery unit in a battery unit module in the first half cycle of a first control clock signal and output the voltage signal of a second battery unit in the battery unit module in the second half cycle of the first control clock signal to output a voltage square wave signal under the first control clock signal; and The level shifter is configured to extract the differential mode voltage in the voltage square wave signal, polarity-invert the differential mode voltage, and then mount the polarity-inverted differential mode voltage to a preset output common mode voltage in a fixed proportion, so as to provide a stable common mode reference for the differential mode voltage square wave signal. The level shifter is configured to separate a differential mode voltage and a common mode voltage in the voltage square wave signal, suppress common mode voltage interference, and output a differential mode voltage square wave signal; The voltage spike blocking unit is configured to suppress voltage spike interference in the differential mode voltage square wave signal based on an on-off state of the voltage spike blocking unit, and output an effective square wave signal in the differential mode voltage square wave signal. The square wave demodulation amplifier module is configured to perform full-differential chopping demodulation processing on the effective square wave signal to obtain a detection signal for representing a battery cell voltage difference between the first battery cell and the second battery cell.

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