Manufacturing method and structure of CPO optical module assembly

Abstract

The invention discloses a manufacturing method and a structure of a CPO optical module assembly, and belongs to the technical field of semiconductor packaging. The technology comprises the following steps that an EIC wafer and a PIC wafer are prefabricated, an EIC chip set and a PIC chip set are formed, and an end face coupler and an optical waveguide layer are arranged at one end of the upper layer in the front face of the PIC chip set; a plurality of EIC chip sets are temporarily and positively installed and fixed; all the EIC chip sets are plastically packaged, solidified and thinned, the end faces of the metal columns on the EIC chips are exposed, and a plastic package body is formed; manufacturing an RDL layer above the plastic package body; metal balls are planted on the RDL layer, and then the PIC chip set is inversely installed; removing the temporary fixation, and cutting to form an OE light engine module; an OE optical engine module, an optical fiber array assembly and a heat dissipation block are assembled on the PCB, and the optical fiber array assembly is attached to the end face coupler of the PIC chipset and one end of the optical waveguide layer. According to the invention, the difficulty of a packaging process is reduced, the product performance is improved, and the process cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a manufacturing method of a CPO optical module assembly and a structure thereof, and belongs to the technical field of semiconductor packaging, in particular to an optoelectronic co-encapsulation structure and a manufacturing method thereof. BACKGROUND

[0002] Co-packaged optics (CPO) is an optoelectronic co-encapsulation technology that co-encapsulates optical engines and switch chips together, achieving high integration, reducing cost, reducing power consumption, and improving transmission rate. An optical engine (OE) refers to a part of an optical transceiver module responsible for processing optical signals. CPO co-assembles optical engines and switch chips on the same Socketed (socket), forming a co-encapsulation of chips and modules. The closer the optical engine is to the switch chip, the shorter the optical signal distance, and the smaller the SerDes (SERializer / DESerializer, serializer / deserializer) power consumption.

[0003] According to the physical structure, CPO can be divided into three forms: 2D packaged CPO, 2.5D packaged CPO, and 3D packaged CPO. 2D packaging is to place PIC (Photonic Integrated Circuit) and EIC (Electrical Integrated Circuit) side by side on a substrate or PCB (Printed Circuit Board), and establish interconnection through wire or substrate wiring, mainly based on wire bonding / flip chip / FOWLP (Fanout Wafer Level Packaging) technology; 2.5D packaging is to flip both EIC and PIC on a adapter board, and connect PIC and EIC to the underlying packaging substrate or PCB 800 through the metal internal interconnection on the adapter board, mainly based on silicon interposer / glass interposer / EMIB (Embedded Multi-die Interconnect Bridge) technology; 3D packaging vertically interconnects optoelectronic chips, mainly based on PIC as adapter board / EIC as interposer / embedded organic substrate technology; Co-packaged optical devices are currently in the early stages of industrialization, and each packaging technology has its advantages and disadvantages. The advantages of 2D packaging are easy to package, low price and high flexibility. However, as the bandwidth demand continues to increase, the effects of parasitic parameters on pins and bumps cannot be eliminated, and the interconnection density cannot continue to increase, which will limit the further improvement of system performance, and the high-speed interconnection performance is poor. 2.5D packaging is based on silicon interposer / glass interposer / EMIB technology, which has the disadvantages of high cost and low yield, and the processing of glass is more difficult and not fully compatible with conventional silicon processes. There is no mature and stable process at the moment, and the heat dissipation performance of glass is poor, so additional heat dissipation solutions need to be considered. Compared with 2.5D packaging, the parasitic parameters of electrical interconnection between EIC and PIC in 3D packaging are further reduced, and the bonding pitch is further reduced, which is conducive to realizing higher bandwidth signal interconnection.

[0004] Published patent: CN117908200A, patent name: Optoelectronic co-encapsulation module based on advanced packaging and preparation method thereof, as shown in Figure 1 It comprises: An optoelectronic interposer substrate; an optical chip and an electrical chip located on the first surface of the optoelectronic interposer substrate and electrically connected through the optoelectronic interposer substrate; a circuit board located on the second surface of the optoelectronic interposer substrate and electrically connected to the optical chip and the electrical chip through the optoelectronic interposer substrate; an optical fiber array assembly located on the first surface of the optoelectronic interposer substrate and coupled to the optoelectronic interposer substrate; a grating coupler and a first optical waveguide are provided in the optoelectronic interposer substrate for transmitting optical signals between the optical fiber array assembly and the optical chip; the optical chip includes a waveguide layer and a device layer, and the optical interconnection between the waveguide layer and the device layer adopts evanescent wave coupling.

[0005] The invention improves the problems of high frequency loss, low integration, and small heat dissipation area of high-speed optical modules, and solves the problem of optical chip optical port protection in advanced packaging process, but the signal interconnection between chips of this structure is realized through an interposer, and the integration and high-speed performance will be between 2D packaging structure and 3D packaging structure; If a silicon interposer is used, the main disadvantages are: the TSV (Through Silicon Via) related process has a high manufacturing cost; the Handle process of the wafer is high and easy to crack; since silicon is a semiconductor, the signal integrity is poor; not suitable for large-size chip packaging; silicon waveguide loss is large and requires an external laser source for compensation; If a glass interposer is used, the main disadvantages are: the processed glass may introduce micro-cracks, increase the problem of via / surface roughness, and have potential impact on product reliability and performance; the aperture of TGV (Through Glass Via) hole is relatively larger than that of TSV hole, the metal plating filling process of TGV hole is prone to have the problem of cavity, the plating time and cost are higher; the bonding force between glass and metal is poor, which is prone to delamination, and an adhesion layer needs to be introduced to increase the bonding force between them to prevent delamination; the glass has poor heat dissipation, and high-power light engines need additional heat dissipation design; If EMIB technology is used, the main disadvantages are: when heterogeneous integration is performed, the integrated chips have differences in electrical characteristics and manufacturing engineering, thereby causing problems such as uneven heating; an HDI (High Density Interconnector) high-density interconnection substrate embedding process is needed, and the difficulty and cost of substrate manufacturing increase; the CTE matching between materials is poor. SUMMARY

[0006] In order to overcome the deficiencies of the existing packaging process, the application provides a manufacturing method and structure of a CPO optical module assembly to reduce the difficulty of packaging process, improve product performance, and reduce process cost.

[0007] The technical solutions of the application are as follows: The application provides a manufacturing method and structure of a CPO optical module assembly based on an advanced packaging process.

[0008] This approach first involves prefabricating EIC and PIC wafers. EIC prefabrication includes: forming 120mm metal pillars above the pads, and back-side thinning and dicing to form a single chip. PIC prefabrication includes: forming micro-metal pillars above the pads, vacuum laminating a non-conductive adhesive film onto the micro-metal pillar surface, and back-side thinning and dicing to form a single chip. Next, temporary bonding and molding processes are used to reconstruct the EIC chip (metal pillars facing upwards) wafer or panel. The molding body is thinned across its entire surface until the metal pillars on the EIC chip are exposed. Then, photolithography and electroplating processes are used to create a redistribution layer to bring out the signals from the EIC chip. Next, ball-mounting is used to achieve signal interconnection between the chip signals and the PCB board. Then, the prefabricated PIC chip is flip-chip bonded to the pads brought out by the EIC chip using thermoforming, achieving signal interconnection between the EIC and PIC chips. Finally, the reconstructed wafer or panel is diced into individual OE optical engine modules. Solder paste or flux is applied to the corresponding soldering areas on the PCB board, and TIM (Thermal Interface Material) is applied to the PIC mounting area. The optical engine module with the metal ball side facing down is then mounted onto the PCB board. At the same time, TIM (Thermal Interface Material) is applied to one side of the EIC chip, and the heat sink is mounted onto the PCB board. The EIC forms an upward heat dissipation path through the TIM and the heat sink. Meanwhile, the fiber optic array assembly is precisely mounted onto the side of the PIC chip without metal solder balls, thus forming the CPO optoelectronic co-package module.

[0009] This invention provides a packaging structure for a CPO optical module, comprising: The OE optical engine module includes several EIC chips, several PIC chips, and an RDL layer. The RDL layer includes a first surface and a second surface facing each other. Metal pillars are provided on the front side of the EIC chips and are fixed to the first surface of the RDL layer through the metal pillars. The front side of the PIC chip is provided with micro metal pillars, and is fixed to the second surface of the RDL layer through the micro metal pillars. The EIC chip and the PIC chip are connected by telecommunications through the RDL layer. The PIC chip has an end face coupler and its optical waveguide layer on one end of the inner upper layer of the front side, and the second surface of the RDL layer is also provided with a metal ball. It also includes a PCB board, a fiber optic array assembly and a heat sink, wherein the PCB board is provided with an array of copper pillar heat dissipation channels that run through the top and bottom of the PCB board. The back of the PIC chip is fixedly connected to the array of copper pillar heat dissipation channels on the PCB board. The back of the EIC chip is fixedly connected to one end of the heat sink, the front of the EIC chip is fixedly connected to the PCB board through the metal ball, and the other end of the heat sink is fixedly connected to the PCB board. The optical fiber array assembly is arranged on one side of the end face coupler and the optical waveguide layer of the PIC chip and is fixed to the PCB board, and the optical fiber array assembly is precisely connected with the PIC chip through the end face coupler and the optical waveguide layer.

[0010] As an implementable manner of the present application, the non-conductive adhesive film covers the micro metal pillars, and the top end of the micro metal pillar is provided with a solder ball.

[0011] As an implementable manner of the present application, the overall thickness H3 of the PIC chip group is equal to the thickness H2 of the PIC chip plus the film thickness h3 of the non-conductive adhesive film.

[0012] As an implementable manner of the present application, the inner core of the metal ball is a copper core ball, and the outer part is wrapped with a solder plating layer.

[0013] As an implementable manner of the present application, a nickel plating layer is further arranged between the inner core and the solder plating layer of the metal ball.

[0014] As an implementable manner of the present application, plastic sealing material is further included, the plastic sealing material seals all EIC chip groups and metal pillars, and exposes the end face of the metal pillar to form a plastic sealing surface.

[0015] As an implementable manner of the present application, the EIC chip group at least includes a group of transimpedance amplifiers and a driver.

[0016] As an implementable manner of the present application, the end face coupler of the PIC chip and the optical waveguide layer on one side thereof protrude the RDL and are fixed to the PCB.

[0017] The present application further provides a manufacturing method of the CPO optical module assembly, and the process steps are as follows: Step one, pre-preparation of EIC wafer and PIC wafer to form EIC chip group and PIC chip group, the EIC chip group contains EIC chips, the front surface of the EIC chip is provided with a metal pillar, the PIC chip group contains a PIC chip, one end of the upper layer inside the front surface of the PIC chip is pre-prepared with an end face coupler and an optical waveguide layer, and the front surface of the PIC chip is sequentially provided with a micro metal pillar and a solder ball and covered with a non-conductive adhesive film; Step two, temporarily fixing a plurality of EIC chip groups in a normal manner; Step three, plastic sealing of all EIC chip groups and solidification and thinning to expose the end face of the metal pillar on the EIC chip to form a plastic sealing body; Step four, manufacturing an RDL layer on the plastic sealing body; Step five, planting a metal ball on the RDL layer 400, and flip-chip mounting the PIC chip group through a hot-press welding process. Step six, release the temporary fixing, cut to form OE light engine module, expose the back of EIC chip; Step seven, fix the OE light engine module, fiber array assembly and heat sink block on the PCB board, the PCB board is provided with array type copper column heat dissipation channel, the back of the PIC chip is connected with the array type copper column heat dissipation channel through thermal interface material I, the fiber array assembly is attached to the end face coupler of the PIC chip and the end of the optical waveguide layer; one end of the heat sink block is fixedly connected with the back of the EIC chip through thermal interface material II, and the other end of the heat sink block is welded and fixed with the PCB board.

[0018] As an implementation manner of the present application, in step seven, the fiber emission port of the fiber array assembly is aligned with the end face coupler of the end face coupler and the optical waveguide layer, and the optical interconnection between the optical waveguide layer and the coupler adopts evanescent wave coupling. Beneficial effects

[0019] The present application provides a manufacturing method and structure of a CPO optical module assembly. The present application realizes signal interconnection and conduction of three-dimensional optoelectronic chips by means of plastic sealing material, copper core soldering ball, copper column and conventional photoetching and electroplating process, cancels the adapter plate structure used in 2.5D packaging, vertically interconnects optoelectronic chips, and shortens the interconnection path, thereby reducing the packaging size, increasing the integration degree, shortening the delay and reducing the energy consumption. The PIC chip is connected with the array type copper heat dissipation channel of the PCB board through TIM to realize downward heat dissipation path, and the EIC chip is connected with the heat sink through TIM to realize upward heat dissipation path, thereby forming a double-sided heat dissipation structure. The present application does not need to use TSV and TGV technologies and organic adapter plate, and the process flow is relatively simple and easy to implement. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 FIG. 1 is a schematic diagram of an existing optoelectronic co-encapsulation module structure; Figure 2 FIG. 2 is a process flow diagram of a manufacturing method of a CPO optical module assembly according to the present application; Figure 3 FIG. 3 is a sectional view of an embodiment of a structure of a CPO optical module assembly according to the present application; Figure 4 FIG. 4 is a plan view of the position relationship between the EIC chip group and the PIC chip group in FIG. 1; Figure 3 FIG. 5 is a plan view of the position relationship between the EIC chip, the PIC chip, the fiber array assembly and the heat sink block in FIG. 1; Figure 5 Figure 3 FIG. 6 is a flow chart of a forming process of the pattern in FIG. 1; Figures 6A to 6O FIG. 7 is a flow chart of a forming process of the pattern in FIG. 2; Figure 3 In FIG. 7, the EIC chip group 100 ​​EIC chip 110 Metal column 120 PIC chipset 200 PIC chip 210 End-face coupler and its optical waveguide layer 211 Micrometal column 220 Non-conductive adhesive film 230 Interference prevention zone 231 RDL layer 400 Pad I451 Pad II453 Metal ball 500 Temporary bonding carrier 900 Thermal foaming film or temporary bonding adhesive 910 Fiber optic array assembly 920 Heat sink 930. Detailed Implementation

[0021] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] This invention discloses a method for manufacturing a CPO optical module assembly, such as... Figure 2 As shown, its process flow is as follows: S101, prefabrication of EIC wafer and PIC wafer to form EIC chipset and PIC chipset, wherein an end coupler and optical waveguide layer are set at one end of the upper inner layer of the front side of the PIC chipset. S102, temporarily and securely mount several EIC chipsets; S103, mold all EIC chipsets and cure and thin them to expose the metal pillar end faces on the EIC chips to form a molded body; S104, Create an RDL layer on top of the molding compound; S105, metal balls are implanted on the RDL layer, and then the PIC chipset is flip-chip; S106, release the temporary fixation, cut to form the OE optical engine module, exposing the back of the EIC chip; S107, assembling the OE optical engine module, the optical fiber array assembly and the heat sink on the PCB board, wherein the optical fiber array assembly is attached to the end face coupler and the optical waveguide layer of the PIC chip set. Embodiment

[0024] A CPO optical module packaging structure can be formed by the above-mentioned method for manufacturing a CPO optical module assembly, as shown in Figures 3 to 5 The CPO optical module packaging structure includes a plurality of EIC chip sets 100, a plurality of PIC chip sets 200, an RDL layer 400 and metal balls 500, and a PCB board 800, an optical fiber array assembly 920 and a heat sink 930. The EIC chip set 100 includes an EIC chip 110 and a metal column 120. The metal column 120 is arranged on the front pad of the EIC chip 110, the height h1 of the metal column 120 is greater than or equal to 45 microns, and the thickness H1 of the EIC chip 110 ranges from 200 to 600 microns. The material of the metal column 120 can be one or a mixture of several conductive metals such as copper, iron, gold and silver. In this case, the material of the metal column 120 is preferably copper. The EIC chip set 100 includes at least one set of trans-impedance amplifiers (TIA) and one driver. The TIA is the core component of the EIC chip set, which is responsible for converting weak current signals (such as photoelectric current generated by a photodetector) into voltage signals and amplifying them to a processable level. The driver provides stable operating current for the TIA to ensure that the signal quality meets the subsequent processing requirements. Both of them work together to complete the whole process of receiving optical signals, current detection, voltage conversion and signal amplification, which is a key module in optical communication systems. Figure 4 The EIC chip set 100 is encapsulated by the encapsulating material 300, which protects the EIC chip set 100 in the encapsulating body and forms an encapsulating surface 301. The encapsulating surface 301 exposes the end surface of the metal column 120 on the EIC chip set 100, thereby forming a reconstituted wafer or a reconstituted panel.

[0025] The encapsulating material 300 can be in the form of powder, liquid or sheet. Depending on the state of the encapsulating material 300, the matching equipment and process are slightly different. In the operation process of the sheet-shaped encapsulating material, a film press is needed to attach the encapsulating material to the surface of the product.

[0026] The RDL layer (i.e. the redistribution metal layer) 400 is arranged on the encapsulating surface 301 and includes opposite first and second surfaces. The EIC chip 110 is fixed to the first surface of the RDL layer 400 through the metal column 120, and the electrical connection between the EIC chip 110 and the metal column 120 is realized.

[0027] The PI window above the metal pad layer of the lead-out signal of the RDL layer 400 is opened to expose the metal layer part to form a port. The specific form of the port includes a signal terminal array, a pad, or an opening, etc. Figure 3 Here, the pads I 451 and the pads II 453 are shown. The size of the pads I 451 is greater than the size of the pads II 453; the pads I 451 and the pads II 453 can make the internal and external circuits of the chip conductive, lead out signals, and play a good heat conduction function, etc.

[0028] The PIC chip set 200 includes a PIC chip 210 and a micro metal pillar 220. The micro metal pillar 220 is arranged on the front pad of the PIC chip 210, the top end of the micro metal pillar 220 is provided with a solder ball 221, and the height of the micro metal pillar 220 and the solder ball 221 and h2 is in the range of 20-45 microns. Generally, the cross section of the micro metal pillar 220 is circular or rectangular, and the diameter is 10-30 microns. The material of the micro metal pillar 220 can be one or a mixture of several of the conductive metals such as copper, iron, gold, silver, etc. In this case, the material of the micro metal pillar 220 is preferably copper. The non-conductive adhesive film 230 completely covers the micro metal pillar 220 and the solder ball 221 thereof, and the film thickness h3 of the non-conductive adhesive film 230 is greater than the height of the micro metal pillar 220 and the solder ball 221 and h2. The thickness H2 of the PIC chip 210 is in the range of 100-300 microns.

[0029] One end of the upper layer of the internal front of the PIC chip 210 is provided with an end face coupler and an optical waveguide layer 211, and the film area above the end face coupler and the optical waveguide layer 211 is an anti-interference area 231, and the micro metal pillar 220 is not arranged. The end face coupler is used to couple the optical signal in the optical fiber into the structure of the optical waveguide inside the PIC chip 210 to achieve efficient optical signal transmission. A standard single inverted taper edge coupler is the most basic form of all edge couplers, and there are various design structures based on this, and this patent takes a silicon inverted taper waveguide plus an upper auxiliary silicon nitride waveguide as an example. The upper auxiliary silicon nitride waveguide is usually made of a material with a lower refractive index than silicon, such as silicon nitride (SiN) and silicon oxynitride (SiON). In principle, the upper auxiliary silicon nitride waveguide is placed above the silicon inverted taper waveguide so that the propagation mode distributed in the narrow taper outside can be transmitted and constrained upward. Because of the existence of the upper auxiliary silicon nitride waveguide with a higher refractive index than the surrounding silicon dioxide cladding layer, the light is often limited in multiple auxiliary waveguides.

[0030] The PIC chip set 200 is fixedly connected with the pads II 453 of the second surface of the RDL layer 400 through the micro metal pillar 220 and the solder ball 221 thereof.

[0031] The above-mentioned EIC chip set 100, PIC chip set 200 and RDL layer 400 form an optical engine module, and the EIC chip 110 and the PIC chip 210 are electrically connected through the RDL layer 400. The second surface of the RDL layer 400 is also provided with metal balls 500. The metal balls 500 are soldered to the pads I451 led out by the EIC chip 110.

[0032] The number and distribution of the metal balls 500 are determined according to actual product needs. The diameter D1 of the metal balls 500 ranges from 130 to 350 microns; and the material thereof is a metal or a composite metal with excellent electrical conductivity, such as copper. The metal balls 500 are preferably copper-core solder balls, the inner core of which is a copper ball 510 with a diameter ranging from 100 to 320 microns; and the outer layer is a solder plating layer 530 with a thickness ranging from 3 to 30 microns. The diameter D1 of the selected metal balls 500 is greater than the overall thickness H3 of the PIC chip set 200 (i.e., the overall thickness H3 of the PIC chip set 200 = the thickness H2 of the PIC chip 210 + the film thickness h3 of the non-conductive adhesive film 230). Alternatively, a metal ball 500 with a 2- to 3-um nickel plating layer between the inner core and the outer layer can also be used. The nickel plating layer can reduce the wetting behavior between the copper core and the substrate, so as to enhance the corrosion resistance, wear resistance and electrical conductivity of the inner core.

[0033] The PCB board 800 is provided with a pre-mounted PIC chip area and a soldering area. The pads in the soldering area are brushed with solder paste or flux, or are subjected to an anti-oxidation treatment, so as to facilitate subsequent soldering and integration of other chips, and realize signal interconnection and conduction of multiple chips.

[0034] The pre-mounted PIC chip area is provided with an array of copper column groups 810. The copper columns in the copper column groups 810 penetrate the PCB board 800 from top to bottom, and are exposed at both ends to form heat dissipation channels.

[0035] The PIC chip area is coated with a thermal interface material I710 (TIM), and then the light engine module is mounted on the PCB board 800 with the metal balls 500 facing downward. The PIC chip 210 forms a downward heat dissipation path through the thermal interface material I710 and the arrayed copper column heat dissipation channels of the PCB board 800. The EIC chip 110 is fixed to the PCB board 800 through the metal balls 500, and signal interconnection and conduction between the EIC chip 110 and the PIC chip 210 and the PCB board 800 are realized. The solder plating layer 530 on the metal balls 500 cooperates with the flux of the PCB board 800 to better fix the metal balls 500 to the PCB board 800. The thermal interface material I710 can be in the form of a heat-conductive silicone gasket, a heat-conductive gel or a heat-conductive silicone grease.

[0036] The heat dissipation block 930 is a ┓-shaped wide plate with one side open, and is arranged above the EIC chip 110 to fully cover the EIC chip 110.

[0037] One end of the heat sink 930 is fixed to the back of the EIC chip 110 through thermal interface material II 720 (Thermal Interface Material, abbreviated as TIM), and the other end is fixed to the PCB board 800, without electrical connection, as shown. Figure 3 The EIC chip 110 forms an upward heat dissipation path through the thermal interface material II 720 and the heat sink 930, and precisely attaches the fiber array assembly 920 to the end face coupler of the PIC chip 210 and one side of the optical waveguide layer 211, thereby forming a CPO optoelectronic co-packaging module.

[0038] In order to prevent the fiber array assembly 920 from interfering with the heat sink 930 in the vertical direction, the end face coupler of the PIC chip 210 and one side of the optical waveguide layer 211 protrude from the RDL 400 and are mounted on the PCB 800, as shown. Figure 3

[0039] In operation, the end face coupler of the PIC chip 210 and the optical waveguide layer 211 arranged at the inner edge are used to transmit optical signals between the fiber array assembly 920 and the PIC chip 210. When the fiber array assembly 920 is attached to the PCB board 800, the fiber emission port needs to be aligned with the end face coupler at the edge of the PIC chip 210. The optical interconnection between the optical waveguide layer and the coupler uses evanescent wave coupling for precise butt joint to ensure efficient transmission of optical signals. The optical fiber emitted by the fiber array assembly 920 is directly coupled to the PIC chip to realize transmission of optical signals. The other end of the fiber array assembly 920 is connected to external optical fibers to realize high-speed data transmission and stable heat dissipation. The thermal interface material II 720 can be in the form of a heat-conducting silicone gasket, heat-conducting gel, heat-conducting silicone grease, etc.

[0040] The above-mentioned CPO optical module packaging structure can be realized through the specific process of the manufacturing method of the CPO optical module assembly of the present application, as shown. Figures 6A to 6O The process is as follows: Step one, as shown in Figures 6A to 6D The EIC wafer and the PIC wafer are preformed to form the EIC chip group 100 and the PIC chip group 200.

[0041] The EIC wafer is preformed, as shown in Figure 6A ​As shown, the process is as follows: first, take the EIC wafer (not shown in the figure), which contains a plurality of EIC chips 110, and prepare metal columns 120 above the front pads of the EIC chips 110 (the height h1 of the metal columns 120 is ≥45 microns, and the initial height of the metal columns 120 covers the plating copper column tolerance and subsequent plastic packaging process tolerance, grinding and thinning process tolerance, etc. Then, thin the back of the EIC chip 110, so that the thickness H1 of the EIC chip 110 is in the range of 200-600 microns, and finally, scribe to form a plurality of independent EIC chip groups 100.

[0042] PIC wafer pre-preparation, Figures 6B to 6D As shown, the process is as follows: first, take the PIC wafer (not shown in the figure), which contains a plurality of PIC chips 210, each of which is pre-prepared with an end-coupler and an optical waveguide layer 211; Prepare micro metal columns 220 above the front pads of the PIC chips 210, and prepare solder balls 221 at the top of the micro metal columns 220, and the height of the micro metal columns 220 and solder balls 221 is in the range of 20-45 microns. Generally, the cross section of the micro metal column 220 is circular or rectangular, with a diameter of 10-30 microns. Then, vacuum the non-conductive film 230 (Non-Conductive Film) to the front of the PIC chip 210 (the film thickness h3 of the non-conductive film 230 is greater than the height h2 of the micro metal column 220 and solder ball 221, to ensure that the non-conductive film can completely cover the micro metal column 220), thin the back, so that the thickness H2 of the PIC chip 210 is in the range of 100-300 microns, and then scribe to form a plurality of independent PIC chip groups 200, Figure 6B PIC chip group 200 is a top view schematic diagram, Figure 6C PIC chip group 200 is a C-C cross-sectional schematic diagram, Figure 6B PIC chip group 200 is a B-B cross-sectional schematic diagram. Figure 6D PIC chip group 200 is a B-B cross-sectional schematic diagram. Figure 6B PIC chip group 200 is a B-B cross-sectional schematic diagram.

[0043] Step two, see Figure 6E As shown, temporarily fix a plurality of EIC chip groups 100 in a vertical manner. The specific process is as follows: take a temporary bonding carrier 900, paste a thermal foaming film 910 on the temporary bonding carrier 900, or coat a layer of temporary bonding glue, then vertically mount the EIC chip group 100 on the temporary bonding carrier 900, with the metal column 120 facing up. The material of the temporary bonding carrier 900 can be metal or glass, the metal material is commonly used for pyrolytic bonding, and the glass material is suitable for both pyrolytic bonding and laser decomposition bonding principles; the temporary bonding carrier 900 can be a conventional rectangular panel or a circular wafer.

[0044] Step three, see Figure 6F andFigure 6G As shown, all EIC chipsets 100 are plastic encapsulated and solidified, thinned, and the end faces of the metal pillars 120 on the EIC chips are exposed to form a plastic encapsulated body. The specific process is as follows: the EIC chipsets 100 are protected in the plastic encapsulated body by molding plastic encapsulation process with plastic encapsulation material 300, and then solidified. Then the plastic encapsulated body is uniformly thinned, as shown in Figure 6G As shown, the metal pillars 120 on the EIC chipsets 100 are exposed to form a reconstituted wafer or a reconstituted panel. The plastic encapsulation material 300 can be selected as powder, liquid or sheet, and the matched equipment and process are slightly different according to the selected state of the plastic encapsulation material 300. The sheet-shaped plastic encapsulation material needs to be attached to the product surface by means of a film press during operation.

[0045] Step four, see Figure 6H As shown, an RDL layer 400 is made above the plastic encapsulated body. The specific process is as follows: the RDL layer 400 is made above the plastic encapsulated body by sputtering, photoetching, electroplating, adhesive removal, etching and other processes in sequence, the signals connected by the metal pillars 120 are led out, and then a layer of dielectric passivation layer 410 is made above the RDL layer 400 by photoetching development process, and the PI above the metal pad layer of the led-out signal of the RDL layer 400 is windowed to expose the metal layer part, respectively forming the pad I 451 and the pad II 453. The pad I 451 is distributed around the pad II 453, and the size of the pad I 451 is larger than the size of the pad II 453. According to the complexity of the chip interconnection requirement, the led-out of all signals can be realized by the superposition of the multi-layer dielectric passivation layer 410 and the RDL layer 400. This case takes one layer of RDL layer 400 as an example, and the structure schematic diagram is as follows:

[0046] Step five, see Figure 6I and Figure 6J As shown, metal balls 500 are planted on the RDL layer 400, and the PIC chipsets 200 are inverted. The specific process of planting metal balls 500 on the RDL layer 400 is as follows: the metal balls 500 are welded to the pad I 451 led out by the EIC chip 110 by ball drop process, which is used for subsequent signal interconnection and conduction between the EIC chip 110 and the PIC chip 210 and the PCB board 800. The number and distribution of the metal balls 500 are determined according to the actual needs of the product. The diameter D1 of the metal balls 500 is in the range of 130-350 microns, and the material is copper or other metal with excellent conductivity.

[0047] Metallic ball 500 is preferably a copper core solder ball, with a copper core 510 having a diameter ranging from 100 to 320 microns, and an outer solder plating layer 530 having a thickness ranging from 3 to 30 microns. The diameter D1 of the metallic ball 500 is greater than the overall thickness H3 of the PIC chip set 200 (i.e., the overall thickness H3 of the PIC chip set 200 = the thickness H2 of the PIC chip 210 + the film thickness h3 of the non-conductive adhesive film 230). The PIC chip has an end face coupler and an optical waveguide layer 211 disposed on the upper layer of the PIC chip front face. Figure 6J As shown, the specific process of mounting the inverted PIC chip set 200 on the RDL layer 400 is as follows: the pre-prepared PIC chip set 200 is inverted and soldered to the solder pad II 453 led out by the EIC chip 110 through a hot-press welding process, realizing the signal interconnection between the EIC chip 110 and the PIC chip 210. The process sequence of mounting the metallic ball 500 on the RDL layer 400 can be adjusted according to actual conditions.

[0048] Step six, see Figure 6J As shown, the temporary fixing is released, and the OE light engine module is cut. The specific process is as follows: according to the characteristics of the selected temporary bonding carrier material and the temporary bonding material, the debonding process is carried out, the temporary bonding carrier 900 and the thermal foaming film or temporary bonding adhesive 910 are removed, and the back surface of the EIC chip 110 is exposed.

[0049] See Figure 6J As shown, the recombined wafer or panel is cut into a plurality of independent OE light engine modules through a cutting process. In the figure, the OE light engine module contains at least one transimpedance amplifier (TIA), one driver (Driver), and one PIC chip.

[0050] Step seven, see Figures 6K to 6O As shown, the OE light engine module, the optical fiber array assembly 920, and the heat sink 930 are fixed on the PCB board 800. The specific process is as follows: take the PCB board 800, and the PCB board 800 is provided with a pre-mounted PIC chip area and a soldering area.

[0051] The pre-mounted PIC chip area is provided with an arrayed copper column group, and the copper columns in the copper column group penetrate the PCB board 800 from top to bottom, with both ends exposed, forming an arrayed copper column heat dissipation channel 811. Solder paste or flux is brushed on the welding area, thermal interface material I710 (TIM) is applied on the PIC chip area, and then the light engine module is attached to the PCB board 800 with the metal ball facing down, and the PIC chip 210 forms a downward heat dissipation path through the thermal interface material I710 and the array copper column heat dissipation channel of the PCB board 800. The thermal interface material I710 can be in the form of a heat-conducting silicone pad, a heat-conducting gel, a heat-conducting silicone grease, etc. The specific process of fixing the optical fiber array assembly 920 and the heat sink 930 on the PCB board 800 is as follows: prepare the heat sink 930, which is a wide plate with one side open and covers the EIC chip 110 completely. Thermal interface material II720 (TIM) is applied on the back of the EIC chip 110 to fix one end of the heat sink 930, which completely covers the back of the EIC chip 110.

[0052] Then the other end of the heat sink 930 is fixed to the PCB board 800 without electrical connection, as shown in the following figure, the heat sink 930 above the EIC chip 110 covers the EIC chip 110 while avoiding interference with other components, and the size is as large as possible within the existing size range to enhance the heat dissipation effect. The EIC chip 110 forms an upward heat dissipation path through the thermal interface material II720 and the heat sink 930, and the optical fiber array assembly 920 is precisely attached to the end face coupler and one side of the optical waveguide layer 211 of the PIC chip 210, thereby forming a CPO optoelectronic co-packaging module. The end face coupler and the optical waveguide layer are arranged at one end of the edge of the PIC chip for transmitting optical signals between the optical fiber array assembly and the PIC chip. When the optical fiber array assembly is attached to the PCB board, the optical fiber exit port needs to be aligned with the end face coupler at the edge of the PIC chip, and the optical interconnection between the waveguide layer and the coupler uses evanescent wave coupling. The thermal interface material II720 can be in the form of a heat-conducting silicone pad, a heat-conducting gel, a heat-conducting silicone grease, etc.

[0053] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any changes or replacements within the technical range disclosed in the embodiments of the present application can be easily thought of by those skilled in the art, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A packaging structure for a CPO optical module, characterized in that, include: The OE optical engine module includes several EIC chips (110), several PIC chips (210) and an RDL layer (400). The RDL layer (400) includes a first surface and a second surface opposite to each other. Metal pillars (120) are provided on the front side of the EIC chip (110) and are fixed to the first surface of the RDL layer (400) through the metal pillars (120). The PIC chip (210) has micro metal pillars (220) on its front side, and is fixed to the second surface of the RDL layer (400) through the micro metal pillars (220). The EIC chip (110) and the PIC chip (210) are connected by the RDL layer (400). The PIC chip (210) has an end face coupler and its optical waveguide layer (211) on one end of the upper inner layer on the front side, and the second surface of the RDL layer (400) is also provided with a number of metal balls (500). It also includes a PCB board (800), a fiber optic array assembly (920) and a heat sink (930), wherein the PCB board (800) is provided with an array of copper pillar heat dissipation channels (811) that run vertically through the PCB board (800); The back of the PIC chip (210) is fixedly connected to the array of copper pillar heat dissipation channels (811) of the PCB board (800); The back of the EIC chip (110) is fixedly connected to one end of the heat sink (930), the front of the EIC chip (110) is fixedly connected to the PCB board (800) through the metal ball (500), and the other end of the heat sink (930) is fixedly connected to the PCB board (800). The fiber array assembly (920) is disposed on one side of the end face coupler and its optical waveguide layer (211) of the PIC chip (210) and is fixedly connected to the PCB board (800). The fiber array assembly (920) is precisely connected to the PIC chip (210) through the end face coupler and its optical waveguide layer (211).

2. The packaging structure according to claim 1, characterized in that, It also includes a non-conductive adhesive film (230) that covers the micro-metal pillar (220), and solder balls (221) are provided at the top of the micro-metal pillar (220), with the solder balls (221) exposed above the non-conductive adhesive film (230).

3. The packaging structure according to claim 1, characterized in that, The diameter D1 of the metal ball (500) is greater than the overall thickness H3 of the PIC chip group (200), and the overall thickness H3 of the PIC chip group (200) is equal to the thickness H2 of the PIC chip (210) plus the film thickness h3 of the non-conductive adhesive film (230).

4. The packaging structure according to claim 3, characterized in that, The core of the metal ball (500) is a copper core ball, and its exterior is coated with a layer of solder plating.

5. The packaging structure according to claim 4, characterized in that, A nickel plating layer is also provided between the core of the metal ball (500) and the solder plating layer.

6. The packaging structure according to claim 1, characterized in that, It also includes a molding compound (300) that encapsulates all EIC chips (110) and metal pillars (120) and exposes the end face of the metal pillars (120) to form a molding cover (301).

7. The packaging structure according to claim 1, characterized in that, The EIC chipset (100) includes at least one set of transimpedance amplifiers and drivers.

8. The packaging structure according to claim 1, characterized in that, The end coupler of the PIC chip (210) and its optical waveguide layer (211) protrude RDL (400) and are fixed to the PCB (800).

9. A method for manufacturing a CPO optical module assembly, the process steps of which are as follows: Step 1: Prefabrication of EIC wafers and PIC wafers to form EIC chipset (100) and PIC chipset (200). The EIC chipset (100) includes an EIC chip (110). Metal pillars (120) are fabricated on the front side of the EIC chip (110). The PIC chipset (200) includes a PIC chip (210). An end face coupler and its optical waveguide layer (211) are prefabricated on one end of the upper layer inside the front side of the PIC chip (210). Micro metal pillars (220) and solder balls (221) are sequentially fabricated on the front side of the PIC chip (210) and covered with a non-conductive adhesive film (230). Step 2: Temporarily fix several EIC chipsets (100); Step 3: Moldulate all EIC chipsets (100) and cure and thin them to expose the end faces of the metal pillars (120) on the EIC chips, forming a molded body; Step 4: Create an RDL layer (400) on the molding compound; Step 5: Metal balls (500) are implanted on the RDL layer (400), and the PIC chipset (200) is flip-chip bonded through a thermo-pressurization process; Step 6: Remove the temporary fixation, cut to form the OE optical engine module, and expose the back of the EIC chip (110); Step 7: Fix the OE optical engine module, fiber array assembly (920) and heat sink (930) on the PCB board (800). The PCB board (800) is provided with an array-type copper pillar heat dissipation channel (811). The back of the PIC chip (210) is electrically connected to the array-type copper pillar heat dissipation channel (811) through thermal interface material I (710). The fiber array assembly (920) is attached to one end of the end face coupler and its optical waveguide layer (211) of the PIC chip (210). One end of the heat sink (930) is fixed to the back of the EIC chip through thermal interface material II (720). The other end of the heat sink (930) is soldered to the PCB board (800).

10. The manufacturing method according to claim 9, characterized in that, In step seven, the fiber optic outlet of the fiber array assembly (920) is aligned with the end face coupler and the end face coupler of its optical waveguide layer (211), and the optical interconnection between the optical waveguide layer and the coupler adopts evanescent wave coupling.

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