Extensible server architecture system suitable for various processors

Abstract

The invention provides an extensible server architecture system suitable for various processors, which comprises a main board carrying a processor; the backboard is integrated with a multi-protocol interface control chip, a programmable clock buffer, a plurality of impedance adjusting circuits, a plurality of expansion slots and a plurality of groups of differential high-speed signal channels, the backboard is connected with the mainboard and the expansion slots through internal wiring, and the expansion slots are used for connecting pluggable expansion modules; the plurality of switching chips are arranged on a connecting path of the back plate and the mainboard and are used for topological connection of the processor and the expansion slot; the switching chip supports automatic negotiation of a PCIe / CXL protocol; according to the invention, the bus protocol difference between the processor and the pluggable expansion module is automatically adapted through the multi-protocol interface control chip and the switching chip, so that the universality of the system is improved; through the impedance adjusting circuit and the programmable clock buffer, the difference of different pluggable expansion modules in electrical characteristics and time sequences is solved, and the compatibility stability of different devices is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server architecture, and in particular to an extensible server architecture system suitable for multiple types of processors. BACKGROUND

[0002] With the continuous promotion of autonomous controllable information infrastructure, domestic CPUs (Central Processing Unit) such as Haiguang and Feiteng are widely used in the server field, and gradually take on the core computing task in key industries such as finance, energy and communication. However, the existing server hardware architecture is generally built around the Intel or AMD (a kind of x86 architecture processor and its supporting chip set, technology ecological system) system, and its mainboard, chip set, firmware interface and backplane interconnection structure are deeply bound to the technical standards and ecological system of international manufacturers. The inertia of this architecture makes it difficult for the backplane design of the existing server to adapt to domestic processors in terms of bus protocol, pin definition, electrical characteristics and clock synchronization mechanism, which limits the universality of the server architecture system.

[0003] Therefore, there is an urgent need for a server architecture system that supports multiple protocols for different processors to meet the needs of high reliability and universality. SUMMARY

[0004] To overcome the shortcomings of the prior art, the present application provides an extensible server architecture system suitable for multiple types of processors, comprising: a mainboard carrying a processor; a backplane integrated with a multi-protocol interface control chip, a programmable clock buffer, multiple impedance adjustment circuits, multiple expansion slots and multiple groups of differential high-speed signal channels; the backplane connects the mainboard and multiple expansion slots through internal wiring, and the expansion slots are used to connect pluggable expansion modules; the multi-protocol interface control chip is connected with the mainboard and the expansion slots, and is used to realize protocol intercommunication between the processor and the pluggable expansion modules; the programmable clock buffer is connected with the mainboard and the expansion slots, and is used for timing synchronization between the processor and the expansion slots; multiple impedance adjustment circuits are embedded in each group of differential high-speed signal channels to ensure signal integrity; a plurality of switching chips installed on the connection path of the backplane and the mainboard, used to realize the topology connection of the processor and the expansion slot, and the switching chip supports PCIe / CXL protocol automatic negotiation.

[0005] Optionally, the programmable clock buffer includes a phase-locked loop, a frequency divider and a phase alignment circuit. The input terminal of the phase-locked loop is connected to the reference clock of the motherboard, and the output terminal is connected to the input terminal of the frequency divider. The phase-locked loop is used to generate a high-frequency clock signal based on the reference clock input from the motherboard through feedback adjustment, and output it to the frequency divider. The multiple output terminals of the frequency divider are respectively connected to the input terminals of the expansion slots, and are used to divide the high-frequency clock signal as needed to generate multiple reference clocks and distribute them to multiple expansion slots; The phase alignment circuit is connected to the frequency divider and the processor, and is used to perform phase alignment calibration on each of the reference clocks and the reference clock of the processor before the reference clock is distributed and during operation, so as to realize timing synchronization between the multiple expansion slots and the processor.

[0006] Optionally, each group of differential high-speed signal channels includes several differential signal line pairs; Each of the differential signal line pairs is configured with an impedance adjustment circuit; The impedance adjustment circuit is used to adjust the terminating impedance between the differential signal line pairs to ensure signal integrity on the differential signal line pairs.

[0007] Optionally, the impedance adjustment circuit includes an adjustable matching network, a reflected wave detection unit, and a control logic unit; The reflected wave detection unit is disposed on the differential signal line pair and is used to monitor the reflected wave energy on the differential signal line pair in real time, extract the reflected signal from the reflected wave energy and convert it into digital parameters, which are recorded as reflected wave data. The control logic unit is connected to the reflected wave detection unit and the adjustable matching network respectively, and is used to calculate the optimal impedance value based on the reflected wave data using an impedance matching algorithm, and generate an adjustment command based on the optimal impedance value and send it to the adjustable matching network. The adjustable matching network is used to dynamically adjust the terminating impedance between the differential signal line pairs based on the adjustment command using a differential variable resistor network.

[0008] Optionally, each of the differential high-speed signal channels includes a differential signal compensator, which is used to dynamically adjust and compensate for signal attenuation during signal transmission based on the signal bit error rate.

[0009] Optionally, the backplane adopts a multi-layer PCB stack-up design: The PCB stack-up includes multiple signal layers and multiple reference plane layers, wherein the reference plane layers include ground plane layers and power plane layers; The signal layer and the reference plane layer are arranged alternately.

[0010] Optionally, the system also includes a programmable configuration interface; The programmable configuration interface is connected to the BMC of the motherboard for receiving BMC control commands. The programmable configuration interface is connected to the switching chip for communication and is used to configure the operating parameters of the switching chip through the BMC control instructions, thereby realizing the dynamic switching of the system's operating mode.

[0011] Optionally, the operating modes of the system include: processor direct-connect mode and processor-switch chip off-line mode.

[0012] Optionally, the switching chip is configured with a hot-plug detection circuit on its periphery and a credit counting flow control unit on its internal side; The hot-plug detection circuit is used to support the hot-plug detection of the pluggable expansion module; The credit counting flow control unit is used for flow control of the high-speed signal channel.

[0013] Optionally, the pluggable expansion module includes: a domestically produced graphics processor, a neural network processor, or a field-programmable gate array (FPGA) accelerator card.

[0014] Compared with the closest existing technology, the present invention has the following beneficial effects: This invention provides a scalable server architecture system suitable for multiple processor types, comprising: a motherboard housing a processor; a backplane integrating a multi-protocol interface control chip, a programmable clock buffer, multiple impedance adjustment circuits, multiple expansion slots, and multiple sets of differential high-speed signal channels; the backplane connects the motherboard and the multiple expansion slots via internal wiring, the expansion slots being used to connect pluggable expansion modules; the multi-protocol interface control chip is connected to the motherboard and the expansion slots to enable protocol interoperability between the processor and the pluggable expansion modules; the programmable clock buffer is connected to the motherboard and the expansion slots for timing synchronization between the processor and the expansion slots; multiple impedance adjustment circuits are embedded in each set of differential high-speed signal channels to ensure signal integrity; several switching chips are installed on the connection path between the backplane and the motherboard to realize the topology connection between the processor and the expansion slots, the switching chips supporting PCIe / CXL protocol auto-negotiation; in this invention, the multi-protocol interface control chip dynamically parses the PCIe protocols of the processor and external devices through a built-in protocol conversion engine. The CXL link layer packet format ensures electrical compatibility at the physical layer while enabling protocol interoperability between the processor and standard PCIe / CXL devices (pluggable expansion modules). The switching chip automatically identifies the type of external device and dynamically configures the channel protocol mode, thereby eliminating compatibility issues caused by protocol differences between the processor at the transaction layer and the link layer. The combination of these two technologies enables the backplane to be compatible with the PCIe / CXL protocol, automatically eliminates bus protocol differences between the processor and pluggable expansion modules, solves protocol mismatch problems, and improves the versatility of the architecture system. The impedance adjustment circuit dynamically matches the differential signal line impedance and combines it with multi-time domain synchronization of the programmable clock buffer to jointly solve the differences in electrical characteristics and timing of different pluggable expansion modules, ensuring high-speed signal integrity and thus guaranteeing the reliability of data transmission and the stability of compatibility between different devices. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a scalable server architecture system applicable to multiple types of processors, provided by the present invention. Detailed Implementation

[0016] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0017] Example 1 This invention provides a scalable server architecture system suitable for multiple processor types, such as... Figure 1 As shown, it includes: The motherboard contains a processor; The backplane integrates a multi-protocol interface control chip, a programmable clock buffer, multiple impedance adjustment circuits, multiple expansion slots, and multiple sets of differential high-speed signal channels. The backplane connects the motherboard and the multiple expansion slots via internal wiring. The expansion slots are used to connect pluggable expansion modules. The multi-protocol interface control chip is connected to the motherboard and the expansion slots to enable protocol interoperability between the processor and the pluggable expansion modules. The programmable clock buffer is connected to the motherboard and the expansion slots for timing synchronization between the processor and the expansion slots. Multiple impedance adjustment circuits are embedded in each set of differential high-speed signal channels to ensure signal integrity. Several switching chips are installed on the connection path between the backplane and the motherboard to realize the topological connection between the processor and the expansion slot. The switching chips support PCIe / CXL protocol auto-negotiation.

[0018] The processors used in the aforementioned motherboards include mainstream international processors (Intel and AMD, etc.) as well as domestic processors (Phytium, Hygon, Shenwei, and Loongson, etc.).

[0019] The multi-protocol interface control chip dynamically parses the link layer packet formats of the processor and pluggable expansion modules' PCIe (Peripheral Component Interconnect Express, a high-speed serial expansion bus standard) and CXL (Compute Express Link, a high-speed interconnect protocol) through a built-in protocol conversion engine. While maintaining electrical compatibility at the physical layer, it enables protocol interoperability between the processor and external standard PCIe / CXL devices (pluggable expansion modules). The switching chip automatically identifies the type of external device through a negotiation mechanism and dynamically configures the channel protocol mode, thereby eliminating compatibility issues caused by protocol differences between the processor at the transaction layer and the link layer. The combination of the two enables the backplane to be compatible with PCIe / CXL protocols, automatically adapts to the bus protocol differences between the processor and external devices, and solves the protocol mismatch problem, mainly the bus protocol differences between domestic processors and external standard protocol devices. Among them, the switching chip can automatically identify the protocol type of the connected pluggable expansion device (such as whether it is a PCIe network card or a CXL memory expansion card) and dynamically switch the underlying electrical and protocol stack configuration without manual intervention or hardware jumpers, thus solving the problem of protocol incompatibility between the processor on the motherboard and heterogeneous devices. At the same time, the number of native PCIe lanes of domestic CPUs (such as Phytium / Loongson) is limited. Through the automatic negotiation capability of the switching chip, a single x16 lane can be intelligently split into: 2 x8 PCIe links for GPU (Graphics Processing Unit), or 1 x8 CXL + 1 x8 PCIe hybrid link. This can maximize the use of limited channel resources, make up for the scalability disadvantage of domestic CPUs, and significantly reduce the deployment complexity of heterogeneous computing platforms.

[0020] PCIe is a common standard for interconnecting domestic processors with expansion devices (pluggable expansion modules). Domestic accelerator cards rely on PCIe. CXL is a key evolution protocol for solving memory consistency (such as the pooling of domestic GPU memory) and low-latency communication. It is compatible with the PCIe physical layer and is suitable for domestic application scenarios.

[0021] The processor and the motherboard are directly connected via a high-speed interconnect channel.

[0022] The aforementioned programmable clock buffer includes a phase-locked loop, a frequency divider, and a phase alignment circuit; The input terminal of the phase-locked loop is connected to the reference clock of the motherboard, and the output terminal is connected to the input terminal of the frequency divider. The phase-locked loop is used to generate a high-frequency clock signal based on the reference clock input from the motherboard through feedback adjustment, and output it to the frequency divider. The multiple output terminals of the frequency divider are respectively connected to the input terminals of the expansion slots, and are used to divide the high-frequency clock signal as needed to generate multiple reference clocks and distribute them to multiple expansion slots; The phase alignment circuit is connected to the frequency divider and the processor, and is used to perform phase alignment calibration on each of the reference clocks and the reference clock of the processor before the reference clock is distributed and during operation, so as to realize timing synchronization between the multiple expansion slots and the processor.

[0023] The programmable clock buffer's initial reference clock originates from a reference clock generated by a reference clock generator on the motherboard. The processor's clock signal on the motherboard is also a reference clock generated by the same generator, ensuring frequency consistency between the processor and various pluggable expansion modules. After receiving the reference clock from the motherboard, the programmable clock buffer generates multiple sets of identical but independent reference clocks via a phase-locked loop and a frequency divider, distributing them to multiple expansion slots. The frequency, phase, and spread spectrum modulation of each output reference clock can be configured individually.

[0024] In summary, the programmable clock buffer dynamically matches the clock requirements of different devices (such as domestic CPUs and international GPUs) by performing on-demand frequency division and phase alignment calibration on the input reference clock, eliminating the timing synchronization differences between processors and international devices, and adapting to different protocols.

[0025] For example, a processor (such as Loongson) may require a 125MHz reference clock, while a certain international GPU requires 100MHz. In this case, the reference clock generator on the motherboard is used to independently provide the clock frequency to the processor. The programmable clock buffer dynamically adjusts the clock frequency of the expansion slot device (international GPU) through a frequency divider (e.g., processor channel 1 outputs 125MHz, expansion slot device channel 2 outputs 100MHz).

[0026] The timing consistency between expansion slot devices and processors is ensured by using phase alignment circuits, avoiding clock skew issues during cross-slot communication. This ensures that there are no timing conflicts when multiple expansion slots correspond to pluggable expansion modules and when processors exchange data.

[0027] Meanwhile, the programmable clock buffer is connected to the BMC (Baseboard Management Controller) chip on the motherboard, receiving configuration commands issued by the IPMI protocol (such as modifying the division ratio of the frequency divider or disabling spread spectrum modulation). It can flexibly switch the clock mode in real time according to the load requirements (such as enabling low jitter mode for computationally intensive tasks and enabling spread spectrum modulation to reduce electromagnetic interference for intensive tasks), thereby improving system stability. By providing compatibility assurance, dynamically disabling spread spectrum modulation can meet the stringent requirements of devices supporting the CXL protocol for low jitter clocks, avoiding synchronization failures between domestic CPUs and international devices due to differences in clock specifications.

[0028] Each of the aforementioned differential high-speed signal channels includes several differential signal pairs (e.g., a PCIe x16 channel contains 16 differential pairs). The channel performance depends on the equal length, equal spacing, and impedance control of the line pairs. The differential signal pairs are the underlying foundation of the channel, which integrates line pairs, compensators, protocol controllers, etc., to achieve end-to-end data transmission.

[0029] Each differential signal line pair is equipped with an impedance adjustment circuit to adjust the terminating impedance between the differential signal line pairs, ensuring signal integrity on the differential signal line pairs.

[0030] The reason for configuring an impedance adjustment circuit for each differential signal line pair is that the impedance of different expansion slots or different differential signal line pairs in the same expansion slot may vary, requiring independent calibration to avoid crosstalk between channels caused by sharing a matching circuit.

[0031] The impedance adjustment circuit described above includes an adjustable matching network, a reflected wave detection unit, and a control logic unit. The reflected wave detection unit is disposed on the differential signal line pair and is used to monitor the reflected wave energy on the differential signal line pair in real time, extract the reflected signal from the reflected wave energy and convert it into digital parameters, which are recorded as reflected wave data. Specifically, the reflected wave detection unit monitors the reflected wave energy on the differential signal line pair in real time, extracts the reflected signal from the reflected wave energy through a high-precision directional coupler or time-domain reflectometer, and converts the reflected signal into digital parameters via a high-speed analog-to-digital converter.

[0032] The control logic unit is connected to the reflected wave detection unit and the adjustable matching network respectively, and is used to calculate the optimal impedance value based on the reflected wave data through an impedance matching algorithm, and generate an adjustment command based on the optimal impedance value and send it to the adjustable matching network. The adjustment command includes differential impedance value and common mode impedance value. The adjustable matching network is used to dynamically adjust the terminating impedance between the differential signal line pairs based on the adjustment command using a differential variable resistor network. Specifically, a differential variable resistor network (such as a numerically controlled differential terminating resistor chip) is used to synchronously adjust the common-mode and differential impedances of the two signal lines to ensure that the differential impedance dynamically matches the preset target value and the common-mode impedance is stable, thereby ensuring signal integrity and avoiding signal phase imbalance caused by single-ended adjustment, which meets the requirements of high-speed protocols (such as PCIe / CXL) for differential impedance consistency.

[0033] In summary, the impedance adjustment circuit dynamically adjusts the terminal impedance by real-time detection of signal reflection energy, ensuring that the differential signal line impedance always matches the characteristics of the currently inserted pluggable expansion module. Its core is to automatically compensate for differences in drive capability and pin load between different pluggable expansion modules through closed-loop control (detection-calculation-adjustment), eliminating signal reflections caused by impedance abrupt changes. Ultimately, this ensures that high-speed signals maintain a complete eye diagram when switching between different devices, meaning the signal waveform remains stable, clear, and regular without the need for manual hardware jumper intervention.

[0034] Each of the differential high-speed signal channels includes a differential signal compensator, which is used to dynamically adjust and compensate for signal attenuation during signal transmission based on the signal bit error rate.

[0035] The differential high-speed signal channel, also known as the high-speed signal link, is a physical trace on the backplane used to transmit high-speed differential signals (such as PCIe 5.0 / CXL 1.1), providing electrical connection paths and carrying protocol signals.

[0036] Each of the aforementioned differential high-speed signal channels includes a differential signal compensator. Specifically, the differential signal compensator is a circuit module embedded in the differential high-speed signal channel. It dynamically adjusts and compensates for signal attenuation, jitter, or distortion during signal transmission based on signal quality data obtained from the signal error rate detection module, thereby optimizing signal quality, especially for long-distance transmission.

[0037] The aforementioned differential high-speed signal channels are used to describe the physical connectivity of the backplane and are the infrastructure of the server architecture system. The differential signal compensator, as an enhancement method, is used to solve the signal integrity problems unique to the domestic processor environment, such as long-distance transmission loss. The two work together to ensure the reliable transmission of high-speed signals in the processor architecture.

[0038] The backplane adopts a multi-layer PCB (Printed Circuit Board) design: The PCB stack-up includes multiple signal layers and multiple reference plane layers, wherein the reference plane layers include ground plane layers and power plane layers; The signal layer and the reference plane layer are arranged alternately.

[0039] Specifically, the backplane employs an 8-24 layer high-density PCB stack-up design, achieving electromagnetic shielding through alternating signal layers and power / ground plane layers. Key high-speed signal layers utilize a stripline structure, sandwiched between adjacent ground plane layers to form a complete return path. The power layers employ a segmented layout, isolating different voltage domains with appropriate spacing and incorporating decoupling capacitor arrays between layers. The power layers and ground planes create a Faraday cage effect, confining high-frequency electromagnetic radiation within the PCB, preventing signal layers from intersecting with power layers, maintaining differential pair impedance stability, and reducing signal reflection. This design reduces high-frequency signal crosstalk by over 40%, while simultaneously reducing electromagnetic interference through the ground plane shielding effect.

[0040] By isolating the signal layer from the power layer and ground plane layer as described above, electromagnetic shielding is achieved, improving the ability to suppress electromagnetic interference, and thus improving signal integrity and transmission accuracy.

[0041] The system also includes a programmable configuration interface; The programmable configuration interface is connected to the BMC of the motherboard for receiving BMC control commands. The programmable configuration interface is connected to the switching chip for communication and is used to configure the operating parameters of the switching chip through the BMC control instructions, thereby realizing the dynamic switching of the system's operating mode.

[0042] The system operates in two modes: processor direct-connect mode and processor-switch chip off-line mode.

[0043] Among them, the processor direct connection mode is used for domestic GPUs / NPUs (Neural Processing Units). The direct connection mode can reduce the access latency of key devices such as domestic GPUs / NPUs and improve computing efficiency. The switching chip off-line mode supports the parallel access of multiple devices through PCIe splitting, solves the bottleneck of insufficient native channels of domestic CPUs, realizes the sharing of bandwidth by multiple devices, improves scalability, and meets different business needs by dynamically switching different operating modes.

[0044] The programmable configuration interface is also connected to the BIOS of the motherboard for receiving firmware configuration instructions.

[0045] The aforementioned motherboard BIOS (Basic Input / Output System) is a low-level firmware embedded in the motherboard chip, responsible for hardware initialization and basic settings management; the BMC is a dedicated microcontroller independent of the CPU, providing remote monitoring (temperature / power consumption), fault diagnosis, and firmware update functions through the IPMI protocol.

[0046] The aforementioned BMC is also communicatively connected to the programmable clock buffer and differential signal compensator. The BMC control commands include operating mode switching commands, clock adjustment commands, and signal optimization commands. The clock adjustment commands are sent to the programmable clock buffer on the backplane to adjust the reference clock parameters of each expansion slot. The signal optimization commands interact with the differential signal compensator on the motherboard / backplane to dynamically adjust the pre-emphasis and equalization strength in the differential signal compensator to optimize the signal.

[0047] The switching chip is externally configured with a hot-plug detection circuit and internally configured with a credit-based flow control unit. The hot-plug detection circuit is used to support hot-plug detection of the pluggable expansion module. The credit-based flow control unit is used for flow control of the high-speed signal channel.

[0048] Meanwhile, the backplane supports hot-swapping and link self-recovery capabilities, where the link refers to a high-speed signal channel.

[0049] The switching chip directly realizes the sensing of hot-plug signals and flow control through hardware design, namely hot-plug detection circuit and Credit-Based flow control unit; the backplane provides physical layer support, such as connector electrical characteristics and link redundancy, to ensure signal stability and self-recovery when pluggable expansion modules are plugged in and out; the two together form a complete function, with the switching chip processing logic layer protocols and the backplane ensuring physical layer reliability.

[0050] The pluggable expansion module includes: a domestically produced graphics processor, neural network processor, or field-programmable gate array accelerator card, i.e., an AI accelerator module.

[0051] The pluggable expansion module communicates with the processor by dynamically allocating PCIe / CXL channels through the switching chip, and ensures high-speed signal integrity through impedance adjustment circuits and differential compensators on the backplane.

[0052] The pluggable expansion module design in this architecture system is a key component for achieving domestic production, high performance, and flexible expansion of the server architecture system. Through protocol adaptation, dynamic resource management, and signal integrity enhancement, it solves the hardware expansion capability problem in the processor ecosystem. Simultaneously, by inserting modules such as domestically produced GPUs and AI accelerator cards, it provides heterogeneous computing capabilities for domestic processors, meeting the needs of scenarios such as AI training and high-performance computing.

[0053] Example 2 In this embodiment, the above-described server architecture system is applied to a 4U rack server based on a domestic CPU platform (taking Phytium FT-2000+ as an example). The server motherboard is connected to the backplane via a gold finger interface. The backplane is a 24-layer high-speed PCB, integrating 10 PCIe 5.0 expansion slots, each supporting x16 lanes, and also equipped with 2 CXL reserved slots.

[0054] In terms of structural design, a clock management chip is embedded in the backplane, which can provide an independent reference clock for each expansion slot, supporting jitter extension of spread spectrum modulation and clock domain synchronization.

[0055] In terms of signal integrity, each PCIe channel is equipped with a third-order differential compensation network and reserved with equal-length serpentine traces to calibrate latency, supporting link self-training and hot-swap callback correction mechanisms.

[0056] In terms of topology, the first two expansion slots are directly controlled by the CPU, resulting in low latency and high bandwidth, making them suitable for deployment of domestic GPUs / NPUs; the remaining eight expansion slots are bridged through PAM4 (Pulse Amplitude Modulation 4-level) switching chips, supporting shared bus and dynamic bandwidth allocation rate limiting configuration.

[0057] In addition, under BMC control, users can remotely switch extended modes, such as GPU mode or accelerator mode, via IPMI (Intelligent Platform Management Interface) commands. The port mapping table and clock output strategy of the switching chip can be dynamically adjusted to meet the needs of multiple application scenarios, such as edge computing, cloud rendering and industrial control.

[0058] This system performs signal quality tests under full load configuration, meets CXL load compatibility requirements, and supports hot-switching between standard ATX power supplies (Advanced Technology eXtended, a motherboard and power supply specification) and redundant power supplies.

[0059] This system verifies the adaptability and reliability of the architecture of this invention in the domestic CPU environment, demonstrating good promotional value.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit its scope of protection. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that after reading the present invention, they can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the application, but these changes, modifications or equivalent substitutions are all within the scope of protection of the claims pending approval.

Claims

1. A scalable server architecture system suitable for multiple processor types, characterized in that, include: The motherboard contains a processor; The backplane integrates a multi-protocol interface control chip, a programmable clock buffer, multiple impedance adjustment circuits, multiple expansion slots, and multiple sets of differential high-speed signal channels. The backplane connects the motherboard and the multiple expansion slots via internal wiring. The expansion slots are used to connect pluggable expansion modules. The multi-protocol interface control chip is connected to the motherboard and the expansion slots to enable protocol interoperability between the processor and the pluggable expansion modules. The programmable clock buffer is connected to the motherboard and the expansion slots for timing synchronization between the processor and the expansion slots. Each of the differential high-speed signal channels is embedded with multiple impedance adjustment circuits to ensure signal integrity; Several switching chips are installed on the connection path between the backplane and the motherboard to realize the topological connection between the processor and the expansion slot. The switching chips support PCIe / CXL protocol auto-negotiation.

2. The system as described in claim 1, characterized in that, The programmable clock buffer includes a phase-locked loop, a frequency divider, and a phase alignment circuit; The input terminal of the phase-locked loop is connected to the reference clock of the motherboard, and the output terminal is connected to the input terminal of the frequency divider. The phase-locked loop is used to generate a high-frequency clock signal based on the reference clock input from the motherboard through feedback adjustment, and output it to the frequency divider. The multiple output terminals of the frequency divider are respectively connected to the input terminals of the expansion slots, and are used to divide the high-frequency clock signal as needed to generate multiple reference clocks and distribute them to multiple expansion slots; The phase alignment circuit is connected to the frequency divider and the processor, and is used to perform phase alignment calibration on each of the reference clocks and the reference clock of the processor before the reference clock is distributed and during operation, so as to realize timing synchronization between the multiple expansion slots and the processor.

3. The system as described in claim 1 or 2, characterized in that, Each group of differential high-speed signal channels includes several differential signal line pairs; Each of the differential signal line pairs is configured with an impedance adjustment circuit; The impedance adjustment circuit is used to adjust the terminating impedance between the differential signal line pairs to ensure signal integrity on the differential signal line pairs.

4. The system as described in claim 3, characterized in that, The impedance adjustment circuit includes an adjustable matching network, a reflected wave detection unit, and a control logic unit. The reflected wave detection unit is disposed on the differential signal line pair and is used to monitor the reflected wave energy on the differential signal line pair in real time, extract the reflected signal from the reflected wave energy and convert it into digital parameters, which are recorded as reflected wave data. The control logic unit is connected to the reflected wave detection unit and the adjustable matching network respectively, and is used to calculate the optimal impedance value based on the reflected wave data using an impedance matching algorithm, and generate an adjustment command based on the optimal impedance value and send it to the adjustable matching network. The adjustable matching network is used to dynamically adjust the terminating impedance between the differential signal line pairs based on the adjustment command using a differential variable resistor network.

5. The system as described in claim 1 or 2, characterized in that, Each of the differential high-speed signal channels includes a differential signal compensator, which is used to dynamically adjust and compensate for signal attenuation during signal transmission based on the signal bit error rate.

6. The system as described in claim 1, characterized in that, The backplane adopts a multi-layer PCB design: The PCB stack-up includes multiple signal layers and multiple reference plane layers, wherein the reference plane layers include ground plane layers and power plane layers; The signal layer and the reference plane layer are arranged alternately.

7. The system as described in claim 1, characterized in that, The system also includes a programmable configuration interface; The programmable configuration interface is connected to the BMC of the motherboard for receiving BMC control commands. The programmable configuration interface is connected to the switching chip for communication and is used to configure the operating parameters of the switching chip through the BMC control instructions, thereby realizing the dynamic switching of the system's operating mode.

8. The system as described in claim 7, characterized in that, The system operates in two modes: processor direct-connect mode and processor-switch chip off-line mode.

9. The system as described in claim 1, characterized in that, The switching chip is externally configured with a hot-plug detection circuit and internally configured with a credit counting flow control unit. The hot-plug detection circuit is used to support the hot-plug detection of the pluggable expansion module; The credit counting flow control unit is used for flow control of the high-speed signal channel.

10. The system as claimed in claim 1, characterized in that, The pluggable expansion module includes: a domestically produced graphics processor, a neural network processor, or a field-programmable gate array accelerator card.

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