Memory device for controlling operation timing based on internal temperature and method thereof

Abstract

The invention relates to a memory device for controlling operation timing based on internal temperature and a method thereof. A memory device includes a base chip and a memory chip stacked over the base chip. The base chip includes a temperature control circuit configured to control at least one of a time between consecutive column commands when a consecutive column operation is performed and a time between consecutive row commands when a consecutive row operation is performed based on information including an internal temperature of the memory device.

Description

Cross Reference to Related Applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0104953, filed on August 6, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to semiconductor memory devices, including but not limited to controlling operation timing. BACKGROUND

[0003] Recently, stacked memory systems, such as high bandwidth memory (HBM) devices, are being used in a wide range of applications due to their excellent bandwidth. Unlike conventional memory systems using a parallel data bus, stacked memory systems include stacked memory devices including base chips and memory chips interconnected by through silicon vias (TSVs). The stacked memory devices include a physical interface (e.g., a physical layer) for communication with a processor. The physical layer is designed for high-speed data transmission and efficient communication. SUMMARY

[0004] In an embodiment, a memory device can include a memory chip and a base chip on which the memory chip is stacked. The base chip can include a temperature control circuit configured to control a time between consecutive column commands when consecutive column operations are performed, based on information including an internal temperature of the memory device.

[0005] In an embodiment, a memory device can include a memory chip and a base chip on which the memory chip is stacked. The base chip can include a temperature control circuit configured to control a time between consecutive row commands when consecutive row operations are performed, based on information including an internal temperature of the memory device.

[0006] In an embodiment, a memory device can include a memory chip and a base chip stacked with the memory chip. The base chip can include a temperature control circuit including a first selector and a second selector. The first selector can be configured to control a read time between consecutive read commands when consecutive read operations are performed, based on information including an internal temperature of the memory device. The second selector can be configured to control a write operation time between consecutive write commands when consecutive write operations are performed, based on information including an internal temperature of the memory device.

[0007] In an embodiment, a method can include determining an internal temperature of a memory device including a storage chip and a base chip stacked with the storage chip from each other, identifying a time interval between consecutive operation commands based on the internal temperature, and controlling a timing between operation commands of the memory device based on the time interval during operation of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the disclosure.

[0009] Figure 2 illustrates a temperature control circuit according to an embodiment of the disclosure.

[0010] Figure 3 illustrates an operation timing of a temperature control circuit according to an embodiment of the disclosure.

[0011] Figure 4 illustrates a temperature control circuit according to an embodiment of the disclosure.

[0012] Figure 5 illustrates a temperature control circuit according to an embodiment of the disclosure.

[0013] Figure 6 illustrates a temperature control circuit according to an embodiment of the disclosure.

[0014] Figure 7 is a block diagram illustrating a stacked storage system according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0015] Terms such as "first" and "second" are used to distinguish various elements, and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element can be referred to as a second element, and in another example, a second element can be referred to as a first element.

[0016] When an element is referred to as being "connected" to another element, the elements can be directly connected, or connected through one or more intermediate elements between the elements. When two elements are referred to as being "directly connected," one element is directly connected to the other element without an intermediate element between the two elements.

[0017] Terms such as "above," "on," "inner," "higher," "high," "low," "left," "right," "column," "row," "horizontal," and other terms implying relative spatial relationships or orientations are used only to facilitate description or reference to the drawings, and are not limited in the opposite direction.

[0018] The term "bit group" includes a combination of logic levels of bits included in a signal. When the logic levels of bits included in a signal change, the bit group of the signal is different. For example, when a signal includes a first combination of two bits, the logic bit group of the signal is a first bit group, and when the signal includes a second combination of two bits, the bit group of the signal is a second bit group.

[0019] Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The detailed description of embodiments is provided as examples to describe the concepts disclosed in the present application for illustrative purposes. The concepts of the present disclosure can be implemented in various forms according to examples or embodiments of the concepts, and the scope of the present disclosure is not limited to the examples or embodiments described in the specification.

[0020] Figure 1 is a block diagram illustrating a memory device 10 according to an embodiment of the present disclosure.

[0021] As Figure 1 shown, the memory device 10 includes a base chip 100 and a memory chip 101. The memory chip 101 is stacked above or on the base chip 100. The memory chip 101 includes a plurality of slice chips, for example, 3120, 3130, 3140, 3150, 3220, 3230, 3240, and 3250 in Figure 7 The number L of slice chips may, for example, be one of 4, 8, and 12, where L is a positive integer. The present disclosure is not limited to these examples. Through-silicon vias ("TSVs") are formed in the memory chip 101 and the base chip 100. The TSVs are structures that provide electrical connections by extending through the memory chip 101 and the base chip 100, and advantageously transmit signals and data at high speed between the memory chip 101 and the base chip 100.

[0022] The base chip 100 includes a physical channel (PHY) 111, a memory controller (MC) 113, a temperature control circuit (TCTR) 115, a TSV physical channel (TSV PHY) 117, and a test circuit (DFT) 119.

[0023] The physical channel 111 controls the generation, transmission, and reception of signals or data, and the physical connection between the memory device 10 and a processor (for example, 3300 in Figure 7 , such as a CPU or a GPU). The physical channel 111 converts data between the processor and the memory device 10 into an electrical signal, an optical signal, or an electromagnetic signal, and vice versa, converting the converted signal back into data. In addition, the physical channel 111 manages a physical medium and a bandwidth for transmitting signals or data, synchronizes the processor and the memory device 10, and detects errors occurring in signals and data.

[0024] The memory controller 113 manages data transfer between the processor and the memory device 10. The memory controller 113 can be configured to improve the efficiency of the memory hierarchy and enhance the performance of the memory system. The memory controller 113 translates logical addresses generated during processes into physical addresses, controls the storage of data in the memory chip 101, and controls the output of data stored in the memory chip 101. The memory controller 113 controls parallel processing of data to improve memory bandwidth, detects and corrects errors in the data to improve the stability of the memory system, and controls the access timing of memory cells included in the memory chip 101, for example, to ensure effective communication between the processor and the memory device 10. The memory controller 113 controls the physical channel 111, the temperature control circuit 115, and the TSV physical channel 117.

[0025] Temperature control circuit 115 controls operation timing based on the internal temperature of memory device 10. Temperature control circuit 115 receives information including the internal temperature of memory device 10 from a temperature sensor (not shown). The temperature sensor may be located in base chip 100, in at least one slice of memory chip 101, or in both base chip 100 and memory chip 101. Operation timing includes: column-to-column delay tCCD, a first time between consecutive column commands when consecutive column operations are performed, including but not limited to minimum or shortest time; and row-to-row delay tRRD, a second time between consecutive row commands when consecutive row operations are performed, including but not limited to minimum or shortest time. Column operations include read operations and write operations, and row operations include activation operations. During row operations, at least one word line connected to a memory cell is selected to access the memory cell, while during column operations, at least one bit line connected to a memory cell is selected to access the memory cell. In one embodiment, a method includes: determining the internal temperature of a memory device, the memory device including base chips and memory chips stacked on top of each other; identifying time intervals between successive operation commands based on the internal temperature; and controlling the timing between operation commands of the memory device based on time intervals during operation of the memory device.

[0026] TSV physical channel 117 transmits and receives signals and data via a TSV connected to memory chip 101. TSV physical channel 117 is controlled by memory controller 113 to transmit data via TSV during write operations of memory chip 101 and to receive data via TSV during read operations of memory chip 101.

[0027] Test circuit 119 employs various techniques to perform tests to detect defects that may occur during the manufacturing process, reducing test time and costs. Tests performed in test circuit 119 may include Built-in Self-Test (BIST), Boundary Scan, Design for Debugging (DfD), and Error Correction Code (ECC). BIST is a technique that utilizes embedded test logic within the chip and performs tests independently of external control, either on its own or independently of test circuit 119. Boundary Scan, described in the IEEE 1149.1 standard, is a technique used to test connections via TSVs. DfD is a technique that improves debugging ease during the design phase, allowing for rapid diagnosis and resolution of potential problems in the silicon. ECC is a technique used to ensure the integrity of data stored in memory.

[0028] Figure 2 A temperature control circuit 115 according to an embodiment of the present disclosure is shown.

[0029] like Figure 2As shown, the temperature control circuit 115 includes a selector 21, which generates a selection operation timing signal tCCD-S based on the temperature code TCD[1:0] from a first operation timing signal tCCD1, a second operation timing signal tCCD2, and a third operation timing signal tCCD3. The selector 21 receives the first operation timing signal tCCD1 through a first input terminal "0", the second operation timing signal tCCD2 through a second input terminal "1", and the third operation timing signal tCCD3 through a third input terminal "2". The temperature control circuit 115 receives the temperature code TCD[1:0] from a temperature sensor (not shown) located in at least one of the base chip 100 and the memory chip 101. The bit group including the bits of the temperature code TCD[1:0] corresponds to the internal temperature of the memory device 10. For example, the temperature code TCD[1:0] includes a first bit group "00" corresponding to a low temperature (e.g., 40°C), a second bit group "01" corresponding to a high temperature (e.g., 70°C), and a third bit group "10" corresponding to a critical temperature (e.g., 90°C). When the temperature code TCD[1:0] includes the second bit group "01", this second bit group indicates that the first bit TCD[0] of the temperature code is "1" and the second bit TCD[1] of the temperature code is "0". In an embodiment, the bit groups included in the temperature code TCD[1:0] correspond to the internal temperature range of the memory device 10. For example, a temperature code TCD[1:0] including the first bit group "00" corresponds to a first temperature range (e.g., less than 70°C), a temperature code TCD[1:0] including the second bit group "01" corresponds to a second temperature range (e.g., between 70°C and 90°C), and a temperature code TCD[1:0] including the third bit group "10" corresponds to a third temperature range (e.g., 90°C or higher).

[0030] When the temperature code TCD[1:0] including the first bit group is received, the temperature control circuit 115 selects the first operation timing signal tCCD1 received at the first input terminal "0" to output the first operation timing signal tCCD1 as the selection operation timing signal tCCD-S. When the temperature code TCD[1:0] including the second bit group is received, the temperature control circuit 115 selects the second operation timing signal tCCD2 received at the second input terminal "1" to output the second operation timing signal tCCD2 as the selection operation timing signal tCCD-S. When the temperature code TCD[1:0] including the third bit group is received, the temperature control circuit 115 selects the third operation timing signal tCCD3 received at the third input terminal "2" to output the third operation timing signal tCCD3 as the selection operation timing signal tCCD-S. In an embodiment, the first operation timing signal tCCD1 is generated based on tCCD, where tCCD is a base timing value, a time interval or period between consecutive column commands, or the time between executing consecutive column operations. The second operation timing signal tCCD2 is generated based on 1.5 times the base timing value or 1.5 times tCCD as the time between consecutive column commands. The third operation timing signal tCCD3 is generated based on 2 times the base timing value or 2 times tCCD as the time between consecutive column commands. This disclosure is not limited to these examples.

[0031] Figure 3 Examples are shown, such as Figure 2 The operating timing of the temperature control circuit 115 shown.

[0032] As shown in the example Figure 3As shown, when the temperature control circuit 115 detects a low temperature, it selects a first operation timing signal tCCD1 as the selection operation timing signal tCCD-S. The first operation timing signal tCCD1 is generated at intervals of tCCD, where tCCD is the basic timing value between consecutive commands when consecutive operations are executed. When the temperature control circuit 115 detects a high temperature, it selects a second operation timing signal tCCD2 as the selection operation timing signal tCCD-S. The second operation timing signal tCCD2 is generated at intervals of 1.5 times the basic timing value tCCD. When the temperature control circuit 115 detects a critical temperature, it selects a third operation timing signal tCCD3 as the selection operation timing signal tCCD-S. The third operation timing signal tCCD3 is generated at intervals of 2 times the basic timing value tCCD. At low temperatures, consecutive column commands for consecutive column operations (e.g., read command RD for read operations or write command WT for write operations) are input according to a first operation timing signal tCCD1 at intervals equal to the basic timing value tCCD. At high temperatures, the read command RD or write command WT is input according to a second operation timing signal tCCD2 at intervals equal to 1.5 times the basic timing value tCCD. At critical temperatures, the read command RD or write command WT is input according to a third operation timing signal tCCD3 at intervals equal to 2 times the basic timing value tCCD. BAx represents the bank address used to select the memory bank, and CAn represents the column address used to select the column line during a read or write operation.

[0033] Figure 4 A temperature control circuit 115 according to an embodiment of the present disclosure is shown.

[0034] like Figure 4As shown, the temperature control circuit 115 includes a selector 23. The selector 23 generates a selection operation timing signal tCCD-S based on the temperature code TCD[1:0] from the first operation timing signal tCCD1, the second operation timing signal tCCD2, the third operation timing signal tCCD3, and the fourth operation timing signal tCCD4. The selector 23 receives the first operation timing signal tCCD1 through the first input terminal "0", the second operation timing signal tCCD2 through the second input terminal "1", the third operation timing signal tCCD3 through the third input terminal "2", and the fourth operation timing signal tCCD4 through the fourth input terminal "3". The bit group including the temperature code TCD[1:0] corresponds to the internal temperature of the memory device 10. For example, temperature code TCD[1:0] includes a first bit group "00" corresponding to a first temperature, a second bit group "01" corresponding to a second temperature, a third bit group "10" corresponding to a third temperature, and a fourth bit group "11" corresponding to a fourth temperature. According to embodiments, the first, second, third, and fourth temperatures can be determined in various different ways. In an embodiment, the bit group including the bits of temperature code TCD[1:0] corresponds to the internal temperature range of the memory device 10. For example, temperature code TCD[1:0] includes a first bit group "00" corresponding to a first temperature range, a second bit group "01" corresponding to a second temperature range, a third bit group "10" corresponding to a third temperature range, and a fourth bit group "11" corresponding to a fourth temperature range. According to the embodiments, the first temperature range, the second temperature range, the third temperature range, and the fourth temperature range can be determined in a variety of different ways.

[0035] When the temperature code TCD[1:0] including the first bit group is received, the temperature control circuit 115 selects the first operation timing signal tCCD1 received at the first input terminal "0" to output the first operation timing signal tCCD1 as the selection operation timing signal tCCD-S. When the temperature code TCD[1:0] including the second bit group is received, the temperature control circuit 115 selects the second operation timing signal tCCD2 received at the second input terminal "1" to output the second operation timing signal tCCD2 as the selection operation timing signal tCCD-S. When the temperature code TCD[1:0] including the third bit group is received, the temperature control circuit 115 selects the third operation timing signal tCCD3 received at the third input terminal "2" to output the third operation timing signal tCCD3 as the selection operation timing signal tCCD-S. When the temperature code TCD[1:0], including the fourth bit group, is received, the temperature control circuit 115 selects the fourth operation timing signal tCCD4 received at the fourth input terminal "3" to output the fourth operation timing signal tCCD4 as a selection operation timing signal tCCD-S. In this example, the first operation timing signal tCCD1 is generated based on tCCD, where tCCD is a basic timing value or a time interval between consecutive column commands or the time between executing consecutive column operations; the second operation timing signal tCCD2 is generated based on 1.5 times the basic timing value or 1.5 times tCCD as the time interval between consecutive column commands; the third operation timing signal tCCD3 is generated based on 2 times the basic timing value or 2 times tCCD as the time interval between consecutive column commands; and the fourth operation timing signal tCCD4 is generated based on 2.5 times the basic timing value or 2.5 times tCCD as the time interval between consecutive column commands. This disclosure is not limited to this example.

[0036] Figure 5 A temperature control circuit 115 according to an embodiment of the present disclosure is shown.

[0037] See Figure 5The temperature control circuit 115 includes a selector 25, which generates a selection operation timing signal tRRD-S based on the temperature code TCD[1:0] from the first operation timing signal tRRD1, the second operation timing signal tRRD2, the third operation timing signal tRRD3, and the fourth operation timing signal tRRD4. The selector 25 receives the first operation timing signal tRRD1 through the first input terminal "0", the second operation timing signal tRRD2 through the second input terminal "1", the third operation timing signal tRRD3 through the third input terminal "2", and the fourth operation timing signal tRRD4 through the fourth input terminal "3". The bit group including the temperature code TCD[1:0] corresponds to one of the internal temperature and internal temperature range of the memory device 10. When the temperature code TCD[1:0] including the first bit group is received, the temperature control circuit 115 selects the first operation timing signal tRRD1 received at the first input terminal "0" to output the first operation timing signal tRRD1 as the selection operation timing signal tRRD-S. When the temperature code TCD[1:0] including the second bit group is received, the temperature control circuit 115 selects the second operation timing signal tRRD2 received at the second input terminal "1" to output the second operation timing signal tRRD2 as the selection operation timing signal tRRD-S. When the temperature code TCD[1:0] including the third bit group is received, the temperature control circuit 115 selects the third operation timing signal tRRD3 received at the third input terminal "2" to output the third operation timing signal tRRD3 as the selection operation timing signal tRRD-S. When the temperature code TCD[1:0] including the fourth bit group is received, the temperature control circuit 115 selects the fourth operation timing signal tRRD4 received at the fourth input terminal "3" to output the fourth operation timing signal tRRD4 as a selection operation timing signal tRRD-S. In this example, the first operation timing signal tRRD1 is generated based on tRRD, where tRRD is a basic timing value or a time interval or time between consecutive line commands, or the time between executing consecutive line operations. The second operation timing signal tRRD2 is generated with 1.5 times the basic timing value or 1.5 times tRRD as the time between consecutive line commands. The third operation timing signal tRRD3 is generated with twice the basic timing value or twice tRRD as the time between consecutive line commands. The fourth operation timing signal tRRD4 is generated with 2.5 times the basic timing value or 2.5 times tRRD as the time between consecutive line commands. This disclosure is not limited to these examples.

[0038] Figure 6 A temperature control circuit 115 according to an embodiment of the present disclosure is shown.

[0039] like Figure 6As shown, the temperature control circuit 115 includes a first selector 27 and a second selector 29.

[0040] The first selector 27 generates a selected read operation timing signal tCCD-RDS based on the temperature code TCD[1:0] from the first read operation timing signal tCCD1-RD, the second read operation timing signal tCCD2-RD, the third read operation timing signal tCCD3-RD, and the fourth read operation timing signal tCCD4-RD. The first selector 27 receives the first read operation timing signal tCCD1-RD through the first input terminal "0", the second read operation timing signal tCCD2-RD through the second input terminal "1", the third read operation timing signal tCCD3-RD through the third input terminal "2", and the fourth read operation timing signal tCCD4-RD through the fourth input terminal "3". When the temperature code TCD[1:0] including the first bit group is received, the first selector 27 selects the first read operation timing signal tCCD1-RD received at the first input terminal "0" to output the first read operation timing signal tCCD1-RD as the selected read operation timing signal tCCD-RDS. When the temperature code TCD[1:0] including the second bit group is received, the first selector 27 selects the second read operation timing signal tCCD2-RD received at the second input terminal "1" to output the second read operation timing signal tCCD2-RD as the selected read operation timing signal tCCD-RDS. When the temperature code TCD[1:0] including the third bit group is received, the first selector 27 selects the third read operation timing signal tCCD3-RD received at the third input terminal "2" to output the third read operation timing signal tCCD3-RD as the selected read operation timing signal tCCD-RDS. When the temperature code TCD[1:0] including the fourth bit group is received, the first selector 27 selects the fourth read operation timing signal tCCD4-RD received at the fourth input terminal "3" to output the fourth read operation timing signal tCCD4-RD as the selected read operation timing signal tCCD-RDS. In this example, the first read operation timing signal tCCD1-RD is generated based on tCCD, which is the basic read timing value, the time interval between consecutive read commands, or the time between consecutive read operations. The second read operation timing signal tCCD2-RD is generated based on 1.5 times the basic read timing value or 1.5 times tCCD as the time between consecutive read commands. The third read operation timing signal tCCD3-RD is generated based on twice the basic read timing value or twice tCCD as the time between consecutive read commands. The fourth read operation timing signal tCCD4-RD is generated based on 2.5 times the basic read timing value or 2.5 times tCCD as the time between consecutive read commands. This disclosure is not limited to this example.

[0041] The second selector 29 generates a selected write operation timing signal tCCD-WTS based on the temperature code TCD[1:0] from the first write operation timing signal tCCD1-WT, the second write operation timing signal tCCD2-WT, the third write operation timing signal tCCD3-WT, and the fourth write operation timing signal tCCD4-WT. The second selector 29 receives the first write operation timing signal tCCD1-WT through the first input terminal "0", the second write operation timing signal tCCD2-WT through the second input terminal "1", the third write operation timing signal tCCD3-WT through the third input terminal "2", and the fourth write operation timing signal tCCD4-WT through the fourth input terminal "3". When the temperature code TCD[1:0] including the first bit group is received, the second selector 29 selects the first write operation timing signal tCCD1-WT received at the first input terminal "0" to output the first write operation timing signal tCCD1-WT as the selected write operation timing signal tCCD-WTS. When the temperature code TCD[1:0] including the second bit group is received, the second selector 29 selects the second write operation timing signal tCCD2-WT received at the second input terminal "1" to output the second write operation timing signal tCCD2-WT as the selected write operation timing signal tCCD-WTS. When the temperature code TCD[1:0] including the third bit group is received, the second selector 29 selects the third write operation timing signal tCCD3-WT received at the third input terminal "2" to output the third write operation timing signal tCCD3-WT as the selected write operation timing signal tCCD-WTS. When the temperature code TCD[1:0] including the fourth bit group is received, the second selector 29 selects the fourth write operation timing signal tCCD4-WT received at the fourth input terminal "3" to output the fourth write operation timing signal tCCD4-WT as the selected write operation timing signal tCCD-WTS. In this example, the first write operation timing signal tCCD1-WT is generated based on tCCD, which is the basic write timing value, the time interval between consecutive write commands, or the time between consecutive write operations. The second write operation timing signal tCCD2-WT is generated based on 1.5 times the basic write timing value or 1.5 times tCCD as the time between consecutive write commands. The third write operation timing signal tCCD3-WT is generated based on twice the basic write timing value or twice tCCD as the time between consecutive write commands. The fourth write operation timing signal tCCD4-WT is generated based on 2.5 times the basic write timing value or 2.5 times tCCD as the time between consecutive write commands. This disclosure is not limited to this example.

[0042] Figure 7A block diagram illustrating a stacked storage system 3 according to an embodiment of the present disclosure. (See attached diagram.) Figure 7 As shown, the stacked memory system 3 includes a first stacked memory device 3100, a second stacked memory device 3200, a processor 3300, an interposer 3400, and a substrate 3500.

[0043] An interposer layer 3400 is disposed above or on the substrate 3500, and a first stacked memory device 3100, a second stacked memory device 3200, and a processor 3300 are disposed on the interposer layer 3400. The processor 3300 is disposed between the first stacked memory device 3100 and the second stacked memory device 3200. The interposer layer 3400 electrically connects the substrate 3500, the first stacked memory device 3100, the second stacked memory device 3200, and the processor 3300 to each other. Because the spacing between the first stacked memory device 3100, the second stacked memory device 3200, and the processor 3300 varies considerably, they can be electrically connected using various types of wires.

[0044] Processor 3300 includes a first controller 3310 for controlling a first stacked memory device 3100 and a first processing interface circuit 3320 electrically connecting the first stacked memory device 3100 to the first controller 3310. Processor 3300 also includes a second controller 3330 for controlling a second stacked memory device 3200 and a second processing interface circuit 3340 electrically connecting the second stacked memory device 3200 to the second controller 3330. Processor 3300 provides signals including commands and addresses for controlling various internal operations of the first stacked memory device 3100 to the first stacked memory device 3100 via the first processing interface circuit 3320, and receives signals from the first stacked memory device 3100 via the first processing interface circuit 3320. Processor 3300 provides signals including commands and addresses for controlling various internal operations of the second stacked memory device 3200 to the second stacked memory device 3200 via the second processing interface circuit 3340, and receives signals from the second stacked memory device 3200 via the second processing interface circuit 3340.

[0045] The first stacked memory device 3100 includes a first base chip 3110 and first slice chips 3120, 3130, 3140, and 3150. The first stacked memory device 3100 can be coupled with… Figure 1The illustrated memory device 10 is similarly implemented. First slice chips 3120, 3130, 3140, and 3150 are sequentially stacked on or above the first base chip 3110 and receive various signals from the first base chip 3110 via through-holes. Figure 7 As shown, the first stacked memory device 3100 includes four first slice chips 3120, 3130, 3140 and 3150, which can be arranged and stacked with different numbers of slice chips, such as 4 slice chips, 8 slice chips, 12 slice chips, 16 slice chips, etc.

[0046] The first base chip 3110 includes a first core interface circuit 3111. The first core interface circuit 3111 is configured to communicate with a first processing interface circuit 3320 to receive signals sent from the processor 3300 and to provide signals generated by the first slice chips 3120, 3130, 3140, and 3150 to the processor 3300. The first base chip 3110 includes a temperature control circuit that controls the operating timing of the first stacked memory device 3100 based on the internal temperature of the storage system 3 (e.g., the internal temperature of the first stacked memory device 3100). The temperature control circuit may be similar to... Figure 1 The temperature control circuit 115 shown is used to implement this. Alternatively, one or more temperature control circuits may be located elsewhere in the storage system 3.

[0047] The second stacked memory device 3200 includes a second base chip 3210 and second slice chips 3220, 3230, 3240, and 3250. The second stacked memory device 3200 can be similar to... Figure 1 The memory device 1 shown is used to implement this. Second slice chips 3220, 3230, 3240, and 3250 are sequentially stacked on or above the second base chip 3210 to receive various signals from the second base chip 3210 via vias. In Figure 7, the second stacked memory device 3200 shown includes four second slice chips 3220, 3230, 3240, and 3250, but different numbers of slice chips can be arranged and stacked, such as 4 slice chips, 8 slice chips, 12 slice chips, 16 slice chips, etc.

[0048] The second base chip 3210 includes a second core interface circuit 3211. The second core interface circuit 3211 is configured to communicate with the second processing interface circuit 3340 to receive signals sent from the processor 3300 and to provide signals generated by the second slice chips 3220, 3230, 3240, and 3250 to the processor 3300. The second base chip 3210 may include a temperature control circuit that controls the operating timing of the second stacked memory device 3200 based on the internal temperature of the storage system 3 (e.g., the internal temperature of the second stacked memory device 3200). The temperature control circuit may be similar to... Figure 1 The temperature control circuit 115 shown is used to achieve this.

[0049] The concept has been disclosed in conjunction with various examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and concept of this disclosure. The embodiments disclosed in this specification should be considered illustratively and not restrictively. The scope of this disclosure is not limited to the description, and all distinguishing features within the equivalent scope should be interpreted as being included in this disclosure. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A memory device, comprising: Memory chips; as well as A base chip on which the memory chip is stacked, the base chip including a temperature control circuit that controls the time between consecutive column commands when consecutive column operations are performed based on information including the internal temperature of the memory device.

2. The memory device according to claim 1, wherein, The information including the internal temperature includes a temperature code generated from a temperature sensor located in at least one of the base chip and the memory chip.

3. The memory device according to claim 2, wherein, One of the multiple bit groups is included in the temperature code and corresponds to the internal temperature of the memory device.

4. The memory device according to claim 2, wherein, One of the multiple bit groups is included in the temperature code and corresponds to the internal temperature range of the memory device.

5. The memory device according to claim 1, wherein, The temperature control circuit selects one of the first, second, and third operation timing signals as the selected operation timing signal output based on the temperature code.

6. The memory device according to claim 5, wherein, The temperature control circuit: When the temperature code for the first bit group is received, the first operation timing signal is selected and the first operation timing signal is output as the selected operation timing signal. When the temperature code for the second bit group is received, the second operation timing signal is selected and the second operation timing signal is output as the selected operation timing signal. as well as When the temperature code for the third bit group is received, the third operation timing signal is selected and output as the selection operation timing signal.

7. The memory device according to claim 5, wherein, The temperature control circuit: The first operation timing signal is received based on the basic timing value; The second operation timing signal is received based on 1.5 times the basic timing value; as well as The third operation timing signal is received based on twice the basic timing value.

8. The memory device according to claim 1, wherein, The basic chip also includes: A physical channel that controls the generation, transmission, reception, and physical connection of signals and data between the processor and the memory device; A storage controller that manages data transfer between the processor and the memory device; TSV physical channels, which send and receive signals and data via TSVs connected to the memory chip, where TSV stands for Through Silicon Via; and A test circuit that performs tests on the memory chip.

9. The memory device according to claim 1, wherein, The column operations are either read or write operations.

10. The memory device according to claim 1, wherein, The temperature control circuit controls the second time between consecutive line commands when consecutive line operations are executed, based on the information including the internal temperature.

11. The memory device according to claim 10, wherein, The row operation is an activation operation.

12. A memory device, comprising: Memory chips; as well as A base chip on which the memory chip is stacked, the base chip including a temperature control circuit that controls the time between consecutive line commands when consecutive line operations are performed based on information including the internal temperature of the memory device.

13. The memory device according to claim 12, wherein, The information including the internal temperature includes a temperature code generated from a temperature sensor located in at least one of the base chip and the memory chip.

14. The memory device according to claim 13, wherein, One of the multiple bit groups is included in the temperature code and corresponds to one of the internal temperature of the memory device and the internal temperature range of the memory device.

15. A memory device, comprising: Memory chips; A base chip, on which the memory chip is stacked, the base chip includes a temperature control circuit, the temperature control circuit comprising: A first selector, which: controls the read time between consecutive read commands when a consecutive read operation is performed, based on information including the internal temperature of the memory device; and The second selector controls the write time between consecutive write commands when a consecutive write operation is performed, based on information including the internal temperature of the memory device.

16. The memory device according to claim 15, wherein, The information including the internal temperature includes a temperature code generated from a temperature sensor located in at least one of the base chip and the memory chip.

17. The memory device according to claim 16, wherein, One of the multiple bit groups is included in the temperature code and corresponds to the internal temperature of the memory device.

18. The memory device according to claim 15, wherein, The first selector selects one of the first read operation timing signal, the second read operation timing signal, and the third read operation timing signal based on the temperature code as the selected read operation timing signal output.

19. The memory device according to claim 15, wherein, The second selector selects one of the first write operation timing signal, the second write operation timing signal, and the third write operation timing signal based on the temperature code as the selected write operation timing signal output.

20. The memory device according to claim 15, wherein, The basic chip also includes: A physical channel, which controls the generation, transmission, reception, and physical connection of signals and data between the processor and the memory device; A storage controller that manages data transfer between the processor and the memory device; TSV physical channels, which send and receive signals and data via TSVs connected to the memory chip, where TSV stands for Through Silicon Via; and A test circuit that performs tests on the memory chip.

21. A method for a memory device, comprising: Determine the internal temperature of a memory device, the memory device comprising memory chips and base chips stacked on top of each other; The time interval between consecutive operation commands is identified based on the internal temperature. as well as The timing between operation commands of the memory device is controlled based on the time interval during operation of the memory device.

Images