Memory device

Abstract

A memory device includes a logic die configured to communicate with a host device through a plurality of channels, each channel of the plurality of channels including a separate interface; and a plurality of memory dies stacked on the logic die, each memory die of the plurality of memory dies including a memory cell array corresponding to at least one channel of the plurality of channels, where the logic die includes: a first pin configured to receive a clock signal having a first clock frequency; a second pin configured to receive a write command / address signal based on the clock signal; a third pin configured to receive a write strobe signal having a second clock frequency; and a DQ pin configured to receive a write data signal based on a plurality of internal write data strobe signals, the plurality of internal write data strobe signals being based on the write strobe signal.

Description

[0001] This application is a divisional application of application No. 202110075443.7, filed on January 20, 2021, entitled "Memory device transmitting and receiving data at high speed and low power." TECHNICAL FIELD

[0002] Embodiments relate to a semiconductor device, and more particularly, to a memory device transmitting and receiving data at high speed and low power. BACKGROUND

[0003] Electronic devices such as smartphones, graphics accelerators, and artificial intelligence (AI) accelerators process data by using a memory device such as a dynamic random access memory (DRAM). As the amount of data to be processed by electronic devices increases, a memory device with high capacity and high bandwidth is required. In particular, a memory device providing a wide input / output in a multi-channel interface manner, such as a high bandwidth memory, is increasingly used for the purpose of processing data at high speed.

[0004] When a memory device supports high bandwidth, data can be transmitted at high speed between a memory controller and the memory device. To ensure the integrity of data when data is transmitted at high speed, a data strobe signal can be exchanged between the memory controller and the memory device. When a data signal is transmitted between the memory controller and the memory device, the data strobe signal can be periodically toggled between a high level and a low level. As such, the data strobe signal can provide timing information for latching a level of the data signal. That is, in the case of transmitting data at high speed, a data strobe signal with a high frequency can be required. However, data exchange based on a data strobe signal with a high frequency can cause an increase in power consumption of the memory device. SUMMARY

[0005] One aspect is to provide a memory device transmitting and receiving data at high speed and low power.

[0006] According to an aspect of an example embodiment, there is provided a memory device including a buffer die configured to communicate with a host device through a plurality of channels each constituting an independent interface, and a plurality of core dies stacked on the buffer die through a through-silicon via, each of the plurality of core dies including an array of memory cells corresponding to at least one of the plurality of channels. The buffer die includes a command / address receiver configured to receive a command provided from the host device to a first channel of the plurality of channels based on a clock signal provided from the host device to the first channel, a control logic circuit configured to generate an internal command depending on the command received from the command / address receiver and a reset signal before a write data strobe signal provided from the host device to the first channel starts to toggle, a write data strobe signal divider configured to generate a plurality of internal write data strobe signals toggling depending on toggling of the write data strobe signal, the plurality of internal write data strobe signals toggling at different phases, respectively, and configured to initialize the plurality of internal write data strobe signals to a given value in response to the reset signal, and a data transceiver configured to receive write data provided from the host device to the first channel based on the plurality of internal write data strobe signals, wherein a core die of the plurality of core dies supporting the first channel is configured to store the write data transmitted from the buffer die in response to the internal command transmitted from the buffer die.

[0007] According to still another aspect of example embodiments, there is provided a memory device including a buffer die configured to communicate with a host device through a plurality of channels each constituting an independent interface, and a first core die stacked on the buffer die by a through-silicon via and including a first memory cell array corresponding to a first channel of the plurality of channels, and a second core die stacked on the first core die by a through-silicon via and including a second memory cell array corresponding to the first channel. The buffer die includes a command / address receiver configured to receive a command and a stack identifier provided from the host device to the first channel based on a clock signal provided from the host device to the first channel, a control logic circuit configured to generate an internal command depending on the command received from the command / address receiver and a reset signal before a write data strobe signal provided from the host device to the first channel starts to toggle, a write data strobe signal divider configured to generate a plurality of internal write data strobe signals toggling depending on toggling of the write data strobe signal, the plurality of internal write data strobe signals toggling at different phases, respectively, and configured to initialize the plurality of internal write data strobe signals to a given value in response to the reset signal, and a data transceiver configured to receive write data provided from the host device to the first channel based on the plurality of internal write data strobe signals, wherein a core die corresponding to the stack identifier among the first core die and the second core die is configured to store the write data transmitted from the buffer die in response to the internal command transmitted from the buffer die.

[0008] According to still another aspect of example embodiments, there is provided a memory device including a buffer die configured to communicate with a host device through a plurality of channels each constituting an independent interface, and a first core die stacked on the buffer die by a through-silicon via and including a first memory cell array corresponding to a first channel of the plurality of channels, and a second core die stacked on the first core die by a through-silicon via and including a second memory cell array corresponding to the first channel. The buffer die includes a command / address receiver configured to receive a command and a stack identifier provided from the host device to the first channel based on a clock signal provided from the host device to the first channel, a control logic circuit configured to generate an internal command depending on the command received from the command / address receiver and a reset signal before a write data strobe signal provided from the host device to the first channel starts to toggle, a write data strobe signal divider configured to generate a plurality of internal write data strobe signals toggling depending on toggling of the write data strobe signal, the plurality of internal write data strobe signals toggling at different phases, respectively, and configured to initialize the plurality of internal write data strobe signals to a given value in response to the reset signal, and a data transceiver configured to receive write data provided from the host device to the first channel based on the plurality of internal write data strobe signals, wherein a core die corresponding to the stack identifier among the first core die and the second core die is configured to store the write data transmitted from the buffer die in response to the internal command transmitted from the buffer die.

[0009] According to yet another aspect of example embodiments, there is provided a semiconductor package including a package substrate, a interposer substrate stacked on the package substrate, a system on chip stacked on the interposer substrate and including at least one processor and a memory controller, and a memory device including a buffer die stacked on the interposer substrate and in communication with the system on chip through the interposer substrate and a plurality of core dies stacked on the buffer die through a through silicon via. The buffer die is configured to receive a write command provided from the memory controller based on a clock signal provided from the memory controller, initialize a plurality of internal write data strobe signals to a given value before a write data strobe signal provided from the memory controller is toggled, generate the plurality of internal write data strobe signals depending on a toggle of the write data strobe signal, the plurality of internal write data strobe signals toggling at different phases, and receive write data provided from the memory controller based on the plurality of internal write data strobe signals. One of the plurality of core dies stores the received write data. A sum of a number of a leading period of the write data strobe signal and a number of a trailing period of the write data strobe signal is even. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other aspects will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings, in which:

[0011] Figure 1 is a block diagram illustrating a memory system according to an embodiment;

[0012] Figure 2 is an example block diagram of a memory device of Figure 1 ;

[0013] Figure 3 is a table indicating example conditions for generating a reset signal by a control logic circuit of a memory device of Figure 2 ;

[0014] Figure 4 is a flowchart illustrating an example write operation of a memory device according to an embodiment;

[0015] Figure 5A and Figure 5B is a timing diagram illustrating an example of a write operation of Figure 4 ;

[0016] Figure 6 is a flowchart illustrating an example write operation of a memory device according to an embodiment;

[0017] Figure 7A and Figure 7B is a timing diagram illustrating an example of a write operation of Figure 6 ;

[0018] Figure 8is a flowchart illustrating an exemplary read operation of a memory device according to an embodiment;

[0019] Figure 9 is a timing diagram illustrating an example of a read operation of Figure 8 ;

[0020] Figure 10A and Figure 10B is a block diagram illustrating a write data strobe signal (WDQS) divider according to various embodiments;

[0021] Figure 11 is an exemplary block diagram illustrating a memory interface of a memory system of Figure 1 according to an embodiment;

[0022] Figure 12 is a block diagram illustrating a stacked memory device according to various embodiments;

[0023] Figure 13 is an exemplary more detailed block diagram illustrating a stacked memory device of Figure 12 according to an embodiment;

[0024] Figure 14 is an exemplary more detailed block diagram illustrating a stacked memory device of Figure 12 according to an embodiment; and

[0025] Figure 15 is a block diagram illustrating an embodiment of a buffer die of a stacked memory device of Figure 13 ;

[0026] Figure 16 is a diagram illustrating a semiconductor package according to an embodiment;

[0027] Figure 17 is a diagram illustrating an implementation example of a semiconductor package according to an embodiment;

[0028] Figure 18 is a diagram illustrating a semiconductor package according to another embodiment; and

[0029] Figure 19 is a block diagram illustrating a computing system according to an embodiment. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments will be described in detail with sufficient technical details so that those of ordinary skill in the art to which the disclosure pertains can easily implement the embodiments of the disclosure.

[0031] Figure 1 is a block diagram illustrating a memory system according to an embodiment. Referring to Figure 1The memory system 10 can include a memory controller 100 and a memory device 200. The memory controller 100 can control overall operations of the memory device 200. For example, the memory controller 100 can control the memory device 200 so that data is output from or stored in the memory device 200. For example, the memory controller 100 can be implemented as a part of a system on chip (SoC), but is not limited thereto.

[0032] The memory controller 100 can include a memory interface (I / F) 110. Through the memory interface 110, the memory controller 100 can transmit various signals to the memory device 200 and can receive various signals from the memory device 200. For example, as shown in FIG. 1, through the memory interface 110, the memory controller 100 can transmit a clock signal CK, a command / address signal C / A, a write data strobe signal WDQS, and a data signal DQ to the memory device 200, and can receive a read data strobe signal RDQS and a data signal DQ from the memory device 200. Figure 1

[0033] The memory device 200 can operate under the control of the memory controller 100. For example, under the control of the memory controller 100, the memory device 200 can output stored data or can store data provided from the memory controller 100.

[0034] The memory device 200 can include a host interface (I / F) 210 and a memory cell array 220. Through the host interface 210, the memory device 200 can transmit various signals to the memory controller 100 and can receive various signals from the memory controller 100. For example, through the host interface 210, the memory device 200 can transmit a read data strobe signal RDQS and a data signal DQ to the memory controller 100, and can receive a clock signal CK, a command / address signal C / A, a write data strobe signal WDQS, and a data signal DQ from the memory controller 100. The host interface 210 can generate a control signal iCTRL based on the signals provided from the memory controller 100. In response to the control signal iCTRL, the memory cell array 220 can store data "DATA" or can output stored data "DATA".

[0035] ​The array of memory cells 220 can include a plurality of memory cells. For example, the memory cells can be dynamic random access memory (DRAM) cells. In this case, the memory interface 110 and the host interface 210 can communicate with each other based on one of standards such as double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), wide I / O, high bandwidth memory (HBM), and / or hybrid memory cube (HMC).

[0036] The memory interface 110 can generate a clock signal CK and can transmit the clock signal CK to the memory device 200. In some embodiments, the clock signal CK can be a differential signal. The clock signal CK can be a signal that periodically toggles between a high level and a low level. The memory interface 110 can transmit a command / address signal C / A to the memory device 200 based on a toggle timing of the clock signal CK.

[0037] The memory interface 110 can generate a write data strobe signal WDQS and can transmit the write data strobe signal WDQS to the memory device 200. In some embodiments, the write data strobe signal WDQS can be a differential signal. For a write operation and a read operation of the memory device 200, the memory interface 110 can generate the write data strobe signal WDQS that periodically toggles between a high level and a low level. The memory interface 110 can transmit a data signal DQ to the memory device 200 based on a toggle timing of the write data strobe signal WDQS.

[0038] The memory interface 110 can receive a read data strobe signal RDQS from the memory device 200. In some embodiments, the read data strobe signal RDQS can be a differential signal. The memory interface 110 can receive a data signal DQ from the memory device 200 and can latch the received data signal DQ based on a toggle timing of the read data strobe signal RDQS. As such, the memory interface 110 can receive data "DATA" included in the data signal DQ.

[0039] The host interface 210 can receive the clock signal CK from the memory controller 100. The host interface 210 can receive the command / address signal C / A from the memory controller 100 and can latch the command / address signal C / A based on a toggle timing (e.g., a rising edge and / or a falling edge) of the clock signal CK. As such, the host interface 210 can receive a command or an address included in the command / address signal C / A.

[0040] In Figure 1An example is shown in which commands and addresses are transmitted from the memory controller 100 to the memory device 200 using the same input / output channel, but embodiments are not limited thereto. For example, in some embodiments, commands and addresses can be transmitted from the memory controller 100 to the memory device 200 using different input / output channels.

[0041] The host interface 210 can receive a write data strobe signal WDQS from the memory controller 100. The host interface 210 can receive a data signal DQ and can latch the data signal DQ based on a toggling timing (e.g., rising edge and / or falling edge) of the write data strobe signal WDQS. In this way, the host interface 210 can receive data "DATA" included in the data signal DQ.

[0042] The host interface 210 can generate a read data strobe signal RDQS and can transmit the read data strobe signal RDQS to the memory controller 100. The host interface 210 can generate the read data strobe signal RDQS that periodically toggles between a high level and a low level in a read operation of the memory device 200. In an exemplary embodiment, the host interface 210 can generate the read data strobe signal RDQS based on the write data strobe signal WDQS received from the memory controller 100. The host interface 210 can transmit the data signal DQ to the memory controller 100 based on a toggling timing of the read data strobe signal RDQS.

[0043] In an exemplary embodiment, each of the write data strobe signal WDQS and the read data strobe signal RDQS can have a frequency twice as high as a frequency of the clock signal CK. When the data signal DQ is transmitted based on the data strobe signals WDQS and RDQS, the memory controller 100 and the memory device 200 can transmit and receive data at a high speed.

[0044] Figure 2 is an exemplary block diagram of a memory device of the memory system of Figure 1 Referring to Figure 2 , the memory device 200 can include a command / address (CA) receiver 211, a control logic circuit 212, a write data strobe signal (WDQS) divider 213, a read data strobe signal (RDQS) transmitter 214, a data transceiver 215, and a memory cell array 220. In some embodiments, the C / A receiver 211, the control logic circuit 212, the WDQS divider 213, the RDQS transmitter 214, and the data transceiver 215 can be included in the host interface 210 of Figure 1 .

[0045] The C / A receiver 211 can receive a command CMD by latching the command / address signal C / A based on the clock signal CK. The received command CMD can be provided to the control logic circuit 212. Although Figure 2 The C / A receiver 211 can receive an address by latching the command / address signal C / A based on the clock signal CK, although not shown. The received address can be provided to an address register placed inside or outside the control logic circuit 212 to be decoded.

[0046] The control logic circuit 212 can decode the received command CMD and can generate a control signal for controlling any other component of the memory device 200 depending on the result of decoding the command CMD. For example, the control logic circuit 212 can generate a control signal iCTRL for storing or outputting data "DATA" in or from the memory cell array 220 based on the result of decoding the command CMD. For example, the control logic circuit 212 can generate a reset signal RESET for resetting the WDQS divider 213 based on the result of decoding the command CMD.

[0047] The control logic circuit 212 can receive power state information PWS of the memory device 200. For example, in some embodiments, the control logic circuit 212 can receive the power state information PWS from outside of the memory device 200 or from outside of the memory system 10 (e.g., from a host device). In other embodiments, the power state information PWS can be generated by the memory device 200. For example, the power state information PWS can include voltage information provided to or generated by the memory device 200. The control logic circuit 212 can determine a power state of the memory device 200 based on the power state information PWS. For example, based on the power state information PWS, the control logic circuit 212 can determine whether the memory device 200 is in a power-up state or the memory device 200 is in a power-down exit state.

[0048] The control logic circuit 212 can generate a reset signal RESET for resetting the WDQS divider 213. The control logic circuit 212 can generate the reset signal RESET before a write data strobe signal WDQS provided from the memory controller 100 flips. In some example embodiments, the control logic circuit 212 can generate the reset signal RESET based on the command CMD or the power state information PWS. The condition for generating the reset signal RESET by the control logic circuit 212 will be described more fully. Figure 3 The condition for generating the reset signal RESET by the control logic circuit 212 will be described more fully.

[0049] The WDQS divider 213 can generate a plurality of internal write data strobe signals dWDQS based on the write data strobe signal WDQS. In detail, the WDQS divider 213 can generate the internal write data strobe signals dWDQS that flip depending on a flip of the write data strobe signal WDQS. The WDQS divider 213 can divide a frequency of the write data strobe signal WDQS to generate the internal write data strobe signals dWDQS having different phases. For example, the WDQS divider 213 can halve the frequency of the write data strobe signal WDQS to generate four internal write data strobe signals dWDQS having different phases. In this case, the phases of the internal write data strobe signals dWDQS can be 0 degree, 90 degree, 180 degree, and 270 degree.

[0050] The WDQS divider 213 can initialize the internal write data strobe signals dWDQS to a given value in response to a reset signal RESET before the write data strobe signal WDQS flips. Each of the internal write data strobe signals dWDQS can be initialized to a given value (hereinafter referred to as a "reset value") of a high level or a low level. In an exemplary embodiment, the WDQS divider 213 can initialize one half of the internal write data strobe signals dWDQS to a low level and can initialize the other half to a high level. The internal write data strobe signals dWDQS can maintain the reset value until the write data strobe signal WDQS flips.

[0051] In a case where the internal write data strobe signals dWDQS are maintained at the reset value depending on the reset operation, the WDQS divider 213 can generate the internal write data strobe signals dWDQS having desired phases. As such, the memory device 200 can not separately perform an auto synchronization for synchronizing the internal write data strobe signals dWDQS with phases of the clock signal CK.

[0052] The RDQS transmitter 214 can generate a read data strobe signal RDQS based on the internal write data strobe signals dWDQS and can transmit the read data strobe signal RDQS to the memory controller 100. For example, the RDQS transmitter 214 can transmit the read data strobe signal RDQS based on rising edges and / or falling edges of the internal write data strobe signals dWDQS. A frequency of the read data strobe signal RDQS transmitted to the memory controller 100 can be equal to a frequency of the write data strobe signal WDQS.

[0053] The data transceiver 215 can transmit and receive a data signal DQ including data "DATA" based on an internal write data strobe signal dWDQS. In a write operation, the data transceiver 215 can receive the data "DATA" by latching the data signal DQ based on the internal write data strobe signal dWDQS. For example, the data transceiver 215 can latch the data signal DQ received from the memory controller 100 based on a rising edge and / or a falling edge of the internal write data strobe signal dWDQS. The received data "DATA" can be provided to and stored in the memory cell array 220. In an exemplary embodiment, when the data "DATA" is transferred to the memory cell array 220, the data "DATA" can be transferred based on a flip timing of a clock signal CK. That is, in a case where the data "DATA" is transferred to the memory cell array 220, a domain can be changed from a domain of a write data strobe signal WDQS to a domain of the clock signal CK.

[0054] In a read operation, the data transceiver 215 can transmit a data signal DQ including data "DATA" to the memory controller 100 based on an internal write data strobe signal dWDQS. The data "DATA" can be read from the memory cell array 220. For example, the data transceiver 215 can transmit the data "DATA" based on a rising edge and / or a falling edge of the internal write data strobe signal dWDQS. As such, the data "DATA" can be aligned with a flip timing of a read data strobe signal RDQS and can be transmitted to the memory controller 100. In an exemplary embodiment, when the data "DATA" is read from the memory cell array 220, the data "DATA" can be read based on a flip timing of a clock signal CK. The data transceiver 215 can align the read data "DATA" with the flip timing of the read data strobe signal RDQS to be transmitted to the memory controller 100. That is, in a case where the data "DATA" is transmitted to the memory controller 100, a domain can be changed from a domain of the clock signal CK to a domain of the read data strobe signal RDQS (i.e., a domain of the write data strobe signal WDQS).

[0055] As described above, the memory device 200 can initialize the internal write data strobe signal dWDQS to a given value before the write data strobe signal WDQS flips. In this case, the internal write data strobe signal dWDQS generated at the time when the write data strobe signal WDQS flips can have a desired phase. In the case where the internal write data strobe signal dWDQS has the desired phase, the memory device 200 can transmit and receive data "DATA" based on the internal write data strobe signal dWDQS. As such, the memory device 200 can not separately perform auto synchronization for adjusting the phase of the internal write data strobe signal dWDQS. In the case where auto synchronization is not separately performed, the memory device 200 can not receive a separate command for auto synchronization and can not include a separate circuit for auto synchronization. In other words, a separate command for auto synchronization can be omitted, and a separate circuit for auto synchronization can be omitted. As such, power consumption of the memory device 200 can be reduced.

[0056] As described above, the memory device 200 can generate the read data strobe signal RDQS and the data signal DQ based on the internal write data strobe signal dWDQS. Because the internal write data strobe signal dWDQS is generated based on the write data strobe signal WDQS, the read data strobe signal RDQS and the data signal DQ can be generated based on the write data strobe signal WDQS. In this case, compared to the case where the read data strobe signal RDQS and the data signal DQ are generated based on the clock signal CK, power consumption of the memory device 200 can be reduced.

[0057] Figure 3 is to indicate a command for resetting the internal write data strobe signal dWDQS by the memory device 200 Figure 2 is a table of exemplary conditions in which the control logic circuit of the memory device generates the reset signal. Referring to Figure 2 and Figure 3 , the control logic circuit 212 can generate the reset signal RESET depending on at least one of the conditions of the divider reset condition table DRCT. In the case where the command CMD matches the divider reset condition, or in the case where the power state of the memory device 200 determined depending on the power state information PWS matches the divider reset condition, the control logic circuit 212 can generate the reset signal RESET. In this case, the control logic circuit 212 can generate the reset signal RESET before the write data strobe signal WDQS flips.

[0058] In an example embodiment, the control logic circuit 212 can generate the reset signal RESET in a case where the memory device 200 is in a power-up state (i.e., after a power-up sequence of the memory device 200). For example, the control logic circuit 212 can determine whether the memory device 200 is in the power-up state based on a power state of the memory device 200 determined depending on the power state information PWS.

[0059] In an example embodiment, the control logic circuit 212 can generate the reset signal RESET in a case where the memory device 200 is in a power-down exit state (i.e., after a power-down exit sequence of the memory device 200). For example, the control logic circuit 212 can determine whether the memory device 200 is in the power-down exit state based on a power state of the memory device 200 determined depending on the power state information PWS. Further, the control logic circuit 212 can generate the reset signal RESET in response to a command CMD indicating the power-down exit.

[0060] In an example embodiment, the control logic circuit 212 can generate the reset signal RESET in a case where the memory device 200 is in a self-refresh exit state (i.e., after a self-refresh exit sequence of the memory device 200). For example, the control logic circuit 212 can generate the reset signal RESET in response to a command CMD indicating the self-refresh exit.

[0061] In an example embodiment, the control logic circuit 212 can generate the reset signal RESET in response to an active command ACT. For example, the active command ACT can be a command for enabling a selected word line of the memory cell array 220. Alternatively, the control logic circuit 212 can generate the reset signal RESET in response to a write command WR and / or a read command RD.

[0062] In an example embodiment, the control logic circuit 212 can generate the reset signal RESET in response to a divider reset command DR. Here, the divider reset command DR can be a command CMD transmitted from the memory controller 100, and indicates a reset of the WDQS divider 213.

[0063] Figure 4 is a flowchart illustrating an example write operation of a memory device according to an embodiment. Referring to Figure 2 and Figure 4 In operation S201, the memory device 200 can initialize an internal write data strobe signal dWDQS to a given value before the write data strobe signal WDQS is toggled. For example, the memory device 200 can determine the given value depending on the power state of the memory device 200 determined depending on the power state information PWS. Figure 3the reset condition to perform the reset operation. In this way, the internal write data strobe signal dWDQS can remain at the reset value and then start toggling.

[0064] In operation S202, the memory device 200 can generate the internal write data strobe signal dWDQS toggling at a different phase depending on the toggling of the write data strobe signal WDQS. When the internal write data strobe signal dWDQS remains at the reset value and then starts toggling, the memory device 200 can generate the internal write data strobe signal dWDQS having a desired phase.

[0065] In an exemplary embodiment, the sum of the number of pre-amble cycles of the write data strobe signal WDQS and the number of post-amble cycles of the write data strobe signal WDQS can be even when the write data strobe signal WDQS toggles. In this case, even if the toggling of the internal write data strobe signal dWDQS is stopped due to the stop of the toggling of the write data strobe signal WDQS, the internal write data strobe signal dWDQS can remain at the reset value without performing an additional reset action. In this way, in the case where the write data strobe signal WDQS toggles again, the internal write data strobe signal dWDQS having a desired phase can be generated without an additional reset operation.

[0066] In operation S203, the memory device 200 can receive data "DATA" by latching the data signal DQ based on the internal write data strobe signal dWDQS. In operation S204, the memory device 200 can store the received data "DATA" in the memory cell array 220.

[0067] Figure 5A and Figure 5B is a timing diagram illustrating an example of a write operation of Figure 4 Referring to Figure 5A and Figure 5B , the memory device 200 can receive a clock signal CK, a command / address signal C / A including a write command WR, a write data strobe signal WDQS, and a data signal DQ including data D0 to D7. Hereinafter, as illustrated in Figure 5A and Figure 5B , an example will be described that the memory device 200 generates four internal write data strobe signals dWDQS[0] to dWDQS[3] toggling at different phases when the write data strobe signal WDQS toggles, but the number of internal write data strobe signals dWDQS generated by the memory device 200 can be variously determined.

[0068] Referring to Figure 2 and Figure 5AAt a first time t1, the memory device 200 can initialize the internal write data strobe signals dWDQS[0] to dWDQS[3] to a reset value. For example, the memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a low level, and can initialize the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] to a high level.

[0069] For example, as described with reference to Figure 3 the memory device 200 can reset the internal write data strobe signals dWDQS[0] to dWDQS[3] based on the command CMD or the power state of the memory device 200. That is, the memory device 200 can reset the internal write data strobe signals dWDQS[0] to dWDQS[3] based on various reset conditions before the write data strobe signal WDQS starts to toggle.

[0070] At a second time t2, the memory device 200 can receive the command / address signals C / A including a write command WR. The memory device 200 can receive the command CMD by latching the command / address signals C / A based on rising edges and falling edges of the clock signal CK. In Figure 5A the example shown in FIG. 2B, the write command WR is received during two cycles of the command / address signals C / A, but embodiments are not limited thereto.

[0071] The memory device 200 can receive the toggled write data strobe signal WDQS from a third time t3 to a sixth time t6. Before the write data strobe signal WDQS toggles (i.e., before the third time t3), the write data strobe signal WDQS can remain static. For example, the write data strobe signal WDQS can remain at a low level, as shown in Figure 5A The frequency of the write data strobe signal WDQS can be twice the frequency of the clock signal CK. When the write data strobe signal WDQS toggles, the write data strobe signal WDQS can include one leading period and one trailing period. That is, the sum of the number of leading periods of the write data strobe signal WDQS and the number of trailing periods of the write data strobe signal WDQS can be even. In Figure 5A the example shown in FIG. 2B, the trailing of the write data strobe signal WDQS corresponds to a toggle period from the fifth time t5 to the sixth time t6, but embodiments are not limited thereto.

[0072] In a case where the write data strobe signal WDQS is flipped from the third time t3, the memory device 200 can generate the internal write data strobe signals dWDQS[0] to dWDQS[3] having desired phases based on the reset values of the internal write data strobe signals dWDQS[0] to dWDQS[3]. For example, at the third time t3, the memory device 200 can generate the first internal write data strobe signal dWDQS[0] having the same edge timing as that of the write data strobe signal WDQS. The memory device 200 can generate the second internal write data strobe signal dWDQS[1] about which the phase is delayed by 90 degrees from the first internal write data strobe signal dWDQS[0], the third internal write data strobe signal dWDQS[2] about which the phase is delayed by 180 degrees from the first internal write data strobe signal dWDQS[0], and the fourth internal write data strobe signal dWDQS[3] about which the phase is delayed by 270 degrees from the first internal write data strobe signal dWDQS[0]. In this case, the frequency of each of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be half of the frequency of the write data strobe signal WDQS.

[0073] At a fourth time t4 at which the write latency WL elapses from the second time t2 at which the write command WR is received, the memory device 200 can start to receive the data signal DQ including the data D0 to D7. The memory device 200 can receive the data D0 to D7 by latching the data signal DQ based on the internal write data strobe signals dWDQS[0] to dWDQS[3]. For example, the memory device 200 can latch the data signal DQ at the falling edge of each of the internal write data strobe signals dWDQS[0] to dWDQS[3]. In this case, the data D0 and D4 can be received based on the first internal write data strobe signal dWDQS[0], the data D1 and D5 can be received based on the second internal write data strobe signal WDQS[1], the data D2 and D6 can be received based on the third internal write data strobe signal dWDQS[2], and the data D3 and D7 can be received based on the fourth internal write data strobe signal dWDQS[3]. As such, from the fourth time t4 to a fifth time t5, the data D0 to D7 can be received from the data signal DQ.

[0074] Since the toggling of the write data strobe signal WDQS stops at the sixth time t6, the toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] can also stop. Even though the toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] stops, the internal write data strobe signals dWDQS[0] to dWDQS[3] can still have the same value as at the first time t1. Thus, after the sixth time t6, each of the internal write data strobe signals dWDQS[0] to dWDQS[3] can retain its reset value.

[0075] Reference Figure 2 and Figure 5B In some embodiments, the write data strobe signal WDQS may include two preamble periods and two postamble periods. In this case, in order to generate a desired phase (i.e., with respect to the flipping of the write data strobe signal WDQS) Figure 5A The memory device 200 can initialize the internal write data strobe signals dWDQS[0] to dWDQS[3] to the same phase as the internal write data strobe signals dWDQS[0] to dWDQS[3]. Figure 5A The reset values ​​are different. That is, the reset values ​​of the internal write data strobe signals dWDQS[0] to dWDQS[3] (i.e., the reset value of the WDQS divider 213) can be defined by the number of preamble cycles of the write data strobe signal WDQS. Figure 5B The example shown corresponds to the flip period from the fifth time t5 to the sixth time t6, but the embodiment is not limited to this.

[0076] At the first time t1, the memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a high level, and can initialize the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] to a low level. In this case, the internal write data strobe signals dWDQS[0] to dWDQS[3] generated when the write data strobe signal WDQS starts to flip from the third time t3 can have the desired phase. Thus, as referenced Figure 5A The memory device 200 can receive data D0 to D7 by latching the data signal DQ based on the falling edge of the internal write data strobe signals dWDQS[0] to dWDQS[3].

[0077] As described above, the memory device 200 can initialize the internal write data strobe signal dWDQS to a reset value before the write data strobe signal WDQS flips, and can generate the internal write data strobe signal dWDQS having a desired phase. As such, the memory device 200 can not separately perform an auto-sync for adjusting the phase of the internal write data strobe signal dWDQS. That is, the auto-sync can be omitted. Without performing the auto-sync, additional flipping of the write data strobe signal WDQS for the auto-sync can not be needed. That is, since a period in which the write data strobe signal WDQS is held static before the data D0 to D7 is transmitted is increased, the flipping period can be shortened.

[0078] Figure 6 is a flowchart illustrating an exemplary write operation of a memory device according to an embodiment. Referring to Figure 2 and Figure 6 In operation S211, the memory device 200 can initialize the internal write data strobe signal dWDQS to a given value before the write data strobe signal WDQS flips.

[0079] In operation S212, the memory device 200 can generate the internal write data strobe signal dWDQS depending on flipping of the write data strobe signal WDQS corresponding to the first write command and the second write command. In an exemplary embodiment, the memory device 200 can generate the write data strobe signal WDQS corresponding to the first write command and the second write command without an additional reset operation. For example, even if flipping of the write data strobe signal WDQS is stopped between a first flipping period of the write data strobe signal WDQS according to the first write command and a second flipping period of the write data strobe signal WDQS according to the second write command, the memory device 200 can generate the internal write data strobe signal dWDQS without the additional reset operation.

[0080] In operation S213, the memory device 200 can receive first data and second data based on the internal write data strobe signal dWDQS thus generated. Here, the first data can correspond to the first write command, and the second data can correspond to the second write command. In operation S214, the memory device 200 can store the first data and the second data in the memory cell array 220.

[0081] Figure 7A and Figure 7B is a timing diagram illustrating an example of a write operation of Figure 6 Referring to Figure 7A and Figure 7BThe memory device 200 can receive a clock signal CK, command / address signals C / A including a first write command WRa and a second write command WRb, a write data strobe signal WDQS, and data signals DQ including first data Da0 to Da7 and second data Db0 to Db7. In detail, Figure 7A is a timing diagram illustrating a write operation when a gap between the first write command WRa and the second write command WRb is equal to or less than a reference time (i.e., when the first data Da0 to Da7 and the second data Db0 to Db7 are seamless). Figure 7B is a timing diagram illustrating a write operation when a gap between the first write command WRa and the second write command WRb exceeds a reference time (i.e., when the first data Da0 to Da7 and the second data Db0 to Db7 are not seamless). Here, the reference time can be a transmission time of data corresponding to one write command. For example, as shown in Figure 7A and Figure 7B , the reference time can correspond to two cycles of the clock signal CK when the transmission time of data corresponding to one write command corresponds to two cycles of the clock signal CK.

[0082] Referring to Figure 2 and Figure 7A , before the write data strobe signal WDQS flips, that is, at a first time t1, the memory device 200 can initialize a first internal write data strobe signal dWDQS[0] and a second internal write data strobe signal dWDQS[1] to a low level, and can initialize a third internal write data strobe signal dWDQS[2] and a fourth internal write data strobe signal dWDQS[3] to a high level.

[0083] Based on the clock signal CK, the memory device 200 can receive the first write command WRa at a second time t2, and can receive the second write command WRb at a third time t3. For example, in some embodiments, a gap between the first write command WRa and the second write command WRb can be equal to or less than two cycles of the clock signal CK.

[0084] The memory device 200 can receive the flipped write data strobe signal WDQS from a fourth time t4 to an eighth time t8. In this case, the write data strobe signal WDQS can have one flip period (i.e., from the fourth time t4 to the eighth time t8) corresponding to the first write command WRa and the second write command WRb. As such, as shown in Figure 7A , the write data strobe signal WDQS can have one leading and one trailing with respect to both the first write command WRa and the second write command WRb.

[0085] The memory device 200 can generate the first internal write data strobe signal dWDQS[0] having the same edge timing as that of the write data strobe signal WDQS based on the reset values of the internal write data strobe signals dWDQS[1] through dWDQS[3] at the fourth time t4, and can generate the second through fourth internal write data strobe signals dWDQS[1] through dWDQS[3] with phase differences of 90 degrees, 180 degrees, and 270 degrees, respectively, from the first internal write data strobe signal dWDQS[0]. After performing the reset operation at the first time t1, the memory device 200 can generate the internal write data strobe signals dWDQS[0] through dWDQS[3] without an additional reset operation.

[0086] At a fifth time t5, which is the write latency WL from the second time t2 at which the first write command WRa is received, the memory device 200 can start receiving the data signal DQ including the first data Da0 through Da7. At a sixth time t6, which is the write latency WL from the third time t3 at which the second write command WRb is received, the memory device 200 can start receiving the data signal DQ including the second data Db0 through Db7.

[0087] The memory device 200 can receive the first data Da0 through Da7 and the second data Db0 through Db7 by latching the data signal DQ based on the internal write data strobe signals dWDQS[0] through dWDQS[3]. For example, the memory device 200 can latch the data signal DQ at falling edges of each of the internal write data strobe signals dWDQS[0] through dWDQS[3]. As such, from the fifth time t5 to the seventh time t7, the first data Da0 through Da7 and the second data Db0 through Db7 can be received from the data signal DQ.

[0088] Referring to Figure 2 and Figure 7B Before the write data strobe signal WDQS flips, that is, at the first time t1, the memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a low level, and can initialize the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] to a high level.

[0089] Based on the clock signal CK, the memory device 200 can receive the first write command WRa at the second time t2, and can receive the second write command WRb at the third time t3. For example, an interval between the first write command WRa and the second write command WRb can exceed two periods of the clock signal CK.

[0090] The memory device 200 can receive a write data strobe signal WDQS including a toggle period corresponding to the first write command WRa and the second write command WRb, respectively. The write data strobe signal WDQS can have a first (1st) toggle period (i.e., from the fourth time t4 to the seventh time t7) corresponding to the first write command WRa and a second (2nd) toggle period (i.e., from the eighth time t8 to the eleventh time t11) corresponding to the second write command WRb. That is, toggling of the write data strobe signal WDQS can be stopped between the first toggle period and the second toggle period (i.e., from the seventh time t7 to the eighth time t8). As such, the write data strobe signal WDQS can have one leading edge and one trailing edge for each of the first toggle and the second toggle, as shown in Figure 7B

[0091] The memory device 200 can generate toggled internal write data strobe signals dWDQS[0] to dWDQS[3] from the fourth time t4 to the seventh time t7 with respect to the first toggle, and can generate toggled internal write data strobe signals dWDQS[0] to dWDQS[3] from the eighth time t8 to the eleventh time t11 with respect to the second toggle. After performing the reset operation at the first time t1, the memory device 200 can generate the internal write data strobe signals dWDQS[0] to dWDQS[3] without an additional reset operation.

[0092] Toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be stopped from the seventh time t7 to the eighth time t8. When toggling is stopped, the internal write data strobe signals dWDQS[1] to dWDQS[3] can maintain the same values as at the first time t1. As such, the toggled internal write data strobe signals dWDQS[0] to dWDQS[3] with respect to the second toggle can have a desired phase (i.e., the phase of the toggled internal write data strobe signals dWDQS[0] to dWDQS[3] with respect to the first toggle).

[0093] At a fifth time t5, which is the write latency WL from the second time t2 at which the first write command WRa is received, the memory device 200 can start receiving a data signal DQ including first data Da0 to Da7. At a ninth time t9, which is the write latency WL from the third time t3 at which the second write command WRb is received, the memory device 200 can start receiving a data signal DQ including second data Db0 to Db7.

[0094] ​The memory device 200 can receive the first data Da0 to Da7 and the second data Db0 to Db7 by latching the data signal DQ based on the internal write data strobe signals dWDQS[0] to dWDQS[3]. For example, the memory device 200 can latch the data signal DQ at a falling edge of each of the internal write data strobe signals dWDQS[0] to dWDQS[3]. As such, from the fifth time t5 to the eleventh time t11, the first data Da0 to Da7 and the second data Db0 to Db7 can be received from the data signal DQ.

[0095] As described with reference to Figure 7A and Figure 7B , in a case where the internal write data strobe signals dWDQS are initialized to a reset value before the write data strobe signal WDQS starts to flip, the memory device 200 can generate the internal write data strobe signals dWDQS with a desired phase without an additional reset operation, and can receive write data corresponding to a plurality of write commands. As such, power consumption of the memory device 200 can be reduced.

[0096] A write operation according to a plurality of write commands is described with reference to Figure 6 , Figure 7A and Figure 7B , but embodiments are not limited thereto. For example, in a read operation according to a plurality of read commands, the memory device 200 can generate the internal write data strobe signals dWDQS without performing an additional reset operation. Alternatively, in a write operation according to a write command and a read operation according to a read command, the memory device 200 can generate the internal write data strobe signals dWDQS without performing an additional reset operation.

[0097] Figure 8 is a flowchart illustrating an exemplary read operation of a memory device according to an embodiment. With reference to Figure 2 and Figure 8 , in operation S221, the memory device 200 can initialize the internal write data strobe signals dWDQS to a given value before the write data strobe signal WDQS flips. As such, the internal write data strobe signals dWDQS can remain at a reset value before flipping.

[0098] In operation S222, the memory device 200 can generate the internal write data strobe signals dWDQS that flip at different phases depending on flipping of the write data strobe signal WDQS. Since the internal write data strobe signals dWDQS remain at a reset value before flipping, the memory device 200 can generate the internal write data strobe signals dWDQS with a desired phase.

[0099] In operation S223, the memory device 200 can transmit the read data strobe signal RDQS and data "DATA" read from the memory cell array 220 to the memory controller 100 based on the internal write data strobe signal dWDQS.

[0100] Figure 9 is a timing diagram illustrating an example of a read operation of Figure 8 Referring to Figure 2 and Figure 9 , the memory device 200 can receive a clock signal CK, a command / address signal C / A including a read command RD, and a write data strobe signal WDQS. The memory device 200 can transmit a data signal DQ including the read data strobe signal RDQS and data D0 to D7 to the memory controller 100 in response to the memory controller 100 (referring to Figure 1 ).

[0101] At a first time t1, the memory device 200 can initialize the internal write data strobe signals dWDQS[0] to dWDQS[3] to a reset value. The memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a low level, and can initialize the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] to a high level.

[0102] The memory device 200 can receive the command / address signal C / A including the read command RD at a second time t2. The memory device 200 can receive the read command RD by latching the command / address signal C / A based on rising edges and falling edges of the clock signal CK. An example is illustrated in Figure 9 as receiving the read command RD during two cycles of the command / address signal C / A, but embodiments are not limited thereto.

[0103] The memory device 200 can receive the toggled write data strobe signal WDQS from a third time t3 to a sixth time t6. When the write data strobe signal WDQS toggles, the write data strobe signal WDQS can include one pre-cycle and one post-cycle.

[0104] At the third time t3, the memory device 200 can generate the first internal write data strobe signal dWDQS[0] having the same edge timing as that of the write data strobe signal WDQS. The memory device 200 can generate the second internal write data strobe signal dWDQS[1] to the fourth internal write data strobe signal dWDQS[3] having phase differences of 90 degrees, 180 degrees, and 270 degrees, respectively, delayed with respect to the first internal write data strobe signal dWDQS[0].

[0105] The memory device 200 can generate the toggled read data strobe signal RDQS based on the internal write data strobe signals dWDQS[0] to dWDQS[3] from the third time t3 to the sixth time t6. When the read data strobe signal RDQS toggles, the read data strobe signal RDQS can include a pre-period and a post-period. In Figure 9 the example in which the time at which the toggled write data strobe signal WDQS is started to be received and the time at which the toggled read data strobe signal RDQS is started to be transmitted are the same, i.e., both correspond to the third time t3, but there can be a delay between the time at which the toggled write data strobe signal WDQS is started to be received and the time at which the toggled read data strobe signal RDQS is started to be transmitted. Hereinafter, for convenience of description, it is assumed that the time at which the toggled write data strobe signal WDQS is started to be received and the time at which the toggled read data strobe signal RDQS is started to be transmitted are the same.

[0106] The memory device 200 can generate the data signal DQ including the data D0 to D7 based on the internal write data strobe signals dWDQS[0] to dWDQS[3] from the fourth time t4 to the fifth time t5. At the fourth time t4 at which the read latency RL elapses from the second time t2 at which the read command RD is received, the memory device 200 can start to transmit the data signal DQ including the data D0 to D7. As such, the data D0 to D7 can be aligned with the toggling timing of the read data strobe signal RDQS and can be transmitted to the memory controller 100.

[0107] Since the toggling of the write data strobe signal WDQS is stopped at the sixth time t6, the toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be stopped. In this case, each of the internal write data strobe signals dWDQS[0] to dWDQS[3] can have the same value as at the first time t1. That is, after the sixth time t6, each of the internal write data strobe signals dWDQS[0] to dWDQS[3] can maintain the reset value. As such, as described with reference to Figure 7A and Figure 7B , the memory device 200 can generate the internal write data strobe signals dWDQS[0] to dWDQS[3] having a desired phase without an additional reset operation and can perform the following write operation and read operation. The example of the read operation has been described with reference to Figure 8 and Figure 9 . However, it will be understood by those of ordinary skill in the art that the technical concept of the write operation described above with reference to Figure 5B , Figure 7A and Figure 7B may also be applied to the read operation. Therefore, for the sake of brevity, repeated description thereof is omitted.

[0108] Figure 10A and Figure 10B is a block diagram illustrating a WDQS divider according to various embodiments. For example, Figure 2 The WDQS divider 213 of the memory device 200 of Figure 10A may be implemented using the WDQS divider 230 shown in Figure 10B or the WDQS divider 240 shown in Figure 5A Each of the WDQS dividers 230 and 240 can generate four internal write data strobe signals dWDQS[0] to dWDQS[3] based on a write data strobe signal WDQS, as described with reference to

[0109] With reference to Figure 10A , the WDQS divider 230 can include a first latch 231 and a second latch 232. Each of the first latch 231 and the second latch 232 can include a first input terminal D, a second input terminal D', a first output terminal Q, a second output terminal Q', a reset terminal RST, and a clock terminal C. Each of the first latch 231 and the second latch 232 can receive a complementary input through the first input terminal D and the second input terminal D', and can output a complementary value through the first output terminal Q and the second output terminal Q'.

[0110] The first input terminal D of the first latch 231 can be connected with the second output terminal Q' of the second latch 232, and the second input terminal D' of the first latch 231 can be connected with the first output terminal Q of the second latch 232. The first output terminal Q of the first latch 231 can be connected with the first input terminal D of the second latch 232, and the second output terminal Q' of the first latch 231 can be connected with the second input terminal D' of the second latch 232.

[0111] A reset signal RESET can be input to the reset terminal RST of each of the first latch 231 and the second latch 232. The first latch 231 and the second latch 232 can be reset by the reset signal RESET. For example, as described with reference to Figure 5A and Figure 5B , each of the first latch 231 and the second latch 232 can be initialized to a low level or a high level depending on a number of leading cycles of the write data strobe signal WDQS. When each of the first latch 231 and the second latch 232 is reset, each of the first latch 231 and the second latch 232 can output a reset value through the first output terminal Q and can output a complementary value through the second output terminal Q'.

[0112] A write data strobe signal WDQS can be input to a clock terminal C of the first latch 231, and a complementary write data strobe signal WDQSB can be input to a clock terminal C of the second latch 232. The write data strobe signal WDQS and the complementary write data strobe signal WDQSB can be input to the clock terminals C of the first latch 231 and the second latch 232, respectively. In this case, the write data strobe signal WDQS and the complementary write data strobe signal WDQSB can be provided from the memory controller 100 as a differential signal. The first latch 231 can output values input to input terminals D and D' to output terminals Q and Q' based on a rising edge of the write data strobe signal WDQS. The second latch 232 can output values input to input terminals D and D' to output terminals Q and Q' based on a rising edge of the complementary write data strobe signal WDQSB.

[0113] A first internal write data strobe signal dWDQS[0] can be output from a first output terminal Q of the first latch 231, and a third internal write data strobe signal dWDQS[2] can be output from a second output terminal Q' of the first latch 231. A second internal write data strobe signal dWDQS[1] can be output from a first output terminal Q of the second latch 232, and a fourth internal write data strobe signal dWDQS[3] can be output from a second output terminal Q' of the second latch 232.

[0114] Referring to Figure 5A and Figure 10A When the reset signal RESET is input before the write data strobe signal WDQS is toggled, the WDQS divider 230 can output the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] having a low level through the first output terminal Q and can output the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] having a high level through the second output terminal Q' depending on the reset signal RESET. When the write data strobe signal WDQS is toggled, the WDQS divider 230 can output toggled internal write data strobe signals dWDQS[0] to dWDQS[3] based on a rising edge of the write data strobe signal WDQS and a rising edge of the complementary write data strobe signal WDQSB.

[0115] Referring to Figure 10BThe WDQS divider 240 may include a first latch 241 and a second latch 242. Each of the first latch 241 and the second latch 242 may include an input terminal D, a first output terminal Q, a second output terminal Q', a reset terminal RST, and a clock terminal C. Each of the first latch 241 and the second latch 242 may output complementary values ​​through the first output terminal Q and the second output terminal Q'. The input terminal D of the first latch 241 may be connected to the second output terminal Q' of the second latch 242. The first output terminal Q of the first latch 241 may be connected to the input terminal D of the second latch 242.

[0116] A first internal write data strobe signal dWDQS[0] can be output from the first output terminal Q of the first latch 241, and a third internal write data strobe signal dWDQS[2] can be output from the second output terminal Q' of the first latch 241. A second internal write data strobe signal dWDQS[1] can be output from the first output terminal Q of the second latch 242, and a fourth internal write data strobe signal dWDQS[3] can be output from the second output terminal Q' of the second latch 242. In this way, the operation of the WDQS divider 240 can be combined with... Figure 10A The operation of the WDQS divider 230 is basically the same, so additional descriptions will be omitted to avoid repetition.

[0117] Figure 11 It is shown Figure 1 An exemplary block diagram of the memory interface of the memory system 10. (Refer to...) Figure 11 The memory interface (I / F) 110 may include a phase-locked loop 111, a phase controller 112, a first transmitter 113, a second transmitter 114, an internal clock divider 115, a third transmitter 116, and a fourth transmitter 117. The phase-locked loop 111 can generate a first internal clock signal ICS1. The phase controller 112 can generate a second internal clock signal ICS2 with a phase different from that of the first internal clock signal ICS1, based on the first internal clock signal ICS1. For example, the first internal clock signal ICS1 and the second internal clock signal ICS2 may be 90 degrees out of phase.

[0118] The first transmitter 113 can transmit the data "DATA" based on the second internal clock signal ICS2. Thus, the first transmitter 113 can send a data signal DQ including the data "DATA" to the memory device 200. The second transmitter 114 can send the first internal clock signal ICS1 as a write data strobe signal WDQS to the memory device 200.

[0119] The internal clock divider 115 can divide the first internal clock signal ICS1 to generate a first divided internal clock signal dICS1 and a second divided internal clock signal dICS2 having different phases. An edge timing of the first divided internal clock signal dICS1 can be the same as that of the first internal clock signal ICS1, and the first divided internal clock signal dICS1 and the second divided internal clock signal dICS2 can be 270 degrees out of phase. For example, the frequencies of the divided internal clock signals dICS1 and dICS2 can be half of the frequency of the second internal clock signal ICS2.

[0120] The third transmitter 116 can transmit the first divided internal clock signal dICS1 to the memory device 200 as the clock signal CK. Since the edge timing of the first divided internal clock signal dICS1 is the same as that of the second internal clock signal ICS2, the clock signal CK and the write data strobe signal WDQS can be output at the same edge timing. The fourth transmitter 117 can transmit the command CMD and / or the address ADD based on the second divided internal clock signal dICS2. In this way, the fourth transmitter 117 can transmit a command / address signal C / A including the command CMD and / or the address ADD to the memory device 200.

[0121] As described above, the clock signal CK and the write data strobe signal WDQS can be generated by one phase-locked loop 111. In this way, the operating current of the memory controller 100 can be reduced.

[0122] Figure 12 is a block diagram illustrating a stacked memory device according to various embodiments. Referring to Figure 12 , the stacked memory device 300 can include a buffer die 310 and a plurality of core dies 320 to 350. For example, the buffer die 310 can also be referred to as an "interface die", a "base die", a "logic die", or a "master die", and each of the core dies 320 to 350 can also be referred to as a "memory die" or a "slave die". An example is shown in Figure 12 that the stacked memory device 300 includes four core dies 320 to 350, but the number of core dies can vary differently. For example, the stacked memory device 300 can include 8, 12, or 16 core dies.

[0123] The buffer die 310 and the core dies 320 to 350 can be stacked and can be electrically connected by using through silicon vias (TSVs). In this way, the stacked memory device 300 can have a three-dimensional memory structure in which a plurality of dies 310 to 350 are stacked. For example, the stacked memory device 300 can be implemented according to an HBM or an HMC standard.

[0124] The stacked memory device 300 can support multiple channels (or vaults) that are independent of each other in terms of functions. For example, as shown in Figure 12 FIG. 1, the stacked memory device 300 can support 8 channels CH0 to CH7. In a case where each of the channels CH0 to CH7 supports 128 DQ I / Os, the stacked memory device 300 can support 1204 DQ I / Os. However, embodiments are not limited thereto. For example, the stacked memory device 300 can support 1024 or more DQ I / Os, and can support 8 or more channels (e.g., 16 channels). In a case where the stacked memory device 300 supports 16 channels, each channel can support 64 DQ I / Os.

[0125] Each of the core dies 320 to 350 can support at least one channel. For example, as shown in Figure 12 FIG. 2, the core dies 320 to 350 can support channel pairs CH0 and CH2, CH1 and CH3, CH4 and CH6, and CH5 and CH7, respectively. In this case, the core dies 320 to 350 can support different channels. However, embodiments are not limited thereto. For example, at least two of the core dies 320 to 350 can support the same channel. For example, each of the core dies 320 to 350 can support a first channel CH0.

[0126] Each channel can form an independent command and data interface. For example, a clock can be provided for the channels independently based on independent timing requirements, and the channels can not be synchronized. For example, based on independent commands, each channel can change a power state or can perform a refresh operation.

[0127] Each channel can include a plurality of memory banks 301. Each memory bank 301 can include memory cells connected with a word line and a bit line, a row decoder, a column decoder, a sense amplifier, etc. For example, as shown in Figure 12 FIG. 3, each of the channels CH0 to CH7 can support 8 memory banks 301. However, embodiments are not limited thereto. For example, each of the channels CH0 to CH7 can support 8 or more memory banks 301. An example is shown in Figure 12 FIG. 4, where memory banks belonging to one channel are included in one core die, but the memory banks belonging to one channel can be distributed to a plurality of core dies. For example, in a case where each of the core dies 320 to 350 supports a first channel CH0, the memory banks included in the first channel CH0 can be distributed to the core dies 320 to 350.

[0128] In an exemplary embodiment, one channel can be divided into two pseudo-channels that operate independently of each other. For example, the pseudo-channels can share command and clock inputs (e.g., clock signal CK and clock enable signal CKE) of the corresponding channel, but can independently decode and execute commands. For example, in a case where one channel supports 128 DQ I / Os, each pseudo-channel can support 64 DQ I / Os. For example, in a case where one channel supports 64 DQ I / Os, each pseudo-channel can support 32 DQ I / Os.

[0129] The buffer die 310 and the core dies 320 to 350 can each include a TSV region 302. TSVs configured to penetrate the dies 310 to 350 can be disposed in the TSV region 302. The buffer die 310 can exchange signals and / or data with the core dies 320 to 350 through the TSVs. Each of the core dies 320 to 350 can exchange signals and / or data with the buffer die 310 through the TSVs, and the core dies 320 to 350 can exchange signals and / or data with each other through the TSVs. In this case, the signals and / or data can be independently exchanged through the corresponding TSVs for each channel. For example, in a case where an external host device transmits a command and an address to the first channel CH0 for the purpose of accessing a memory cell of the first core die 320, the buffer die 310 can transmit a control signal to the first core die 320 through a TSV corresponding to the first channel CH0, and can access the memory cell of the first channel CH0.

[0130] The buffer die 310 can include a physical layer (PHY) 311. The physical layer 311 can include an interface circuit for communication with an external host device. For example, the physical layer 311 can include an interface circuit corresponding to the host interface 210 described with reference to FIG. 1. Signals and / or data received through the physical layer 311 can be transmitted to the core dies 320 to 350 through the TSVs. Figure 1 to Figure 11

[0131] In an exemplary embodiment, the buffer die 310 can include a channel controller corresponding to each channel, respectively. The channel controller can manage a memory reference operation of the corresponding channel, and can determine a timing requirement of the corresponding channel.

[0132] ​In an exemplary embodiment, the buffer die 310 may include multiple pins for receiving signals from an external host device. Through these pins, the buffer die 310 may receive a clock signal CK, a command / address signal C / A, a write data strobe signal WDQS, and a data signal DQ, and may transmit a read data strobe signal RDQS and a data signal DQ. For example, for each channel, the buffer die 310 may include 2 pins for receiving the clock signal CK, 14 pins for receiving the command / address signal C / A, 8 pins for receiving the write data strobe signal WDQS, 8 pins for transmitting the read data strobe signal RDQS, and 128 pins for transmitting and receiving the data signal DQ.

[0133] Figure 13 This illustrates an embodiment. Figure 12 A more detailed exemplary block diagram of the stacked memory device. (Refer to...) Figure 13 The stacked memory device 400 may include a buffer die 410 and a core die 420. The core die 420 may support channel CHa in multiple channels. The buffer die 410 and the core die 420 may communicate with each other via TSVs 402 and 403 located in TSV regions 401. TSV region 401 may correspond to channel CHa. For example, the buffer die 410 may send the internal command iCMD to the core die 420 via TSV 402, and may exchange data "DATA" with the core die 420 via TSV 403.

[0134] The buffer die 410 may include a C / A receiver 411, control logic circuitry 412, a WDQS divider 413, an RDQS transmitter 414, and a data transceiver 415. The C / A receiver 411, control logic circuitry 412, WDQS divider 413, RDQS transmitter 414, and data transceiver 415 may include... Figure 12 In the physical layer 311 of the stacked memory device 300, it serves as the interface circuit for channel CHa. That is, for each channel, Figure 12 The physical layer 311 may include Figure 13 The interface circuit shown. The C / A receiver 411, control logic circuit 412, WDQS divider 413, RDQS transmitter 414, and data transceiver 415 can respectively correspond to... Figure 2 The C / A receiver 211, control logic circuit 212, WDQS divider 213, RDQS transmitter 214, and data transceiver 215 are included, so additional descriptions will be omitted to avoid repetition.

[0135] The buffer die 410 can receive a clock signal CK, a command / address signal C / A, a write data strobe signal WDQS, and a data signal DQ provided through the channel CHa. The buffer die 410 can transmit a read data strobe signal RDQS and the data signal DQ generated at the channel CHa to an external host device.

[0136] The C / A receiver 411 can receive a command CMD by latching the command / address signal C / A based on the clock signal CK. The received command CMD can be provided to the control logic circuit 412.

[0137] The control logic circuit 412 can generate a reset signal RESET before the write data strobe signal WDQS starts to toggle, depending on the command CMD or the power state information PWS. The control logic circuit 412 can decode the command CMD and can generate an internal command iCMD depending on the command CMD. For example, the internal command iCMD can be generated in a format different from that of the command CMD in accordance with an internal communication protocol between the buffer die 410 and the core die 420, or can be generated in the same format as that of the command CMD. The internal command iCMD can be transmitted to the core die 420 supporting the channel CHa through the TSV 402.

[0138] The WDQS divider 413 can be reset in response to the reset signal RESET. As such, the WDQS divider 413 can initialize an internal write data strobe signal dWDQS to a reset value. The WDQS divider 413 can generate the internal write data strobe signal dWDQS toggling at a different phase depending on toggling of the write data strobe signal WDQS.

[0139] In an exemplary embodiment, the stacked memory device 400 can transmit or receive the write data strobe signal WDQS without a separate termination resistor. In other words, a separate termination resistor can be omitted. In this case, the write data strobe signal WDQS can be in a static low state or a static high state, rather than a high impedance state High-Z. As such, a reset operation of the WDQS divider 413 can be easily performed.

[0140] The RDQS transmitter 414 can generate a read data strobe signal RDQS based on the internal write data strobe signal dWDQS, and can transmit the read data strobe signal RDQS to an external host device. The read data strobe signal RDQS can be generated to have the same frequency as that of the write data strobe signal WDQS.

[0141] The data transceiver 415 can transmit and receive a data signal DQ including data "DATA" based on an internal write data strobe signal dWDQS. In a write operation, the data transceiver 415 can receive the data "DATA" by latching the data signal DQ based on the internal write data strobe signal dWDQS. The received data "DATA" can be transmitted to the core die 420 supporting the channel CHa through the TSV 403. In a read operation, the data transceiver 415 can receive the data "DATA" transmitted from the core die 420 through the TSV 403. The data transceiver 415 can transmit a data signal DQ including the data "DATA" to an external host device based on the internal write data strobe signal dWDQS. The data "DATA" can be aligned with a flip timing of a read data strobe signal RDQS and can be transmitted.

[0142] The core die 420 can include a command decoder 421, a data input / output (I / O) circuit 422, and a memory cell array 423. The command decoder 421, the data input / output circuit 422, and the memory cell array 423 can be circuits supporting the channel CHa.

[0143] The command decoder 421 can decode an internal command iCMD transmitted from the buffer die 410 through the TSV 402. For example, the internal command iCMD can include an activate command, a write command, a read command, a refresh command, etc. associated with the memory cell array 220. In a write operation, the command decoder 421 can receive the internal command iCMD including the write command. In a read operation, the command decoder 421 can receive the internal command iCMD including the read command. The command decoder 421 can control the data input / output circuit 422 and the memory cell array 423 depending on the internal command iCMD.

[0144] The data input / output circuit 422 can exchange data with the buffer die 410 through the TSV 403. In a write operation, the data input / output circuit 422 can receive the data "DATA" transmitted from the buffer die 410 through the TSV 403, and can transmit the data "DATA" to the memory cell array 423. The memory cell array 423 can store the data "DATA". In a read operation, the data input / output circuit 422 can read the data "DATA" from the memory cell array 423, and can transmit the received data "DATA" to the buffer die 410 through the TSV 403.

[0145] In an exemplary embodiment, the buffer die 410 can further include an error correction code (ECC) circuit (not shown) for detecting and correcting errors of the data "DATA". For example, in a write operation, the ECC circuit can generate error detection bits (e.g., parity bits) for the data "DATA" received through the data transceiver 415. In a read operation, the ECC circuit can detect and correct errors of the data "DATA" transferred from the core die 420 by using the error detection bits, and can transfer the data "DATA" corrected of errors to the data transceiver 215.

[0146] As described above, the stacked memory device 400 can initialize the internal write data strobe signal dWDQS to a reset value before the write data strobe signal WDQS starts to flip. In this case, the internal write data strobe signal dWDQS generated at the time when the write data strobe signal WDQS flips can have a desired phase. As such, the stacked memory device 400 can adjust the phase of the internal write data strobe signal dWDQS without performing a separate auto synchronization. The stacked memory device 400 can transmit and receive the data "DATA" based on the internal write data strobe signal dWDQS having the desired phase.

[0147] Figure 14 is an exemplary more detailed block diagram illustrating a stacked memory device according to an embodiment. Figure 12 Figure 14 Referring to FIG. 4, the stacked memory device 400 can include a buffer die 410, a core die 420 (hereinafter, with respect to an embodiment of the core die 420, "a first core die 420"), and a second core die 430. The first core die 420 and the second core die 430 can support the same channel CHa among a plurality of channels. In this case, the first core die 420 and the second core die 430 can be distinguishable by using a stack identifier SID. For example, the first core die 420 can correspond to a first stack identifier SID0, and the second core die 430 can correspond to a second stack identifier SID1. In Figure 14 an embodiment, the first core die 420 and the second core die 430 can be distinguished by using a stack identifier SID. For example, the first core die 420 can correspond to a first stack identifier SID0, and the second core die 430 can correspond to a second stack identifier SID1. In Figure 14 an embodiment, the first core die 420 and the second core die 430 can be distinguished by using a stack identifier SID. For example, the first core die 420 can correspond to a first stack identifier SID0, and the second core die 430 can correspond to a second stack identifier SID1. In

[0148] ​The buffer die 410 and the first core die 420 and the second core die 430 can communicate with each other through the TSVs 402 and 403 placed in the TSV region 401. For example, the buffer die 410 can transmit an internal command iCMD to the first core die 420 and / or the second core die 430 through the TSV 402, and can exchange data "DATA" with the first core die 420 and / or the second core die 430 through the TSV 403. In Figure 14 An example in which the buffer die 410 communicates with the first core die 420 and the second core die 430 by using the same TSVs 402 and 403 is shown in FIG. 4, but the buffer die 410 can communicate by using separate TSVs corresponding to the first core die 420 and the second core die 430, respectively.

[0149] The second core die 430 can include a command decoder 431, a data input / output (I / O) circuit 432, and a memory cell array 433. Operations of the command decoder 431, the data input / output circuit 432, and the memory cell array 433 can be substantially the same as those of the command decoder 421, the data input / output circuit 422, and the memory cell array 423 of the core die 420, as described with reference to FIG. 4, and thus, repetitive descriptions thereof are omitted for brevity. Figure 13

[0150] The C / A receiver 411 can receive a command CMD and a stack identifier SID by latching the command / address signal C / A based on the clock signal CK. The stack identifier SID can be an address indicating at least one core die for the purpose of distinguishing core dies supporting the same channel. The received command CMD and the stack identifier SID can be provided to the control logic circuit 412.

[0151] Based on the stack identifier SID, the control logic circuit 412 can transmit an internal command iCMD to at least one of the first core die 420 and the second core die 430. For example, in the case where the stack identifier SID indicates a first stack identifier SID0, the control logic circuit 412 can transmit the internal command iCMD to the first core die 420.

[0152] In an exemplary embodiment, as Figure 15 ​As shown, in a case where internal commands iCMD and data "DATA" are transferred to the first core die 420 and the second core die 430 through the common TSVs 402 and 403, the buffer die 410 can transfer the stack identifier SID to the first core die 420 and the second core die 430. The first core die 420 and the second core die 430 can decode the transferred stack identifier SID to selectively receive the internal commands iCMD and the data "DATA". For example, in a case where the stack identifier SID indicates the first stack identifier SID0, the first core die 420 can receive the internal commands iCMD and the data "DATA" transferred through the TSVs 420 and 430. In this case, the second core die 430 can not receive the internal commands iCMD and the data "DATA" transferred through the TSVs 420 and 430.

[0153] In another embodiment, in a case where the internal commands iCMD and the data "DATA" are transferred to the first core die 420 and the second core die 430 through separate TSVs, the buffer die 410 can transfer the internal commands iCMD and the data "DATA" to the core dies corresponding to the stack identifier SID through the separate TSVs.

[0154] As described above, in a case where the first core die 420 and the second core die 430 support the same channel CHa, the stacked memory device 400 can perform a write operation and a read operation on at least one of the first core die 420 and the second core die 430 depending on the stack identifier SID.

[0155] Figure 13 is a block diagram illustrating an embodiment of a buffer die of a stacked memory device according to an embodiment. Figure 15 Referring to Figure 15 , the buffer die 410 can include a command address input / output block AWORD and data input / output blocks DWORD0 to DWORD3. An example is shown in Figure 16 that the buffer die 410 includes four data input / output blocks DWORD0 to DWORD3, but the number of data input / output blocks included in the buffer die 410 can vary differently. For example, the buffer die 410 can include two data input / output blocks.

[0156] The command address input / output block AWORD can include a C / A receiver 411, a control logic circuit 412, and a clock tree 416. The C / A receiver 411 can receive a command CMD by latching a command / address signal C / A received from a first pad P1 based on a clock signal CK received from a second pad P2. The control logic circuit 412 can generate a reset signal RESET based on the command CMD or power state information PWS, and can transmit the reset signal RESET to the respective data input / output blocks DWORD0 to DWORD3. The control logic circuit 412 can generate an internal command iCMD depending on the command CMD, and can transmit the internal command iCMD to the core die 420. The clock tree 416 can be implemented with an inverter chain including a plurality of inverters. An internal clock signal iCK generated by the clock tree 416 based on the clock signal CK can be transmitted to the respective data input / output blocks DWORD0 to DWORD3.

[0157] Each of the data input / output blocks DWORD0 to DWORD3 can receive the internal clock signal iCK and the reset signal RESET from the command address input / output block AWORD. Each of the data input / output blocks DWORD0 to DWORD3 can include a WDQS divider 413, an RDQS transmitter 414, and a data transceiver 415. The WDQS divider 413 can generate an internal write data strobe signal dWDQS based on a write data strobe signal WDQS received from a third pad P3. The WDQS divider 413 can initialize the internal write data strobe signal dWDQS to a reset value in response to the reset signal RESET. The RDQS transmitter 414 can generate a read data strobe signal RDQS based on the internal write data strobe signal dWDQS. The read data strobe signal RDQS can be transmitted to an external host device through a fourth pad P4. The data transceiver 415 can generate a data signal DQ including data "DATA" transmitted from the core die 420 based on the internal write data strobe signal dWDQS. The data signal DQ can be transmitted to the external host device through a fifth pad P5.

[0158] As described above, the second pad P2 through which the clock signal CK is received can be placed at the command address input / output block AWORD, and the third pad P3 and the fourth pad P4 through which the write data strobe signal WDQS and the read data strobe signal RDQS are respectively received can be placed at the data input / output block DWORD. The clock signal CK received by the command address input / output block AWORD can be transmitted to the data input / output block DWORD through the clock tree 416. In this way, in a case where the read data strobe signal RDQS is generated based on the clock signal CK, the influence of the power noise and the process-voltage-temperature (PVT) variation can be increased due to the inverter chain placed on a path through which the clock signal CK is transmitted. In a case where the read data strobe signal RDQS is generated based on the write data strobe signal WDQS received by the data input / output block DWORD, since the inverter chain is not placed on a path through which the write data strobe signal WDQS is transmitted, the influence of the power noise and the PVT variation can be reduced. In this way, the reliability of the read data strobe signal RDQS can be improved.

[0159] Figure 16 is a diagram illustrating a semiconductor package according to an embodiment. Referring to Figure 12 , the semiconductor package 1000 can include a stacked memory device 1100, a system on chip 1200, an interposer 1300, and a package substrate 1400. The stacked memory device 1100 can include a buffer die 1110 and core dies 1120 to 1150. The buffer die 1110 can correspond to the buffer die 310 of Figure 12 , and the core dies 1120 to 1150 can respectively correspond to the core dies 320 to 350 of Figure 13 .

[0160] Each of the core dies 1120 to 1150 can include an array of memory cells. The buffer die 1110 can include a physical layer 1111 and a direct access area (DAB) 1112. The physical layer 1111 can be electrically connected with a physical layer 1210 of the system on chip 1200. Through the physical layer 1111, the stacked memory device 1100 can receive a signal from or transmit a signal to the system on chip 1200. The physical layer 1111 can include the interface circuit of the buffer die 410 described with reference to Figure 1 .

[0161] The direct access area 1112 can provide an access path capable of testing the stacked memory device 1100 without passing through the system on chip 1200. The direct access area 1112 can include a conduction device (e.g., a port or a pin) capable of directly communicating with an external test device. Test signals and data received through the direct access area 1112 can be transmitted to the core dies 1120 to 1150 through the TSVs. In order to test the core dies 1120 to 1150, data read from the core dies 1120 to 1150 can be transmitted to a test device through the TSVs and the direct access area 1112. As such, a direct access test can be performed with respect to the core dies 1120 to 1150.

[0162] The buffer die 1110 and the core dies 1120 to 1150 can be electrically connected through the TSVs 1101 and the bumps 1102. The buffer die 1110 can receive signals from the system on chip 1200, which are provided to each channel through the bumps 1102 allocated for each channel. For example, the bumps 1102 can be micro bumps.

[0163] The system on chip 1200 can run an application supported by the semiconductor package 1000 by using the stacked memory device 1100. For example, the system on chip 1200 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), or a digital signal processor (DSP), and can run a specialized computation.

[0164] The system on chip 1200 can include a physical layer 1210 and a memory controller 1220. The physical layer 1210 can include an input / output circuit for exchanging signals with the physical layer 1111 of the stacked memory device 1100. The system on chip 1200 can provide various signals to the physical layer 1111 through the physical layer 1210. The signals provided to the physical layer 1111 can be transmitted to the core dies 1120 to 1150 through the interface circuit of the physical layer 1111 and the TSVs 1101.

[0165] The memory controller 1220 can control the overall operation of the stacked memory device 1100. The memory controller 1220 can provide signals for controlling the stacked memory device 1100 to the stacked memory device 1100 through the physical layer 1210. The memory controller 1220 can correspond to Figure 17 a memory controller 100 of FIG. 1.

[0166] The interposer 1300 can connect the stacked memory device 1100 and the system on chip 1200. The interposer 1300 can connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system on chip 1200, and can provide a physical path formed by using a conductive material. As such, the stacked memory device 1100 and the system on chip 1200 can be stacked on the interposer 1300, and can exchange signals with each other.

[0167] The bumps 1103 can be attached on an upper surface of the package substrate 1400, and the solder balls 1104 can be attached on a lower surface of the package substrate 1400. For example, the bumps 1103 can be flip chip bumps. The interposer 1300 can be stacked on the package substrate 1400 through the bumps 1103. The semiconductor package 1000 can exchange signals with any other external package or semiconductor device through the solder balls 1104. For example, the package substrate 1400 can be a printed circuit board (PCB).

[0168] Figure 17 FIG. 1 is a diagram illustrating an implementation example of a semiconductor package according to an embodiment. Referring to FIG. 1, Figure 12 to Figure 16 The semiconductor package 2000 can include a plurality of stacked memory devices 2100 and a system on chip 2200. The stacked memory devices 2100 and the system on chip 2200 can be stacked on an interposer 2300, and the interposer 2300 can be stacked on a package substrate 2400. The semiconductor package 2000 can exchange signals with any other external package or semiconductor device through solder balls 2001 attached on a lower surface of the package substrate 2400.

[0169] Each of the stacked memory devices 2100 can be implemented in accordance with an HBM standard. However, embodiments are not limited thereto. For example, each of the stacked memory devices 2100 can be implemented based on a GDDR, HMC, or Wide I / O standard. Each of the stacked memory devices 2100 can correspond to Figure 16 the stacked memory device 300, 400, or 1100 of FIGS. 1 to 3.

[0170] The system on chip 2200 can include at least one processor such as a CPU, an AP, a GPU, or an NPU, and a plurality of memory controllers for controlling the plurality of stacked memory devices 2100. The system on chip 2200 can exchange signals with the corresponding stacked memory devices through the memory controllers. The system on chip 2200 can correspond to Figure 18 the system on chip 1200 of FIG. 4.

[0171] Figure 18 FIG. 5 is a diagram illustrating a semiconductor package according to another embodiment. Referring to FIG. 5, Figure 12 to Figure 13, the semiconductor package 3000 can include a stacked memory device 3100, a host die 3200, and a package substrate 3300. The stacked memory device 3100 can include a buffer die 3110 and core dies 3120 to 3150. The buffer die 3110 can include a physical layer 3111 for communication with the host die 3200, and each of the core dies 3120 to 3150 can include a memory cell array. The stacked memory device 3100 can correspond to Figure 1 to Figure 15 the stacked memory devices 300 and 400 of FIGS. 1A and 1B.

[0172] The host die 3200 can include a physical layer 3210 for communication with the stacked memory device 3100 and a memory controller 3220 for controlling overall operations of the stacked memory device 3100. In addition, the host die 3200 can include a processor for controlling overall operations of the semiconductor package 3000 and run applications supported by the semiconductor package 3000. For example, the host die 3200 can include at least one processor such as a CPU, an AP, a GPU, or an NPU.

[0173] The stacked memory device 3100 can be seated on the host die 3200 based on the TSVs 3001 to be stacked vertically on the host die 3200. As such, the buffer die 3110, the core dies 3120 to 3150, and the host die 3200 can be electrically connected through the TSVs 3001 and the bumps 3002 without an interposer. For example, the bumps 3002 can be micro bumps.

[0174] The bumps 3003 can be attached on an upper surface of the package substrate 3300, and the solder balls 3004 can be attached on a lower surface of the package substrate 1400. For example, the bumps 3003 can be flip chip bumps. The host die 3200 can be stacked on the package substrate 3300 through the bumps 3003. The semiconductor package 3000 can exchange signals with any other external package or semiconductor device through the solder balls 3004.

[0175] In another embodiment, the stacked memory device 3100 can be implemented with only the core dies 3120 to 3150 without the buffer die 3110. In this case, each of the core dies 3120 to 3150 can include an interface circuit for communication with the host die 3200 as described with reference to Figure 19 Each of the core dies 3120 to 3150 can exchange signals with the host die 3200 through the TSVs 3001.

[0176] Figure 19is a block diagram illustrating a computing system according to an embodiment. The computing system 4000 can be implemented with one electronic device, or can be distributed to and implemented with two or more electronic devices. For example, the computing system 4000 can be implemented with at least one of various electronic devices such as a desktop computer, a laptop computer, a tablet computer, a smart phone, an autonomous vehicle, a digital camera, a wearable device, a health care device, a server system, a data center, a drone, a hand-held game console, an Internet of Things (IoT) device, a graphics accelerator, an AI accelerator.

[0177] Referring to Figure 16 to Figure 18 , the computing system 4000 can include a host 4100, an accelerator subsystem 4200, and an interconnect 4300. The host 4100 can control overall operations of the accelerator subsystem 4200, and the accelerator subsystem 4200 can operate under the control of the host 4100. The host 4100 and the accelerator subsystem 4200 can be connected through the interconnect 4300. Various signals and data can be exchanged between the host 4100 and the accelerator subsystem 4200 through the interconnect 4300.

[0178] The host 4100 can include a host processor 4110, a host memory controller 4120, a host memory 4130, and an interface 4140. The host processor 4110 can control overall operations of the computing system 4000. The host processor 4110 can control the host memory 4130 through the host memory controller 4120. For example, the host processor 4110 can read data from the host memory 4130 or can store data in the host memory 4130. The host processor 4110 can control the accelerator subsystem 4200 connected through the interconnect 4300. For example, the host processor 4110 can transmit a command to the accelerator subsystem 4200 and can assign a task to the accelerator subsystem 4200.

[0179] The host processor 4110 can be a general-purpose processor or a main processor that performs general computation associated with various operations of the computing system 4000. For example, the host processor 4110 can be a CPU or an AP.

[0180] The host memory 4130 can be a main memory of the computing system 4000. The host memory 4130 can store data processed by the host processor 4110 or can store data received from the accelerator subsystem 4200. For example, the host memory 4130 can be implemented with a DRAM.

[0181] The interface 4140 can be configured to allow the host 4100 to communicate with the accelerator subsystem 4200. Through the interface 4140, the host processor 4110 can send control signals and data to the accelerator subsystem 4200, and can receive signals and data from the accelerator subsystem 4200. In an exemplary embodiment, the host processor 4110, the host memory controller 4120, and the interface 4140 can be implemented with one chip.

[0182] The accelerator subsystem 4200 can perform certain functions under the control of the host 4100. For example, the accelerator subsystem 4200 can perform computations specific to a certain application under the control of the host 4100. The accelerator subsystem 4200 can be implemented in various types, such as a module type, a card type, a package type, a chip type, and a device type, so as to be physically or electrically connected with the host 4100, or to be wired or wirelessly connected with the host 4100. For example, the accelerator subsystem 4200 can be implemented with one of the semiconductor packages described with reference to FIGS. 1A to 1C. Figure 1 to Figure 18 The accelerator subsystem 4200 can be implemented in various types, such as a module type, a card type, a package type, a chip type, and a device type, so as to be physically or electrically connected with the host 4100, or to be wired or wirelessly connected with the host 4100. For example, the accelerator subsystem 4200 can be implemented with one of the semiconductor packages described with reference to FIGS. 1A to 1C.

[0183] In an exemplary embodiment, the accelerator subsystem 4200 can be implemented through one of various packaging technologies. For example, the accelerator subsystem 4200 can be implemented through a packaging technology, such as a ball grid array (BGA) technology, a multi-chip package (MCP) technology, a system on package (SOP) technology, a system in package (SIP) technology, a package on package (POP) technology, a chip scale package (CSP) technology, a wafer level package (WLP) technology, or a panel level package (PLP) technology. For example, all or part of the components of the accelerator subsystem 4200 can be connected through copper-copper bonding. For example, all or part of the components of the accelerator subsystem 4200 can be connected through an interposer, such as a silicon interposer, an organic interposer, a glass interposer, or an active interposer. For example, all or part of the components of the accelerator subsystem 4200 can be stacked based on TSVs. For example, all or part of the components of the accelerator subsystem 4200 can be connected through a high-speed connection path (e.g., a silicon bridge).

[0184] The accelerator subsystem 4200 can include a special-purpose processor 4210, a local memory controller 4220, a local memory 4230, and a host interface 4240. The special-purpose processor 4210 can operate under the control of the host processor 4110. For example, the special-purpose processor 4210 can read data from the local memory 4230 through the local memory controller 4220 in response to a command of the host processor 4110. The special-purpose processor 4210 can process the read data by performing a computation on the read data. The special-purpose processor 4210 can transfer the processed data to the host processor 4110 or can store the processed data in the local memory 4230.

[0185] The special-purpose processor 4210 can perform a special-purpose computation for a specific application based on a value stored in the local memory 4230. For example, the special-purpose processor 4210 can perform a computation that is specialized for an application such as artificial intelligence, streaming analysis, video transcoding, data indexing, data encoding / decoding, and data encryption. As such, the special-purpose processor 4210 can process various types of data such as image data, voice data, motion data, biometric data, and key values. For example, the special-purpose processor 4210 can include at least one of a GPU, an NPU, a TPU, a VPU, an ISP, and a DSP.

[0186] The special-purpose processor 4210 can include one processor core or can include a plurality of processor cores such as dual cores, quad cores, or hexa cores. In an exemplary embodiment, the special-purpose processor 4210 can include a number of cores that is greater than a number of cores of the host processor 4110 for the purpose of performing a computation that is specialized for parallelism. For example, the special-purpose processor 4210 can include 1000 or more cores.

[0187] In an exemplary embodiment, the special-purpose processor 4210 can be a processor that is specialized for image data computation. In this case, the special-purpose processor 4210 can read image data stored in the local memory 4230 through the local memory controller 4220 and can perform a computation on the read data. The special-purpose processor 4210 can transfer the computation result to the host processor 4110 or can store the computation result in the local memory 4230. The host processor 4110 can store the transferred computation result in the host memory 4130 or in a frame buffer allocated to a separate memory. The data stored in the frame buffer can be transferred to a separate display device.

[0188] In an exemplary embodiment, the dedicated processor 4210 can be a processor dedicated to neural network-based training and inference. The dedicated processor 4210 can read neural network parameters (e.g., neural network model parameters, weights, and biases) from the local memory 4230 and can perform training or inference on the read neural network parameters. The neural network parameters can be provided from the host processor 4110, can be values obtained through processing of the dedicated processor 4210, or can be pre-stored values. For example, the host processor 4110 can provide the dedicated processor 4210 with weight parameters for inference. In this case, the weight parameters can be parameters updated through training of the host processor 4110. The dedicated processor 4210 can perform training or inference by matrix multiplication and accumulation based on the neural network parameters of the local memory 4230. The dedicated processor 4210 can transfer a result of the calculation to the host processor 4110 or can store the result of the calculation in the local memory 4230.

[0189] The local memory controller 4220 can control overall operations of the local memory 4230. In an exemplary embodiment, the local memory controller 4220 can process data to be written in the local memory 4230 and can write the processed data in the local memory 4230. Alternatively, the local memory controller 4220 can process data read from the local memory 4230. For example, the local memory controller 4220 can perform error correction code (ECC) encoding and ECC decoding, can verify data in a cyclic redundancy check (CRC) manner, or can perform data encryption or data decryption. The local memory controller 4220 can correspond to the memory controller described with reference to Figure 1 to Figure 18 The local memory controller 4220 can transmit a write data strobe signal WDQS to the local memory 4230. In this case, the number of leading periods of the write data strobe signal WDQS and the number of trailing periods of the write data strobe signal WDQS can be an even number.

[0190] The local memory 4230 can be used only by the dedicated processor 4210. In an exemplary embodiment, the local memory 4230 can be mounted on one substrate together with the dedicated processor 4210 or can be implemented in the form of a die, a chip, a package, a module, a card, or an apparatus so as to be connected with the dedicated processor 4210 based on a separate connector. The local memory 4230 can correspond to the memory described with reference to Figure 19The described memory device or stacked memory device. For example, the local memory 4230 can divide the frequency of a write data strobe signal WDQS transmitted from the local memory controller 4220, and can generate an internal write data strobe signal dWDQS having a different phase at low power. The local memory 4230 can communicate with the local memory controller 4220 based on the internal write data strobe signal dWDQS.

[0191] In an exemplary embodiment, the local memory 4230 can include 32 or more data pins. For example, the local memory 4230 can include 1024 or more data pins for the purpose of providing a wide bandwidth. As such, the bus width of each chip of the local memory 4230 can be greater than the bus width of each chip of the host memory 4130.

[0192] In an exemplary embodiment, the local memory 4230 can operate based on a DDR, LPDDR, GDDR, HBM, HMC, or Wide I / O standard interface. However, embodiments are not limited thereto. For example, the local memory 4230 can operate based on various standard interfaces.

[0193] In an exemplary embodiment, the local memory 4230 can include a logic circuit capable of performing some calculations. The logic circuit can perform a linear operation, a comparison operation, a compression operation, a data conversion operation, an arithmetic operation on data read from the local memory 4230 or data to be written to the local memory 4230. As such, the size of data processed by the logic circuit can be reduced. In the case of reducing the size of data, the bandwidth efficiency between the local memory 4230 and the local memory controller 4220 can be improved.

[0194] The host interface 4240 can be configured to allow the accelerator subsystem 4200 to communicate with the host 4100. The accelerator subsystem 4200 can transmit signals and data to the host 4100 through the host interface 4240, and can receive control signals and data from the host 4100. In an exemplary embodiment, the dedicated processor 4210, the local memory controller 4220, and the host interface 4240 can be implemented with one chip.

[0195] The interconnect 4300 can provide a transmission path between the host 4100 and the accelerator subsystem 4200, and can perform a role of a data bus or a data link. The data transmission path can be established wired or wirelessly. The interface 4140 and the host interface 4240 can communicate over the interconnect 4300 based on a given protocol. For example, the interfaces 4140 and 4240 can communicate with each other based on one of various standards, such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (External SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnect), PCIe (PCI Express), NVMe (NVM Express), AXI (Advanced eXtensible Interface), AMBA (ARM Microcontroller Bus Architecture), IEEE 1394, USB (Universal Serial Bus), SD (Secure Digital) card, MMC (MultiMediaCard), eMMC (Embedded Multi-Media Card), UFS (Universal Flash Storage), CF (CompactFlash), and Gen-Z. Alternatively, the interfaces 4140 and 4240 can communicate with each other based on a communication link between devices, such as openCAPI (Coherent Accelerator Processor Interface), CCIX (Cache Coherent Interconnect for Accelerators), CXL (Compute Express Link), and NVLINK. Alternatively, the interfaces 4140 and 4240 can communicate with each other based on a wireless communication technology, such as LTE, 5G, LTE-M, NB-IoT, LPWAN, Bluetooth, NFC (Near Field Communication), Zigbee, Z-Wave, or WLAN.

[0196] In an exemplary embodiment, the accelerator subsystem 4200 can further include a sensor capable of sensing image data, voice data, motion data, biometric data, and surrounding environment information. In an exemplary embodiment, in a case where the sensor is included in the accelerator subsystem 4200, the sensor can be connected with any other component (e.g., the dedicated processor 4210 or the local memory 4230) based on the above-described packaging technology. The accelerator subsystem 4200 can process data sensed through the sensor based on a specific operation.

[0197] In ​ An example in which the dedicated processor 4210 uses one local memory 4230 through one local memory controller 4220 is illustrated in FIG. 4, but embodiments are not limited thereto. For example, the dedicated processor 4210 can use a plurality of local memories through one local memory controller 4220. For another example, the dedicated processor 4210 can use a plurality of local memories through a plurality of local memory controllers corresponding to the local memories, respectively.

[0198] The memory device according to various embodiments described herein can generate an internal write data strobe signal based on a write data strobe signal provided from a memory controller for the purpose of high-speed exchange of data. In this case, the memory device can initialize the internal write data strobe signal to a given value, so that the internal write data strobe signal having a desired phase can be generated in a write operation and a read operation. As such, the memory device can not separately perform auto synchronization for adjusting the phase of the internal write data strobe signal. That is, auto synchronization and a circuit for implementing the auto synchronization can be omitted. Accordingly, power consumption of the memory device can be reduced.

[0199] The memory device according to various embodiments described above can generate a read data strobe signal to be provided to the memory controller based on the write data strobe signal, so that reliability of the read data strobe signal is improved.

[0200] The memory controller according to various embodiments described above can generate the clock signal and the write data strobe signal based on one phase-locked loop. As such, power consumption of the memory controller can be reduced.

[0201] Although various exemplary embodiments have been described, it will be readily apparent to one of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.​​​

Claims

1. A memory device, comprising: A logic die configured to communicate with a host device via multiple channels, each of which includes an independent interface; as well as Multiple memory dies are stacked on the logic die, and each of the multiple memory dies includes a memory cell array corresponding to at least one of the multiple channels. The logic die includes: The first pin is configured to receive a clock signal with a first clock frequency; The second pin is configured to receive write command / address signals based on the clock signal; The third pin is configured to receive a write strobe signal with a second clock frequency; and The DQ pin is configured to receive write data signals based on a plurality of internal write data strobe signals, wherein the plurality of internal write data strobe signals are based on the write strobe signals. Wherein, the first clock frequency is half of the second clock frequency. The write strobe signal includes a major flip-flop period aligned with the write data signal. Wherein, the number of write preamble cycles of the write strobe signal before the main flip period is even. The number of write lead cycles following the main flip period of the write strobe signal is even.

2. The memory device according to claim 1, wherein: The number of write preamble cycles preceding the main flip period for the write strobe signal is two. The number of write afterlead cycles following the main flip period of the write strobe signal is two.

3. The memory device according to claim 1, wherein, Each of the plurality of memory dies includes a plurality of memory banks.

4. The memory device according to claim 1, wherein, The plurality of memory dies stacked on the logic die are electrically connected via through-silicon vias.

5. The memory device according to claim 1, wherein, The logic die includes: A write data strobe frequency divider is configured to generate a plurality of internal write data strobe signals that are flipped based on the flipping of the write strobe signal, the plurality of internal write data strobe signals being flipped with different phases respectively.

6. The memory device according to claim 5, wherein, The logic die also includes: A command / address receiver, configured to receive the write command / address signal via the first pin; Control logic circuitry, configured to generate internal commands based on the write command / address signals; and The data transceiver is configured to receive write data based on the plurality of internal write data strobe signals. The memory die among the plurality of memory dies is configured to store the write data in response to the internal command.

7. The memory device according to claim 5, wherein, The plurality of internal write data gating signals include a first internal write data gating signal, a second internal write data gating signal, a third internal write data gating signal, and a fourth internal write data gating signal, corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. Wherein, the frequency of each of the first internal write data strobe signal to the fourth internal write data strobe signal is half the frequency of the write data strobe signal.

8. A memory device, comprising: A logic die configured to communicate with a host device via multiple channels, each of which includes an independent interface; as well as Multiple memory dies are stacked on the logic die, and each of the multiple memory dies includes a memory cell array corresponding to at least one of the multiple channels. The logic die includes: The first pin is configured to receive a clock signal with a first clock frequency; The second pin is configured to receive write command / address signals based on the clock signal; The third pin is configured to receive a write strobe signal with a second clock frequency; The fourth pin is configured to transmit a read strobe signal with a third clock frequency, the read strobe signal being based on the write strobe signal; and The DQ pin is configured to send a read data signal based on the read strobe signal. Wherein, the first clock frequency is half of the second clock frequency and the third clock frequency. The write strobe signal includes a main flip period. Wherein, the number of read preamble cycles of the write strobe signal before the main flip period is even. The number of read guide cycles following the main flip period of the write strobe signal is even.

9. The memory device according to claim 8, wherein: The number of read preamble cycles preceding the main flip period for the write strobe signal is four. The number of read lead cycles following the main flip period of the write strobe signal is two.

10. The memory device according to claim 8, wherein, Each of the plurality of memory dies includes a plurality of memory banks.

11. The memory device according to claim 8, wherein, The plurality of memory dies stacked on the logic die are electrically connected via through-silicon vias.

12. The memory device according to claim 8, wherein, The logic die includes: A write data strobe frequency divider is configured to generate a plurality of internal write data strobe signals that are flipped based on the flipping of the write strobe signal, the plurality of internal write data strobe signals being flipped with different phases respectively.

13. The memory device according to claim 12, wherein, The logic die also includes: A command / address receiver, configured to receive the write command / address signal via the first pin; Control logic circuitry, configured to generate internal commands based on the write command / address signals; and The data transceiver is configured to receive write data based on the plurality of internal write data strobe signals. The memory die among the plurality of memory dies is configured to store the write data in response to the internal command.

14. The memory device according to claim 12, wherein, The plurality of internal write data strobe signals include a first write data strobe signal, a second write data strobe signal, a third write data strobe signal, and a fourth write data strobe signal, corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively. Wherein, the frequency of each of the first write data strobe signal to the fourth internal write data strobe signal is half the frequency of the write data strobe signal.

15. A memory device, comprising: A logic die configured to communicate with a host device via multiple channels, each of which includes an independent interface; as well as Multiple memory dies are stacked on the logic die, and each of the multiple memory dies includes a memory cell array corresponding to at least one of the multiple channels. The logic die includes: The first pin is configured to receive a clock signal with a first clock frequency; The second pin is configured to receive write command / address signals based on the clock signal; The third pin is configured to receive a write strobe signal with a second clock frequency; The fourth pin is configured to transmit a read strobe signal with a third clock frequency, the read strobe signal being based on the write strobe signal; and The DQ pin is configured to send a read data signal based on the read strobe signal. Wherein, the first clock frequency is half of the second clock frequency and the third clock frequency. The read strobe signal includes a main flip period aligned with the read data signal. Wherein, the number of read preamble cycles of the read strobe signal before the main flip period is even, and The number of read guide cycles following the main flip period of the read strobe signal is even.

16. The memory device according to claim 15, wherein, The number of read preamble cycles preceding the main flip period of the read strobe signal is two, and The number of read afterlead cycles of the read strobe signal after the main flip period is two.

17. The memory device according to claim 15, wherein, Each of the plurality of memory dies includes a plurality of memory banks.

18. The memory device according to claim 15, wherein, The plurality of memory dies stacked on the logic die are electrically connected via through-silicon vias.

19. The memory device according to claim 15, wherein, The logic die includes: A write data strobe frequency divider is configured to generate a plurality of internal write data strobe signals that are flipped based on the flipping of the write strobe signal, the plurality of internal write data strobe signals being flipped with different phases respectively.

20. The memory device of claim 19, wherein, The plurality of internal write data strobe signals include a first write data strobe signal, a second write data strobe signal, a third write data strobe signal, and a fourth write data strobe signal, respectively corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, and Wherein, the frequency of each of the first write data strobe signal to the fourth write data strobe signal is half the frequency of the write data strobe signal.

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