Low-dropout rectifier bridge circuit with wide input voltage range

Abstract

The application provides a low-voltage-drop rectifier bridge circuit with a wide voltage input range, comprising a diode rectifier circuit, a low-voltage-drop auxiliary structure and other load circuits; the input end of the diode rectifier circuit is connected with an AC input signal, and the output end outputs a rectified positive power rail and a reference ground; the input end of the low-voltage-drop auxiliary structure is connected in parallel with the input end of the diode rectifier circuit to the AC input signal, the output end is connected to the positive power rail and the reference ground, and the control signal input end receives a high-side control signal and a low-side control signal; the input end of the other load circuits is connected to the output end of the diode rectifier circuit and the low-voltage-drop auxiliary structure, and the output end outputs the high-side control signal and the low-side control signal to the control signal input end of the low-voltage-drop auxiliary structure. The application clamps the AC signal with a wide voltage input range to a low-voltage domain by using a high-voltage MOS, and selects the corresponding side channel through a cross-coupled circuit structure, so as to reduce the forward voltage drop when the diode is turned on.

Description

Technical Field

[0001] This invention relates to the field of low-dropout rectifier bridge circuit technology, and more specifically, to a low-dropout rectifier bridge circuit with a wide voltage input range. Background Technology

[0002] Existing technologies, such as traditional diode rectifier bridges, have large voltage drops, limiting the minimum input signal voltage and making them unsuitable for low-power applications. All-MOS active rectifier bridges require additional independent power supplies and drive control circuitry, resulting in complex systems, high costs, and unsuitability for single-power-supply applications, making on-chip integration difficult. Other existing hybrid diode and MOS semi-active rectification solutions struggle to meet the requirements of a wide input voltage range.

[0003] Patent application CN222506449U discloses a frequency converter protection circuit for input phase loss and relay activation detection, including a relay activation detection circuit, an input phase loss detection circuit, and a signal synthesis circuit. The signal synthesis circuit includes a NAND gate, with input A of the NAND gate connected to the relay activation detection circuit, input B of the NAND gate connected to the input phase loss detection circuit, and output Y of the NAND gate connected to a controller. However, this patent cannot completely solve the existing technical problems, nor can it meet the needs of this invention. Summary of the Invention

[0004] In view of the deficiencies in the prior art, the purpose of this invention is to provide a low-dropout rectifier bridge circuit with a wide voltage input range.

[0005] The low-dropout rectifier bridge circuit with a wide voltage input range provided by the present invention includes: a diode rectifier circuit, a low-dropout auxiliary structure, and other load circuits;

[0006] The input terminal of the diode rectifier circuit is connected to the AC input signal, and its output terminal outputs the rectified positive power rail and reference ground.

[0007] The input terminal of the low voltage drop auxiliary structure is connected in parallel with the input terminal of the diode rectifier circuit to the AC input signal, its output terminal is connected to the positive power rail and the reference ground, and its control signal input terminal receives the high-side control signal and the low-side control signal.

[0008] The input terminals of the other load circuits are connected to the output terminals of the diode rectifier circuit and the low-dropout auxiliary structure, and their output terminals output the high-side control signal and the low-side control signal to the control signal input terminal of the low-dropout auxiliary structure.

[0009] Preferably, the diode rectifier circuit includes a first diode, a second diode, a third diode, and a fourth diode;

[0010] The anodes of both the first and second diodes are connected to the reference ground, and the cathodes are respectively connected to the first and second input terminals of the AC input signal.

[0011] The anodes of the third and fourth diodes are connected to the first and second input terminals of the AC input signal, respectively, and the cathodes of both diodes are connected to the positive power rail.

[0012] Preferably, the low voltage drop auxiliary structure includes a lower half-bridge voltage drop reduction circuit and an upper half-bridge voltage drop reduction circuit;

[0013] The lower half-bridge voltage drop reduction circuit includes a first high-voltage NMOS, a second high-voltage NMOS, a third high-voltage NMOS, a fourth high-voltage NMOS, a first resistor, and a second resistor;

[0014] The gate terminal of the first high-voltage NMOS is connected to one end of the first resistor, the drain terminal is connected to one end of the second resistor, and the source terminal is connected to the reference ground;

[0015] The gate terminal of the second high-voltage NMOS is connected to the other end of the second resistor, the drain terminal is connected to the other end of the first resistor, and the source terminal is connected to the reference ground;

[0016] The gate terminal of the third high-voltage NMOS is connected to the low-side control signal terminal, the drain terminal is connected to the first input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the first high-voltage NMOS.

[0017] The gate terminal of the fourth high-voltage NMOS is connected to the low-side control signal terminal, the drain terminal is connected to the second input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the second high-voltage NMOS.

[0018] The upper half-bridge voltage drop reduction circuit includes a first high-voltage PMOS, a second high-voltage PMOS, a third high-voltage PMOS, a fourth high-voltage PMOS, a third resistor, and a fourth resistor;

[0019] The gate terminal of the first high-voltage PMOS is connected to one end of the third resistor, the drain terminal is connected to one end of the fourth resistor, and the source terminal is connected to the positive power rail.

[0020] The gate terminal of the second high-voltage PMOS is connected to the other end of the fourth resistor, the drain terminal is connected to the other end of the third resistor, and the source terminal is connected to the positive power rail.

[0021] The gate terminal of the third high-voltage PMOS is connected to the high-side control signal terminal, the drain terminal is connected to the first input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the first high-voltage PMOS.

[0022] The gate terminal of the fourth high-voltage PMOS is connected to the high-side control signal terminal, the drain terminal is connected to the second input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the second high-voltage PMOS.

[0023] Preferably, the other load circuit includes a voltage-regulating capacitor and a load circuit;

[0024] The positive plate of the voltage regulator capacitor is connected to the positive power rail, and its negative plate is connected to the reference ground;

[0025] The input terminal of the load circuit is connected to the positive power rail and the reference ground, and its output terminal outputs the high-side control signal and the low-side control signal.

[0026] Preferably, the low-side control signal is based on the voltage of the reference ground, and the high-side control signal is based on the voltage of the positive power rail; the level of the low-side control signal is the low-voltage power domain voltage, and the level of the high-side control signal is the voltage of the positive power rail minus a low-voltage power domain voltage.

[0027] Preferably, when the system is powered on, the diode rectifier circuit operates first, generating the initial positive power rail and the reference ground; based on the initial positive power rail and the reference ground, the other load circuits operate and generate the high-side control signal and the low-side control signal; subsequently, the low-dropout auxiliary structure starts operating based on the high-side control signal and the low-side control signal.

[0028] Preferably, when the AC input signal is such that the voltage at the first input terminal is higher than the voltage at the second input terminal:

[0029] In the lower half-bridge voltage drop reduction circuit, the difference between the low-side control signal and the voltage at the second input terminal is greater than the threshold voltage of the fourth high-voltage NMOS, causing the channel of the fourth high-voltage NMOS to be turned on, pulling down the gate voltage of the first high-voltage NMOS to turn it off; the gate voltage of the second high-voltage NMOS is clamped by the gate of the third high-voltage NMOS; the gate of the second high-voltage NMOS is at a high level, causing its channel to be turned on, thereby connecting the reference ground and the second input terminal through the turned-on second high-voltage NMOS and fourth high-voltage NMOS;

[0030] In the upper half-bridge voltage drop reduction circuit, the difference between the first input terminal voltage and the high-side control signal is greater than the threshold voltage of the third high-voltage PMOS, causing the channel of the third high-voltage PMOS to be turned on, pulling up the gate voltage of the second high-voltage PMOS to turn it off; the gate voltage of the first high-voltage PMOS is clamped by the gate of the fourth high-voltage PMOS; the channel of the first high-voltage PMOS is turned on, thereby connecting the positive power rail and the first input terminal through the turned-on first high-voltage PMOS and the third high-voltage PMOS.

[0031] Preferably, the gate of the third high-voltage NMOS is connected to the low-side control signal, and its source potential follows the gate potential, being clamped up to the level of the low-side control signal; the gate of the fourth high-voltage PMOS is connected to the high-side control signal, and its source potential follows the gate potential, being clamped down to the level of the high-side control signal.

[0032] Preferably, when the low-voltage-drop auxiliary structure is activated, the voltage of the positive power rail is:

[0033]

[0034] The voltage of the reference ground is:

[0035]

[0036] Where I is the total current of the entire chip. , , , These are the on-resistances of the first high-voltage PMOS, the third high-voltage PMOS, the second high-voltage NMOS, and the fourth high-voltage NMOS, respectively. and These are the voltages at the first and second input terminals of the AC input signal, respectively.

[0037] Preferably, for low-power applications, the on-resistance of the first high-voltage PMOS, the third high-voltage PMOS, the second high-voltage NMOS, and the fourth high-voltage NMOS is configured such that when the total current I is a low-power level current, the voltage drop of the low-voltage drop auxiliary structure is lower than the forward voltage drop of the diode.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] (1) By using high-voltage MOS gate-source clamping, the input high-voltage signal is restricted to the low-side / high-side low-voltage domain, thereby protecting the internal circuit and adapting to a wider voltage input range;

[0040] (2) By using the cross-coupled MOS structure, the MOS channel of the corresponding bridge arm is adaptively selected according to the polarity of the input signal, thereby bypassing the forward-conducting diode, solving the problem of large voltage drop loss of traditional diode rectifier bridge, and achieving a lower rectified voltage drop. Attached Figure Description

[0041] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0042] Figure 1 Schematic diagram of a low-dropout rectifier bridge circuit with a wide input voltage range;

[0043] Figure 2 The conduction status and current path when A is high and B is low;

[0044] Figure 3 This describes the conduction status and current path when A is low and B is high. Detailed Implementation

[0045] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0046] Example

[0047] like Figure 1 This invention provides a low-dropout rectifier bridge circuit with a wide voltage input range, including a diode rectifier circuit 1, a low-dropout auxiliary structure 2, and other load circuits 3. Specifically: the input terminal of the diode rectifier circuit 1 is connected to the input AC signal, and its output terminals are VDD and GND; the input terminal of the low-dropout auxiliary structure 2 is connected in parallel with the input terminal of the diode rectifier circuit 1, and its output terminal is connected to VDD and GND, with the control signal input terminal... and The input terminal of the other load circuit 3 is connected to the output terminal of the diode rectifier circuit 1 and the low voltage drop auxiliary structure 2, and the output terminal is connected to the control input terminal of the low voltage drop auxiliary structure 2.

[0048] The diode rectifier circuit 1 includes: upper half-bridge diodes D3 and D4 and lower half-bridge diodes D1 and D2. Specifically: the anodes of diodes D1 and D2 are connected to the rectified reference ground GND, and their cathodes are connected to the input terminals A and B of the AC input signal, respectively; the anodes of diodes D3 and D4 are connected to terminals A and B of the AC input signal, respectively, and their cathodes are connected to the rectified positive power rail VDD.

[0049] The low-dropout auxiliary structure 2 includes: a lower half-bridge voltage drop reduction circuit composed of high-voltage NMOS transistors Mn1, Mn2, Mn3, and Mn4 and resistors R1 and R2; and an upper half-bridge voltage drop reduction circuit composed of high-voltage PMOS transistors Mp1, Mp2, Mp3, and Mp4 and resistors R3 and R4. Specifically: in the lower half-bridge voltage drop reduction circuit, the gate terminal of Mn1 is connected to one end of resistor R2, the drain terminal is connected to one end of resistor R1, and the source terminal is connected to GND; the gate terminal of Mn2 is connected to the other end of resistor R1, the drain terminal is connected to the other end of resistor R2, and the source terminal is connected to GND; the gate terminal of Mn3 is connected to the low-side control signal terminal. The drain terminal is connected to the AC input signal terminal A, and the source terminal is connected to the drain terminal of Mn1; the gate terminal of Mn4 is connected to the same low-side control signal terminal as Mn3. The drain of Mp1 is connected to the other end B of the AC input signal, and the source is connected to the drain of Mn2. In the upper half-bridge voltage drop reduction circuit, the gate of Mp1 is connected to one end of resistor R4, the drain is connected to one end of resistor R3, and the source is connected to VDD; the gate of Mp2 is connected to the other end of resistor R3, the drain is connected to the other end of resistor R4, and the source is connected to VDD; the gate of Mp3 is connected to the high-side control signal terminal. The drain terminal is connected to AC input signal terminal A, and the source terminal is connected to the drain terminal of Mp1; the gate terminal of Mp4 is connected to the same high-side control signal terminal as Mp3. The drain terminal is connected to the other end B of the AC signal, and the source terminal is connected to the drain terminal of Mp2.

[0050] Other load circuit 3 includes: a voltage regulator capacitor C and a load circuit Load. The positive plate of the voltage regulator capacitor C is connected to the rectified positive power rail VDD, and the negative plate is connected to GND. The output of the load circuit Load is connected to the high-side and low-side control signal inputs of the low-dropout auxiliary structure 2, respectively. .

[0051] This embodiment operates through the following steps:

[0052] When the system is powered on, assume the AC input signal state is A high and B low, or vice versa. First, diode rectifier circuit 1 starts working, generating rectified power rails VDD and GND. The initial rectified power rail voltage is:

[0053]

[0054]

[0055] From input voltage After rectification voltage The loss is the forward voltage drop of the two diodes. .

[0056] Then, based on the power rail after initial rectification, the load circuit starts working, generating a high-side control signal. and low-side control signal .in: As a low-side control signal based on GND, the specific level can be designed to be a common low-voltage power supply voltage such as 1.8V / 2.7V / 3V / 3.3V, depending on actual needs; As a high-side control signal based on VDD, the specific level can be designed as follows: Common low-voltage power supply voltages include -1.8V, 2.7V, 3V, and 3.3V. Specific implementation methods are not limited.

[0057] because When the voltage exceeds the threshold voltage of Mn4, the Mn4 channel turns on, pulling down the gate voltage of Mn1, turning Mn1 off. The gate of Mn2 is clamped by the gate of Mn3, with the highest voltage being... Otherwise, the gate-source voltage of Mn3 is less than 0, the channel is closed, thus protecting the gate of Mn2 from being below the breakdown voltage. At the same time, since the gate of Mn2 is at a high level, the channel is turned on, and then GND to B is connected through the channels of Mn2 and Mn4, which is equivalent to bypassing the D2 diode, reducing the voltage drop to almost 0.

[0058] The operation of the high-side circuit is similar. When the voltage exceeds the threshold voltage of Mp3, the Mp3 channel turns on, pulling up the gate voltage of Mp2. Mp2 is turned off; while the gate voltage of Mp1 is clamped by the gate of Mp4, with a minimum value of This protects Mp1 so that its gate-source voltage is less than its breakdown voltage. At the same time, the Mp1 channel is turned on, and VDD and A are connected through the channels of Mp1 and Mp3, which is equivalent to bypassing diode D3, reducing the voltage drop to almost zero.

[0059] Taking low-side clamping as an example, A is high and B is low. The gate potential of Mn2 is the source potential of Mn3 because there is no current in the gate and there is no voltage drop across resistor R1 (it is only used for ESD protection). The gate of Mn3 comes from a low-voltage domain signal generated through other circuits (load), with a maximum voltage of VH (based on GND).

[0060] The source of MN3 follows the gate, with a maximum gate voltage VH. Otherwise, the gate-source voltage of Mn3 is less than 0, the channel is closed, there is no current, so the source potential will not increase further, thus achieving clamping.

[0061] Similarly, on the high side, the gate of Mp1 is the source of Mp4. The lowest point is when the gate-source voltage of Mp4 is 0. At this point, the lowest point of the gate of Mp1 is the gate VL of Mp4. VL is a low-voltage domain signal based on VDD. The voltage to VDD is low voltage (<5V), so the gate-source voltage of Mp1 is also clamped to low voltage.

[0062] When the low-dropout auxiliary structure 2 is activated, the rectified power rail voltage becomes:

[0063]

[0064]

[0065] Where I is the total current of the entire chip. , , , These are the on-resistances of Mp1, Mp3, Mn2, and Mn4, respectively. For low-power chips, taking a 20uA quiescent current as an example, the on-resistance of a single high-voltage MOS on-chip only needs to be less than 1kohm, and the voltage drop on the MOS branch is only 40mV, far less than the forward voltage drop of a diode (usually around 0.6V), thus achieving a low-voltage-drop rectification effect. A MOS with an on-resistance of 1kohm is easily achievable for on-chip integration.

[0066] like Figure 2 and Figure 3 When A is high and B is low, the gate of Mn2 is high and the gate of Mn1 is low, so the Mn2 branch is turned on, bypassing the lower transistor on the B side. Conversely, when A is low and B is high, the gate of Mn2 is low and the gate of Mn1 is high, so the Mn1 branch is turned on, bypassing the lower transistor on the A side. The source potentials of Mn3 and Mn4 follow A / B respectively, so their polarities are consistent. When A is high and B is low, the source potential of Mn3 is also higher than that of Mn4. Since there is no current at the gate, there is no voltage drop across R1 and R2, so the source potentials of Mn3 and Mn4 are the same as the gate potentials of Mn2 and Mn1.

[0067] Similar to the high-side half-bridge, when A is high and B is low, the source potential of Mp4 is low, there is no voltage drop across R4, the gate potential of Mp1 is low, the Mp1 branch is on, and the upper transistor D3 on the A side is bypassed. When A is low and B is high, the gate potential of Mp2 is low, the Mp2 branch is on, and the upper transistor on the B side is bypassed.

[0068] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0069] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A low-dropout rectifier bridge circuit with a wide voltage input range, characterized in that, include: Diode rectifier circuits, low-dropout auxiliary structures, and other load circuits; The input terminal of the diode rectifier circuit is connected to the AC input signal, and its output terminal outputs the rectified positive power rail and reference ground. The input terminal of the low voltage drop auxiliary structure is connected in parallel with the input terminal of the diode rectifier circuit to the AC input signal, its output terminal is connected to the positive power rail and the reference ground, and its control signal input terminal receives the high-side control signal and the low-side control signal. The input terminal of the other load circuit is connected to the output terminal of the diode rectifier circuit and the low voltage drop auxiliary structure, and its output terminal outputs the high-side control signal and the low-side control signal to the control signal input terminal of the low voltage drop auxiliary structure; The diode rectifier circuit includes a first diode, a second diode, a third diode, and a fourth diode; The anodes of both the first and second diodes are connected to the reference ground, and the cathodes are respectively connected to the first and second input terminals of the AC input signal. The anodes of the third and fourth diodes are respectively connected to the first and second input terminals of the AC input signal, and the cathodes of both diodes are connected to the positive power rail. The low voltage drop auxiliary structure includes a lower half-bridge voltage drop reduction circuit and an upper half-bridge voltage drop reduction circuit; The lower half-bridge voltage drop reduction circuit includes a first high-voltage NMOS, a second high-voltage NMOS, a third high-voltage NMOS, a fourth high-voltage NMOS, a first resistor, and a second resistor; The gate terminal of the first high-voltage NMOS is connected to one end of the first resistor, the drain terminal is connected to one end of the second resistor, and the source terminal is connected to the reference ground; The gate terminal of the second high-voltage NMOS is connected to the other end of the second resistor, the drain terminal is connected to the other end of the first resistor, and the source terminal is connected to the reference ground; The gate terminal of the third high-voltage NMOS is connected to the low-side control signal terminal, the drain terminal is connected to the first input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the first high-voltage NMOS. The gate terminal of the fourth high-voltage NMOS is connected to the low-side control signal terminal, the drain terminal is connected to the second input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the second high-voltage NMOS. The upper half-bridge voltage drop reduction circuit includes a first high-voltage PMOS, a second high-voltage PMOS, a third high-voltage PMOS, a fourth high-voltage PMOS, a third resistor, and a fourth resistor; The gate terminal of the first high-voltage PMOS is connected to one end of the third resistor, the drain terminal is connected to one end of the fourth resistor, and the source terminal is connected to the positive power rail. The gate terminal of the second high-voltage PMOS is connected to the other end of the fourth resistor, the drain terminal is connected to the other end of the third resistor, and the source terminal is connected to the positive power rail. The gate terminal of the third high-voltage PMOS is connected to the high-side control signal terminal, the drain terminal is connected to the first input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the first high-voltage PMOS. The gate terminal of the fourth high-voltage PMOS is connected to the high-side control signal terminal, the drain terminal is connected to the second input terminal of the AC input signal, and the source terminal is connected to the drain terminal of the second high-voltage PMOS. The other load circuits include voltage stabilizing capacitors and load circuits; The positive plate of the voltage regulator capacitor is connected to the positive power rail, and its negative plate is connected to the reference ground; The input terminal of the load circuit is connected to the positive power rail and the reference ground, and its output terminal outputs the high-side control signal and the low-side control signal.

2. The low-dropout rectifier bridge circuit with a wide voltage input range according to claim 1, characterized in that, The low-side control signal is based on the voltage of the reference ground, and the high-side control signal is based on the voltage of the positive power rail; the level of the low-side control signal is the low-voltage power domain voltage, and the level of the high-side control signal is the voltage of the positive power rail minus a low-voltage power domain voltage.

3. The low-dropout rectifier bridge circuit with a wide voltage input range according to claim 1, characterized in that, When the system is powered on, the diode rectifier circuit operates first, generating the initial positive power rail and the reference ground; based on the initial positive power rail and the reference ground, the other load circuits operate and generate the high-side control signal and the low-side control signal; subsequently, the low-dropout auxiliary structure starts operating based on the high-side control signal and the low-side control signal.

4. The low-dropout rectifier bridge circuit with a wide voltage input range according to claim 1, characterized in that, When the AC input signal is such that the voltage at the first input terminal is higher than the voltage at the second input terminal: In the lower half-bridge voltage drop reduction circuit, the difference between the low-side control signal and the voltage at the second input terminal is greater than the threshold voltage of the fourth high-voltage NMOS, causing the channel of the fourth high-voltage NMOS to be turned on, pulling down the gate voltage of the first high-voltage NMOS to turn it off; the gate voltage of the second high-voltage NMOS is clamped by the gate of the third high-voltage NMOS; the gate of the second high-voltage NMOS is at a high level, causing its channel to be turned on, thereby connecting the reference ground and the second input terminal through the turned-on second high-voltage NMOS and fourth high-voltage NMOS; In the upper half-bridge voltage drop reduction circuit, the difference between the first input terminal voltage and the high-side control signal is greater than the threshold voltage of the third high-voltage PMOS, causing the channel of the third high-voltage PMOS to be turned on, pulling up the gate voltage of the second high-voltage PMOS to turn it off; the gate voltage of the first high-voltage PMOS is clamped by the gate of the fourth high-voltage PMOS; the channel of the first high-voltage PMOS is turned on, thereby connecting the positive power rail and the first input terminal through the turned-on first high-voltage PMOS and the third high-voltage PMOS.

5. The low-dropout rectifier bridge circuit with a wide voltage input range according to claim 4, characterized in that, The gate of the third high-voltage NMOS is connected to the low-side control signal, and its source potential follows the gate potential, being clamped up to the level of the low-side control signal; the gate of the fourth high-voltage PMOS is connected to the high-side control signal, and its source potential follows the gate potential, being clamped down to the level of the high-side control signal.

6. The low-dropout rectifier bridge circuit with a wide voltage input range according to claim 4, characterized in that, When the low-voltage-drop auxiliary structure is activated, the voltage of the positive power rail is: The voltage of the reference ground is: Where I is the total current of the entire chip. , , , These are the on-resistances of the first high-voltage PMOS, the third high-voltage PMOS, the second high-voltage NMOS, and the fourth high-voltage NMOS, respectively. and These are the voltages at the first and second input terminals of the AC input signal, respectively.

7. The low-dropout rectifier bridge circuit with a wide voltage input range according to claim 6, characterized in that, For low-power applications, the on-resistance of the first high-voltage PMOS, the third high-voltage PMOS, the second high-voltage NMOS, and the fourth high-voltage NMOS is configured such that when the total current I is a low-power level current, the voltage drop of the low-voltage drop auxiliary structure is lower than the forward voltage drop of the diode.

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