High-integration 64-channel orthogonal frequency conversion digital TR assembly

Abstract

The invention discloses a high-integration 64-channel orthogonal frequency conversion digital TR assembly which comprises a frequency synthesizer module and two digital radio frequency modules. The two digital radio frequency modules have the same structure, and one digital radio frequency module receives a control signal, transmits a baseband signal, returns a monitoring signal and receives the baseband signal through the other digital radio frequency module; the frequency synthesizer module comprises a network port module, a first connector module, a frequency synthesis module and a first FPGA module; the digital radio frequency module comprises a second FPGA module, a second connector module, a clock module, a radio frequency transceiver module and a radio frequency SiP module; the radio frequency transceiver module completes digital-to-analog conversion, analog-to-digital conversion and orthogonal up-conversion of a transmitted signal; and the radio frequency SiP module completes processing such as up-down conversion and the like of radio frequency transceiving signals. The integration level of the digital TR assembly can be effectively improved, the size and the weight of the digital TR assembly are reduced, and 64-channel transceiving signal synchronous processing is achieved.

Description

Technical Field

[0001] This invention belongs to the field of digital TR circuit technology, specifically relating to a highly integrated 64-channel quadrature frequency conversion digital TR component. Background Technology

[0002] In the application of phased array antennas, digital TR modules are increasingly used. As a core component of phased array antennas, digital TR modules urgently need to undergo miniaturization and integration. Currently, conventional digital TR modules suffer from drawbacks such as large size, limited channel count, and the need for independent pre-stage quadrature frequency conversion modules, making them unsuitable for the development trend of modern digital array radars. Specifically, the limiting factors are mainly as follows: 1. The size is relatively large. Currently, most transceiver links use single-function devices. The number and variety of devices required to complete the overall transceiver function are large, resulting in a relatively large system size. 2. The number of channels is limited. Due to the system structure and size, it is impossible to design more channels in a limited space. Generally, it is 4 channels or 8 channels, and the total number of channels is not large. 3. The transmit / receive link frequency band is generally intermediate frequency, which requires an independent frequency converter or quadrature frequency converter module, resulting in poor integration. Summary of the Invention

[0003] The purpose of this invention is to address the shortcomings of existing digital TR components by providing a highly integrated 64-channel quadrature frequency conversion digital TR component.

[0004] One aspect of the present invention provides a highly integrated 64-channel quadrature frequency conversion digital TR component, including a frequency synthesizer module and two digital radio frequency modules; The two digital radio frequency modules have the same structure. One digital radio frequency module receives control signals and transmits baseband signals from the frequency synthesizer module via the other digital radio frequency module, and sends monitoring signals and receives baseband signals back to the frequency synthesizer module. The frequency synthesis module includes a network port module, a first connector module, a frequency synthesis module, and a first FPGA module; the digital radio frequency module includes a second FPGA module, a second connector module, a clock module, a radio frequency transceiver module, and a radio frequency SiP module. The first FPGA module communicates with an external host computer via a network port module, receiving control signals and transmitting baseband data from the host computer; the first connector module is used to communicate with the digital radio frequency module, receiving monitoring signals and receiving baseband signals from the digital radio frequency module from the first connector module, and sending them to the external host computer via the network port module; the frequency synthesis module is used to provide the board-level reference clock and mixing local oscillator clock for the digital radio frequency module. The second FPGA module connects to the second connector module and the RF transceiver module to process transmitted and received data. The second connector module transmits received baseband signals and transmitted baseband signals. The RF transceiver module communicates with the second FPGA module to perform digital signal communication, including digital-to-analog conversion, analog-to-digital conversion, and quadrature up / down conversion. The RF transceiver module includes eight RF transceiver chips, each supporting four channels of transmitted and received signals. The RF SiP module connects to the external antenna and the RF transceiver module to perform transmitted baseband beamforming, received baseband beamforming, and quadrature up / down conversion. The clock module provides a high-speed link synchronization clock tree for the second FPGA module and the RF transceiver module.

[0005] The highly integrated 64-channel orthogonal frequency conversion digital TR component according to the above aspects of the present invention can effectively improve the integration of digital TR components, reduce the size and weight of digital TR components, and realize synchronous processing of 64-channel transmit and receive signals. Attached Figure Description

[0006] To more clearly illustrate the technical solutions of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 This is a structural block diagram of a highly integrated 64-channel orthogonal frequency converter digital TR component according to an embodiment of the present invention. Detailed Implementation

[0007] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0008] One embodiment of the present invention provides a highly integrated 64-channel quadrature frequency converter digital TR component (hereinafter referred to as digital TR component). For example... Figure 1 As shown, the digital TR component of this embodiment includes a frequency synthesizer module 1, a first digital radio frequency module 2, and a second digital radio frequency module 3. The first digital radio frequency module 2 and the second digital radio frequency module 3 have the same design. The difference is that the second digital radio frequency module 3 receives control signals and transmits baseband signals from the frequency synthesizer module 1 via the first digital radio frequency module 2, and sends monitoring signals and receives baseband signals back to the frequency synthesizer module 1.

[0009] Frequency synthesis module 1 includes a network port module 1-1, a first connector module 1-2, a frequency synthesis module 1-3, a first power supply module 1-4, and a first FPGA module 1-5. First digital radio frequency module 2 includes a second FPGA module 2-1, a second connector module 2-2, a first clock module 2-3, a second power supply module 2-4, a first radio frequency transceiver module 2-5, and a first radio frequency SiP module 2-6. Second digital radio frequency module 3 includes a third FPGA module 3-1, a third connector module 3-2, a second clock module 3-3, a third power supply module 3-4, a second radio frequency transceiver module 3-5, and a second radio frequency SiP module 3-6.

[0010] Network port module 1-1 connects the network port and the first FPGA module 1-5; the first connector module 1-2 connects the first FPGA module 1-5 and the second connector module 2-2; the frequency synthesis module 1-3 connects to an external reference clock at its input and connects to the first clock module 2-3 and the second clock module 3-3 at its output; the first power module 1-4 connects to an external power supply at its input and connects to the electrical components of this module, the second power module 2-4, and the third power module 3-4 at its output.

[0011] The second FPGA module 2-1 connects to the second connector module 2-2 and the first RF transceiver module 2-5; the second connector module 2-2 connects to the first connector module 1-2, the second FPGA module 2-1, and the third connector module 3-2; the clock module 2-3 has its input connected to the frequency synthesis module 1-3 and its output connected to the second FPGA module 2-1 and the first RF transceiver module 2-5; the second power module 2-4 has its input connected to the first power module 1-4 and its output connected to each power-consuming module; the first RF transceiver module 2-5 connects to the second FPGA module 2-1 and the first RF SiP module 2-6.

[0012] The third FPGA module 3-1 connects to the third connector module 3-2 and the second RF transceiver module 3-5; the third connector module 3-2 connects to the second connector module 2-2 and the third FPGA module 3-1; the clock module 3-3 has its input connected to the frequency synthesis module 1-3 and its output connected to the third FPGA module 3-1 and the second RF transceiver module 3-5; the third power module 3-4 has its input connected to the first power module 1-4 and its output connected to each power-consuming module; the second RF transceiver module 3-5 connects to the third FPGA module 3-1 and the second RF SiP module 3-6.

[0013] Frequency synthesis module 1 communicates with an external host computer through network port module 1-1, obtains control signals and transmit baseband data from the external host computer, processes the signals, and sends them to the first digital radio frequency module 2 through the first connector module 1-2. The control signals and transmit baseband signals required by the second digital radio frequency module 3 are forwarded through the first digital radio frequency module 2. The first FPGA module 1-5 receives the monitoring signals and receive baseband signals of the first digital radio frequency module 2 through the first connector module 1-2, and sends them to the external host computer through network port module 1-1. The monitoring signals and receive baseband signals of the second digital radio frequency module 3 are forwarded through the first digital radio frequency module 2.

[0014] The frequency synthesis module 1 communicates with the digital radio frequency module 2 through the first connector module 1-2, provides the board-level reference clock and mixing local oscillator clock for the digital radio frequency module 2 and the digital radio frequency module 3 through the frequency synthesis module 1-3, provides the operating power for the digital radio frequency module 2 and the digital radio frequency module 3 through the first power supply module 1-4, completes the preliminary data processing through the first FPGA module 1-5, and transmits the processed data to the digital radio frequency module 2 through the first connector module 1-2.

[0015] The frequency synthesis modules 1-3 include a temperature-controlled crystal oscillator, multiple power dividers, and multiple phase-locked loops (PLLs). The temperature-controlled crystal oscillator is connected to an external reference clock, which is then output to two PLLs via two power dividers. One PLL outputs two mixing local oscillator clocks, providing mixing local oscillator clocks for the first digital radio frequency (RF) module 2 and the second RF module 3, respectively. The other PLL generates a board-level reference clock and divides it into three outputs: two outputs to the first RF module 2 and the second RF module 3, and the remaining one output to the first FPGA modules 1-5 as the system operating clock. The second PLL has a ping-pong ring structure and features dual-channel local oscillator clock switching functionality.

[0016] The first digital radio frequency module 2 is connected to an external antenna via the first radio frequency SiP module 2-6. The first digital radio frequency module 2 performs transmitting baseband beamforming, digital-to-analog conversion, orthogonal upconversion, and radio frequency transmission; and performs receiving radio frequency signal orthogonal downconversion, analog-to-digital conversion, and receiving baseband beamforming.

[0017] The second FPGA module 2-1 handles data transmission and reception processing and board-level control. A high-performance FPGA can be selected, providing ample hardware and software support resources. By optimizing the selection of FPGA devices, the bandwidth requirements for multi-channel transmission and reception signals can be met, thereby improving digital bandwidth capabilities. The second connector module 2-2 is used to transmit and receive baseband signals.

[0018] The first clock module 2-3 provides a multi-channel high-speed link synchronous clock tree for the second FPGA module 2-1 and the first RF transceiver module 2-5 through a two-level clock structure. In one embodiment, the first clock module 2-3 provides 8 synchronous reference clocks and 2 sets of core synchronous clocks for the second FPGA module 2-1 through a two-level clock structure, and provides 8 synchronous operating clocks and 8 synchronous pulse clocks for the first RF transceiver module 2-5 through a two-level clock structure.

[0019] Specifically, the first clock module 2-3 distributes the board-level reference clock received from the frequency synthesizer module 1 into four clock channels. Two of these channels are output to the second FPGA module 2-1 as the GT (Gigabit Transceiver) reference clock, one channel is output to the second FPGA module 2-1 as the system operating clock, and the last channel output generates a synchronous clock tree for eight high-speed links between the second FPGA module 2-1 and the first RF transceiver module 2-5 through a two-stage clock structure. The first digital RF module 2 distributes the mixing local oscillator signal received from the frequency synthesizer module 1 to the first RF SiP module 2-6 through a 16-channel equal-diameter power divider circuit as the mixing local oscillator clock for transceiver frequency conversion.

[0020] The first RF transceiver module 2-5 communicates with the second FPGA module 2-1 to perform digital signal conversion, digital-to-analog conversion, analog-to-digital conversion, and local oscillator generation, and controls the quadrature up-conversion and down-conversion functions. The first RF transceiver module 2-5 includes eight RF transceiver chips, each supporting four channels of transmit and receive signals. The RF transceiver chips support external local oscillator input and local local oscillator generation, multi-channel synchronization and multi-chip synchronization, and quadrature mixing, digital-to-analog conversion, and analog-to-digital conversion.

[0021] The first RF SiP module 2-6 is connected to the first RF transceiver module 2-5 to realize intermediate frequency (IF) signal transmission and RF signal transmission and reception. The first RF SiP module 2-6 uses highly integrated SiP devices to replace the RF transceiver and frequency conversion function circuits, realizing bidirectional amplification, bandpass filtering, and bidirectional transceiver frequency conversion functions for RF transceiver signals.

[0022] The first RF SiP module 2-6 uses 16 highly integrated RF SiP devices and requires 16 local oscillator clocks. The first clock module 2-3 provides 16 local oscillator clocks to the first RF SiP module 2-6 through a 16-channel equal-diameter power divider circuit, serving as the mixing local oscillator clock for transmit / receive conversion. The SiP devices support transmit / receive channel switching, performing up-conversion, filtering, attenuation, amplification, and limiting processing on the transmitted signal, and limiting, low-noise amplification, attenuation, amplification, filtering, and down-conversion processing on the received signal. The first RF SiP module 2-6 has an RF switching circuit, which enables the switching of the transmit / receive path.

[0023] The frequency synthesis module 1, the first digital radio frequency module 2, and the second digital radio frequency module 3 also have debugging and testing interface sockets, which can perform serial communication and JTAG debugging.

[0024] The first power module 1-4 receives power input from the outside and forwards it to the first digital radio frequency module 2 and the second digital radio frequency module 3. The first digital radio frequency module 2 receives the +12V power forwarded by the frequency synthesizer module 1 through the second connector module 2-2, and generates the required voltages at each stage through its internal DC-DC-LDO power system. The first power module 1-4 and the second power module 2-4 consist of a two-stage DC-DC-LDO power supply, which converts the externally input +12V into voltages such as +9V, +5V, +3.3V, +2.5V, +1.8V, +1.2V, +1V, and +0.85V to meet the operating voltage requirements of the internal components of the frequency synthesizer module 1, digital radio frequency module 2, and digital radio frequency module 3.

[0025] Frequency synthesis module 1, first digital radio frequency module 2 and second digital radio frequency module 3 use SMA type radio frequency connectors to transmit system clock and local oscillator clock, use J30 series flexible wire connectors to transmit power, and use FMC series hard connectors to transmit high-speed digital signals.

[0026] The first FPGA module 1-5 and the second FPGA module 2-1 receive control signals and transmit baseband signals, and perform signal processing internally, including but not limited to multi-beamforming, digital up-conversion, interpolation filtering, decimation filtering, and amplitude and phase correction. The processed signal is output to the first RF transceiver module, which performs digital-to-analog conversion and analog quadrature conversion before outputting it to the first RF SiP module. The first RF SiP module amplifies, low-pass filters, mixes, band-pass filters, and limits the transmitted signal, and finally outputs it to the antenna to complete signal transmission. Through the reverse path, the first digital RF module 2 can complete signal reception.

[0027] The frequency synthesis module 1 and the first digital radio frequency module 2 can independently form a 32-channel digital TR component, and the switching of the transmit and receive paths is realized through the switching circuit of the first radio frequency SiP module 2-6.

[0028] When transmitting signals, the specific transmission process is as follows: The first FPGA module 1-5 communicates with the external host computer through the network port module 1-1 to receive control signals and baseband data of the transmission beam. The first FPGA module 1-5 controls the frequency synthesis module 1-3 to generate the board-level reference clock and the mixing local oscillator clock.

[0029] The first FPGA module 1-5 completes data communication and control signal communication with the second FPGA module 2-1 and the third FPGA module 3-1 through the first connector module 1-2, the second connector module 2-2 and the third connector module 3-2, including sending transmit beam baseband data and control signals.

[0030] The second FPGA module 2-1 can communicate with the first FPGA module 1-5 through the first connector module 1-2 and the second connector module 2-2; the FPGA module 3-1 can communicate with the first FPGA module 1-5 through the first connector module 1-2, the second connector module 2-2 and the third connector module 3-2.

[0031] The first connector module 1-2 and the second connector module 2-2 are selected as high-speed signal connectors. In this embodiment, a high-speed differential FMC connector is selected.

[0032] After receiving the baseband signal of the transmit beam, the second FPGA module 2-1 performs signal processing such as filtering, frequency conversion, and DBF (digital beamforming) within the FPGA, and transmits the transmit beam data to the RF transceiver module 2-5. The RF transceiver module 2-5 performs digital-to-analog conversion, quadrature up-conversion, and amplitude and phase correction control on 32 RF signals, and then outputs the intermediate frequency (IF) signal to the first RF SiP module 2-6. The first RF SiP module 2-6 completes the transmit link path through an RF switching circuit, performs filtering, attenuation, up-conversion, bandpass filtering, amplification, and limiting processing on the received IF signal, and outputs the RF signal to the external transmit antenna.

[0033] After receiving the baseband signal from the transmit beam, the third FPGA module 3-1 performs signal processing such as filtering, frequency conversion, and deep bandpass filtering (DBF) within the FPGA, and then transmits the transmit beam data to the second RF transceiver module 3-5. The second RF transceiver module 3-5 performs digital-to-analog conversion, quadrature up-conversion, amplitude and phase correction control, and outputs the 32 RF signals to the second RF SiP module 3-6. The second RF SiP module 3-6 establishes the transmit link path through a switching circuit, performs filtering, attenuation, up-conversion, bandpass filtering, amplification, and limiting processing on the received intermediate frequency signal, and outputs the RF signal.

[0034] The specific reception process is as follows: the first RF SiP module 2-6 and the second RF SiP module 3-6 establish a receiving link through an RF switching circuit. They perform amplitude limiting, amplification, bandpass filtering, attenuation, down-conversion, low-pass filtering, and low-noise amplification on the 64 RF signals received from the external receiving antenna, outputting the intermediate frequency (IF) signal to the first RF transceiver module 2-5 and the second RF transceiver module 3-5. The first RF transceiver module 2-5 and the second RF transceiver module 3-5 perform quadrature down-conversion and analog-to-digital conversion on the received IF signal, and transmit the received waveform data signal to the second FPGA module 2-1 and the third FPGA module 3-1. The second FPGA module 2-1 and the third FPGA module 3-1 perform filtering, frequency conversion, and DBF signal processing on the received waveform data, and transmit the processed received beam baseband data to the first FPGA module 1-5. The first FPGA module 1-5 summarizes the received beam baseband signal through the network port module 1-1 and sends it back to the external host computer along with the monitoring signal.

[0035] The second FPGA module 2-1 can communicate with the first FPGA module 1-5 only through the first connector module 1-2 and the second connector module 2-2; the third FPGA module 3-1 can only communicate with the first FPGA module 1-5 through the first connector module 1-2, the second connector module 2-2, and the third connector module 3-2. The connection between the first digital radio frequency module 2 and the second digital radio frequency module 3 is established by the second connector module 2-2 and the third connector module 3-2.

[0036] In this embodiment, the first RF SiP module 2-6 and the second RF SiP module 3-6 employ SiP (System-in-Package) technology to highly integrate a complete RF transceiver circuit, including switching circuits, low-noise amplifiers, low-pass filters, multi-stage attenuators, mixers, bandpass filters, multi-stage bidirectional amplifiers, limiters, etc. The first RF transceiver module 2-5 and the second RF transceiver module 3-5 use RF transceiver chips to integrate functionally separate analog-to-digital converters, digital-to-analog converters, quadrature local oscillator generators, and quadrature mixers. The first clock module 2-3 and the second clock module 3-3 adopt a two-stage clock structure, capable of outputting a total of 84 synchronous clocks to meet the component requirements, providing synchronous clocks for all RF transceiver chips and FPGA processing circuits. A 32-channel equal-diameter power divider circuit is used to provide local oscillator clocks for all RF SiP chips.

[0037] In summary, the digital TR component of this invention integrates a radio frequency transceiver module to perform digital-to-analog conversion and quadrature up-conversion of the transmitted signal, thereby achieving intermediate frequency signal output; it also integrates a radio frequency SiP module to perform up-conversion, amplification, filtering, and limiting of the radio frequency transceiver signal.

[0038] This invention employs a highly integrated RF SiP module and an RF transceiver module, which can effectively reduce the types and number of components required for system composition and improve integration. By selecting highly integrated RF transceiver chips, the digital bandwidth requirement can be reduced, and the number of transceiver channels can be increased under the same digital bandwidth capability. The highly integrated design scheme can support the reduction of the overall size of the components and realize the reduction of system size.

[0039] This invention improves the integration of digital TR components, reduces their size and weight, and has 64-channel RF transceiver processing capability. It can achieve synchronous processing of 64-channel transceiver signals, and can be directly connected to an external Ku-band antenna and host computer to realize complete radar functions. The signal bandwidth capability reaches 200MHz.

[0040] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A highly integrated 64-channel orthogonal frequency converter digital TR component, characterized in that, Includes a frequency synthesizer module and two digital radio frequency modules; The two digital radio frequency modules have the same structure. One digital radio frequency module receives control signals and transmits baseband signals from the frequency synthesizer module via the other digital radio frequency module, and sends monitoring signals and receives baseband signals back to the frequency synthesizer module. The frequency synthesis module includes a network port module, a first connector module, a frequency synthesis module, and a first FPGA module; the digital radio frequency module includes a second FPGA module, a second connector module, a clock module, a radio frequency transceiver module, and a radio frequency SiP module. The first FPGA module communicates with an external host computer via a network port module, receiving control signals and transmitting baseband data from the host computer; the first connector module is used to communicate with the digital radio frequency module, receiving monitoring signals and receiving baseband signals from the digital radio frequency module from the first connector module, and sending them to the external host computer via the network port module; the frequency synthesis module is used to provide the board-level reference clock and mixing local oscillator clock for the digital radio frequency module. The second FPGA module is connected to the second connector module and the RF transceiver module to complete the processing of transmitted and received data. The second connector module is used to transmit and receive baseband signals and transmit baseband signal data; the RF transceiver module is used to communicate with the second FPGA module for digital signal communication, and to complete digital-to-analog conversion, analog-to-digital conversion and quadrature up-conversion. The RF transceiver module includes 8 RF transceiver chips, each of which supports 4 channels of transmit and receive signals; the RF SiP module is connected to the external antenna and the RF transceiver module, and is used to complete transmit baseband beamforming, receive baseband beamforming and quadrature up-conversion; the clock module is used to provide a high-speed link synchronization clock tree for the second FPGA module and the RF transceiver module.

2. The digital TR component as described in claim 1, characterized in that, The frequency synthesis module includes a temperature-controlled crystal oscillator, a power divider, and a phase-locked loop (PLL). The temperature-controlled crystal oscillator is connected to an external reference clock and outputs to two PLLs via two power dividers. One PLL outputs two mixing local oscillator clocks, which are provided to two digital RF modules respectively. The other PLL generates a board-level reference clock and divides it into three outputs, two of which are output to the two digital RF modules and the other one is output to the first FPGA module.

3. The digital TR component as described in claim 2, characterized in that, The clock module of the digital RF module distributes the board-level reference clock received from the frequency synthesizer module into 4 clocks, of which 2 are output to the second FPGA module as GT reference clocks, 1 is output to the second FPGA module as the system operating clock, and 1 output generates a synchronous clock tree of 8 high-speed links between the second FPGA module and the RF transceiver module through a 2-level clock structure. The mixed local oscillator signal received from the frequency synthesizer module is distributed to the RF SiP module through a 16-power divider circuit of equal diameter, serving as the mixed local oscillator clock for transceiver frequency conversion.

4. The digital TR component as described in any one of claims 1-3, characterized in that, The frequency synthesizer module also includes a first power supply module, and the digital radio frequency module also includes a second power supply module. The first power supply module obtains power input from the outside and forwards it to the two digital radio frequency modules. The second power supply module receives the power forwarded by the frequency synthesizer module through the second connector module and generates the required voltages for each stage through its internal DC-DC-LDO power system.

5. The digital TR component as described in any one of claims 1-3, characterized in that, The radio frequency SiP module has a radio frequency switching circuit, which enables the switching of the transmit and receive paths.

6. The digital TR component as described in any one of claims 1-3, characterized in that, The first connector module and the second connector module use high-speed differential FMC connectors.

7. The digital TR component as described in any one of claims 1-3, characterized in that, RF SiP modules highly integrate fully functional RF transceiver circuits through SiP technology, including switching circuits, low-noise amplifiers, low-pass filters, multi-stage attenuators, mixers, bandpass filters, multi-stage bidirectional amplifiers, and limiters; RF transceiver modules integrate functionally separate analog-to-digital converters, digital-to-analog converters, quadrature local oscillators, and quadrature mixers through RF transceiver chips.

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