A method and system for online upgrading of an intelligent door lock as a whole

Abstract

This invention relates to the field of software update technology, specifically to a method and system for overall online upgrade of smart door locks, comprising the following steps: acquiring firmware and chip encoding to construct an upgrade package and digest value; allocating transmission bandwidth blocks by comparing task increment differences; sending the upgrade package; calculating attenuation rate parameters based on time offset rate and write latency difference; adjusting the packet sending interval and the upper limit of retransmission times; decrypting and verifying the firmware; distributing decrypted data through an interface; writing to a non-running partition to verify integrity; and generating an upgrade audit log. In this invention, bandwidth allocation based on task increment differences optimizes scheduling; attenuation rate is calculated using offset rate and latency difference; packet sending interval is flexibly adjusted to adapt to real-time networks; data security is ensured by combining algorithmic decryption and digest value verification; precise distribution is achieved based on encoding identification of the target interface; firmware is written to a non-running partition to achieve seamless upgrades; and data aggregation generates logs to improve collaborative update efficiency.

Description

Technical Field

[0001] This invention relates to the field of software update technology, and in particular to a method and system for overall online upgrade of smart door locks. Background Technology

[0002] The field of software update technology mainly covers the program version maintenance and function iteration mechanisms of various computing devices and embedded systems. Specifically, it involves the technical scope of replacing or patching the instruction set stored internally by the device through wired or wireless communication paths. In particular, the traditional online upgrade method for smart door locks involves the user first enabling Bluetooth on a mobile terminal and establishing a connection with the communication module inside the door lock. The client application on the mobile terminal downloads the firmware upgrade package from the cloud server, and then sends the firmware data in segments to the main control microprocessor of the door lock via Bluetooth. The main control microprocessor caches the received data in external memory, executes verification instructions after data transmission is complete, and controls the system to restart to run the new firmware program.

[0003] Upgrading existing traditional smart door locks relies on mobile terminals to establish a single-channel Bluetooth connection for serial data transmission. This point-to-point communication mode lacks a mechanism to differentiate data streams from multi-chip firmware during the interaction process. When faced with complex electromagnetic environments or fluctuations in hardware write speed, the fixed transmission frequency cannot match the data receiving capability, leading to packet loss or backlog. Simply caching data to external storage ignores real-time verification of transmission quality. Blindly restarting the system to replace firmware carries the risk of upgrade failure due to incomplete data. Rigid transmission logic increases the overall maintenance time and cost, and a single master control processing method cannot meet the needs of multi-component collaborative iteration. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method and system for overall online upgrades of smart door locks.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for overall online upgrade of a smart door lock, comprising the following steps:

[0006] S1: Obtain multi-chip firmware data and chip code identifiers corresponding to different functional modules in the smart door lock, perform binding and compression processing to build upgrade package files and verification digest values, collect the number of tasks entering and leaving to calculate the task increment difference, and compare the task increment difference with the total bandwidth usage to allocate transmission bandwidth blocks.

[0007] S2: The upgrade package file is sent using the transmission bandwidth block. The time offset rate is calculated based on the interval between sending and receiving N consecutive packets. The time offset rate is compared with the difference in local cache write latency. If the time offset rate exceeds a preset threshold, the attenuation rate parameter is calculated. The packet sending interval and the upper limit of the number of retransmissions are adjusted based on the attenuation rate parameter to obtain the firmware data packet.

[0008] S3: Call the AES algorithm to decrypt the firmware data packet and construct decrypted firmware data; call the SHA-256 algorithm to verify the decrypted firmware data based on the check digest value; identify the target functional chip interface based on the chip code identifier; and distribute the decrypted firmware data through the target functional chip interface.

[0009] S4: Write the decrypted firmware data into the non-running partition corresponding to the target function chip interface, generate a partition flag, verify the integrity based on the partition flag, and generate an upgrade audit log by summarizing the delay data and the abnormal data that triggers the upper limit of the number of retransmissions.

[0010] As a further aspect of the present invention, step S1 includes:

[0011] S11: Traverse all peripheral nodes connected to the smart lock control board, obtain multi-chip firmware data and corresponding chip code identifiers for different functional modules in the smart lock, compress the bound data using the LZMA lossless compression algorithm, generate upgrade package file, and simultaneously calculate the hash value of the original data to generate a verification digest value.

[0012] S12: Real-time monitoring of the status of the system task queue within a preset sampling period, counting the number of pending tasks entering the queue and the number of completed tasks leaving the queue, and generating task increment difference by calculating the absolute value of the difference between the two and combining it with the task priority weight.

[0013] S13: Obtain the total bandwidth usage of the current network channel, subtract the minimum bandwidth required for the system's basic heartbeat keep-alive from the total bandwidth usage according to the preset bandwidth allocation model, and dynamically calculate the available transmission rate based on the inverse relationship of the task increment difference to generate a transmission bandwidth block.

[0014] As a further aspect of the present invention, step S2 includes:

[0015] S21: Send the upgrade package file at the rate limited by the transmission bandwidth block, record the sending timestamp and receiving confirmation timestamp of N consecutive data packets, calculate the average round-trip delay and combine it with the data packet size to generate the time offset rate;

[0016] S22: Obtain the average flash memory write time of the door lock main control chip as the local cache write latency difference value, compare the time offset rate with the local cache write latency difference value, if the former is greater than the latter and exceeds the preset safety buffer threshold, it is determined that there is a risk of transmission congestion, and then the attenuation calculation model is called to generate attenuation rate parameters.

[0017] S23: The default packet transmission interval is extended by weighting using the attenuation rate parameter, and the maximum allowed retransmission number is reduced proportionally to update the upper limit of the retransmission number. After the data packet is reassembled at the receiving end, the firmware data packet is extracted.

[0018] As a further aspect of the present invention, step S3 includes:

[0019] S31: Load the preset AES symmetric key, perform decryption operation on the received firmware data packet to restore the original binary stream, generate decrypted firmware data, and immediately calculate the SHA-256 digest value of the data and perform bit-to-bit matching verification with the check digest value;

[0020] S32: Parse the hardware type field and bus address field in the chip encoding identifier, find the corresponding physical communication port in the pre-stored hardware mapping table, and identify the target functional chip interface;

[0021] S33: Activate the data transmission channel of the target function chip interface, and use DMA direct memory access to transmit the verified decrypted firmware data in fragments to the corresponding submodule controller.

[0022] As a further aspect of the present invention, step S4 includes:

[0023] S41: Send a partition switching command to the target submodule, lock the currently running main partition, sequentially write the decrypted firmware data into the reserved backup storage area, i.e., the non-running partition, and write the target magic number flag at the beginning of the partition after writing to generate the partition flag bit;

[0024] S42: Read all data in the non-running partition and perform CRC32 cyclic redundancy check. If the check result is consistent with the check code included in the partition flag, the integrity verification is deemed to be successful; otherwise, the rollback mechanism is triggered and the non-running partition is erased.

[0025] S43: Collect the average network transmission latency, write time, and abnormal packet loss events that trigger the maximum number of retransmissions during the entire upgrade process. Encapsulate the above information into encrypted text records according to the time sequence, generate upgrade audit logs, and upload them to the cloud server.

[0026] As a further aspect of the present invention, the calculation of the task increment difference and the generation of the transmission bandwidth block in S12 and S13 include:

[0027] Obtain the sampling period The number of high-priority tasks entering the task queue Number of tasks completed Combined with preset task weight coefficients Calculate the task increment difference ;

[0028] Based on the current system's maximum allowed total bandwidth With basic keep-alive bandwidth The transmission bandwidth block allocated to the upgrade task is calculated using the task increment difference. The calculation formula is as follows:

[0029] ;

[0030] in, Represents the base of the natural logarithm. The bandwidth attenuation sensitivity coefficient represents the factor used to adjust how well bandwidth adapts to changes in load. This represents the difference in task increments. The baseline threshold representing system load balancing This represents the maximum total bandwidth currently allowed by the system. Represents the basic keep-alive bandwidth. This represents the transmission bandwidth block.

[0031] As a further aspect of the present invention, the calculation process of the attenuation rate parameter in S22 includes:

[0032] Obtain the currently measured time offset rate Difference between local cache write latency and the local cache write latency Combined with the packet loss count within the current transmission window With total number of packages Calculate the attenuation rate parameter used to adjust the transmission strategy. The calculation formula is as follows:

[0033] ;

[0034] in, Represents the attenuation rate parameter, The weighting factor represents the impact of latency. Represents the natural logarithm function. This represents the time offset rate. This represents the difference in local cache write latency. This represents the packet loss penalty weighting factor. Represents the packet loss count within the transmission window. This represents the total number of packets within the transmission window.

[0035] As a further aspect of the present invention, the writing and flag generation process of the non-running partition in S41 includes:

[0036] The A / B partition status of the memory connected to the target function chip interface is detected, and the active partition pointed to by the current program counter is identified as partition A. Then, the non-running partition is automatically positioned as partition B.

[0037] Before writing the decrypted firmware data to partition B, first write all-F padding data to the starting address of partition B for erasure verification. After confirming that it is empty, start writing data and append metadata structure including firmware version number and length information to the end of the data to generate the partition flag bit.

[0038] As a further aspect of the present invention, the process of generating the upgrade audit log in S43 includes:

[0039] Initialize a circular buffer to temporarily store log entries and capture key event nodes in real time during the upgrade process, including handshake success, key negotiation, block transfer start, block transfer end, and verification results;

[0040] The peak data of the time offset rate, the specific packet sequence number that triggered the retransmission, and the total number of triggers for the maximum number of retransmissions are structured and encoded. The device fingerprint of the door lock device is used to digitally sign the log content to generate the upgrade audit log.

[0041] A smart door lock overall online upgrade system, the smart door lock overall online upgrade system being used to implement the above-mentioned smart door lock overall online upgrade method, the system comprising:

[0042] The resource scheduling and packaging module is used to obtain multi-chip firmware data and chip code identifiers corresponding to different functional modules in the smart door lock, perform binding and compression processing to build upgrade package files and verification digest values, collect the number of tasks entering and leaving, calculate the task increment difference, and compare the task increment difference with the total bandwidth usage to allocate transmission bandwidth blocks.

[0043] An adaptive transmission control module is used to distribute the upgrade package file using the transmission bandwidth block, calculate the time offset rate based on the interval between sending and receiving N consecutive packets, compare the time offset rate with the local cache write latency difference, and if the time offset rate exceeds a preset threshold, calculate the attenuation rate parameter, and adjust the packet sending interval and the maximum number of retransmissions based on the attenuation rate parameter to obtain firmware data packets.

[0044] The secure distribution routing module is used to call the AES algorithm to decrypt the firmware data packet and construct decrypted firmware data, call the SHA-256 algorithm to verify the decrypted firmware data based on the check digest value, identify the target functional chip interface based on the chip code identifier, and distribute the decrypted firmware data through the target functional chip interface.

[0045] The partition verification and auditing module is used to write the decrypted firmware data into the non-running partition corresponding to the target function chip interface, generate a partition flag bit, verify integrity based on the partition flag bit, and generate an upgrade audit log by summarizing the delay data and the abnormal data that triggers the upper limit of the number of retransmissions.

[0046] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0047] In this invention, a unified upgrade package is constructed by acquiring the firmware and encoding identifiers of multiple chips corresponding to different functional modules in a smart door lock, performing binding compression, optimizing resource scheduling by dynamically allocating transmission bandwidth blocks based on task increment differences, calculating attenuation rate parameters using time offset rate and write latency difference, flexibly adjusting packet sending interval and retransmission limit to adapt to real-time network conditions, ensuring data security by combining algorithm decryption and verification digest values, accurately identifying target interface distribution data based on chip encoding, writing firmware to non-running partitions and verifying integrity to achieve seamless upgrades, and summarizing latency data to generate audit logs to improve the efficiency of multi-component collaborative updates. Attached Figure Description

[0048] Figure 1 This is a flowchart of an online upgrade method for a smart door lock according to the present invention;

[0049] Figure 2 This is a flowchart illustrating the generation and allocation of transmission bandwidth blocks in this invention.

[0050] Figure 3 This is a flowchart illustrating the transmission rate adjustment and data acquisition process of the present invention.

[0051] Figure 4 This is a flowchart of the firmware decryption, verification, and distribution process of the present invention;

[0052] Figure 5 This is a flowchart of the firmware writing verification and log generation process of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the software-based technical solution is described in detail below with reference to system architecture diagrams and embodiments. It should be understood that the specific embodiments described herein are only for explaining the technical solutions of this invention and do not constitute a limitation on the scope of protection.

[0054] In the description of this invention, the system architecture relationships or data processing flows indicated by terms such as "layer," "module," "interface," "data flow," "client," and "server" are all defined based on the architecture diagram or flowchart corresponding to the embodiments. This way of describing is only used to clearly illustrate the logical relationships between the elements in the technical solution, and not to limit the physical deployment form. The term "multiple" includes two or more technical units, including but not limited to multiple data nodes, processing threads, service instances, or functional components and other scalable elements. The specific number is determined according to the actual business scenario and needs to be specifically specified.

[0055] Please see Figure 1 and Figure 2 This invention provides a technical solution: a method for overall online upgrade of a smart door lock, comprising the following steps:

[0056] S1: Obtain multi-chip firmware data and chip code identifiers corresponding to different functional modules in the smart door lock, perform binding and compression processing to build upgrade package files and verification digest values, collect the number of tasks entering and leaving, calculate the task increment difference, compare the task increment difference with the total bandwidth usage, and allocate transmission bandwidth blocks.

[0057] The steps in S1 include:

[0058] S11: Traverse all peripheral nodes connected to the smart lock control board, obtain multi-chip firmware data and corresponding chip code identifiers for different functional modules in the smart lock, compress the bound data using the LZMA lossless compression algorithm, generate upgrade package file, and simultaneously calculate the hash value of the original data to generate a verification digest value.

[0059] S12: Real-time monitoring of the status of the system task queue within a preset sampling period, counting the number of pending tasks entering the queue and the number of completed tasks leaving the queue, and generating task increment difference by calculating the absolute value of the difference between the two and combining it with the task priority weight.

[0060] S13: Obtain the total bandwidth usage of the current network channel. Based on the preset bandwidth allocation model, subtract the minimum bandwidth required for the system's basic heartbeat keep-alive from the total bandwidth usage. Then, dynamically calculate the available transmission rate based on the inverse relationship of the task increment difference and generate a transmission bandwidth block.

[0061] The calculation of the task increment difference and the generation of the transmission bandwidth block in S12 and S13 include:

[0062] Obtain the sampling period The number of high-priority tasks entering the task queue Number of tasks completed Combined with preset task weight coefficients Calculate the incremental difference of the task ;

[0063] Based on the current system's maximum allowed total bandwidth With basic keep-alive bandwidth The transmission bandwidth block allocated to the upgrade task is calculated using the task increment difference. The calculation formula is as follows:

[0064] ;

[0065] in, Represents the base of the natural logarithm. The bandwidth attenuation sensitivity coefficient represents the factor used to adjust how well bandwidth adapts to changes in load. The difference represents the incremental difference in tasks. The baseline threshold representing system load balancing This represents the maximum total bandwidth currently allowed by the system. Represents the basic keep-alive bandwidth. This represents the transmission bandwidth block.

[0066] The main control MCU first initializes the bus scanning program, traversing all slave devices connected to the I2C bus address range 0x08 to 0x77, and the devices corresponding to the SPI bus chip select lines CS1 to CS3. The system identifies the fingerprint module firmware size as 512KB, the face module firmware size as 2MB, and the NFC module firmware size as 64KB. After obtaining the above multi-chip firmware data, the system reads the unique chip code identifier stored in the OTP area of ​​each module, for example, the fingerprint module ID is 0x1A0100FF. The main control MCU calls the compression interface in LZMASDK, sets the dictionary size to 64KB, the compression level to 5, and binds the above three firmware files with the corresponding chip code identifiers in binary concatenation, and then performs the compression operation. The original data volume is 2576KB, and after compression, an upgrade package file of size 1545KB is generated. While compressing the data stream output, the hardware SHA-256 acceleration engine performs streaming computation on the uncompressed raw concatenated data to generate a 32-byte checksum value, which is appended to the header of the upgrade package file.

[0067] Next, the task increment difference calculation phase begins. The system sets the sampling period. The interval is 200 milliseconds. The system monitors the FreeRTOS task queue in real time, recording the number of high-priority tasks entering the queue within this 200-millisecond period. The statistics show 8 tasks. The high-priority tasks mentioned above refer to tasks with a priority value greater than 10, including user fingerprint matching requests and motor drive commands; the number of tasks that were processed and left the queue simultaneously. The statistics are 5. The system has preset task weight coefficients. The coefficient is 1.5, set based on the average statistical value of CPU utilization by the task. The task increment difference is calculated according to the formula. The calculation process is as follows This value reflects that the current system is in a state of increasing load backlog.

[0068] Next, the system calculates the allocation of transmission bandwidth blocks. It obtains the negotiated physical layer rate of the current Bluetooth BLE 5.0 connection through the link layer driver and calculates the maximum total bandwidth allowed by the system based on the signal-to-noise ratio. The bandwidth is 1250Kbps. To ensure uninterrupted basic services such as Bluetooth heartbeats and battery level reporting, the system reserves basic keep-alive bandwidth. The bandwidth is 50Kbps. To determine the specific bandwidth allocated to the upgrade task, an adjustment factor needs to be determined. Bandwidth attenuation sensitivity factor. The value is set to 0.8. This value was derived by fitting curves simulating the impact of different loads on data throughput in a laboratory environment. It is used to control the steepness of the bandwidth decrease as the load increases; it serves as the baseline threshold for system load balancing. Setting it to 6.0 represents the balance point of the system's processing capacity. The system uses the task increment difference to calculate the transmission bandwidth block allocated to the upgrade task. The calculation formula is as follows:

[0069] ;

[0070] in, This represents the transmission bandwidth block, i.e., the available rate allocated to the upgrade task; This represents the maximum total bandwidth currently allowed by the system. Represents the basic keep-alive bandwidth; The base of the natural logarithm; The bandwidth attenuation sensitivity coefficient represents the sensitivity of bandwidth to changes in load. This represents the difference in task increments; This represents the baseline threshold for system load balancing.

[0071] The system obtains the incremental difference of the tasks collected in real time. and preset parameters , These values ​​are directly substituted into the aforementioned transmission bandwidth block calculation formula. After processing by the system's internal floating-point unit, the final transmission bandwidth block allocated to the upgrade task is calculated. The calculated bandwidth is 922.2 Kbps. This indicates that the system allocated approximately 73.8% of the total bandwidth for firmware upgrade transmission. The system adjusted the Bluetooth connection interval to 15 ms and limited the maximum number of data packets in each connection event to a value adapted to the 922.2 Kbps rate, generating the final transmission bandwidth block configuration.

[0072] Table 1. Bandwidth Allocation Parameters for Smart Door Locks

[0073]

[0074] Refer to Table 1, which lists the key parameter settings and explanations involved in the bandwidth allocation calculation in this embodiment. The formula introduces a sigmoid function as a bandwidth adjustment factor, utilizing ( This feature accurately captures the degree of deviation of the system load from the baseline, enabling an adaptive and smooth transition in bandwidth allocation.

[0075] Please see Figure 1 and Figure 3 S2: Utilize the transmission bandwidth block to distribute the upgrade package file, calculate the time offset rate based on the interval between sending and receiving N consecutive packets, compare the time offset rate with the difference in local cache write latency, and if the time offset rate exceeds the preset threshold, calculate the attenuation rate parameter, and adjust the packet sending interval and the upper limit of retransmission times based on the attenuation rate parameter to obtain the firmware data packet;

[0076] The steps in S2 include:

[0077] S21: Send the upgrade packet file at the rate limited by the transmission bandwidth block, record the sending timestamp and receiving acknowledgment timestamp of N consecutive data packets, calculate the average round-trip delay and combine it with the data packet size to generate the time offset rate;

[0078] S22: Obtain the average flash memory write time of the door lock main control chip as the local cache write latency difference value, compare the time offset rate with the local cache write latency difference value, if the former is greater than the latter and exceeds the preset safety buffer threshold, it is determined that there is a risk of transmission congestion, and then the attenuation calculation model is called to generate attenuation rate parameters.

[0079] The calculation process for the attenuation rate parameter in S22 includes:

[0080] Get the current measurement time offset rate Difference between local cache write latency and local cache write latency Combined with the packet loss count within the current transmission window With total number of packages Calculate the attenuation rate parameter used to adjust the transmission strategy. The calculation formula is as follows:

[0081] ;

[0082] in, Represents the attenuation rate parameter. The weighting factor represents the impact of latency. Represents the natural logarithm function. Represents the time offset rate. This represents the difference in local cache write latency. This represents the packet loss penalty weighting factor. Represents the packet loss count within the transmission window. Represents the total number of packets within the transmission window;

[0083] S23: The default packet transmission interval is weighted and extended using the attenuation rate parameter. At the same time, the maximum allowed retransmission number is reduced proportionally to update the upper limit of the retransmission number. After the data packet is reassembled at the receiving end, the firmware data packet is extracted.

[0084] Received from the transmission bandwidth block generated by S1, the system divides the upgrade packet file into fixed-length data packets, each with a payload of 240 bytes. The sending end controls the transmission logic according to the calculated rate, sending approximately 480 data packets per second. The system is set to continuously monitor a certain number of packets. The timeframe is set to 50, meaning a statistical window is formed by sending 50 data packets. The sender records the timestamps from the first packet to the 50th packet within this window, as well as the timestamp of the received ACK acknowledgment frame. The system calculates the average round-trip time (RTT) for these 50 packets, which is currently measured to be 45 milliseconds. Combining the packet size and physical layer overhead, the system normalizes the data to generate a time offset rate. In this embodiment, The value is taken directly as the average round-trip time, which is 45 milliseconds.

[0085] Simultaneously, the system reads the status register of the Flash controller inside the door lock's main control chip to obtain the average programming time of the current Flash page. The page programming time for this type of Flash is 30 milliseconds under the current temperature and voltage conditions; this value represents the local cache write latency difference. The system will use the time offset rate. Difference between local cache write latency and local cache write latency A comparison is performed. The preset safety buffer threshold is 5ms. Because... If the difference exceeds the preset threshold of 5ms, the system determines that the network transmission rate is too fast, causing the receiving end's buffer to be unable to process the data in time, resulting in a risk of overflow and packet loss. Therefore, the attenuation mechanism must be activated.

[0086] The system calls the attenuation calculation model to adjust the transmission parameters. First, it retrieves the transmission statistics within the current transmission window: total number of packets in the window. The count is 50; this is the number of packets that are considered lost due to timeout and failure to receive an ACK during this window. There are two. The attenuation calculation formula requires setting weighting parameters: time delay influence weighting factor. Set to 0.6, this value emphasizes sensitivity to latency jitter; packet loss penalty weighting factor. Set to 2.0, this value is used to impose a severe rate penalty when actual packet loss occurs. The system calculates the attenuation rate parameter used to adjust the transmission strategy. The calculation formula is as follows:

[0087] ;

[0088] in, Represents the attenuation rate parameter; The weighting factor represents the impact of latency; Represents the natural logarithm function Represents the time offset rate; This represents the difference in local cache write latency. This represents the weighting factor for packet loss penalties; Represents the packet loss count within the transmission window; This represents the total number of packets within the transmission window.

[0089] The system will monitor the current time offset rate. ms, local cache write latency difference ms, and the packet loss count in the statistics window. With total number of packages Combined with preset time delay impact weighting factors Weighting factor for packet loss penalty Substitute these values ​​into the attenuation rate parameter calculation formula. The calculated attenuation rate parameter used to adjust the transmission strategy is then obtained. This result indicates that the current transmission strategy requires approximately 24.64% suppression adjustment. Based on this parameter, the system weighted the extension of the default packet transmission interval. The current default transmission interval is 20 milliseconds, and the adjusted transmission interval is... Milliseconds. Simultaneously, the system proportionally reduces the maximum allowed retransmission count. The default maximum retransmission count is 10, and the updated limit is [missing value]. Second-rate.

[0090] Table 2 Transmission Congestion Control Parameters

[0091]

[0092] Refer to Table 2, which lists the key parameter settings and explanations involved in the attenuation rate calculation in this embodiment. After the above adjustments, the receiving end receives data stably at a pace adapted to the Flash write speed. When all data packets have been received, the receiving end reassembles the data stream according to the packet sequence number, removes duplicate packets, fills in retransmitted packets, and finally extracts the complete firmware data packet.

[0093] Please see Figure 1 and Figure 4S3: Call the AES algorithm to decrypt the firmware data packet and construct the decrypted firmware data; call the SHA-256 algorithm to verify the decrypted firmware data based on the checksum value; identify the target function chip interface based on the chip code identifier; and distribute the decrypted firmware data through the target function chip interface.

[0094] The steps in S3 include:

[0095] S31: Load the preset AES symmetric key, perform decryption operation on the received firmware data packet to restore the original binary stream, generate decrypted firmware data, and immediately calculate the SHA-256 digest value of the data and perform bit-to-bit matching verification with the check digest value.

[0096] S32: Parse the hardware type field and bus address field in the chip encoding identifier, find the corresponding physical communication port in the pre-stored hardware mapping table, and identify the target function chip interface;

[0097] S33: Activate the data transmission channel of the target function chip interface, and use DMA direct memory access to transmit the verified decrypted firmware data in fragments to the corresponding submodule controller.

[0098] The receiving end's main control chip allocates a buffer in RAM to store the firmware data packet extracted in step S2. The system retrieves the preset AES-256 symmetric key and corresponding initialization vector from the secure storage area. It then calls the hardware encryption / decryption coprocessor to decrypt the firmware data packet using ciphertext block chaining mode. The decryption process is performed in 16-byte blocks, taking approximately 150 milliseconds in total, ultimately restoring the original binary stream, i.e., the decrypted firmware data. Simultaneously with the decrypted data stream, the system concurrently starts the SHA-256 calculation engine to calculate the digest value of the entire decrypted data. The calculated digest value is compared bit-by-bit with the checksum value generated in step S1 and included in the packet header. If all 32 bytes are identical, the firmware is confirmed as legitimate.

[0099] After successful verification, the system parses and decrypts the binding information in the firmware data header. The read chip code identifier is 0x1A0100FF. The system parses this identifier according to predefined bit field rules: the high 8 bits 0x1A represent the hardware type as a biometric fingerprint module; the next 8 bits 0x01 represent the bus interface type as UART1; the subsequent fields are the manufacturer ID. The system searches in the pre-stored hardware mapping table and confirms that the 0x1A type corresponds to the physical communication port UART1 on the motherboard, with a baud rate configuration of 921600bps.

[0100] After identifying the target functional chip interface as UART1, the main control MCU activates the DMA controller. The system configures DMA channel 3, with the source address pointing to the SRAM address storing the decrypted firmware data and the destination address pointing to the data transmission register of UART1. The data transmission length is set to 512KB. After DMA transmission is initiated, the data channel is activated, and the decrypted firmware data bypasses the CPU, being directly transmitted in chunks to the fingerprint module controller connected to the UART1 port via hardware signal streams.

[0101] Please see Figure 1 and Figure 5 S4: Write the decrypted firmware data to the non-running partition corresponding to the target function chip interface, generate a partition flag, verify the integrity based on the partition flag, and generate an upgrade audit log by summarizing the delay data and the abnormal data of the maximum number of trigger retransmissions.

[0102] The steps in S4 include:

[0103] S41: Send a partition switching command to the target submodule, lock the currently running main partition, sequentially write the decrypted firmware data to the reserved backup storage area, i.e., the non-running partition, and write the target's magic number flag at the beginning of the partition after writing to generate the partition flag bit;

[0104] The writing and flag generation process for non-running partitions in S41 includes:

[0105] The system detects the A / B partition status of the memory connected to the target function chip interface, identifies the active partition pointed to by the current program counter as partition A, and automatically positions the non-running partition as partition B.

[0106] Before writing decrypted firmware data to partition B, write all F padding data to the starting address of partition B for erasure verification. After confirming that it is empty, start writing data and append metadata structure including firmware version number and length information to the end of the data to generate partition flag bit.

[0107] S42: Read all data in the non-running partition and perform CRC32 cyclic redundancy check. If the check result is consistent with the check code included in the partition flag, the integrity verification is deemed to have passed; otherwise, the rollback mechanism is triggered and the non-running partition is erased.

[0108] S43: Collect the average network transmission latency, write time, and abnormal packet loss events that trigger the maximum number of retransmissions during the entire upgrade process. Encapsulate the above information into encrypted text records according to the time sequence, generate upgrade audit logs, and upload them to the cloud server.

[0109] The process of generating upgrade audit logs in S43 includes:

[0110] Initialize a circular buffer to temporarily store log entries and capture key event nodes in real time during the upgrade process, including handshake success, key negotiation, block transfer start, block transfer end, and verification results;

[0111] The peak data of the time offset rate, the specific packet sequence number that triggers retransmission, and the total number of retransmissions are structured and encoded. The device fingerprint of the door lock device is used to digitally sign the log content to generate an upgrade audit log.

[0112] After receiving the decrypted firmware data transmitted from the main control MCU, the fingerprint module controller initiates the partition writing process. The module's internal Flash memory is divided into partition A (address range 0x08000000-0x08040000) and partition B (address range 0x08040000-0x08080000). The system detects the module's current status, reads the program counter pointer and Boot flag, and confirms that the currently running code is located in partition A. The system automatically locks partition A into a protected state and designates partition B as a non-running partition.

[0113] Before writing begins, the module writes an all-F data block to the starting address of partition B for erase verification. If the read return is not all F, a sector erase command is executed. After confirming that it is empty, the system sequentially writes the received decrypted firmware data to partition B. Each 256 bytes is written as a page, and a readback verification is performed immediately after writing is complete. When all 512KB of data has been written, the system writes a predefined magic number flag 0xA5A55A5A at a specific address at the end of partition B, along with the firmware version number and length information. This set of data constitutes the partition flag.

[0114] The aforementioned magic number refers to a predefined fixed value used as a unique identifier for file format or protocol type in storage media, and here it is used to mark the validity of partition writes.

[0115] Next, integrity verification is performed. The bootloader program within the module reads the entire contents of partition B from the start address to the end address and calculates the CRC32 cyclic redundancy check code using the hardware CRC module. Assuming the calculation result is 0x8F3D12A1, the system reads the original check code pre-stored in the partition flag bit. If the two match, the integrity verification is considered successful, and the upgrade pending activation flag is set.

[0116] Finally, the system aggregates statistical data from the entire S2 to S4 process to generate an upgrade audit log. The data collected by the system includes: average network transmission latency of 45ms, average Flash write time of 30ms, 0 abnormal events triggering the maximum number of retransmissions, and CRC check time of 120ms. The system encapsulates this data into JSON format text in time sequence. To prevent log tampering, the system digitally signs the log content using the door lock device's private key. Subsequently, the main control MCU uploads the encrypted log file to the cloud server via Bluetooth.

[0117] A smart door lock overall online upgrade system, the smart door lock overall online upgrade system is used to execute the above-mentioned smart door lock overall online upgrade method, the system includes:

[0118] The resource scheduling and packaging module is used to obtain multi-chip firmware data and chip code identifiers corresponding to different functional modules in the smart door lock, perform binding and compression processing to build upgrade package files and verification digest values, collect the number of tasks entering and leaving, calculate the task increment difference, compare the task increment difference with the total bandwidth usage, and allocate transmission bandwidth blocks.

[0119] The adaptive transmission control module is used to distribute upgrade package files using transmission bandwidth blocks. It calculates the time offset rate based on the interval between sending and receiving N consecutive packets, compares the time offset rate with the local cache write latency difference, and calculates the attenuation rate parameter if the time offset rate exceeds the preset threshold. Based on the attenuation rate parameter, it adjusts the packet sending interval and the upper limit of the number of retransmissions to obtain firmware data packets.

[0120] The secure distribution routing module is used to call the AES algorithm to decrypt firmware data packets and construct decrypted firmware data, call the SHA-256 algorithm to verify the decrypted firmware data based on the check digest value, identify the target functional chip interface based on the chip code identifier, and distribute the decrypted firmware data through the target functional chip interface.

[0121] The partition verification and auditing module is used to write decrypted firmware data into the non-running partition corresponding to the target functional chip interface, generate partition flag bits, verify integrity based on partition flag bits, and generate upgrade audit logs by summarizing delayed data and abnormal data that trigger the maximum number of retransmissions.

[0122] The above embodiments illustrate preferred embodiments of the present invention. Any equivalent adjustments to the technical solution based on software engineering methods are within the scope of protection, including but not limited to: implementing algorithm logic using different programming languages, refactoring functional modules into services, adjusting data interaction protocols, and optimizing resource scheduling strategies. Any implementation scheme derived from reasonable modifications to the data processing flow, service call chain, or system architecture layer without departing from the core technology of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A method for online upgrading of an intelligent door lock as a whole, characterized in that, Includes the following steps: S1: Obtain multi-chip firmware data and chip code identifiers corresponding to different functional modules in the smart door lock, perform binding compression processing to build upgrade package files and verification digest values, collect the number of tasks entering and leaving to calculate the task increment difference, and allocate transmission bandwidth blocks according to the task increment difference and the total bandwidth usage. S2: The upgrade package file is sent using the transmission bandwidth block. The time offset rate is calculated based on the interval between sending and receiving N consecutive packets. The time offset rate is compared with the difference in local cache write delay. If the comparison result exceeds the preset safety buffer threshold, it is determined that there is a risk of transmission congestion. Then, the attenuation rate parameter is calculated. The default packet sending interval is extended by weighting the attenuation rate parameter. At the same time, the maximum allowed retransmission number is reduced proportionally to update the upper limit of the retransmission number. After the data packet is reassembled at the receiving end, the firmware data packet is extracted. S3: Call the AES algorithm to decrypt the firmware data packet, construct decrypted firmware data, call the SHA-256 algorithm to verify the decrypted firmware data based on the check digest value, identify the target functional chip interface based on the chip code identifier, and distribute the decrypted firmware data through the target functional chip interface; S4: Write the decrypted firmware data into the non-running partition corresponding to the target function chip interface, generate a partition flag, verify the integrity of the checksum in the partition flag, and collect the average network transmission latency, writing time, and abnormal packet loss events that trigger the upper limit of the number of retransmissions during the entire upgrade process to generate an upgrade audit log.

2. The intelligent door lock overall online upgrading method according to claim 1, characterized in that, The steps in S1 include: S11: Traverse all peripheral nodes connected to the smart lock control board, obtain multi-chip firmware data and corresponding chip code identifiers for different functional modules in the smart lock, compress the bound data using the LZMA lossless compression algorithm, generate upgrade package file, and simultaneously calculate the hash value of the original data to generate a verification digest value. S12: Real-time monitoring of the status of the system task queue within a preset sampling period, counting the number of pending tasks entering the queue and the number of completed tasks leaving the queue, and generating task increment difference by calculating the absolute value of the difference between the two and combining it with the task priority weight. S13: Obtain the total bandwidth usage of the current network channel, subtract the minimum bandwidth required for the system's basic heartbeat keep-alive from the total bandwidth usage according to the preset bandwidth allocation model, and dynamically calculate the available transmission rate based on the inverse relationship of the task increment difference to generate a transmission bandwidth block.

3. The method of claim 2, wherein, The steps in S2 include: S21: Send the upgrade package file at the rate limited by the transmission bandwidth block, record the sending timestamp and receiving confirmation timestamp of N consecutive data packets, calculate the average round-trip delay and combine it with the data packet size to generate the time offset rate; S22: Obtain the average flash memory write time of the door lock main control chip as the local cache write latency difference value, compare the time offset rate with the local cache write latency difference value, if the comparison result exceeds the preset safety buffer threshold, it is determined that there is a risk of transmission congestion, and then the attenuation calculation model is called to generate attenuation rate parameters. S23: The default packet transmission interval is extended by weighting using the attenuation rate parameter, and the maximum allowed retransmission number is reduced proportionally to update the upper limit of the retransmission number. After the data packet is reassembled at the receiving end, the firmware data packet is extracted.

4. The intelligent door lock overall online upgrading method according to claim 3, characterized in that, The steps in S3 include: S31: Load the preset AES symmetric key, perform decryption operation on the received firmware data packet to restore the original binary stream, generate decrypted firmware data, and immediately calculate the SHA-256 digest value of the data, and perform bit-to-bit matching verification with the check digest value; S32: Parse the hardware type field and bus address field in the chip encoding identifier, find the corresponding physical communication port in the pre-stored hardware mapping table, and identify the target functional chip interface; S33: Activate the data transmission channel of the target function chip interface, and use DMA direct memory access to transmit the verified decrypted firmware data in fragments to the corresponding submodule controller.

5. The intelligent door lock overall online upgrading method according to claim 4, characterized in that, The steps in S4 include: S41: Send a partition switching command to the target submodule, lock the currently running main partition, sequentially write the decrypted firmware data into the reserved backup storage area, i.e., the non-running partition, and write the target magic number flag at the beginning of the partition after writing to generate the partition flag bit; S42: Read all data in the non-running partition and perform CRC32 cyclic redundancy check. If the check result is consistent with the check code included in the partition flag, the integrity verification is deemed to be successful; otherwise, the rollback mechanism is triggered and the non-running partition is erased. S43: Collect the average network transmission latency, write time, and abnormal packet loss events that trigger the maximum number of retransmissions during the entire upgrade process. Encapsulate the above information into encrypted text records according to the time sequence, generate upgrade audit logs, and upload them to the cloud server.

6. The method for overall online upgrade of a smart door lock according to claim 2, characterized in that, The calculation of the task increment difference and the generation of the transmission bandwidth block in S12 and S13 include: Obtain the sampling period The number of high-priority tasks entering the task queue Number of tasks completed Combined with preset task weight coefficients Calculate the task increment difference ; Based on the current system's maximum allowed total bandwidth With basic keep-alive bandwidth The transmission bandwidth block allocated to the upgrade task is calculated using the task increment difference. The calculation formula is as follows: ； in, The base of the natural logarithm. The bandwidth attenuation sensitivity coefficient represents the factor used to adjust how well bandwidth adapts to changes in load. This represents the difference in task increments. The baseline threshold representing system load balancing This represents the maximum total bandwidth currently allowed by the system. Represents the basic keep-alive bandwidth. This represents the transmission bandwidth block.

7. The method for overall online upgrade of a smart door lock according to claim 3, characterized in that, The calculation process of the attenuation rate parameter in S22 includes: Obtain the currently measured time offset rate Difference between local cache write latency and the local cache write latency Combined with the packet loss count within the current transmission window With total number of packages Calculate the attenuation rate parameter used to adjust the transmission strategy. The calculation formula is as follows: ； in, Represents the attenuation rate parameter, The weighting factor represents the impact of latency. Represents the natural logarithm function. This represents the time offset rate. This represents the difference in local cache write latency. This represents the packet loss penalty weighting factor. Represents the packet loss count within the transmission window. This represents the total number of packets within the transmission window.

8. The method for overall online upgrade of a smart door lock according to claim 5, characterized in that, The writing and flag generation process of the non-running partition in S41 includes: The A / B partition status of the memory connected to the target function chip interface is detected, and the active partition pointed to by the current program counter is identified as partition A. Then, the non-running partition is automatically positioned as partition B. Before writing the decrypted firmware data to partition B, first write all F-filled data to the starting address of partition B for erasure verification. After confirming that it is empty, start writing data and append metadata structure including firmware version number and length information to the end of the data to generate the partition flag bit.

9. The method for overall online upgrade of a smart door lock according to claim 5, characterized in that, The process of generating the upgrade audit log in S43 includes: Initialize a circular buffer to temporarily store log entries and capture key event nodes in real time during the upgrade process, including handshake success, key negotiation, block transfer start, block transfer end, and verification results; The peak data of the time offset rate, the specific packet sequence number that triggered the retransmission, and the total number of triggers for the maximum number of retransmissions are structured and encoded. The device fingerprint of the door lock device is used to digitally sign the log content to generate the upgrade audit log.

10. A smart door lock overall online upgrade system, characterized in that, The system is used to implement the overall online upgrade method for smart door locks as described in any one of claims 1-9, the system comprising: The resource scheduling and packaging module is used to obtain multi-chip firmware data and chip code identifiers corresponding to different functional modules in the smart door lock, perform binding and compression processing to build upgrade package files and verification digest values, collect the number of tasks entering and leaving to calculate the task increment difference, and allocate transmission bandwidth blocks according to the task increment difference and the total bandwidth usage. An adaptive transmission control module is used to distribute the upgrade package file using the transmission bandwidth block, calculate the time offset rate based on the interval between sending and receiving N consecutive packets, compare the time offset rate with the difference in local cache write delay, and if the comparison result exceeds the preset safety buffer threshold, it is determined that there is a risk of transmission congestion. Then, it calculates the attenuation rate parameter, uses the attenuation rate parameter to perform weighted extension processing on the default packet sending interval, and proportionally reduces the maximum allowed retransmission number to update the upper limit of retransmission number. After the data packet is reassembled at the receiving end, the firmware data packet is extracted. The secure distribution routing module is used to call the AES algorithm to decrypt the firmware data packet, construct decrypted firmware data, call the SHA-256 algorithm to verify the decrypted firmware data based on the check digest value, identify the target functional chip interface based on the chip code identifier, and distribute the decrypted firmware data through the target functional chip interface. The partition verification and audit module is used to write the decrypted firmware data into the non-running partition corresponding to the target function chip interface, generate a partition flag, verify the integrity of the checksum in the partition flag, and collect the average network transmission latency, writing time, and abnormal packet loss events that trigger the maximum number of retransmissions during the entire upgrade process, and generate an upgrade audit log.

Images