Circuit board assembly and server
By placing SMT connectors on opposite sides of the circuit board and creating a high-speed interconnect structure that runs vertically through the board, the impedance discontinuity between the top and bottom connectors of the PCB is solved, improving signal integrity and spatial layout while reducing costs.
Patent Information
- Application Number
- CN202411066758.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2026-02-06
AI Technical Summary
In existing technologies, the high-speed interconnect between the SMT connectors on the top and bottom layers of a PCB suffers from impedance discontinuities in the transmission path, resulting in poor high-speed signal integrity.
By placing first and second SMT connectors on opposite sides of the circuit board and setting a high-speed interconnect structure that runs vertically through the circuit board between them, directly connecting the first and second pads, multiple high-speed differential holes and inner layer traces are reduced, the spatial layout is optimized, and impedance continuity is improved.
It improves the signal integrity of high-speed signals, reduces noise, optimizes the spatial layout of the circuit board, reduces costs, and improves heat dissipation.
Smart Images
Figure CN121487101A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit board technology, and more particularly to a circuit board assembly and a server. Background Technology
[0002] With the development of cloud computing, the requirements for server high-speed signal transmission rates and bandwidths are increasing. Pulse Amplitude Modulation 4 (PAM4) technology is increasingly being used for high-speed signal transmission, such as high-speed signals PCIe Gen6 / Gen7 and Ethernet 112G / 224G.
[0003] In related technologies, the top and bottom layers of high-density high-speed server backplane PCBs have surface mount technology (SMT) connectors. SMT connectors are used to connect hardware modules. Currently, the SMT connectors on the top and bottom layers of the PCB need to be interconnected through multiple high-speed interconnect structures. The high-speed interconnect structures include multiple high-speed differential vias and multiple PCB traces on different trace layers in the PCB, thereby achieving high-speed interconnection between the two SMT connectors on the top and bottom layers of the PCB.
[0004] However, in related technologies, the high-speed interconnect between the SMT connectors on the top and bottom layers of the PCB suffers from impedance discontinuities in the transmission path, resulting in poor high-speed signal integrity. Summary of the Invention
[0005] In view of the above problems, embodiments of this application provide a circuit board assembly and server for improving impedance continuity on the transmission path of a high-speed interconnect structure, thereby improving the signal integrity of high-speed signals.
[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:
[0007] A first aspect of this application provides a circuit board assembly, including: a circuit board, a first SMT connector, and a second SMT connector; the first SMT connector has a first high-speed signal pin; the second SMT connector has a second high-speed signal pin with the same definition as the first high-speed signal pin; the circuit board has a first surface and a second surface disposed opposite to each other, the first surface has a first pad, the second surface has a second pad, and the projection of the second pad on the circuit board at least partially overlaps with the projection of the first pad on the circuit board; the first SMT connector is disposed on the first surface, and the first high-speed signal pin is configured to connect to the first pad; the second SMT connector is disposed on the second surface, and the second high-speed signal pin is configured to connect to the second pad; wherein, a high-speed interconnect structure extending through the circuit board in the thickness direction is provided between the first pad and the second pad, and the high-speed interconnect structure is electrically connected to the first pad and the second pad respectively.
[0008] The circuit board assembly provided in this application comprises a first SMT connector disposed on a first surface of the circuit board, the first SMT connector having a first high-speed signal pin, a first pad on the first surface, and the first high-speed signal pin being connected to the first pad; and a second SMT connector disposed on a second surface of the circuit board, the second SMT connector having a second high-speed signal pin, a second pad on the second surface, and the second high-speed signal pin being connected to the second pad; the projection of the second pad on the circuit board at least partially overlaps with the projection of the first pad on the circuit board, and a high-speed interconnect structure penetrating the circuit board vertically between the first pad and the second pad, so as to enable high-speed signal interconnection between the first SMT connector and the second SMT connector. In this way, high-speed signals of the first SMT connector and the second SMT connector on opposite sides of the circuit board can be directly connected through a single high-speed interconnect structure, eliminating the need for multiple high-speed differential vias and multiple layers of traces on the surface and inner layers of the circuit board, reducing the number of high-speed interconnect structures with different impedance characteristics, thereby improving the impedance continuity on the transmission path of the high-speed interconnect structure, and thus improving the signal integrity of high-speed signal transmission and reducing noise.
[0009] In some embodiments, the overlapping area of the first pad and the second pad has a through hole that sequentially penetrates the first pad, the circuit board and the second pad, the through hole being filled with a conductive material, and the through hole and the conductive material filling the through hole together form the high-speed interconnect structure.
[0010] By positioning the vias in the first and second pads to form a via-hole, and placing conductive material in the vias to enable high-speed signal interconnection between the first and second SMT connectors, the spatial layout of the circuit board is optimized and the compactness of the circuit board layout is improved.
[0011] In some embodiments, the projection of the first pad on the circuit board coincides with the projection of the second pad on the circuit board.
[0012] By making the projection of the second pad on the circuit board coincide with the projection of the first pad on the circuit board, the spatial layout of the circuit board is further optimized and the compactness of the circuit board layout is improved. This allows the first pad and the second pad to be interconnected by a high-speed interconnect structure that runs vertically through the circuit board, thereby enabling high-speed signal interconnection between the first SMT connector and the second SMT connector. This improves the impedance continuity on the transmission path of the high-speed interconnect structure and thus enhances the signal integrity of high-speed signal transmission.
[0013] In some embodiments, the first SMT connector has a plurality of first high-speed signal pins, and the second SMT connector has a plurality of second high-speed signal pins, wherein one second high-speed signal pin is disposed opposite to one first high-speed signal pin and has the same pin definition.
[0014] By setting the second high-speed signal pin opposite to the first high-speed signal pin with the same definition, the second high-speed signal pin and its opposite first high-speed signal pin are connected by a high-speed interconnect structure that runs vertically through the circuit board, thereby improving the impedance continuity of the high-speed interconnect structure transmission path and optimizing the spatial layout of the circuit board.
[0015] In some embodiments, a plurality of the first high-speed signal pins respectively form a first high-speed signal transmitting pin group and a first high-speed signal receiving pin group spaced apart; a plurality of the second high-speed signal pins respectively form a second high-speed signal transmitting pin group and a second high-speed signal receiving pin group spaced apart; wherein, the first high-speed signal transmitting pin group and the second high-speed signal transmitting pin group are arranged opposite to each other, and the first high-speed signal receiving pin group and the second high-speed signal receiving pin group are arranged opposite to each other; and the spacing between the first high-speed signal transmitting pin group and the first high-speed signal receiving pin group is equal to the spacing between the second high-speed signal transmitting pin group and the second high-speed signal receiving pin group.
[0016] By setting the first high-speed signal transmitting pin group and the second high-speed signal transmitting pin group relative to each other, and setting the first high-speed signal receiving pin group and the second high-speed signal receiving pin group relative to each other; and by setting the spacing between the first high-speed signal transmitting pin group and the first high-speed signal receiving pin group to be equal to the spacing between the second high-speed signal transmitting pin group and the second high-speed signal receiving pin group, the spatial layout of the circuit board is further optimized, and the impedance continuity on the transmission path of the high-speed interconnect structure is improved.
[0017] In some embodiments, the circuit board also has heat dissipation ventilation holes that extend through the circuit board.
[0018] By setting heat dissipation and ventilation holes on the circuit board, the performance of high-speed signals can be improved.
[0019] In some embodiments, the circuit board assembly includes at least two first SMT connectors, which are spaced apart on the first surface, and the heat dissipation vent is disposed between two adjacent first SMT connectors.
[0020] By setting heat dissipation ventilation holes between two adjacent first SMT connectors, heat dissipation can be provided for adjacent high-speed interconnect structures and circuit boards, thereby improving the performance of high-speed signal transmission.
[0021] In some embodiments, the first SMT connectors on both sides of the heat dissipation vent are symmetrically arranged with the central axis of the heat dissipation vent as the center of symmetry.
[0022] By symmetrically arranging the first SMT connectors on both sides of the heat dissipation vent, the heat dissipation uniformity of the high-speed interconnect structure on both sides of the heat dissipation vent can be improved.
[0023] In some embodiments, the high-speed interconnect structure is a high-speed differential via.
[0024] High-speed signal interconnection between the first and second SMT connectors, which are positioned opposite each other on the circuit board, can be achieved through a high-speed differential via. This method is simple in structure and low in cost.
[0025] In some embodiments, the first SMT connector is a device card connector, and the second SMT connector is a custom card connector.
[0026] A second aspect of this application provides a server including the circuit board assembly provided in the above embodiments.
[0027] The server provided in this application embodiment has the same beneficial effects as the circuit board assembly provided in the above embodiments, and will not be described again here.
[0028] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the circuit board assembly and server provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1 This is a partial structural schematic diagram of the circuit board assembly provided in an embodiment of this application;
[0031] Figure 2 A schematic diagram of a circuit board assembly provided in an embodiment of this application;
[0032] Figure 3 Another schematic diagram of the circuit board assembly provided in the embodiments of this application;
[0033] Figure 4 This is another schematic diagram of the circuit board assembly provided in an embodiment of this application;
[0034] Figure 5 A partial schematic diagram of the first surface of the circuit board in the circuit board assembly provided in the embodiments of this application;
[0035] Figure 6 This is a partial schematic diagram of the second surface of the circuit board in the circuit board assembly provided in the embodiments of this application.
[0036] Figure label:
[0037] 100 - Circuit board assembly;
[0038] 110 - Circuit board; 111 - First surface; 112 - Second surface; 113 - First pad; 114 - Second pad; 115 - Heat dissipation vent; 116 - Inner layer trace; 117 - High-speed differential via; 118 - Surface layer trace;
[0039] 120 - First SMT connector; 121 - First high-speed signal pin; 121a - First high-speed signal transmit pin group; 121b - First high-speed signal receive pin group;
[0040] 130 - Second SMT connector; 131 - Second high-speed signal pin; 131a - Second high-speed signal transmit pin group; 131b - Second high-speed signal receive pin group;
[0041] 140 - High-speed interconnect structure; 150 - Device card; 160 - High-speed cable. Detailed Implementation
[0042] First, the technical terms involved in the embodiments of this application will be explained.
[0043] High-speed interconnect structure: refers to the physical structure that includes connectors, cables, PCB traces, high-speed differential vias, etc., to connect chips and enable high-speed signal transmission paths.
[0044] Signal integrity refers to all problems caused by interconnect structures in high-speed circuit design. Signal integrity means that the receiver can receive a signal that meets the eye height and eye width requirements without affecting the quality of other signals in the system.
[0045] Impedance: Impedance can be understood as the degree to which a passive component in an AC circuit reduces or impedes the flow of current.
[0046] Impedance continuity: When transmitting high-speed signals, the impedance continuity of the high-speed interconnect structure should be satisfied as much as possible. If the impedance is discontinuous or mismatched, it will lead to a deterioration of the waveform of the received signal, an increase in jitter, and a deterioration of the eye diagram.
[0047] SMT (Surface-mount Technology) connectors are a type of surface-mount electronic connector that features higher density integration, higher reliability, and a compact design.
[0048] The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, or PCIe for short) is a high-speed serial point-to-point dual-channel high-bandwidth transmission standard with the advantage of high data transmission rate.
[0049] This application provides a circuit board assembly and a server. A first SMT connector is disposed on a first surface of the circuit board, the first SMT connector having a first high-speed signal pin and a first pad on the first surface, the first high-speed signal pin being connected to the first pad. A second SMT connector is disposed on a second surface of the circuit board, the second SMT connector having a second high-speed signal pin and a second pad on the second surface, the second high-speed signal pin being connected to the second pad. The projection of the second pad on the circuit board at least partially overlaps with the projection of the first pad on the circuit board. A high-speed interconnect structure extending vertically through the circuit board is provided between the first pad and the second pad, enabling high-speed signal interconnection between the first SMT connector and the second SMT connector. Thus, a single high-speed interconnect structure allows direct high-speed signal connection between the first SMT connector and the second SMT connector on opposite sides of the circuit board, eliminating the need for multiple high-speed differential vias and multi-layer traces on the surface and inner layers of the circuit board. This reduces the number of high-speed interconnect structures with different impedance characteristics, thereby improving the impedance continuity along the transmission path of the high-speed interconnect structure, and further improving the signal integrity of high-speed signal transmission while reducing noise.
[0050] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0051] Figure 1 This is a schematic diagram of a circuit board assembly provided in an embodiment of this application. Please refer to... Figure 1 As shown, this application embodiment provides a circuit board assembly 100, which includes a circuit board 110, which can be a printed circuit board (PCB).
[0052] In some embodiments, such as Figure 2As shown, the circuit board assembly 100 also includes a first SMT connector 120 and a second SMT connector 130. The circuit board 110 has a first surface 111 and a second surface 112 disposed opposite to each other. The first SMT connector 120 is disposed on the first surface 111, and the second SMT connector 130 is disposed on the second surface 112. Either side of the circuit board 110 is the first surface 111, and the other side of the circuit board 110 opposite to the first surface 111 is the second surface 112. For example, the first SMT connector 120 is soldered to the first surface 111, and the second SMT connector 130 is soldered to the second surface 112. The first SMT connector 120 is used to connect to a device card 150 with an industry standard interface, and the second SMT connector 130 is used to connect to a custom high-speed interconnect structure or component, for example, in... Figure 2 In the middle, the second SMT connector 130 is connected to the high-speed cable 160, and is connected to the circuit board or chip through the high-speed cable 160.
[0053] The first surface 111 has a first pad 113, and the first SMT connector 120 has a first high-speed signal pin 121, which is connected to the first pad 113. The second surface 112 has a second pad 114, and the second SMT connector 130 has a second high-speed signal pin 131, which is connected to the second pad 114. The first pad 113 and the second pad 114 are interconnected by multiple high-speed interconnect structures to achieve high-speed signal interconnection.
[0054] In some embodiments, such as Figure 2 As shown, multiple high-speed interconnect structures include surface traces 118 of the circuit board 110 connected between the first pad 113 and the second pad 114, high-speed differential vias 117 connected to the surface traces 118 of the circuit board 110, and inner layer traces 116 connected to the high-speed differential vias 117 of the circuit board 110, to achieve high-speed signal interconnection. One end of the high-speed differential via 117 is back-drilled, meaning one end of the high-speed differential via 117 is connected to the surface traces 118 of the circuit board 110, while the other end remains as a through-hole structure after back-drilling between it and the surface of the circuit board 110. However, because the surface traces 118, high-speed differential vias 117, and inner layer traces 116 of the circuit board 110 all have different impedance characteristics, impedance discontinuities occur in the transmission path of the high-speed interconnect structure, resulting in poor high-speed signal integrity.
[0055] For the above issues, please refer to Figure 3As shown, this application embodiment provides a circuit board assembly 100. The projection of the second pad 114 on the circuit board 110 at least partially overlaps with the projection of the first pad 113 on the circuit board 110. The first high-speed signal pin 121 is connected to the first pad 113, and the second high-speed signal pin 131 is connected to the second pad 114. The second high-speed signal pin 131 has the same definition as the first high-speed signal pin 121. The first pad 113 and the second pad 114 are connected by a high-speed interconnect structure 140 that penetrates the circuit board 110 in a vertical direction, and the high-speed interconnect structure 140 is electrically connected to the first pad 113 and the second pad 114 respectively.
[0056] Therefore, in this embodiment, one end of the high-speed interconnect structure 140 is directly connected to the first pad 113, and the other end is directly connected to the second pad 114. Furthermore, the high-speed interconnect structure 140 penetrates the circuit board 110 in a vertical direction (e.g., the thickness direction of the circuit board 110). This eliminates the need for surface traces on the circuit board 110, as well as the need for multiple high-speed differential vias 117 and inner layer traces 116. Instead, the high-speed interconnect structure 140 directly connects the first pad 113 and the second pad 114 in a vertical direction, achieving high speed... The interconnection of high-speed signals reduces the number of high-speed interconnect structures 140 with different impedance characteristics, thereby improving the impedance continuity on the transmission path of the high-speed interconnect structure 140, which in turn improves the signal integrity of high-speed signal transmission, reduces noise, and eliminates the effects of crosstalk, high-speed differential line pair misalignment, and insertion loss introduced by the circuit board 110 traces. In addition, it can optimize the spatial layout of the circuit board 110 and save space for the heat dissipation structure of the high-speed interconnect structure 140. Therefore, the circuit board assembly 100 provided in this application embodiment can be applied to the optimization of high-speed signal PCIe Gen6 PAM4 interconnect scheme in the design of next-generation high-density server circuit boards 110 and to future higher-speed signals (PCIe Gen7 PAM4) and higher density, as well as high-speed interconnect designs with heat dissipation challenges, which can improve the signal integrity of PAM4 high-speed signals on next-generation server density circuit boards 110.
[0057] It is understandable that, such as Figure 3As shown, the projections of the first pad 113 and the second pad 114 on the circuit board 110 overlap the projection of the high-speed interconnect structure 140 on the circuit board 110, thereby allowing the high-speed interconnect structure 140 to be directly connected to the first pad 113 and the second pad 114 in the vertical direction. The first high-speed signal pin 121 on the first SMT connector 120 is connected to the first pad 113, and the second high-speed signal pin 131 on the second SMT connector 130 is connected to the second pad 114. The first SMT connector 120 is connected to the device card 150, and the second SMT connector 130 is connected to connectors, PCBs, or chips through a high-speed cable 160.
[0058] In some embodiments, the high-speed interconnect structure 140 includes a through-hole that sequentially penetrates a first pad 113, a circuit board 110, and a second pad 114 corresponding to the first pad 113 in a vertical direction, and a conductive material filling the through-hole. Thus, the through-hole and the conductive material in the through-hole together form a high-speed interconnect structure 140 connecting the first pad 113 and the second pad 114. That is, the high-speed interconnect structure 140 is formed as a pad-in-hole on the first pad 113 and the second pad 114, wherein the conductive material filling the through-hole is filled with epoxy resin in the through-hole and copper plating on the surface of the epoxy resin.
[0059] Understandably, by setting the high-speed interconnect structure 140 as a via in the tray, it helps to optimize the spatial layout, trace density, and spacing capacity of the congested areas of the circuit board 110, thereby improving the compactness of the spatial layout of the circuit board 110; in addition, it can also reduce the low loss requirements of the PCB board material and reduce costs.
[0060] To further optimize the spatial layout of the circuit board 110, in some embodiments, please refer to... Figure 4 As shown, the projection of the first pad 113 on the circuit board 110 completely overlaps with the projection of the second pad 114 on the circuit board 110. That is, the first pad 113 and its corresponding second pad 114 are aligned on opposite sides of the circuit board 110 to further optimize the spatial layout of the circuit board 110 and improve the compactness of the layout. This allows the first pad 113 and the second pad 114 to achieve high-speed signal interconnection between the first SMT connector 120 and the second SMT connector 130 through a high-speed interconnect structure 140 that runs vertically through the circuit board 110. This improves the impedance continuity on the transmission path of the high-speed interconnect structure 140 and thus enhances the signal integrity of high-speed signal transmission.
[0061] In some embodiments, please refer to Figure 5 and Figure 6As shown, the first SMT connector 120 has a plurality of first high-speed signal pins 121, each of which has a specific definition; the second SMT connector 130 has a plurality of second high-speed signal pins 131, wherein one second high-speed signal pin 131 is arranged opposite to one first high-speed signal pin 121. For example, one second high-speed signal pin 131 and one first high-speed signal pin 121 are symmetrically arranged on opposite sides of the circuit board 110, and the definition of the second high-speed signal pin 131 is the same as the definition of its corresponding first high-speed signal pin 121. This allows the plurality of second high-speed signal pins 131 and the plurality of first high-speed signal pins 121 to be arranged one-to-one on opposite sides of the circuit board 110. For example, the second high-speed signal pins 131 on the second surface 112 of the circuit board 110 have the same definition as the first surface 111. Signal pins 121 are aligned; additionally, each first surface 111 of the circuit board 110 has a first pad 113 at a position corresponding to each first high-speed signal pin 121, and each first high-speed signal pin 121 is connected to its corresponding first pad 113; each second surface 112 of the circuit board 110 has a second pad 114 at a position corresponding to each second high-speed signal pin 131, and each second high-speed signal pin 131 is connected to its corresponding second pad 114, while the first pad 113 and the corresponding second pad 114 are connected through a high-speed interconnect structure 140. For example, the high-speed interconnect structure 140 is a high-speed differential via disposed on the first pad 113 and the second pad 114. In this way, the spatial layout of the circuit board 110 can be optimized, the impedance continuity of the transmission path of the high-speed interconnect structure 140 can be improved, thereby improving the signal integrity of the high-speed interconnect signal.
[0062] For example, in Figure 5 and Figure 6 In this configuration, multiple first high-speed signal pins 121 respectively form a first high-speed signal transmitting pin group 121a and a first high-speed signal receiving pin group 121b spaced apart; multiple second high-speed signal pins 131 respectively form a second high-speed signal transmitting pin group 131a and a second high-speed signal receiving pin group 131b spaced apart; wherein, the first high-speed signal transmitting pin group 121a and the second high-speed signal transmitting pin group 131a are arranged opposite to each other, and the first high-speed signal receiving pin group 121b and the second high-speed signal receiving pin group 131b are arranged opposite to each other; and the spacing between the first high-speed signal transmitting pin group 121a and the first high-speed signal receiving pin group 121b is equal to the spacing between the second high-speed signal transmitting pin group 131a and the second high-speed signal receiving pin group 131b.
[0063] It is understandable that, such as Figure 5As shown, the first high-speed signal transmitting pin group 121a and the first high-speed signal receiving pin group 121b each include a plurality of first high-speed signal pins 121, and each first high-speed signal pin 121 in the first high-speed signal transmitting pin group 121a corresponds one-to-one with each first high-speed pin in the first high-speed signal receiving pin group 121b; correspondingly, as Figure 6 As shown, the second high-speed signal transmitting pin group 131a and the second high-speed signal receiving pin group 131b each include a plurality of second high-speed signal pins 131, and each second high-speed signal pin 131 in the second high-speed signal transmitting pin group 131a is respectively configured to correspond one-to-one with each second high-speed pin in the second high-speed signal receiving pin group 131b, so as to improve the space layout of the circuit board 110 and save space of the circuit board 110.
[0064] Therefore, in this embodiment, by setting the first high-speed signal transmitting pin group 121a and the second high-speed signal transmitting pin group 131a opposite to each other, and setting the first high-speed signal receiving pin group 121b and the second high-speed signal receiving pin group 131b opposite to each other; and by setting the spacing between the first high-speed signal transmitting pin group 121a and the first high-speed signal receiving pin group 121b to be equal to the spacing between the second high-speed signal transmitting pin group 131a and the second high-speed signal receiving pin group 131b, the spatial layout of the circuit board 110 is further optimized, and the impedance continuity on the transmission path of the high-speed interconnect structure 140 is improved.
[0065] As the device density on the circuit board 110 increases, the high-speed interconnect structure 140 between the first SMT connector 120 and the second SMT connector 130 also presents a challenge for heat dissipation. This is because the electrical performance of the high-speed interconnect signal deteriorates under high temperature conditions, resulting in poor electrical performance of the high-speed interconnect signal.
[0066] To address this issue, in some embodiments, the circuit board 110 is provided with heat dissipation ventilation holes 115 that penetrate the circuit board 110, so as to dissipate heat from the high-speed interconnect structure 140 through the heat dissipation ventilation holes 115, thereby improving the electrical performance of the high-speed interconnect signal.
[0067] For example, the heat dissipation vent 115 may be located near the high-speed interconnect structure 140 to improve the heat dissipation effect of the high-speed interconnect structure 140 and improve the electrical performance of the high-speed interconnect signal.
[0068] In some embodiments, the circuit board assembly 100 includes at least two first SMT connectors 120, which are spaced apart from the first surface 111. A heat dissipation vent 115 is disposed between two adjacent first SMT connectors 120. In this way, by providing a heat dissipation vent 115 between two adjacent first SMT connectors 120, heat dissipation can be provided for the adjacent high-speed interconnect structure 140 and the circuit board 110, thereby improving the performance of the transmitted high-speed signal.
[0069] To further improve the heat dissipation effect on two adjacent high-speed interconnect structures 140, in some embodiments, such as Figure 4 As shown, the first SMT connectors 120 on both sides of the heat dissipation vent 115 are symmetrically arranged, which can improve the heat dissipation uniformity of the high-speed interconnect structure 140 on both sides of the heat dissipation vent 115.
[0070] In some embodiments, the heat dissipation ventilation hole 115 between two adjacent first SMT connectors 120 can be an elongated hole, and the length of the heat dissipation ventilation hole 115 on the circuit board 110 is basically aligned with the length of each first SMT connector 120 at both ends. In this way, the high-speed interconnect structure 140 on both sides of the heat dissipation ventilation hole 115 can be cooled to improve the electrical performance of the high-speed interconnect structure 140.
[0071] Therefore, in this embodiment, the high-speed signal interconnection between the first SMT connector 120 and the opposite second SMT connector 130 is achieved through a high-speed interconnect structure 140 with only one high-speed differential via 117. This eliminates the need for multiple high-speed differential vias 117 and multiple layers of traces on the surface and inner layers of the circuit board 110, reducing the number of high-speed interconnect structures 140 with different impedance characteristics. This improves the impedance continuity on the transmission path of the high-speed interconnect structure 140, thereby enhancing the signal integrity of high-speed signal transmission, reducing noise, and eliminating the effects of crosstalk, high-speed differential line pair misalignment, and insertion loss introduced by the traces on the circuit board 110. This improves the signal integrity of PAM4 high-speed signals on the next-generation server density backplane. In addition, it can effectively optimize the spatial layout of the high-density circuit board 110, saving space for heat dissipation structures such as heat dissipation vents 115 on the circuit board 110. This balances the spatial layout between the high-speed interconnect structure 140 and the heat dissipation vents 115 on the circuit board 110, improving the heat dissipation effect of the high-speed interconnect structure 140, and thus improving the electrical performance of the high-speed interconnect structure 140.
[0072] This application also provides a server, including the circuit board assembly provided in the above embodiments.
[0073] The structure and working principle of the circuit board assembly have been described in detail in the above embodiments and will not be repeated here.
[0074] The server provided in this application embodiment has the same beneficial effects as the circuit board assembly provided in the above embodiments, and will not be described again here.
[0075] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0076] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A circuit board assembly, characterized in that, include: A circuit board, a first SMT connector, and a second SMT connector; the first SMT connector has a first high-speed signal pin; the second SMT connector has a second high-speed signal pin with the same definition as the first high-speed signal pin. The circuit board has a first surface and a second surface disposed opposite to each other. The first surface has a first pad, and the second surface has a second pad. The projection of the second pad on the circuit board at least partially overlaps with the projection of the first pad on the circuit board. The first SMT connector is disposed on the first surface, and the first high-speed signal pin is configured to connect to the first pad; the second SMT connector is disposed on the second surface, and the second high-speed signal pin is configured to connect to the second pad. The first pad and the second pad have a high-speed interconnect structure that extends through the circuit board along the thickness direction of the circuit board, and the high-speed interconnect structure is electrically connected to the first pad and the second pad respectively.
2. The circuit board assembly according to claim 1, characterized in that, The overlapping area of the first pad and the second pad has a through hole that passes through the first pad, the circuit board and the second pad in sequence. The through hole is filled with conductive material, and the through hole and the conductive material filled in the through hole together form the high-speed interconnect structure.
3. The circuit board assembly according to claim 1, characterized in that, The projection of the first pad on the circuit board coincides with the projection of the second pad on the circuit board.
4. The circuit board assembly according to any one of claims 1-3, characterized in that, The first SMT connector has a plurality of first high-speed signal pins, and the second SMT connector has a plurality of second high-speed signal pins, wherein one second high-speed signal pin is disposed opposite to one first high-speed signal pin and the pins have the same definition.
5. The circuit board assembly according to claim 4, characterized in that, The plurality of first high-speed signal pins respectively form a first high-speed signal transmitting pin group and a first high-speed signal receiving pin group arranged at intervals; the plurality of second high-speed signal pins respectively form a second high-speed signal transmitting pin group and a second high-speed signal receiving pin group arranged at intervals; The first high-speed signal transmitting pin group and the second high-speed signal transmitting pin group are arranged opposite to each other, and the first high-speed signal receiving pin group and the second high-speed signal receiving pin group are arranged opposite to each other; and the distance between the first high-speed signal transmitting pin group and the first high-speed signal receiving pin group is equal to the distance between the second high-speed signal transmitting pin group and the second high-speed signal receiving pin group.
6. The circuit board assembly according to any one of claims 1-3, characterized in that, The circuit board also has heat dissipation and ventilation holes that penetrate the circuit board.
7. The circuit board assembly according to claim 6, characterized in that, The circuit board assembly includes at least two first SMT connectors, which are spaced apart on the first surface, and the heat dissipation vent is disposed between two adjacent first SMT connectors.
8. The circuit board assembly according to claim 7, characterized in that, The first SMT connectors on both sides of the heat dissipation and ventilation hole are symmetrically arranged with the central axis of the heat dissipation and ventilation hole as the center of symmetry.
9. The circuit board assembly according to any one of claims 1-3, characterized in that, The high-speed interconnect structure is a high-speed differential via.
10. The circuit board assembly according to any one of claims 1-3, characterized in that, The first SMT connector is a device card connector, and the second SMT connector is a custom card connector.
11. A server, characterized in that, Includes the circuit board assembly as described in any one of claims 1-10.