Method for the production of a multi-time erasable programmable memory

Abstract

The present invention relates to a method for manufacturing a multi-time erasable programmable memory, the memory cell of which comprises a transistor for implementing programming and erasing, the method comprising the following steps: after forming active regions and isolation regions on the surface of a substrate and before forming a gate oxide layer of the transistor, covering the active regions with a sacrificial oxide layer, exposing the area of the transistor in the active regions using a mask, etching the sacrificial oxide layer on the active regions in the area of the transistor; and then removing the mask and etching the entire surface of the substrate to remove the sacrificial oxide layer in the remaining regions. The method of the present invention can reduce the size of the memory cell while maintaining its excellent performance.

Description

Method for fabricating repeatedly erasable programmable memory Technical Field

[0001] This invention relates generally to a method for fabricating non-volatile memory, and more specifically, to a method for fabricating repeatedly erasable programmable memory. Background Technology

[0002] In existing non-volatile (NVM) repeatedly erasable programmable memory (MTP) technologies, the transistors in the memory cells are generally required to be designed as high-voltage transistor devices, such as devices operating at 5V. These high-voltage devices typically result in large memory cells that occupy a significant portion of the chip, making it difficult to meet the high-density integration requirements of advanced process nodes.

[0003] As semiconductor manufacturing processes continue to shrink, forcibly reducing the physical size of high-voltage devices and their memory cells proportionally will significantly degrade their inherent electrical characteristics. Specifically, high-voltage devices require high erase voltages, necessitating a larger well size to withstand these high voltages. Forcibly shrinking the well size will lead to performance degradation or even failure. Furthermore, forcibly shrinking the device size lowers the potential barrier between the source and drain of the transistor, resulting in a shorter effective channel length and a significant increase in off-state leakage current. Even worse, the shorter channel length can trigger a punch-through effect, where the depletion regions of the source and drain connect within the channel, allowing carriers to pass directly without gate control, leading to increased current runaway and device malfunction. This series of negative effects caused by size reduction severely restricts the applicability of memories containing high-voltage transistor devices in advanced manufacturing processes.

[0004] Therefore, the industry needs a new method that can both reduce the size of memory cells, especially high-voltage transistor devices and their memory cells, and maintain the excellent performance of transistor devices and their memory cells. Summary of the Invention

[0005] This invention provides a novel method for fabricating repeatedly erasable programmable memories, which can further reduce the physical size of the memory cells while maintaining excellent performance, thereby meeting the needs of higher-density integrated circuits.

[0006] This invention relates to a method for fabricating a repeatedly erasable programmable memory, the memory comprising at least one memory cell formed in an active region on a substrate surface, the memory cell including a transistor for programming and erasing, the transistor including a gate oxide layer on the substrate surface; an isolation region is arranged adjacent to the active region on the substrate surface; the method includes the following steps: after forming the active region and the isolation region on the substrate surface and before forming the gate oxide layer of the transistor, a sacrificial oxide layer is covered on the active region; a photomask is used to expose the transistor region; the sacrificial oxide layer on the active region in the exposed region is etched away; then the photomask is removed; the entire substrate surface is etched to remove the sacrificial oxide layer in the remaining areas, while the transistor region is etched again. Preferably, the photomask exposes only the transistor region for programming and erasing, and a portion of the isolation region adjacent to the transistor region.

[0007] In a preferred embodiment, before using a photomask to etch away the sacrificial oxide layer on the active region of the transistor region, ion implantation is performed on the region using the same photomask to be used for etching.

[0008] In another preferred embodiment, the transistor is located in a well within a substrate, the well being formed after the formation of the active and isolation regions and before ion implantation of the transistor region. More preferably, after the well is formed, ion implantation is performed on the transistor region directly using the same photomask used to form the well, followed by etching to remove the sacrificial oxide layer of the transistor region; provided that if there are other components in the well, the performance of the other components is not degraded by the ion implantation and etching, and the well containing the transistor is formed separately and not together with other wells of the same type in the memory.

[0009] In another preferred embodiment, the substrate is P-type, containing a deep N-well, which in turn contains an adjacent N-well and a P-well; the transistor is PMOS type and located in the N-well; the memory cell further includes an NMOS capacitor located in the P-well, which contains an N+ coupling region located in the P-well; the transistor and capacitor are located in different active regions on the substrate surface and are separated by an isolation region; they share a gate oxide layer and a floating gate. More preferably, the photomask also exposes a portion of the isolation region between the transistor and capacitor regions, but does not expose the capacitor region.

[0010] In yet another preferred embodiment, the memory cell further includes a selection transistor connected in series with the transistors used for programming and erasing, both located within the N-well, with the photomask exposing or concealing the area of ​​the selection transistor. Attached Figure Description

[0011] Figure 1 is a schematic diagram of the sequential formation of a sacrificial oxide (SO) layer and a silicon nitride (SiN) layer on the substrate surface.

[0012] Figure 2 is a schematic diagram of shallow trenches (STI) formed on the substrate surface.

[0013] Figure 3 is a schematic diagram of filling the shallow trench with an isolation material (FOX) to form an isolation region and forming a trap in the substrate.

[0014] Figure 4 is a schematic diagram of etching the sacrificial oxide layer in the transistor region using a photomask.

[0015] Figure 5 is a schematic diagram of etching the entire substrate surface to remove the remaining sacrificial oxide layer.

[0016] Figure 6 is a schematic diagram of the formation of a gate oxide (GO) layer on the substrate surface.

[0017] Figure 7 is a schematic diagram of ion implantation into the transistor region using the same photomask used to etch the transistor region.

[0018] Figure 8 is a top view of a storage cell of a memory prepared by the method of the present invention.

[0019] Figure 9 is a longitudinal sectional view of the storage cell shown in Figure 8 along section line BB.

[0020] Figure 10 is a schematic diagram of the memory cell shown in Figure 9 after the isolation region and active region are formed on the surface of the well.

[0021] Figure 11 is a schematic diagram of the memory cell shown in Figure 10 after ion implantation in the transistor region and etching away all the sacrificial oxide layer from the well surface.

[0022] Figure 12 is a schematic diagram of the memory cell shown in Figure 11 after the gate oxide layer has been formed.

[0023] Figure 13 shows the threshold voltage before ion implantation when the channel length of a 5V PMOS transistor is reduced to 0.19 micrometers.

[0024] Figure 14 shows the source-drain punch-through voltage of a 5V PMOS transistor before ion implantation when the channel length is reduced to 0.19 micrometers.

[0025] Figure 15 shows the relationship between implanted ion concentration and transistor threshold (VT) when the channel length of a 5V PMOS transistor is reduced to 0.19 micrometers.

[0026] Figure 16 shows the relationship between implanted ion concentration and transistor source-drain punch-through voltage (BV) when the channel length of a 5V PMOS transistor is reduced to 0.19 micrometers. Detailed Implementation

[0027] The specific embodiments of the method described in this invention are described in detail below with reference to the accompanying drawings. The same numbers in the drawings indicate the same or similar components. The specific embodiments in the drawings are for illustrative purposes only and should not be used to limit the scope of protection of this invention. Those skilled in the art will understand that the scope of protection of this invention can include various changes and variations beyond the specific examples in the drawings.

[0028] The rewritable programmable memory fabricated in this invention includes at least one memory cell, all of which are constructed on a substrate. The substrate surface has adjacently arranged active regions (AA) and shallow trench isolation regions (FOX). The components of the memory cell are located within the active regions. At least one of the components included in the memory cell is a transistor for programming and erasing. This transistor includes a source and drain located within the active regions, a gate oxide (GO) layer located on the substrate surface, and a floating gate above the gate oxide layer. Programming of the memory cell is achieved by injecting hot carriers into the floating gate through the channel between the source and drain, and erasing is achieved by tunneling hot carriers in the floating gate through a fuller-Nordheim (FN) junction to the channel.

[0029] The components in a memory cell are typically located in wells, and different components may have their own separate wells. Depending on their electrical performance and application, two or more components may share a single well. All wells are located within the substrate.

[0030] The steps for fabricating the memory according to the present invention will be described in detail below with reference to the accompanying drawings. The steps for forming the isolation region and the active region on the substrate, as shown in Figures 1-3, are prior art. The steps shown in Figures 4-7 are the steps of the method of the present invention.

[0031] First, a substrate is provided, typically a silicon substrate. It can be P-type or N-type.

[0032] Before fabricating the memory cells, a sacrificial oxide (SO) layer is first formed on the surface of the substrate to protect it. Then, a sacrificial oxide (SO) layer and a silicon nitride (SiN) layer are sequentially formed on the substrate surface, as shown in Figure 1.

[0033] In the early stages of processing, the silicon surface of the substrate undergoes various mechanical and chemical treatments (such as polishing and etching), which leave damage and trace contamination on the silicon lattice surface. During the formation of the sacrificial oxide layer, silicon atoms on the substrate surface, including those from the damaged and contaminated areas, are consumed to form a layer of silicon dioxide (SiO2), i.e., the sacrificial oxide layer. After subsequent processing steps, this sacrificial oxide layer is completely etched away with hydrofluoric acid (HF), exposing a brand-new, intact, and undamaged substrate surface, which provides a perfect foundation for the subsequent growth of a high-quality gate oxide (GO) layer.

[0034] The silicon nitride (SiN) layer above the sacrificial oxide layer serves as an etching hard mask in the subsequent etching process to form the isolation region. It exhibits excellent etching selectivity, withstands the etching process, and protects the materials on the substrate surface and the substrate itself from over-etching. It also functions as an oxide barrier layer.

[0035] Subsequently, isolation regions and active regions are formed on the substrate surface.

[0036] Figure 2 shows the shallow trench (STI) formed by etching in the silicon nitride layer and the sacrificial oxide layer.

[0037] Next, as shown in Figure 3, a thick field oxide layer is filled into the formed shallow trench as an isolation material. Then, a chemical mechanical polishing (CMP) process is used to polish the filled isolation material until its height is flush with the silicon nitride layer outside the shallow trench, forming an isolation region (FOX). Then, the silicon nitride layer outside the isolation region is etched away, leaving the sacrificial oxide layer beneath the silicon nitride layer. Outside the isolation region (FOX) are the active regions, still covered by the sacrificial oxide layer. There can be multiple active regions (e.g., AA1 and AA2 in Figure 3), depending on the device requirements of the memory cell. Adjacent active regions are separated by isolation regions and each accommodates different devices. Subsequently, different wells are formed in the substrate. There can be multiple wells, such as well 1 and well 2 in Figure 3, used to accommodate different devices in the memory cell. The sacrificial oxide layer retained on the active regions on the substrate surface protects the active regions on the substrate surface during the ion implantation process of forming the wells.

[0038] In the steps of forming the isolation region in the prior art described above, the use of a silicon nitride hard mask results in a difference in height between the formed isolation region and the active region, with the active region being slightly lower than the isolation region. From a top-down view of the substrate, the top surface of the isolation region is slightly convex at the side adjacent to the active region, forming a raised line. From the longitudinal section of the substrate shown in Figure 3 (consistent with the longitudinal section direction of the memory cell along section line BB shown in Figure 9), the top surface of the isolation region adjacent to the active region forms a convex corner.

[0039] In conventional processes, these bumps must be modified; otherwise, they will affect subsequent processes and the performance of the resulting components. For example, when forming the gate oxide layer later, the gate oxide layer thickness on the bumps will be thinner than in other areas. For non-volatile memory (NVM), especially multiple erasable programmable memory (MTP), this can easily lead to charge loss, affecting the stability and reliability of electrical performance. Typically, corner rounding (TCR) is used to make the bumps / corners in the isolation region as smooth as possible, reducing stress at the bumps / corners and promoting thicker gate oxide layers. Alternatively, a two-stage growth method can be used when forming the gate oxide layer: first, a wet etching process followed by a second growth. This reduces stress at the bumps / corners in the isolation region, promoting thicker gate oxide layers at these areas.

[0040] Unlike existing technologies that deliberately modify convex lines / corners, the method of the present invention does not require modification of convex lines / corners. Instead, it utilizes them and adds an etching process to further increase the protrusion of the area, making the gate oxide layer subsequently grown in this area significantly thinner. When performing an erase operation, FN tunneling is more likely to occur at this area with a lower erase voltage.

[0041] The added etching step in the method of this invention is as follows: first, the sacrificial oxide covering the active region of the transistor area on the substrate surface is etched, and then the entire substrate surface is etched to remove the sacrificial oxide layer on the active region in the remaining areas. The details are as follows.

[0042] First, identify the region on the substrate surface where the transistors in the memory cells will be programmed and erased. Use a photomask to expose this transistor region and etch away the sacrificial oxide layer within it to expose the underlying active region, as shown in Figure 4. In Figure 4, PR represents the applied photoresist. The photomask exposes the photoresist in the transistor region, revealing the transistor region to be etched. The sacrificial oxide layer in this region is then etched away to expose the underlying active region AA1. For ease of fabrication, the photomask can also expose a portion of the isolation region adjacent to the target transistor region, as shown in Figure 4.

[0043] Preferably, the photomask exposes only the transistor regions within the active area where programming and erasure are performed, without exposing other components within the active area, to avoid affecting their electrical performance during etching. If the electrical performance of other components will not be degraded by etching, such as transistors, they can also be etched together.

[0044] When the transistor is located in a well alone, or when the well contains other components that can be etched together, the etching process described above can be performed directly using the same photomask used to form the well after the well is formed. In this case, the transistor's well must be formed separately and cannot be formed together with other wells of the same type in the memory, especially wells in logic regions.

[0045] Next, the photomask is removed, and the entire substrate surface is etched to remove the sacrificial oxide layer on the remaining active areas, exposing the active areas in the remaining regions. Simultaneously, the transistor region is etched again. Because the transistor region is a recessed area next to the isolation region's bump, it accumulates more acidic etchant and is thus etched more intensely. In other words, the exposed active areas of the transistor region undergo a strong etching process, while the active areas of other regions are not etched. As shown in Figure 5, the height of the active area AA1 in the transistor region is significantly lower than that of the active areas of other components, such as AA2. The dashed line in Figure 5 represents the height of the active area AA2 of other components.

[0046] The transistor region is etched twice to make the convex lines / corners at the boundary between its active region and the adjacent isolation region more prominent.

[0047] Then, a gate oxide (GO) layer is formed on the entire substrate surface. As shown in Figure 6, the convex angle at the boundary between the active region AA1 and the adjacent isolation region FOX in the transistor region is obvious, and the gate oxide (GO) layer formed here is very thin. See the dashed box in Figure 6.

[0048] In a memory cell, the convex line or corner at the boundary between the active region and the adjacent isolation region of the programming and erasing transistor region is the same as the convex line or corner at the boundary between the channel side of the transistor and the adjacent isolation region. During the erase operation where the transistor tunnels from the floating gate through the gate oxide layer to the channel, erase breakdown is highly likely to occur at the weak gate oxide layer at the convex line or corner. This allows for a significant reduction in the erase voltage. Consequently, the size of the well containing the transistor device can be reduced. This is particularly significant for memory cells and their associated memories containing high-voltage devices. If the erase voltage of the high-voltage device is reduced, the size of its well will be significantly reduced. This allows for a substantial reduction in the size of the memory. Furthermore, a lower erase voltage also reduces the power consumption of the memory and increases its operating speed.

[0049] Taking a 5V high-voltage transistor device as an example, after the etching steps described above in this invention, compared with the same device that has not undergone the etching, the gate oxide layer thickness at the convex line or convex corner can be reduced by at least 20 angstroms, preferably by 20-60 angstroms, the erase operation voltage is reduced by at least 3V, preferably by 3-7V, and the area of ​​its memory cell can be reduced by at least 20%, preferably by 20-45%.

[0050] In a preferred embodiment, before etching away the sacrificial oxide layer in the programming and erasing transistor regions, the same etching mask is used to perform ion implantation on the active region of the transistor region. This increases the ion concentration in the active region, thereby increasing the transistor threshold voltage and the source-drain punch-through voltage, as shown in Figure 7. This avoids leakage current and source-drain punch-through when reducing transistor size, especially channel length. It further reduces device size while maintaining excellent device performance.

[0051] Furthermore, using the same photomask as the sacrificial oxide layer in the etched transistor region for ion implantation is very convenient and efficient. This saves on processes and costs while improving efficiency.

[0052] The implanted ions have the same electrical type as the transistor's well. This ion implantation, relative to the well-forming ion implantation, can be called a compensating ion implantation. The ion implantation dose and energy are determined based on the required threshold and source-drain punch-through voltage. If a single compensating ion implantation cannot achieve the required threshold and source-drain punch-through voltage, a second ion implantation can be performed.

[0053] Taking a 5V high-voltage PMOS transistor as an example, its original channel length is 0.5-0.6 micrometers. When the channel length is reduced to 0.12-0.2 micrometers, the transistor threshold voltage drops sharply to the range of -0.1V to -0.3V, and the source-drain punch-through voltage drops to less than 5V.

[0054] Figures 13 and 14 show that when the channel length of a 5V PMOS transistor is reduced to 0.19 micrometers, before ion implantation according to the present invention, the gate potential (i.e., threshold voltage) when the transistor is turned on is close to 0V, and the source-drain punch-through voltage is 4V (where the drain potential is 0). In Figures 13-14, when the transistor is turned on or the source-drain punch-through occurs, the transistor readout current on the vertical axis reaches a stable peak value.

[0055] Using the method of the present invention, ion implantation is performed on the transistor, with the implantation energy preferably being 30-250 keV, and the post-implantation ion concentration preferably reaching 1×10⁻⁶. 12 - 5×10 13 atoms / cm³; thus, when the channel length is reduced to 0.12-0.2 micrometers, the threshold voltage can reach -0.65V to -1.0V, and the source-drain punch-through voltage can reach 8-15V.

[0056] Figure 15 shows the relationship between ion concentration and transistor threshold voltage (VT) after ion implantation at an energy (P) of 50 KeV when the channel length of a 5V PMOS transistor is reduced to 0.19 micrometers. The gate potential when the transistor is turned on is the threshold voltage VT. As can be seen from Figure 15, the threshold voltage VT of the transistor increases with increasing implanted ion concentration.

[0057] Figure 16 shows the relationship between ion concentration and source-drain punch-through voltage (BV) of a 5V PMOS transistor after ion implantation at an energy (P) of 100 KeV, with the channel length reduced to 0.19 μm. The drain potential of the transistor is 0. As can be seen from Figure 16, the source-drain punch-through voltage BV increases with increasing implanted ion concentration.

[0058] Similar to Figures 13-14, in Figures 15-16, when the transistor is turned on or the source-drain junction is punched through, the transistor readout current on the vertical axis reaches a stable peak value.

[0059] The method of the present invention and the repeatedly erasable programmable memory prepared therefrom are described below with a specific embodiment.

[0060] Figure 8 is a top view of a memory cell of a repeatedly erasable programmable memory prepared by the method of the present invention, and Figure 9 is a longitudinal cross-sectional view of the memory cell shown in Figure 8 along the BB section line. The longitudinal direction is perpendicular to the substrate surface of the memory. In most applications, multiple memory cells can be placed together to form a memory array.

[0061] The memory cell is manufactured using a 130nm logic process, but can also be manufactured using other processes, such as 130nm, 120nm, 90nm, 50nm, etc. It contains a 5V high-voltage transistor and a large-area capacitor.

[0062] The memory cell is constructed within a P-type silicon substrate. A deep N-well is disposed within the P-substrate, electrically isolating the memory cell from the substrate. The N-well and P-well are adjacent to each other and are disposed within the deep N-well. A 5V PMOS transistor 110 is disposed within the N-well. This PMOS transistor 110 includes a P-type drain 111 and a source 112. The drain 111 is connected to the bit line (BL), and the source 112 is connected to the common line (COM). A large NMOS capacitor 120 is disposed within the P-well. The capacitor 120 includes a lightly doped N-region 122A and a heavily doped N+ region 122B, located within the P-well. The heavily doped N+ region 122B is connected to the word line (WL). The word line (WL) is also connected to the P-well via a P+ contact region (not shown).

[0063] Transistor 110 is surrounded by a shallow trench isolation region (FOX) filled with a thick field oxide 114. Between the source 111 and the drain 112 is a channel region 113. Overlying the channel 113 is a gate oxide layer 115. A conductive doped polysilicon gate is placed on top of the gate oxide layer 115, forming the floating gate 116 of the PMOS transistor.

[0064] The floating gate 116 and gate oxide layer 115 extend into the P-well and partially overlap with the active region in the P-well, forming the upper plate and dielectric of the NMOS capacitor 120. The floating gate 116 also partially overlaps with the doped N-region 122A. The floating gate 116 is surrounded by a sidewall isolation layer 117, which is typically formed of silicon nitride or silicon oxide. During the formation of the N+ region, the sidewall isolation layer 117 prevents N+ implants from entering the lightly doped N-region.

[0065] During programming and erasing operations, when the potential of the floating gate 116 is greater than that of WL, and the voltage difference exceeds the threshold voltage of the NMOS capacitor, the P-well region 121 below the floating gate inverts. Electrons emitted from the doped N-region 122A form an electron layer within region 121, thereby forming the lower plate of the NMOS capacitor 120. The lower plate is connected to the word line WL through 122A and 122B.

[0066] During programming, negative and positive potentials are applied to the source and drain of the transistor via the bit line BL and the common line COM, respectively. A voltage difference is applied between the source and drain, generating a high lateral electric field along the channel. Holes are accelerated from one side of the channel to the other, causing impact ionization at the drain depletion region. The hot electrons generated by impact ionization are attracted by the positively biased control gate and injected into the floating gate. The negative source bias attracts most of the hot holes, allowing a very small number of holes to tunnel into the floating gate.

[0067] During erasure, a negative potential is applied to the heavily doped N+ region of the capacitor through the word line WL, and the floating gate acquires a negative potential through capacitive coupling. Simultaneously, a high positive potential is applied to the transistor source through the common line COM, forming an inversion layer in the transistor channel region. The inverted channel connects the source and drain, receiving a positive voltage. The high voltage difference between the floating gate and the inverted channel, applied to the gate oxide layer between them, can cause tunneling, allowing electrons in the floating gate to tunnel into the channel.

[0068] The structure and operating mechanism of this memory cell require a large area for the upper plate of capacitor 120, making its gate capacitance greater than that of transistor 110, at least 2.5 times the gate capacitance of transistor 110. This facilitates tunneling erasure during the erase operation, allowing the floating gate to obtain a higher potential through capacitive coupling. Furthermore, this memory cell contains a 5V high-voltage transistor, resulting in a high erase operation voltage, for example, around 19V. This necessitates relatively large N-wells and P-wells containing the transistors and capacitors to withstand the high erase voltage. The high voltage during erasure will affect the interface between adjacent N-wells and P-wells.

[0069] However, when the memory cell is fabricated using the method of the present invention, the gate oxide layer thickness is significantly reduced at the convex line or convex corner at the junction of the channel side and the isolation region of the transistor, and the erase voltage is significantly reduced. As a result, the required capacitor area and the size of the two wells can be greatly reduced, and the size of the memory cell is greatly reduced.

[0070] The steps for preparing the storage unit according to the present invention are described below with reference to the accompanying drawings.

[0071] The steps for forming the isolation and active regions of the memory cell shown in Figure 8 are identical to those in Figures 1-3. Well 1 and Well 2 in Figure 3 correspond to the N-well and P-well of this memory cell, respectively. The deep N-well of the memory cell is formed before the N-well and P-well. A longitudinal cross-sectional view of the memory cell after the isolation and active regions are formed is shown in Figure 10. The active regions AA1 and AA2 in Figure 10 are the active regions of the transistor and capacitor in the memory cell, respectively.

[0072] Next, prepare to etch the sacrificial oxide layer on the active region of the transistor region. Before starting the etching, use the same photomask to perform compensating N-ion implantation on the active region AA1 of the transistor region. The steps are the same as shown in Figure 7 above. The photomask exposes not only the transistor region but also a portion of its adjacent isolation region, but not the capacitor region. Compensating ions are implanted in two stages until the desired performance is achieved.

[0073] In one specific example, N-ion implantation with 50 KeV energy compensation resulted in an ion concentration of 4.7 × 10⁻⁶ in the region. 12 / cm 3 When the channel length of a transistor is reduced from 0.5 micrometers to 0.19 micrometers, such ion implantation can raise its threshold voltage to -0.74V and the source-drain punch-through voltage to 9V, ensuring normal transistor operation. Before compensating ion implantation, the threshold voltage of a transistor with a channel length reduced to 0.19 micrometers is close to 0V, and the source-drain punch-through voltage is 4V, making it inoperable. The ion implantation ensures the miniaturization of the transistor.

[0074] Next, using the same photomask, the sacrificial oxide layer on the active region AA1 of the transistor is etched. Then, without the photomask, the entire substrate surface is etched to remove the sacrificial oxide layer on other active regions (including active region AA2). These steps are exactly the same as those shown in Figures 4-5 above. A longitudinal cross-sectional view of the memory cell after two etchings is shown in Figure 11. The dashed line above the active region AA1 of the transistor in Figure 11 is a schematic height line of the active region AA2 of the capacitor. It can be clearly seen in the figure that there is a distinct convex angle at the boundary between the top surface of the isolation region FOX and the adjacent active region AA1 of the transistor. This convex angle is the convex line at the boundary between the isolation region and the channel side of the transistor, which is shown as a convex angle in the longitudinal cross-section.

[0075] Next, a gate oxide (GO) layer 115 is formed across the entire substrate surface. As shown in Figure 12, the gate oxide layer at the convex corner where the top surface of the isolation region (FOX 114) meets the side edge of the transistor channel (within the dashed box in the figure) is much thinner than in other areas. The gate oxide layer thickness in other areas is 130 angstroms, while the thickness here is only 80 angstroms. As a result, the erase operation voltage is reduced from 19V in the same device without the etching process of this invention to 14V. The capacitance area and two-well size of the memory cell can be significantly reduced. Combined with the reduction in transistor channel length mentioned above, the total area of ​​the memory cell can be reduced by 45%.

[0076] The aforementioned memory cell may also include a selection transistor, connected in series with the transistor used for programming and erasing, both located within the aforementioned N-well. In this case, the transistor used for programming and erasing may also be referred to as the first transistor, and the selection transistor as the second transistor.

[0077] In the method of this invention, the second transistor can undergo the same compensation ion implantation and secondary etching as the first transistor. That is, during the steps of compensation ion implantation and etching to remove the sacrificial oxide layer of the first transistor region, the photomask simultaneously exposes the second transistor region. Therefore, the channel length of the second transistor can be reduced, and the secondary etching has little impact on its electrical performance as a selector transistor. Alternatively, the photomask may not expose the second transistor, thus avoiding the compensation ion implantation and secondary etching, maintaining its independence and stability.

[0078] The aforementioned memory cells can also be manufactured without using logic processes. In this case, if there are no other components in the well containing the first transistor, or if there are other components in the well, such as the second transistor, and the performance of these other components is not degraded by the compensating ion implantation and sacrificial oxide etching steps of this invention, then after forming the well, the photomask used to form the well can be directly used to perform compensating ion implantation on the entire active region of the well, and the sacrificial oxide layer in that region can be etched away. This further saves on processes and costs.

[0079] Those skilled in the art will recognize that this specification and its accompanying drawings are exemplary rather than restrictive. Furthermore, the specific embodiments and examples described above are merely illustrative of the invention and do not constitute a limitation on the scope of protection of this invention.

Claims

1. A method for fabricating a repeatedly erasable programmable memory, the memory comprising at least one memory cell formed in an active region on a substrate surface, the memory cell including a transistor for programming and erasing, the transistor including a gate oxide layer on the substrate surface; an isolation region being arranged adjacent to the active region on the substrate surface; characterized in that, The method includes the following steps: after forming the active region and isolation region on the substrate surface and before forming the gate oxide layer of the transistor, a sacrificial oxide layer is covered on the active region; a photomask is used to expose the transistor region; the sacrificial oxide layer on the active region in the region is etched away; then the photomask is removed; the entire substrate surface is etched to remove the sacrificial oxide layer in the remaining areas, while the transistor region is etched again.

2. The method for fabricating a repeatedly erasable programmable memory as described in claim 1, characterized in that, Before using a photomask to etch away the sacrificial oxide layer on the active region of the transistor region, ion implantation is performed on the region using the same photomask to be used for etching.

3. The method for fabricating a repeatedly erasable programmable memory as described in claim 1 or 2, characterized in that, The photomask only exposes the transistor region where programming and erasure are performed, and a portion of the isolation region adjacent to the transistor region.

4. The method for fabricating a repeatedly erasable programmable memory as described in claim 2, characterized in that, The transistor is located in a well in the substrate, and the well is formed after the active region and the isolation region are formed and before ion implantation is performed on the transistor region.

5. The method for fabricating a repeatedly erasable programmable memory as described in claim 4, characterized in that, After the well is formed, the transistor region is ion implanted directly using the same photomask used to form the well, and then the sacrificial oxide layer of the transistor region is etched away; provided that: if there are other components in the well, the performance of the other components is not degraded by the ion implantation and etching, and the well in which the transistor is located is formed separately and not together with other wells of the same type in the memory.

6. The method for fabricating a repeatedly erasable programmable memory as described in claim 1 or 2, characterized in that, The substrate is P-type and contains a deep N-well, which contains an adjacent N-well and a P-well. The transistor is PMOS type and is located in the N-well. The memory cell also includes an NMOS capacitor located in the P-well, which contains an N+ coupling region located in the P-well. The transistor and the capacitor are located in different active regions on the substrate surface and are separated by an isolation region. They share a gate oxide layer and a floating gate.

7. The method for fabricating a repeatedly erasable programmable memory as described in claim 6, characterized in that, The photomask also exposes part of the isolation zone between the transistor and capacitor regions, but does not expose the capacitor region.

8. The method for fabricating a repeatedly erasable programmable memory as described in claim 6, characterized in that, The memory cell also includes a selection transistor, which is connected in series with the transistor that performs programming and erasing, and is located together within the N-well, with the photomask exposing or concealing the area of ​​the selection transistor.

Images