Nanocrystalline particle flash memory device based on two-dimensional material and preparation method thereof

Abstract

The invention relates to a nanocrystalline particle flash memory device based on a two-dimensional material and a preparation method of the nanocrystalline particle flash memory device. The device comprises an insulator substrate, a gate bottom electrode, a barrier layer, a floating gate layer, a tunneling layer, a two-dimensional channel layer, a source electrode and a drain electrode, wherein the floating gate layer is composed of metal Pt nanocrystalline particles, the tunneling layer is a BN medium, the barrier layer is high-dielectric-constant HfO2, the gate-control coupling ratio and the programming speed are improved by introducing a high-kappa medium and optimizing the layer thickness design, charge leakage is reduced by passivating medium defects, and the retention characteristic of the device is enhanced. The preparation method comprises the steps of grid pattern definition, barrier layer deposition, metal nanocrystalline formation, BN and two-dimensional material transfer and metal electrode preparation. According to the invention, a clean interface is formed by Van der Waals stack, low power consumption, high retentivity and ultra-fast programming flash memory characteristics are realized, and the method is suitable for the effect of high-density nonvolatile storage application.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and non-volatile memory, and in particular to a nanocrystalline flash memory device based on two-dimensional materials and its fabrication method. Background Technology

[0002] With the rapid development of big data, artificial intelligence, the Internet of Things, and 5G communication technologies, the demand for data processing and storage is growing exponentially. Non-volatile memory (NVM) plays a crucial role in the modern semiconductor industry. NVM retains data even after power loss, making it a key foundation for high energy efficiency and high reliability in computing systems and terminal devices. Since Bell Labs first invented floating-gate memory in 1967, flash memory has rapidly become the mainstream non-volatile storage technology due to its low cost, high storage density, and mature manufacturing process. Currently, commercial flash memory products almost monopolize the NVM market, holding over 99% of the market share.

[0003] However, traditional silicon-based floating-gate flash memory devices still have significant limitations in terms of structure and performance. As device feature sizes continue to shrink and the integration density of flash memory cells increases, the thickness of the gate dielectric layer must be correspondingly reduced to maintain sufficient tunneling efficiency and programming speed. However, reducing the tunneling layer thickness significantly lowers the barrier height, leading to an increased probability of charge leakage in the floating gate layer, thereby reducing the device's retention characteristics and reliability. Furthermore, traditional flash memory uses a continuous metal or polysilicon floating gate structure, where electrons can move freely throughout the entire floating gate layer. If defects or trap paths exist locally, charge may leak collectively along the conduction path. This charge coupling effect leads to problems such as inter-cell crosstalk, retention time decay, and reduced erase / write endurance, limiting the further application of flash memory in high-performance, low-power systems.

[0004] On the other hand, the programming speed of flash memory devices is typically in the microsecond range, which is far lower than the operating frequency of modern processors and high-speed interfaces. This makes it difficult to meet the high read / write speed requirements of real-time data processing, artificial intelligence computing acceleration, and edge computing scenarios. To overcome the performance bottleneck of silicon-based floating-gate flash memory, academia and industry have successively explored various new memory architectures and material systems, including charge-trap flash memory, ferroelectric RAM (FeRAM), phase-change memory (PCM), resistive random access memory (RRAM), and spin-transfer torque memory (STT-MRAM). Although these new memory technologies have improved in terms of speed or power consumption, they still face varying degrees of challenges in terms of integration compatibility, process complexity, maintaining stability, and cost control.

[0005] Two-dimensional materials (2D materials), with their atomic-level thickness, smooth and defect-free surfaces, and van der Waals interfaces without dangling bonds, offer new design possibilities for next-generation high-performance flash memory devices. 2D materials enable heterogeneous integration with traditional silicon processes, and their ultra-thin thickness allows for more efficient gate control, maintaining high on / off ratios and low power consumption while reducing operating voltage. More importantly, the band structure of 2D materials can be controllably adjusted through the number of layers, strain, or external electric field, giving them excellent carrier mobility and band designability. Existing research has shown that flash memory devices built based on 2D materials (such as MoS2, WSe2, InSe, WS2, etc.) can achieve nanosecond-level programming speeds while exhibiting excellent data retention and cycle stability.

[0006] On the other hand, metal nanocrystals (MNCs), due to their independent energy level structure and tunable work function, are widely used as charge trapping layers or floating gate layers in non-volatile memories. Compared to traditional continuous metal floating gates, MNC floating gates possess naturally discrete memory cell characteristics, effectively suppressing lateral charge diffusion and thus reducing the impact of single-charge leakage on the overall memory cell. Each nanocrystal can independently store charge, while adjacent particles are isolated by an insulating medium. Therefore, even if individual particles have leakage channels, it will not lead to a collective loss of overall charge, significantly improving the data retention capability of the device. Furthermore, metal nanocrystals have a high density of states near the Fermi level, which can enhance the potential modulation of the channel layer, improve the coupling efficiency between the memory layer and the channel layer, and facilitate faster programming and erasing processes.

[0007] To balance programming speed and charge retention characteristics, using high-k dielectric materials as both the barrier and tunneling layers is an effective approach. High-k dielectrics (such as HfO2, Al2O3, and BN) allow for thicker physical layers without sacrificing the tunneling barrier, thereby reducing leakage current and improving interface stability. By appropriately selecting the dielectric thickness and material type, excellent charge retention performance can be maintained while accelerating programming speed. Furthermore, thermal annealing passivation effectively repairs internal defects and interface traps in the dielectric, further enhancing device consistency and reliability.

[0008] While two-dimensional materials and metal nanocrystals exhibit significant performance potential in principle, achieving high-quality integration between the two remains a key research challenge. Traditional sputtering or chemical vapor deposition methods often struggle to obtain clean, contamination-free interfaces on the surface of two-dimensional materials, leading to inhomogeneous tunneling barriers or excessively high interface trap densities, thus affecting device stability. Van der Waals stacking technology offers a novel solution: this method relies on interlayer van der Waals forces to achieve stress-free heterogeneous integration of different materials, significantly reducing interface scattering and defect density, and achieving clean tunneling interfaces and highly stable heterogeneous stacked structures.

[0009] In summary, existing silicon-based floating-gate flash memory devices face severe leakage and retention degradation issues after scaling down, and their programming speed remains limited by traditional material systems, failing to break through the microsecond bottleneck. The combination of metal nanocrystals and two-dimensional semiconductor materials offers a feasible solution: by using discrete metal nanocrystals as the floating gate layer, charge leakage can be effectively reduced and retention performance improved; simultaneously, introducing a high-dielectric-constant dielectric as a barrier and tunneling layer can increase the gate-control coupling ratio and optimize programming efficiency; further, combining the high mobility characteristics of the two-dimensional semiconductor channel layer with the van der Waals stacking interface can further achieve low-power, high-speed, and high-reliability flash memory operations. Therefore, constructing a high-performance flash memory device structure based on two-dimensional materials and nanocrystals, achieving ultra-fast programming while maintaining excellent data retention and device stability, has become an important development direction for current non-volatile memory technology. Summary of the Invention

[0010] To address the technical challenge of programming speeds remaining limited to microsecond levels due to the constraints of traditional material systems, this application provides a nanocrystalline flash memory device based on two-dimensional materials and its fabrication method.

[0011] This application provides a nanocrystalline flash memory device based on two-dimensional materials and its fabrication method, which adopts the following technical solution: In a first aspect, a nanocrystalline flash memory device based on two-dimensional materials includes an insulating substrate, a gate bottom electrode, a barrier layer, a floating gate layer, a tunneling layer, a two-dimensional channel layer, a source electrode, and a drain electrode. The gate bottom electrode is located on the surface of the insulating substrate, and the barrier layer covers the gate bottom electrode and the insulating substrate. The floating gate layer composed of nanocrystalline particles covers the barrier layer, the tunneling layer covers the floating gate layer and the barrier layer, the two-dimensional channel layer covers the surface of the tunneling layer, and the source and drain are located on the two-dimensional channel layer. For the barrier layer and tunneling layer, by introducing a high dielectric constant medium and selecting the thickness, the gate control coupling ratio of the flash memory device is increased, thereby improving the programming speed. Furthermore, by improving the interface quality and passivating internal defects in the medium, the charge leakage of the floating gate layer is reduced, thereby improving the retention characteristics. The bottom gate electrode must completely contain the floating gate layer; the source and drain electrodes partially overlap with the two-dimensional channel layer; the device channel region between the source and drain electrodes is completely contained within the floating gate layer.

[0012] By adopting the above technical solutions, comprehensive optimization is achieved in terms of structural design, material selection, and interface control, thereby improving the overall performance of nanocrystalline flash memory devices based on two-dimensional materials. First, by constructing a multi-layer functional stacked structure on the surface of an insulating substrate, the charge trapping layer, tunneling layer, and channel layer are organically combined. The gate bottom electrode and the insulating substrate form a stable potential base, providing a uniform electric field distribution for the upper storage structure. The barrier layer uses a high dielectric constant dielectric material. The high dielectric constant and moderate thickness can effectively improve the capacitive coupling ratio between the gate and the floating gate, enhance the gate's ability to control the charge in the floating gate, and enable the flash memory device to achieve fast programming and erasing at a lower operating voltage, reducing energy consumption and improving operating speed. Introducing a floating gate layer composed of metal nanocrystals between the barrier layer and the tunneling layer effectively improves charge storage and retention characteristics. The metal nanocrystals have a discrete distribution structure, with each particle isolated by an insulating medium. The stored charge presents a spatially discrete state. When there are defects or traps in the local tunneling layer that cause charge leakage, only individual nanocrystal units are affected, and there will be no collective loss of the overall charge. This significantly improves data retention capability and reliability. The metal nanocrystals have a high density of states and an adjustable work function, making the charge injection and trapping process more efficient and further improving the programming efficiency of flash memory devices. The tunneling layer uses high-quality, high-dielectric-constant dielectric materials (such as BN) to ensure sufficient tunneling efficiency while exhibiting low leakage current and excellent interface stability. The two-dimensional channel layer uses semiconductor materials such as MoS2, WSe2, WS2, or InSe. With its atomic-level thickness and flat, dangling-bond-free surface characteristics, it forms a clean van der Waals interface on the tunneling layer, reducing interface traps and carrier scattering effects, and improving channel mobility and current modulation capability. The structure in which the source and drain partially overlap with the two-dimensional channel layer ensures that the channel region is completely contained within the potential control range of the floating gate layer, ensuring that the gate electric field can fully cover the conduction path, achieving a stronger channel modulation depth and a higher switching current ratio.

[0013] Optionally, the insulating substrate 1 is typically a rigid substrate such as a silicon wafer, with a 100nm or 300nm thermally oxidized SiO2 layer grown on the surface of the silicon wafer.

[0014] By adopting the above technical solution, using a silicon wafer with a thermally oxidized SiO2 layer as an insulating substrate, excellent mechanical stability and electrical insulation performance are provided. The thermally oxidized SiO2 layer effectively isolates the gate bottom electrode from the substrate, prevents leakage current, and reduces the impact of interface traps on device performance, thereby improving the electrical stability and reliability of flash memory devices. The surface of the SiO2 layer is flat and compatible with conventional micro-nano processing technology, which is conducive to the high-quality deposition and patterning of subsequent multilayer thin films, ensuring the uniformity and repeatability of the device structure.

[0015] Optionally, the gate bottom electrode material is one or more of Cr, Ti, Sb, Au, and Pt metals.

[0016] By adopting the above technical solutions and using metal materials such as Cr, Ti, Sb, Au, and Pt as gate bottom electrodes, the work function, conductivity, and chemical stability of the electrodes can be flexibly selected according to different application requirements. This enables precise control of the device's threshold voltage, leakage current, and interface contact performance, improving the device's conductivity uniformity and long-term reliability. At the same time, the compatibility of different metals enhances process compatibility and adaptability, providing effective support for realizing high-performance, low-power, and scalable micro-nano electronic devices.

[0017] Optionally, the barrier layer is a high dielectric constant dielectric HfO2 with a thickness of 15 nanometers.

[0018] By adopting the above technical solution, HfO2 with a high dielectric constant is used as a barrier layer with a thickness of 15 nanometers. While maintaining a high gate capacitance coupling efficiency, leakage current is effectively suppressed, and the breakdown voltage and insulation reliability of the device are improved. Its excellent thermal stability and interface quality help to reduce the trapped state density, improve carrier mobility and threshold voltage stability, thereby realizing a high-performance, low-power and long-life microelectronic device structure.

[0019] Optionally, the floating gate layer is composed of Pt nanocrystalline particles. The diameter of the nanocrystalline particles is 3-5 nanometers, and the spacing between the particles is 3-5 nanometers.

[0020] By adopting the above technical solution, Pt nanocrystals with a diameter of 3–5 nanometers and a spacing of 3–5 nanometers are used as floating gate layers, significantly improving charge storage density and charge trapping stability, and enhancing data retention capability; the nanoscale particle distribution effectively reduces inter-charge coupling interference and improves write and erase speed; at the same time, the high work function of metallic Pt helps to form a stable barrier structure, suppressing charge leakage, and achieving high reliability, high speed and low power consumption non-volatile storage characteristics.

[0021] Optionally, the tunneling layer is BN with a thickness of 10-12 nanometers.

[0022] By adopting the above technical solution, using BN with a thickness of 10–12 nanometers as a tunneling layer, the reverse charge leakage is effectively prevented while ensuring electron tunneling efficiency, thus improving data retention characteristics. BN material has high dielectric strength and smooth interface characteristics, which can reduce trap state density, improve tunneling uniformity, and has excellent chemical and thermal stability, thus achieving stable programming and erasing performance and long-term data retention.

[0023] Optionally, the two-dimensional channel layer material is selected from MoS2, WSe2, InSe, and WS2 two-dimensional semiconductor materials.

[0024] By adopting the above technical solutions, using two-dimensional semiconductor materials such as MoS2, WSe2, InSe or WS2 as the channel layer, excellent carrier mobility and gate control capability are achieved, subthreshold swing is reduced and device on / off ratio is improved; the atomically flat interface and dangling bond-free characteristics of two-dimensional materials effectively reduce interface scattering and trapped states, improve channel conductivity and device stability, and help realize ultra-thin channel design, thereby improving the scalability and integration of flash memory devices.

[0025] Optionally, the source and drain materials are selected from N metals selected from Cr, Ti, Sb, Au, Pt, and Pd, with a thickness of 40-60 nanometers.

[0026] By adopting the above technical solution, using metals such as Cr, Ti, Sb, Au, Pt, and Pd as source and drain electrodes, and controlling the thickness within the range of 40-60 nanometers, good ohmic contact with the two-dimensional channel layer is achieved, reducing contact resistance, improving carrier injection efficiency, and enhancing device switching performance and current drive capability. Optimizing the metal thickness can ensure structural stability and reliability, support high reprogramming operations, and help maintain the long-term data retention capability and durability of flash memory devices.

[0027] Secondly, the fabrication method of nanocrystalline flash memory devices based on two-dimensional materials involves reducing the tunneling barrier by forming a clean interface through van der Waals stacking, thereby achieving ultra-fast programming / writing characteristics of the flash memory device; and forming metal nanocrystalline particles through rapid thermal annealing, where the nanocrystalline particles are insulated from each other, reducing charge leakage and increasing data retention capability. The specific steps are as follows: Step 1: Clean the Si / SiO2 substrate with acetone, isopropanol, and deionized water; Step 2: Define the gate pattern and position of the flash memory device on the Si / SiO2 substrate using photolithography, including but not limited to ultraviolet lithography, electron beam lithography, and laser direct writing. After growing the gate metal material, perform a lift-off process to obtain the patterned gate bottom electrode. Techniques for growing the metal material include but are not limited to electron beam evaporation, physical vapor deposition, and thermal evaporation. Step 3: Grow the barrier layer dielectric of the flash memory device using techniques such as atomic layer deposition; Step 4: Use O2 atmosphere for thermal annealing to passivate oxygen vacancy defects inside the dielectric. The thermal annealing temperature is 200°C and the annealing time is 1 hour. Step 5: Define the floating gate region using electron beam lithography, grow a 0.5 nm thick layer of Pt metal using electron beam evaporation, and obtain a patterned metal floating gate layer using a lift-off process. Then, convert it into metal nanocrystal particles through rapid thermal annealing (400°C, 20 seconds). Step 6: The tunneling layer medium BN is transferred to the floating gate region using a dry transfer method. After the transfer is completed, an inert gas atmosphere thermal annealing treatment is performed. The inert gas atmosphere includes nitrogen, argon, etc. The annealing temperature is 200°C and the annealing time is 2.5h. Step 7: The two-dimensional channel material is transferred to the tunneling layer medium using a polystyrene (PS) assisted transfer method. The PS protective layer is removed in toluene solution, followed by inert gas atmosphere thermal annealing. The specific annealing conditions are the same as in Step 6. Step 8: Define the trench region using techniques such as photolithography and etching; Step 9: Define the source and drain regions using electron beam lithography, grow the source and drain metals using electron beam evaporation, and obtain the patterned source and drain through a lift-off process.

[0028] By employing the above technical solution, a clean surface can be obtained by performing multi-step cleaning (acetone, isopropanol, deionized water) on the Si / SiO2 substrate, ensuring a high-quality interface for subsequent thin film deposition and two-dimensional material transfer. This reduces the impact of interface defects on device performance, minimizes tunneling barrier fluctuations, and improves programming / writing stability. Photolithography is used to define the gate pattern and deposit metal materials, forming a precisely patterned gate bottom electrode that achieves complete coverage and high coupling with the floating gate layer. This improves the device's gate-control coupling ratio, increases write speed, and enhances operational accuracy. Atomic layer deposition forms a high-dielectric-constant barrier layer, which, combined with O2 atmosphere thermal annealing, passivates internal oxygen vacancy defects, reducing charge leakage and improving the floating gate's charge retention capability, thus enhancing the device's data retention performance. The floating gate layer uses a 0.5 nm metal thin film, rapidly thermally annealed to form discrete nanocrystalline particles. These particles are insulated from each other, effectively isolating stored charges and preventing global charge leakage caused by a single defect, improving non-volatility and durability. The tunneling layer (BN) is transferred dry and placed in an inert gas atmosphere. Down-annealing forms a high-quality thin film, reducing the tunneling barrier and enabling ultra-fast programming speeds. Simultaneously, it ensures stable charge storage within the floating gate layer. Two-dimensional channel materials are transferred using PS-assisted methods to form a clean van der Waals interface. Combined with annealing, this ensures high-quality contact between the channel material and the tunneling layer, improving carrier mobility and switching performance. Photolithography and etching define the channel region, and source and drain metals are deposited at both ends of the channel to achieve low contact resistance and high carrier injection efficiency, ensuring high-speed switching and stable output. The entire fabrication process, through rapid thermal annealing, dry transfer, and multi-step annealing, effectively controls nanocrystal size, spacing, and film thickness, optimizing the microscopic parameters of the device structure and achieving high-precision device engineering control. The fabrication method, through interface optimization, nanocrystal control, high-quality two-dimensional material transfer, and precise source-drain construction, achieves ultra-fast programming / writing characteristics, excellent data retention, high reliability, and long-term durability of flash memory devices, providing a solid technical foundation for the high-performance applications of next-generation non-volatile memories.

[0029] Optionally, the diameter of the Pt nanocrystals is 3-5 nanometers and the interparticle spacing is 3-5 nanometers. The thickness of the BN tunneling layer is 10-12 nanometers; The source and drain electrodes are made of Cr, Ti, Sb, Au, Pt, Pd, or any combination thereof, and have a thickness of 40-60 nanometers.

[0030] By adopting the above technical solutions, the strict control of the diameter and spacing of Pt nanocrystal particles ensures that the charge of the floating gate layer is discrete and uniformly distributed, reducing charge leakage and improving data retention capability; the thickness of the BN tunneling layer is controlled at 10-12 nanometers, providing a reliable barrier while ensuring sufficient tunneling efficiency, and achieving ultra-fast programming speed; the selection of source and drain metals and their thickness ensures low contact resistance and high carrier injection efficiency, improving device switching speed, stability and overall performance.

[0031] In summary, this application includes at least one of the following beneficial technical effects: 1. By constructing a multilayer functional stacked structure on the surface of an insulating substrate, the floating gate layer, barrier layer, tunneling layer and two-dimensional channel layer are organically combined, enhancing the gate's ability to regulate the floating gate charge, thereby achieving fast programming and erasing, reducing device operating voltage and power consumption, and improving device speed and efficiency. 2. By using metal nanocrystal particles as floating gate layers, a discrete charge storage structure is formed. The particles are isolated by an insulating medium, which reduces charge leakage caused by local defects, improves data retention capability and device reliability, and enhances programming efficiency and write / erase stability. 3. By using high dielectric constant barrier layer and high quality tunneling layer materials (such as HfO2 and BN), the gate control coupling ratio is improved, the leakage current is reduced, the interface stability is optimized, the breakdown voltage and long-term device reliability are improved, and a high-performance, low-power and long-life memory structure is achieved. 4. By selecting two-dimensional semiconductor materials such as MoS2, WSe2, WS2 or InSe as the channel layer, their atomically flat interface and dangling bond-free characteristics can be utilized to reduce interface traps and carrier scattering, thereby improving channel mobility, gate control capability and on / off ratio, and enhancing device stability and scalability. 5. Precisely control the source and drain materials and thickness to achieve low contact resistance and high carrier injection efficiency, ensuring the device's high-speed switching capability and current drive capability, and improving the overall performance and reprogramming durability of flash memory devices; 6. By optimizing the interface in multiple steps, controlling the size and spacing of nanocrystalline particles, transferring two-dimensional materials with high quality, and constructing source and drain electrodes precisely, the device microstructure is comprehensively optimized to achieve ultra-fast programming / writing characteristics, excellent data retention capabilities, high reliability, and long-term durability, providing technical support for the application of next-generation high-performance non-volatile memory. Attached Figure Description

[0032] Figure 1 This is a top view of a nanocrystalline flash memory device based on two-dimensional materials and its preparation method, as described in the embodiments of this application.

[0033] Figure 2This is a bottom view of a nanocrystalline flash memory device based on two-dimensional materials and its preparation method, according to an embodiment of this application.

[0034] Figure 3 This is a flowchart illustrating the fabrication method of a nanocrystalline flash memory device based on two-dimensional materials according to embodiments of this application.

[0035] Figure 4 This application presents an embodiment of a nanocrystalline flash memory device based on two-dimensional materials and its fabrication method. The flat band voltage energy band diagram of the nanocrystalline flash memory device based on two-dimensional materials is shown.

[0036] Figure 5 This is a scanning electron microscope (SEM) characterization image of the nanocrystalline particles in the nanocrystalline particle flash memory device based on two-dimensional materials and its preparation method according to the embodiments of this application.

[0037] Explanation of reference numerals in the attached figures: 1. Insulating substrate; 2. Gate bottom electrode; 3. Barrier layer; 4. Floating gate layer; 5. Tunneling layer; 6. Two-dimensional channel layer; 7. Source; 8. Drain. Detailed Implementation

[0038] The following is in conjunction with the appendix Figure 1-5 This application will be described in further detail.

[0039] This application discloses a nanocrystalline flash memory device based on two-dimensional materials. (Refer to...) Figure 1-5 The device includes an insulating substrate 1, a gate bottom electrode 2, a barrier layer 3, a floating gate layer 4, a tunneling layer 5, a two-dimensional channel layer 6, a source electrode 7, and a drain electrode 8. The gate bottom electrode 2 is located on the surface of the insulating substrate 1. The barrier layer 3 covers the gate bottom electrode 2 and the insulating substrate 1. The floating gate layer 4, composed of nanocrystalline particles, covers the barrier layer 3. The tunneling layer 5 covers the floating gate layer 4 and the barrier layer 3. The two-dimensional channel layer 6 covers the surface of the tunneling layer 5. The source electrode 7 and the drain electrode 8 are located on the two-dimensional channel layer 6. The gate bottom electrode 2 and the insulating substrate 1 form a stable potential substrate. The barrier layer uses a high dielectric constant medium and its thickness is reasonably controlled, which can improve the capacitive coupling ratio between the gate 7 and the floating gate layer 4, thereby enhancing the gate 7's ability to regulate the floating gate charge. This allows the flash memory device to achieve fast programming and erasing at lower voltages, improving operating speed and reducing power consumption.

[0040] For the barrier layer 3 and tunneling layer 5, by introducing a high dielectric constant medium and selecting the thickness, the gate-control coupling ratio of the flash memory device is increased, thereby improving the programming speed. Furthermore, by improving interface quality and passivating internal defects in the dielectric, charge leakage in the floating gate layer 4 is reduced, thus improving retention characteristics. The floating gate layer 4 is composed of discretely distributed metal nanocrystal particles, isolated between which by an insulating dielectric. The stored charge is spatially discrete; even if there are local defects in the tunneling layer, only individual nanocrystal units are affected, preventing overall charge loss and significantly improving data retention and device reliability. The gate bottom electrode 2 must completely encompass the floating gate layer 4. The source electrode 7 and drain electrode 8 are connected to the two-dimensional channel layer 6. The device channel region between source 7 and drain 8 is completely contained within the floating gate layer 4. A high-quality tunneling layer covers the floating gate layer 4, ensuring electron tunneling efficiency while effectively suppressing leakage current. Combined with the two-dimensional channel layer, a clean van der Waals interface is formed, which can reduce interface traps and carrier scattering, improve channel mobility and switching performance. The source 7 and drain 8 partially overlap with the two-dimensional channel layer, so that the channel is completely within the floating gate control range, achieving stronger gate control capability and a higher switching current ratio. Overall, through interface optimization, fine material selection and structural design, ultra-fast programming / erasing, high data retention capability, low power consumption and high reliability of flash memory devices are achieved.

[0041] The nanocrystalline flash memory device based on two-dimensional materials disclosed in this application includes an insulating substrate 1, a gate bottom electrode 2, a barrier layer 3, a floating gate layer 4, a tunneling layer 5, a two-dimensional channel layer 6, a source electrode 7, and a drain electrode 8. The insulating substrate 1 provides mechanical support and electrical isolation for the device. Preferably, a silicon wafer (Si) is used as the substrate, and SiO2 is grown on its surface by dry or wet thermal oxidation, with a thickness of 100–300 nm. The thermally oxidized SiO2 layer not only provides excellent electrical insulation properties but also has a smooth surface, which is beneficial for subsequent thin film deposition and patterning. The choice of substrate has a significant impact on the device's heat dissipation performance, capacitive coupling, and mechanical stability, while also ensuring compatibility with traditional CMOS processes. The gate bottom electrode 2, located on the surface of the insulating substrate, is fundamental for floating gate control and device threshold modulation. Material selection includes one or more of Cr, Ti, Sb, Au, and Pt, with a thickness controlled between 30 and 60 nm. Through metal selection and combination, work function matching, interface contact resistance, threshold voltage, and device conductivity uniformity can be adjusted. Simultaneously, the gate bottom electrode must completely cover the floating gate layer 4 to ensure that the floating gate layer is uniformly modulated by the gate electric field during programming and erasing, achieving high-efficiency electron injection and trapping. Barrier layer 3 covers the gate bottom electrode and the substrate surface, serving to isolate the floating gate layer and provide a high-dielectric-constant dielectric. The preferred material is HfO2, with a thickness of approximately 15 nm. The introduction of a high-dielectric-constant material allows for maintaining a thicker physical layer while preserving a high gate-to-control coupling ratio, thereby reducing leakage current and improving data retention. The quality of the barrier layer and the interface state density directly affect the charge storage efficiency of the floating gate layer; therefore, the deposition conditions, atmosphere, and annealing temperature must be strictly controlled during fabrication to reduce interface defects and internal traps.

[0042] The floating gate layer is composed of Pt nanocrystals with a diameter controlled at 3–5 nm and a spacing of 3–5 nm, enabling discrete storage. This discrete design allows each nanocrystal to store charge independently, while adjacent nanocrystals are isolated by an insulating medium, effectively suppressing lateral charge diffusion and the risk of collective leakage, significantly improving data retention. The high work function of the Pt nanocrystals enhances the potential modulation of the two-dimensional channel layer by the floating gate, improving programming / erasing efficiency. The uniformity of the floating gate layer distribution and the consistency of particle size have a significant impact on device performance stability and repeatability; therefore, precise control of the heat treatment temperature and time is required during fabrication to ensure uniform distribution and stable fixation of the nanocrystals on the barrier layer surface. The tunneling layer 5 covers the floating gate layer and the barrier layer, preferably made of boron nanotubes (BN), with a thickness of approximately 10–12 nm. The tunneling layer not only enables the injection and trapping of electrons from the two-dimensional channel layer to the floating gate layer, but also prevents reverse charge leakage from the floating gate layer, ensuring data retention performance. BN possesses high dielectric strength, chemical stability, and surface smoothness, which helps to form a low-defect, uniform tunneling barrier. The tunneling layer can be fabricated using atomic layer deposition (ALD), chemical vapor deposition (CVD), or mechanical transfer methods to ensure the formation of a high-quality van der Waals interface on the surface of the floating gate layer. Two-dimensional channel layers are made of two-dimensional semiconductor materials such as MoS2, WSe2, InSe or WS2, and are covered on the surface of the tunneling layer. The thickness is about 1–5 layers (0.7–3.5 nm). The atomic-level thickness of the two-dimensional material, the dangling bond-free surface and the flat interface can reduce interface scattering, improve carrier mobility and channel current modulation capability. The channel region is defined by photolithography and dry etching and is completely within the control range of the floating gate layer, so that the gate electric field can cover the entire channel, achieving high on / off ratio and strong channel modulation capability. The source and drain electrodes are located above the two-dimensional channel layer, partially overlapping it. The materials are selected from any combination of Cr, Ti, Sb, Au, Pt, and Pd, with a thickness controlled between 40 and 60 nm. The metal source and drain electrodes form a good ohmic contact with the two-dimensional channel layer, reducing contact resistance and enhancing carrier injection efficiency, thereby improving device switching performance and programming / erasing speed. The overlapping structure ensures the channel is fully controlled by the floating gate electric field, further improving the on / off ratio and data modulation depth.

[0043] The device injects and extracts charge into the floating gate layer by applying voltage to the gate, thus completing the programming and erasing operations. The two-dimensional channel layer provides a high-mobility carrier channel. The nanocrystalline particles of the floating gate layer exchange charge with the channel layer through the tunneling layer. The barrier layer provides capacitive coupling and charge isolation. The discretized design of the floating gate layer reduces the probability of collective leakage. The optimized thickness of the tunneling layer and the barrier layer, along with the selection of a high-k dielectric, ensures fast programming while maintaining good retention performance.

[0044] The device fabrication method of this technical solution includes substrate treatment: cleaning the silicon wafer / SiO2 substrate, immersing it in acetone, isopropanol and deionized water in sequence for ultrasonic cleaning, each step for 5-10 minutes, to remove surface impurities, and then drying. The process includes: fabrication of the gate bottom electrode: photolithography to define the gate bottom electrode region, electron beam evaporation of metal (Cr / Ti / Sb / Au / Pt) with a thickness of 30–60 nm, and lift-off to obtain the patterned gate bottom electrode; Including barrier layer deposition and annealing: ALD deposition of HfO2 barrier layer with a thickness of about 15 nm, followed by thermal annealing at 200–400°C for 1 hour in an oxygen atmosphere to improve the quality of the medium and reduce the density of trapped states; The process includes the fabrication of the floating gate layer: photolithography defines the floating gate region, evaporation of a 0.5 nm Pt thin film, and rapid thermal annealing at 400°C for 20–30 seconds to allow the film to self-assemble into nanocrystalline particles with a diameter of 3–5 nm and a spacing of 3–5 nm, thereby achieving a discretized floating gate. This includes tunneling layer deposition: ALD or transfer method to deposit BN with a thickness of 10–12 nm, followed by thermal annealing to optimize interface quality and ensure a smooth tunneling layer with low defects; Including two-dimensional channel layer transfer and patterning: using polystyrene-assisted transfer method, MoS2 / WSe2 / InSe / WS2 is transferred to BN tunneling layer, and after removing the protective layer, thermal annealing is performed to optimize the interface. Photolithography and etching define the channel region. Source and drain fabrication: Photolithography defines the source and drain regions, electron beam evaporates metal to a thickness of 40–60 nm, and the source and drain structures are formed by peeling, ensuring ohmic contact; Includes packaging and testing: completing device packaging and using a semiconductor parameter analyzer to measure IV characteristics, programming / erasing speed, hold time, and cycle durability.

[0045] The performance optimization and control of this technical solution includes: in terms of programming speed, the thickness of the high-k blocking layer and tunneling layer is optimized, the gate control coupling ratio is increased, and fast programming can be achieved at low voltage, reducing the time from microseconds to nanoseconds. Regarding retention capabilities: the floating gate nanocrystal particles are discretized, so local leakage does not affect the overall storage; a high-quality BN tunneling layer reduces leakage; and a barrier layer and annealing passivation reduce interface traps, ensuring long-term data retention. In terms of power consumption reduction and reliability: the atomic-level thickness of the two-dimensional channel reduces the operating voltage, and the optimized source and drain thickness improves contact efficiency, thereby reducing power consumption and improving the reliability of device reprogramming. Regarding durability: the multi-layered structure has smooth interfaces and low defects, and can withstand 10... 4 -10 5 It features a single programming / erase cycle with minimal threshold voltage variation, making it suitable for high-repetition-rate scenarios.

[0046] The experimental verification and performance results of this technical solution, conducted through electrical testing, show the following results: 1. Programming time can be achieved at the 10–100 ns level; 2. Data retention time can be predicted to be over 10 years; 3. Gate leakage current is less than 10⁻⁻⁶. 12 A. Power consumption is significantly reduced; 4. Repeated programming / erase cycles reach 10. 4 The subsequent threshold voltage drift is less than 100 mV; 5. The switching ratio exceeds 10. 6 It has a subthreshold swing of approximately 70 mV / dec, demonstrating excellent performance.

[0047] Other optional implementations of this technical solution include, but are not limited to, the following: The barrier layer can be made of high-k dielectric materials such as Al2O3 or La2O3, and the thickness can be adjusted from 15–20 nm. The tunneling layer can be a single layer of AlN or MoS2, with an adjustable thickness of 5–15 nm. The floating gate nanocrystalline particle material can be replaced with Au, Pd or Sb to modulate the work function and storage characteristics; Two-dimensional channels can be stacked with heterogeneous structures, such as MoS2 / WSe2, to achieve high mobility and low power consumption operation; Interface treatment techniques, such as plasma cleaning or chemical passivation, can also be used to improve the interface quality between the tunneling layer and the two-dimensional material.

[0048] This application breaks through the bottleneck that traditional silicon-based flash memory cannot simultaneously possess ultra-fast programming speed and non-volatile characteristics, realizing a multi-bit memory device that combines ultra-fast erase and write characteristics, excellent retention characteristics, and high robustness. It solves the shortcoming of traditional memory in terms of operating speed due to the limitation of charge tunneling efficiency, and provides a new path for the development of high-speed and stable non-volatile memory technology.

[0049] This application has the following technical effects: 1. The memory has a large storage window, which can display multiple distinguishable states (>8) through changes in pulse amplitude. 2. By utilizing two-dimensional material band engineering and interface engineering, the tunneling barrier is reduced and the tunneling efficiency is improved, enabling the memory to achieve ultra-fast erasure and write speeds in the tens of nanoseconds.

[0050] 3. Thanks to the excellent interface properties and high-quality lattice structure of two-dimensional materials, the memory has a fast erase and write operation life of up to 20,000 times and has a ten-year non-volatile data retention characteristic.

[0051] Key technical points of this application: The greatest advantage of this application lies in that the memory exhibits excellent data retention characteristics and high robustness while possessing ultra-fast erase and write capabilities. The memory can perform erase and write operations with pulses of tens of nanoseconds in width, and its retention time at room temperature exceeds 10... 5 The memory achieved a lifespan of over 20,000 cycles with ultrafast pulse erase / write, demonstrating exceptional stability and robustness. The most critical technical protection points of this application are the metal nanocrystal floating gate layer and the high lattice quality BN tunneling layer. The stored charges in the discrete metal nanocrystals are isolated from each other by an insulating dielectric. The leakage of a single charge through the defects in the tunneling layer will not lead to the loss of all charges in the floating gate. Therefore, the metal nanocrystal floating gate memory has better data retention characteristics. BN has a low defect state density and has an atomically flat layered surface with no dangling bonds or charge traps. It can effectively suppress and shield the influence of defects in the tunneling layer on the stored charges of the floating gate.

[0052] The implementation principle of the nanocrystalline flash memory device based on two-dimensional materials and its fabrication method in this application is as follows: Based on the physical mechanism of nanoscale charge trapping and van der Waals heterostructure control, high-speed, low-power, and long-term non-volatile storage functions are achieved through high-quality interface construction, discrete design of metal nanocrystalline particles, and two-dimensional semiconductor channel control. Two-dimensional materials (such as MoS2, WSe2, InSe, WS2, etc.) are used as the channel layer to construct an atomically flat van der Waals interface without dangling bonds. This eliminates the dangling bonds and chemical reactions present in traditional three-dimensional semiconductor interfaces between the channel layer and the tunneling layer (BN), significantly reducing interface traps. The density of states and carrier scattering centers are improved to enhance the channel carrier mobility and signal response speed. Structurally, a discrete floating gate layer of metal nanocrystal particles is used as the charge storage unit. The discrete distribution of nanocrystal particles makes each nanocrystal an independent charge trapping center, forming a multi-point storage system. When electrons are injected through the tunneling layer, they are confined inside a single nanocrystal. The insulating medium between the particles prevents lateral charge migration, effectively preventing overall leakage failure caused by local defects in the tunneling layer. The localized storage mode improves data retention capability and significantly enhances the stability and robustness of stored information. Even if some nanocrystals lose charge, it will not affect the reliable reading of the overall storage state. The floating gate layer is prepared using a rapid thermal annealing method to fabricate Pt nanocrystalline particles with a particle diameter controlled at 3–5 nm and a particle spacing of approximately 3–5 nm. Pt has a high work function, which enhances the ability to control the channel layer potential, improves the storage window width and multi-level state resolution, and the rapid thermal annealing process causes the metal film to spontaneously rearrange under the action of surface energy to form spherical nanoparticles. The particles are uniform in size and densely distributed, which helps to stably capture and release charges, ensuring the consistency and reproducibility of device performance. The tunneling layer uses a 10–12 nm thick hexagonal boron nitride (BN) dielectric, whose unique layered structure and high dielectric strength make it an ideal tunneling medium. The high chemical inertness and extremely low defect density of the BN layer ensure a uniform and stable tunneling barrier, which can guarantee high-efficiency electron injection and effectively suppress charge reverse leakage. The van der Waals contact formed between BN and the two-dimensional channel layer eliminates the stress and dangling bond problems of traditional dielectric / semiconductor interfaces, making the electron tunneling process controllable and efficient. Precise control of the BN thickness ensures a balance of electric field distribution during programming and erasing, achieving a balance between high programming speed and excellent retention characteristics. The barrier layer, located between the bottom gate electrode and the floating gate layer, is made of high-dielectric-constant HfO2 dielectric material with a thickness of approximately 15 nm. The introduction of HfO2 significantly improves the gate-control coupling ratio, enabling the gate voltage to more efficiently control the floating gate layer potential and achieve rapid charge trapping at low voltages. Its high-k characteristics reduce electric field penetration while maintaining high capacitance, thereby reducing leakage current and enhancing the charge retention performance of the floating gate layer. After oxygen annealing, the internal oxygen vacancy defects of the barrier layer are passivated, significantly improving the dielectric quality and further suppressing the formation of leakage paths. In terms of programming and erasing mechanisms, flash memory devices form a vertical electric field by applying an external gate voltage, which allows electrons to be injected into Pt nanocrystal particles through the BN tunneling layer via Fowler-Nordheim tunneling or direct tunneling. When a reverse voltage is applied, the stored electrons are pulled back to the channel layer, realizing the erasure process. Due to the high-quality tunneling barrier of the BN layer and the high work function matching of the Pt nanocrystals, the electron injection and extraction processes have extremely high energy selectivity and directionality, making the programming / erasing process fast and controllable, effectively avoiding problems such as charge overshoot and residue in traditional floating gate devices. During the retention phase, charges are stably trapped within discrete Pt nanocrystals. The BN tunneling layer and HfO2 barrier layer form a dual barrier structure, effectively preventing electron leakage. The two-dimensional channel layer exhibits high carrier mobility and band flatness, ensuring the storage state (threshold voltage) remains stable under long-term operation, unaffected by interface trap drift. Electrical testing verifies that the device can operate at 10... 4 After one erase / write cycle, the threshold voltage drift remains stable with less than 100 mV, and the on / off ratio reaches 10. 6 above.

[0053] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A nanocrystalline flash memory device based on two-dimensional materials, characterized in that, It includes an insulating substrate (1), a gate bottom electrode (2), a barrier layer (3), a floating gate layer (4), a tunneling layer (5), a two-dimensional channel layer (6), a source electrode (7), and a drain electrode (8); The gate bottom electrode (2) is located on the surface of the insulating substrate (1), and the barrier layer (3) covers the gate bottom electrode (2) and the insulating substrate (1). The floating gate layer (4) composed of nanocrystalline particles covers the top of the barrier layer (3), the tunneling layer (5) covers the floating gate layer (4) and the barrier layer (3), the two-dimensional channel layer (6) covers the surface of the tunneling layer (5), and the source (7) and drain (8) are located on the top of the two-dimensional channel layer (6). For the barrier layer (3) and tunneling layer (5), by introducing a high dielectric constant medium and selecting the thickness, the gate control coupling ratio of the flash memory device is increased, thereby improving the programming speed, and by improving the interface quality and passivating internal defects of the medium, the charge leakage of the floating gate layer (4) is reduced, thereby improving the retention characteristics. The gate bottom electrode (2) must completely contain the floating gate layer (4); the source (7) and drain (8) partially overlap with the two-dimensional channel layer (6); the device channel region between the source (7) and drain (8) is completely contained within the floating gate layer (4).

2. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that: The insulating substrate (1) is usually a rigid substrate such as a silicon wafer, with a 100nm or 300nm thermally oxidized SiO2 layer grown on the surface of the silicon wafer.

3. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that, The gate bottom electrode (2) is made of one or more of the following metals: Cr, Ti, Sb, Au, and Pt.

4. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that, The barrier layer (3) is a high dielectric constant dielectric HfO2 with a thickness of 15 nanometers.

5. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that, The floating gate layer (4) is composed of nanocrystalline Pt particles. The diameter of the nanocrystalline particles is 3-5 nanometers, and the spacing between the particles is 3-5 nanometers.

6. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that, The tunneling layer (5) is BN with a thickness of 10-12 nanometers.

7. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that, The material of the two-dimensional channel layer (6) is selected from two-dimensional semiconductor materials such as MoS2, WSe2, InSe, and WS2.

8. The nanocrystalline flash memory device based on two-dimensional materials according to claim 1, characterized in that, The source electrode (7) and drain electrode (8) are selected from N metals among Cr, Ti, Sb, Au, Pt and Pd, and have a thickness of 40-60 nanometers.

9. A method for fabricating a nanocrystalline flash memory device based on two-dimensional materials, characterized in that: By creating a clean interface through van der Waals stacking to reduce the tunneling barrier, ultra-fast programming / writing characteristics of flash memory devices are achieved. Rapid thermal annealing forms metal nanocrystals that are insulated from each other, reducing charge leakage and increasing data retention. The specific steps are as follows: Step 1: Clean the Si / SiO2 substrate with acetone, isopropanol, and deionized water; Step 2: Define the gate pattern and position of the flash memory device on the Si / SiO2 substrate using photolithography. Photolithography includes, but is not limited to, ultraviolet lithography, electron beam lithography, and laser direct writing. After growing the gate metal material, perform a lift-off process to obtain the patterned gate bottom electrode. The techniques for growing the metal material include, but are not limited to, electron beam evaporation, physical vapor deposition, and thermal evaporation. Step 3: Grow the barrier layer dielectric of the flash memory device using techniques such as atomic layer deposition; Step 4: Use O2 atmosphere for thermal annealing to passivate oxygen vacancy defects inside the dielectric. The thermal annealing temperature is 200°C and the annealing time is 1 hour. Step 5: Define the floating gate region using electron beam lithography, grow a 0.5 nm thick metal Pt using electron beam evaporation, obtain a patterned metal floating gate layer using a lift-off process, and then convert it into metal nanocrystal particles through rapid thermal annealing (400°C, 20 seconds). Step 6: The tunneling layer medium BN is transferred to the floating gate region using a dry transfer method. After the transfer is completed, an inert gas atmosphere thermal annealing treatment is performed. The inert gas atmosphere includes nitrogen, argon, etc. The annealing temperature is 200°C and the annealing time is 2.5h. Step 7: The two-dimensional channel material is transferred to the tunneling layer medium using a polystyrene (PS) assisted transfer method. The PS protective layer is removed in toluene solution, followed by inert gas atmosphere thermal annealing. The specific annealing conditions are the same as in Step 6. Step 8: Define the trench region using techniques such as photolithography and etching; Step 9: Define the source (7) and drain (8) regions by electron beam lithography, grow the source (7) and drain (8) metals by electron beam evaporation, and obtain the patterned source (7) and drain (8) by lift-off process.

10. The method for fabricating a nanocrystalline flash memory device based on two-dimensional materials according to claim 9, characterized in that: The Pt nanocrystals have a diameter of 3-5 nanometers and a spacing of 3-5 nanometers. The thickness of the BN tunneling layer is 10-12 nanometers; The source and drain electrodes are made of Cr, Ti, Sb, Au, Pt, Pd, or any combination thereof, and have a thickness of 40-60 nanometers.

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