Phase change memory and forming method thereof

Abstract

The invention provides a phase change memory and a forming method thereof. The forming method comprises the following steps: providing a wiring layer; the wiring layer at least comprises a top metal layer extending along a first direction; the first direction is perpendicular to a second direction, and the second direction is the thickness direction of the wiring layer; forming a contact structure extending along the second direction on the wiring layer; one end of the contact structure is connected with the top metal layer; the size of the contact structure in the first direction is gradually increased from bottom to top; forming a phase change memory cell array on the wiring layer; and the contact structure is connected with the phase change memory cell array.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a phase-change memory and a method for forming the same. Background Technology

[0002] Phase-change memory (PCM), as an emerging non-volatile storage device, has significant advantages over flash memory in many aspects, such as read / write speed, read / write cycles, data retention time, cell area, and multi-value implementation.

[0003] However, there are still many problems in the formation process of phase change memory, and there is considerable room for optimization. Summary of the Invention

[0004] In view of this, the present disclosure provides a phase-change memory and a method for forming the same to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide a method for forming a phase-change memory, the method comprising:

[0007] In one optional implementation, the forming method includes:

[0008] A wiring layer is provided; the wiring layer includes at least a top metal layer extending along a first direction; the first direction is perpendicular to a second direction, the second direction being the thickness direction of the wiring layer;

[0009] A contact structure extending along the second direction is formed on the wiring layer; one end of the contact structure is connected to the top metal layer; the size of the contact structure increases from bottom to top in the first direction.

[0010] A phase-change memory cell array is formed on the wiring layer; the contact structure is connected to the phase-change memory cell array.

[0011] In one optional embodiment, forming a contact structure extending along the second direction on the wiring layer includes:

[0012] A dielectric layer is formed on the wiring layer;

[0013] The dielectric layer is etched along the second direction to form a via that penetrates the dielectric layer along the second direction and exposes a portion of the top surface of the top metal layer;

[0014] The contact structure is formed in the through hole.

[0015] In one alternative embodiment, forming the contact structure in the through hole includes:

[0016] A conductive layer is formed; the conductive layer fills the via and covers the dielectric layer;

[0017] The conductive layer covering the dielectric layer is removed by a chemical mechanical polishing process, and the top surface of the remaining conductive layer is flush with the top surface of the dielectric layer to form the contact structure.

[0018] In one alternative implementation, the material of the top metal layer is different from the material of the contact structure.

[0019] In one optional implementation, forming a phase-change memory cell array on the wiring layer includes:

[0020] At least one phase-change memory cell array block is formed on the wiring layer and stacked along the second direction; each phase-change memory cell array block includes a first conductive line, a phase-change memory cell, and a second conductive line; the phase-change memory cell is located between the first conductive line and the second conductive line in the second direction; the phase-change memory cell extends along the second direction; the other end of the contact structure is connected to one of the first conductive line and the second conductive line of the phase-change memory cell array block closest to the contact structure.

[0021] Secondly, embodiments of this disclosure provide a phase-change memory, comprising:

[0022] A wiring layer; the wiring layer includes at least a top metal layer extending along a first direction; the first direction is perpendicular to a second direction, the second direction being the thickness direction of the wiring layer;

[0023] A contact structure located on the wiring layer; the contact structure extends along the second direction; one end of the contact structure is connected to the top metal layer; the size of the contact structure in the first direction increases from bottom to top;

[0024] A phase-change memory cell array located on the wiring layer; the contact structure is connected to the phase-change memory cell array.

[0025] In one alternative implementation, it further includes:

[0026] A dielectric layer located on the wiring layer; the contact structure penetrates the dielectric layer along the second direction; the top surface of the contact structure is flush with the top surface of the dielectric layer.

[0027] In one optional implementation, the phase-change memory cell array includes:

[0028] At least one phase change memory cell array block is stacked along the second direction; each phase change memory cell array block includes a first conductive line, a phase change memory cell, and a second conductive line; the phase change memory cell is located between the first conductive line and the second conductive line in the second direction; the phase change memory cell extends along the second direction; the other end of the contact structure is connected to one of the first conductive line and the second conductive line of the phase change memory cell array block closest to the contact structure.

[0029] In one alternative embodiment, the size of the contact structure in the first direction ranges from 20 nanometers to 25 nanometers.

[0030] In one alternative embodiment, the size of the contact structure in the second direction ranges from 60 nanometers to 80 nanometers.

[0031] The present disclosure provides a phase-change memory (PCM) and a method for forming the same. In the PCM formation method, only one contact structure is formed as the contact structure connecting to the top metal layer in the wiring layer. The radial dimension of the contact structure gradually increases from bottom to top, thereby reducing the potential difference between the top of the contact structure and the top metal layer and suppressing electrochemical corrosion caused by chemical mechanical polishing (CMP) on the top of the contact structure. Furthermore, a tighter and more stable contact interface can be formed between the contact structure and the conductive lines in the PCM cell array, thereby reducing the contact resistance between the contact structure and the conductive lines and improving the reliability of the PCM. Attached Figure Description

[0032] Figure 1 A partial planar schematic diagram of a phase-change memory provided in an embodiment of this disclosure;

[0033] Figure 2 A partial three-dimensional schematic diagram of a phase-change memory provided in an embodiment of this disclosure;

[0034] Figure 3 A schematic diagram of the contact structure in a phase-change memory is provided for some specific examples;

[0035] Figure 4 Transmission electron microscope images of contact structures provided for some specific examples;

[0036] Figure 5 A schematic flowchart illustrating a method for forming a phase-change memory provided in an embodiment of this disclosure;

[0037] Figure 6 A schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. Figure 1 ;

[0038] Figure 7 A schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. Figure 2 ;

[0039] Figure 8 A schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. Figure 3 ;

[0040] Figure 9 A schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. Figure 4 ;

[0041] Figure 10 A schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. Figure 5 ;

[0042] Figure 11 A schematic diagram of the formation process of the phase-change memory provided in the embodiments of this disclosure. Figure 6 ;

[0043] Figure 12 Test results of electromigration testing of the contact structure provided in the embodiments of this disclosure Figure 1 ;

[0044] Figure 13 Test results of electromigration testing of the contact structure provided in the embodiments of this disclosure Figure 2 ;

[0045] Figure 14 This is a schematic diagram of the structure of a phase-change memory provided in an embodiment of this disclosure. Detailed Implementation

[0046] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0048] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0049] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] Figure 1 Partial planar schematic diagrams of phase-change memory provided for some examples. Figure 2 Partial 3D schematic diagrams of phase-change memory provided for some examples. (Refer to reference...) Figure 1 and Figure 2A phase-change memory (PCM) includes at least one array of memory cells stacked along the Z-direction. Here, an example is taken where the PCM includes two arrays of memory cells stacked along the Z-direction. Each array includes a first conductive line, a second conductive line, and a PCM located between the first and second conductive lines in the Z-direction. For example, the first array includes a first conductive line 110, a second conductive line 120, and a PCM 100 located between the first and second conductive lines 110 and 120. The PCM 100 includes a first electrode 101, a gating element 102, a second electrode 103, a PCM 104, and a third electrode 105 stacked along the Z-direction. The second array includes a first conductive line 210, a second conductive line 220, and a PCM 200 located between the first and second conductive lines 210 and 220. The PCM 200 includes a first electrode 201, a gating element 202, a second electrode 203, a PCM 204, and a third electrode 205 stacked along the Z-direction.

[0052] It should be noted that, in Figure 1 and Figure 2 In the example shown, the stacking order of the first electrode, gating element, second electrode, phase change storage element and third electrode in the first phase change storage unit 100 and the second phase change storage unit 200 is only an example. In other embodiments, the positions of gating element 102 and phase change storage element 104 can be interchanged, and the positions of gating element 202 and phase change storage element 204 can also be interchanged.

[0053] Taking the first memory cell array block as an example, the first electrode 101 is formed on the second conductive line 120 and contacts the gating element 102. The first electrode 101 serves as a current path and may be formed of a conductive material. In some embodiments, the first electrode 101 may include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof.

[0054] A gating element 102 is formed between the first electrode 101 and the second electrode 103, and the resistance of the gating element 102 can vary in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may comprise a material having an Ovonic Threshold Switch (OTS) property, which may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn. x Te y 、Ge x Te y 、Nb x O y Si x Asy Te z When the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 can be in a high-resistance state that prevents current from flowing through, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 can be in a low-resistance state that allows current to flow through.

[0055] A second electrode 103 is formed between the gating element 102 and the phase change storage element 104. The second electrode 103 may include a thermally and electrically insulating material, thereby reducing temperature interference and electrical signal interference from the gating element 102 and the phase change storage element 104. In some specific examples, the second electrode 103 may include amorphous carbon.

[0056] A phase change memory element 104 is formed between a second electrode 103 and a third electrode 105. The phase change memory element 104 can reversibly switch between a crystalline and amorphous state, and data storage can be achieved by utilizing the difference in resistivity between its crystalline and amorphous states. Specifically, the crystalline phase of the phase change memory element 104 can be changed by the Joule heating generated by the voltage applied between the second electrode 103 and the third electrode 105, thereby changing the resistance of the phase change memory element 104 and thus changing the data stored in the phase change memory cell 100. In some embodiments, the phase change memory element 104 may include a chalcogenide component, such as at least one of binary compounds like GaSb, InSb, InSe, SbTe, and GeTe; ternary compounds like GeSbTe, GaSeTe, InSbTe, SnSbTe, and InSbGe; and quaternary compounds like AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and TeGeSbS.

[0057] A third electrode 105 is formed on the phase change storage element 104. In some embodiments, the material of the third electrode 105 may be similar to the material of the first electrode 101 or the second electrode 103. In some embodiments, the material of the third electrode 105 may be similar to the material of the second electrode 103.

[0058] The two ends of the phase-change memory cell 100 are connected to a first conductive line 110 and a second conductive line 120, respectively. A third electrode 105 is connected to the first conductive line 110. The first conductive line 110 can be either a word line (WL) or a bit line (BL). The first electrode 101 is connected to the second conductive line 120, which can be either a word line or a bit line. A memory array cell block can include multiple first conductive lines 110 and multiple second conductive lines 120. The extension directions of the first conductive lines 110 and the second conductive lines 120 can intersect and are both perpendicular to the extension direction of the phase-change memory cell 100. The first conductive lines 110 and the second conductive lines 120 can include at least one conductive material selected from tungsten, cobalt, copper, aluminum, or polycrystalline silicon.

[0059] In some embodiments, before forming the memory cell array block, it is necessary to first form a peripheral circuit, which includes a device layer and a wiring layer, and then form a phase change memory cell array on the wiring layer. This allows the peripheral circuit and the phase change memory cell array to be stacked in the vertical direction, which is beneficial to improving the integration of the phase change memory.

[0060] In some specific examples, such as Figure 3 As shown, the wiring layer 301 includes multiple metal layers, wherein the top surface of the top metal layer 302 is flush with the top surface of the wiring layer 301. A contact structure connecting to the top metal layer 302 is then formed on the wiring layer 301. To ensure a large contact area between the bottom of the contact structure and the top metal layer 302, the contact structure is formed in segments. Specifically, a dielectric layer can be formed first, and a via extending through the dielectric layer in the Z direction can be formed within the dielectric layer. The via is filled with conductive material to form the first contact structure 303. Then, another dielectric layer is formed, and a via extending through the dielectric layer in the Z direction and exposing the top surface of the first contact structure 303 is formed within the dielectric layer. The via is filled with conductive material to form the second contact structure 304.

[0061] In some embodiments, during the formation of the second contact structure 304, a chemical mechanical polishing (CMP) process is required to planarize the top of the contact structure so that the top surface of the second contact structure 304 is flush with the top surface of the dielectric layer. However, since the material of the top metal layer 302 is different from that of the contact structure, and the metal path between the top of the second contact structure 304 and the top metal layer 302 is relatively long, a large potential difference exists between the top of the second contact structure 304 and the top metal layer 302. In addition, during the CMP process, the polishing slurry used will create an oxidizing environment on the top of the second contact structure 304, and the polishing slurry itself can act as a conductive medium. These factors will cause the top of the second contact structure 304 to be electrochemically corroded during the CMP process.

[0062] Figure 4 The image shows a transmission electron microscope (TEM) image of the top surface of the second contact structure 304 after CMP treatment. As can be seen from the image, severe electrochemical corrosion occurs on the top of the second contact structure 304. The corroded part becomes loose and porous, and its conductivity decreases accordingly. Under these circumstances, when the conductive lines in the phase change memory cell array are formed on the second contact structure 304, it is difficult to form a tight contact interface between the second contact structure 304 and the conductive lines, resulting in a large contact resistance. This leads to increased power consumption in electrical signal transmission and may even cause an open circuit between the contact structure and the conductive lines, seriously affecting the yield of the phase change memory.

[0063] Therefore, optimizing the formation process of contact structures in phase-change memory has become an urgent problem to be solved. In response, this disclosure proposes the following implementation methods.

[0064] This disclosure provides a method for forming a phase-change memory. Figure 5 The following is a flowchart illustrating the method for forming a phase-change memory provided in this disclosure, as shown in the figure. Figure 5 As shown, the method for forming a phase-change memory includes:

[0065] Step S10: Provide a wiring layer; the wiring layer includes at least a top metal layer extending along a first direction; the first direction is perpendicular to a second direction, and the second direction is the thickness direction of the wiring layer;

[0066] Step S20: A contact structure extending along the second direction is formed on the wiring layer; one end of the contact structure is connected to the top metal layer; the size of the contact structure in the first direction increases from bottom to top;

[0067] Step S30: A phase change memory cell array is formed on the wiring layer; the contact structure is connected to the phase change memory cell array.

[0068] Figures 6 to 11 This is a schematic diagram of the structure of the phase-change memory formation process provided in the embodiments of this disclosure. Below, we will combine... Figures 5 to 11 The method for forming a phase-change memory provided in the embodiments of this disclosure will be described in detail.

[0069] In this embodiment of the disclosure, the first direction is perpendicular to the second direction, the first direction can be the X direction, and the second direction can be the Z direction.

[0070] In some embodiments, such as Figure 6 As shown, before performing step S10, the method for forming a phase-change memory further includes forming a device layer 401, which may include transistors 4011.

[0071] In some specific examples, device layer 401 may include peripheral circuitry for the phase-change memory, and transistor 4011 may be a driving transistor in the peripheral circuitry.

[0072] In some embodiments, the specific process of performing step S10 may include: forming a wiring layer 402 on the device layer 401, the wiring layer 402 including at least a top metal layer 403 extending along a first direction. In some specific examples, the wiring layer 402 may also include a plurality of metal layers arranged along the Z direction and conductive contact structures located between the metal layers.

[0073] In some embodiments, in conjunction with reference Figures 7 to 10 Step S20 is performed to form a contact structure 504 extending in the second direction on the wiring layer 402.

[0074] In some embodiments, refer to Figure 7 The specific process of performing step S20 may include: forming a dielectric layer 501 on the wiring layer 402.

[0075] In some specific examples, the dielectric layer 501 can be formed by a deposition process. The material of the dielectric layer 501 can be one or more of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0076] In the embodiments disclosed herein, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0077] In some embodiments, refer to Figure 8 The specific process of performing step S20 may include: etching the dielectric layer 501 along the second direction to form a through hole 502 that penetrates the dielectric layer 501 along the second direction and exposes a portion of the top surface of the top metal layer 403.

[0078] In some specific examples, a patterned mask layer can be formed on the dielectric layer 501 using photolithography. The patterned mask layer includes openings corresponding to the vias 502. Then, using the patterned mask layer as a mask, the dielectric layer 501 is etched using a dry etching process to form the vias 502. Here, the dry etching process includes, but is not limited to, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0079] In some embodiments, in conjunction with reference Figure 8 and Figure 9 The specific process of performing step S20 may include: forming a conductive layer 503 in the through hole 502 and on the dielectric layer 501, wherein the conductive layer 503 fills the through hole 502 and covers the dielectric layer 501.

[0080] In some specific examples, the material forming the conductive layer 503 can be at least one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), metallic material (e.g., tungsten, titanium, tantalum, aluminum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0081] In some embodiments, in conjunction with reference Figure 9 and Figure 10The specific process of performing step S20 may include: removing the conductive layer 503 covering the dielectric layer 501 by a chemical mechanical polishing process, with the top surface of the remaining conductive layer flush with the top surface of the dielectric layer 501 to form a contact structure 504, the size of the contact structure 504 increasing from bottom to top in the first direction. Here, the projection of the contact structure 504 along the Z direction onto the XY plane can be circular or elliptical, and the size of the contact structure 504 in the first direction can be the radial dimension of the projection of the contact structure 504 along the Z direction onto the XY plane.

[0082] In this embodiment, the material of the top metal layer 403 is different from the material of the contact structure 504. For example, the top metal layer 403 can be made of copper, and the contact structure 504 can be made of tungsten. The top metal layer 403 and the contact structure 504 are two equipotential bodies, and a potential difference exists between the top of the contact structure 504 and the top surface of the top metal layer 403. Since the contact structure 504 consists of only one segment, and the sidewall of the contact structure 504 extends upward in only one direction, the metal path between the top of the contact structure 504 and the top metal layer 403 is short, and the potential difference between the top of the contact structure 504 and the top metal layer 403 is small. Therefore, during the CMP process, the electrochemical corrosion of the top of the contact structure 504 can be suppressed, thereby improving the reliability of the contact structure 504. Furthermore, forming a contact structure 504 consisting of only one segment requires only one dielectric layer to be formed, and only one photolithography and etching process is required, which simplifies the process flow and improves the yield of the phase-change memory while reducing production costs.

[0083] In some specific examples, the dimensions of contact structure 504 in the first direction range from 20 nanometers to 25 nanometers. The dimensions of contact structure 504 in the second direction range from 60 nanometers to 80 nanometers. It should be noted that, relative to... Figure 3 The contact structure shown includes a first contact structure 303 and a second contact structure 304. The contact structure 504 has a smaller dimension in the second direction, and the top of the contact structure 504 has a larger dimension in the first direction than the second contact structure 304 in the first direction. This allows a larger contact area to still be formed between the bottom of the contact structure 504 and the top metal layer 403.

[0084] In some embodiments, refer to Figure 11 In step S30, a phase change memory cell array is formed on the wiring layer 402, and the contact structure 504 is connected to the phase change memory cell array.

[0085] In some embodiments, the specific process of performing step S30 may include: forming at least one phase-change memory cell array block stacked along a second direction on the wiring layer 402. Here, taking the formation of two phase-change memory cell array blocks stacked along the second direction as an example. Each phase-change memory cell array block includes a first conductive line, a phase-change memory cell, and a second conductive line. Taking the phase-change memory cell array block closest to the contact structure 504 as an example, the phase-change memory cell array block includes a first conductive line 110, a phase-change memory cell 100, and a second conductive line 120. The phase-change memory cell 100 is located between the first conductive line 110 and the second conductive line 120 in the second direction; the phase-change memory cell 100 extends along the second direction; the other end of the contact structure 504 is connected to the second conductive line 120 of the phase-change memory cell array block closest to the contact structure 504. The specific structures of the phase-change memory cell 100 and the phase-change memory cell 200 can be found in the foregoing embodiments. Figure 1 and Figure 2 The description will not be repeated here.

[0086] In some specific examples, the first conductive line 110 can be a word line, the second conductive line 120 can be a bit line, the contact structure 504 can be a bit line contact structure, and it is connected to the bottommost bit line and connects the bit line to the driving transistor 4011 in the device layer 401.

[0087] In this embodiment of the disclosure, by optimizing the formation process of the bit line contact structure, the electrochemical corrosion on the top of the bit line contact structure is suppressed. Therefore, a relatively tight contact interface can be formed between the bit line contact structure and the bit line, thereby reducing the contact resistance between the bit line contact structure and the bit line, reducing the power consumption generated during the transmission of electrical signals from the driving transistor to the bit line, and improving the reliability of the phase change memory.

[0088] Figure 12 For multiple Figure 3 The test results of electromigration testing on the structure shown are as follows. Figure 13 For multiple Figure 10 The test results of electromigration testing on the structure shown are as follows. Figure 12 As shown, for Figure 3 The structure shown exhibits severe electrochemical corrosion at the top of the second contact structure 304 during CMP, making it difficult to form a tight contact interface with other conductive structures formed on the second contact structure 304. The rate of change of interface resistance in most structures increases vertically within a short time, indicating an open circuit. For example... Figure 13 As shown, for most Figure 10The structure shown exhibits a resistance change rate remaining below 20.0% after 150 hours, indicating that a relatively stable contact interface can be formed between contact structure 504 and other conductive structures formed thereon. Furthermore, according to... Figure 13 The test results shown can be further extrapolated to indicate that the service life of the contact structure obtained by the forming method provided in this embodiment can reach 17 years. As can be seen from the above electromigration test results, a more stable contact interface can be formed between the contact structure obtained by the forming method provided in this embodiment and the conductive structure formed thereon, thereby effectively improving the reliability of the phase-change memory and extending its service life.

[0089] In some embodiments, such as Figure 14 As shown, a contact structure 505 can also be formed by a method similar to that used to form contact structure 504. One end of contact structure 505 is connected to another top metal layer 404 in wiring layer 402, and the other end of contact structure 505 is connected to the first conductive line 110 of the phase change memory cell array block closest to contact structure 504, so that the first conductive line 110 can be connected to the driving transistor 4012 in device layer 401. The size of contact structure 505 increases from bottom to top in the first direction.

[0090] In some specific examples, the first conductive line 110 is a word line, and the contact structure 505 is a word line contact structure. That is, the word line contact structure in the phase change memory can also be formed by the forming method provided in the embodiments of this disclosure, thereby suppressing the electrochemical corrosion on the top of the word line contact structure and further improving the reliability of the phase change memory.

[0091] Based on a concept similar to the method for forming the phase change memory described above, this disclosure also provides a phase change memory. Figure 11 and Figure 14 This is a schematic diagram of the structure of the phase-change memory provided in this disclosure. The phase-change memory includes: a wiring layer 402, which includes at least a top metal layer 403 extending along a first direction; the first direction is perpendicular to a second direction, which is the thickness direction of the wiring layer 402; a contact structure 504 located on the wiring layer 402; the contact structure 504 extends along the second direction; one end of the contact structure 504 is connected to the top metal layer 403; the size of the contact structure 504 increases from bottom to top in the first direction; a phase-change memory cell array located on the wiring layer 402; and the contact structure 504 is connected to the phase-change memory cell array.

[0092] In this embodiment of the disclosure, the first direction is perpendicular to the second direction, the first direction can be the X direction, and the second direction can be the Z direction.

[0093] In some embodiments, the phase-change memory further includes: a dielectric layer 501 located on the wiring layer 402; a contact structure 504 penetrating the dielectric layer 501 along a second direction; and the top surface of the contact structure 504 being flush with the top surface of the dielectric layer 501.

[0094] In some embodiments, the phase-change memory cell array includes: at least one phase-change memory cell array block stacked along a second direction; each phase-change memory cell array block includes a first conductive line, a phase-change memory cell, and a second conductive line; the phase-change memory cell is located between the first conductive line and the second conductive line in the second direction; the phase-change memory cell extends along the second direction; the other end of the contact structure 504 is connected to the second conductive line 120 of the phase-change memory cell array block closest to the contact structure. For the specific structures of the phase-change memory cell 100 and the phase-change memory cell 200, please refer to the foregoing embodiments. Figure 1 and Figure 2 The description will not be repeated here.

[0095] In some specific examples, the dimensions of contact structure 504 in the first direction range from 20 nanometers to 25 nanometers. The dimensions of contact structure 504 in the second direction range from 60 nanometers to 80 nanometers.

[0096] In some specific examples, the material of the top metal layer 403 is different from the material of the contact structure 504. For example, the material of the top metal layer 403 can be copper, while the material of the contact structure 504 can be tungsten.

[0097] In some embodiments, refer to Figure 14 The phase change memory also includes a contact structure 505, one end of which is connected to another top metal layer 404 in the wiring layer 402, and the other end of which is connected to the first conductive line 110 of the phase change memory cell array block closest to the contact structure 504. The size of the contact structure 505 increases from bottom to top in the first direction.

[0098] This disclosure provides a phase-change memory (PCM) and a method for forming the same. The PCM formation method involves first forming a wiring layer on a device layer, then forming a contact structure on the wiring layer, and finally forming a PCM cell array connected to the contact structure on the wiring layer. In this process, the contact structure connected to the top metal layer in the wiring layer is formed through only one etching process and a conductive material filling process. This shortens the metal path between the top of the contact structure and the top metal layer, reduces the potential difference between the top of the contact structure and the top metal layer, suppresses the electrochemical corrosion caused by the CMP process on the top of the contact structure, and creates a tighter and more stable contact interface between the contact structure and the conductive lines in the PCM cell array. This reduces the contact resistance between the contact structure and the conductive lines, decreases the power consumption generated during the transmission of electrical signals from the driving transistor to the conductive lines, and improves the reliability of the PCM.

[0099] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0100] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0101] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of forming a phase change memory, comprising: The forming method comprises: providing a wiring layer; the wiring layer at least comprises a top metal layer extending along a first direction; the first direction is perpendicular to a second direction, and the second direction is a thickness direction of the wiring layer; forming a contact structure extending along the second direction on the wiring layer; one end of the contact structure is connected with the top metal layer; a size of the contact structure in the first direction increases from bottom to top; forming a phase change memory cell array on the wiring layer; the contact structure is connected with the phase change memory cell array.

2. The method of claim 1, wherein The forming of the contact structure extending along the second direction on the wiring layer comprises: forming a dielectric layer on the wiring layer; etching the dielectric layer along the second direction to form a via hole penetrating through the dielectric layer along the second direction and exposing a part of a top surface of the top metal layer; forming the contact structure in the via hole.

3. The method of claim 2, wherein: The forming of the contact structure in the via hole comprises: forming a conductive layer; the conductive layer fills the via hole and covers the dielectric layer; removing the conductive layer covering the dielectric layer by a chemical mechanical polishing process; a top surface of the remaining conductive layer is flush with a top surface of the dielectric layer to form the contact structure.

4. The method of claim 1, wherein A material of the top metal layer is different from a material of the contact structure.

5. The method of claim 1, wherein The forming of the phase change memory cell array on the wiring layer comprises: forming at least one phase change memory cell array block arranged in a stack along the second direction on the wiring layer; each phase change memory cell array block comprises a first conductive line, a phase change memory cell and a second conductive line; the phase change memory cell is located between the first conductive line and the second conductive line in the second direction; the phase change memory cell extends along the second direction; the other end of the contact structure is connected with one of the first conductive line and the second conductive line of the phase change memory cell array block closest to the contact structure.

6. A phase change memory, characterized by, Comprise: a wiring layer; the wiring layer at least comprises a top metal layer extending along a first direction; the first direction is perpendicular to a second direction, and the second direction is a thickness direction of the wiring layer; a contact structure on the wiring layer; the contact structure extends along the second direction; one end of the contact structure is connected with the top metal layer; a size of the contact structure in the first direction increases from bottom to top; a phase change memory cell array on the wiring layer; the contact structure is connected with the phase change memory cell array.

7. The phase change memory of claim 6, wherein, Further comprise: a dielectric layer on the wiring layer; the contact structure penetrates through the dielectric layer along the second direction; a top surface of the contact structure is flush with a top surface of the dielectric layer.

8. The phase change memory of claim 6, wherein, The phase change memory cell array comprises: at least one array block of phase change memory cells arranged in a stack along the second direction; each of the array blocks of phase change memory cells includes a first conductive line, a phase change memory cell, and a second conductive line; the phase change memory cell is located between the first conductive line and the second conductive line in the second direction; the phase change memory cell extends along the second direction; the other end of the contact structure is connected to one of the first conductive line and the second conductive line of the array block of phase change memory cells closest to the contact structure.

9. The phase change memory of claim 6, wherein, A dimension of the contact structure in the first direction ranges from 20 nanometers to 25 nanometers.

10. The phase change memory of claim 6, wherein, A dimension of the contact structure in the second direction ranges from 60 nanometers to 80 nanometers.

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