Forming method of semiconductor device and semiconductor device

Abstract

The invention discloses a semiconductor device forming method and a semiconductor device.A storage unit layer and a mask layer located on the storage unit layer are formed on a substrate, the storage unit layer comprises a first electrode layer, the first electrode layer comprises a first electrode part and a second electrode part, and the second electrode part is located on the side, away from the substrate, of the first electrode part; the mask layer is located on the surface of the second electrode portion away from the substrate, and the roughness of the surface of the second electrode portion away from the substrate is smaller than that of the surface of the first electrode portion. And carrying out grinding treatment to remove the mask layer and at least part of the second electrode part. The roughness of the top surface of the second electrode part is reduced, so that the residual of the mask layer on the surface of the second electrode part is reduced, and the yield is improved. Due to the fact that the residual risk of the mask layer on the surface of the second electrode part is reduced, the thickness requirement for removing at least part of the second electrode part through grinding is reduced, the grinding time can be shortened, the groove depth caused by the grinding process can be reduced, and then the yield is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor device and a semiconductor device. Background Technology

[0002] The development of artificial intelligence and in-memory computing technologies has placed higher demands on data storage and computing capabilities. Current von Neumann computing architectures require extensive data reading and storage between Dynamic Random Access Memory (DRAM) and Solid State Drives (SSDs). A significant performance gap exists between these two, hindering performance improvements in the current von Neumann computing system. Storage Class Memory (SCM) has been proposed to bridge DRAM and SSDs to improve the current storage architecture. SCM needs to achieve speeds significantly faster than NAND and excellent non-volatility. Among the emerging SCM technologies, 3D Xpoint memory is the most promising, offering advantages such as large capacity, high speed, non-volatility, and good cycle performance. Recently, research on high-capacity non-volatile memory technologies to mitigate the weaknesses of 3D Xpoint memory has become active, such as Phase Change Memory (Phase Change Memory) and Selector Only Memory (SOM).

[0003] In the fabrication of phase-change memory and select-only memory, the silicon nitride mask layer is removed by polishing. However, silicon nitride tends to remain on the surface of the top electrode, leading to a decrease in device yield. Summary of the Invention

[0004] This application provides a method for forming a semiconductor device and a semiconductor device, which reduces the roughness of the top surface of the second electrode portion to reduce the residue of the mask layer on the surface of the first electrode layer and improve the yield of the device.

[0005] This application provides a method for forming a semiconductor device, comprising: providing a substrate, forming a memory cell layer and a mask layer on the substrate, the memory cell layer including a first electrode layer, the first electrode layer including a first electrode portion and a second electrode portion, the second electrode portion being located on the side of the first electrode portion away from the substrate, the mask layer being located on the surface of the second electrode portion away from the substrate, the roughness of the surface of the second electrode portion away from the substrate being less than the roughness of the surface of the first electrode portion; and performing a polishing process to remove the mask layer and at least a portion of the second electrode portion.

[0006] In some embodiments, the method of forming the memory cell layer and the mask layer includes: forming a memory stack on the substrate, the memory stack including a first initial electrode layer, the material of the first initial electrode layer including carbon; doping the first initial electrode layer with modified ions to form a second electrode portion and a first electrode portion, the second electrode portion being doped with the modified ions, the first electrode portion not being doped with the modified ions, or the concentration of the modified ions in the first electrode portion being less than the concentration of the modified ions in the second electrode portion; forming a mask layer on the second electrode portion, and using the mask layer as a mask, etching the memory stack to form the memory cell layer.

[0007] In some embodiments, the method of forming the first initial electrode layer and doping the first initial electrode layer with modified ions includes: forming a first initial electrode portion on the substrate; forming a second initial electrode portion on the first initial electrode portion, the first initial electrode portion and the second initial electrode portion forming the first initial electrode layer; and during the process of forming the second initial electrode portion, introducing a gas containing the modified ions, so that the second initial electrode portion and the first initial electrode portion respectively form the second electrode portion and the first electrode portion.

[0008] In some embodiments, the method of forming the first initial electrode layer and doping the first initial electrode layer with modified ions includes: forming a first initial electrode portion on the substrate; forming a second initial electrode portion on the first initial electrode portion, the first initial electrode portion and the second initial electrode portion forming the first initial electrode layer; and performing ion implantation on the second initial electrode portion using the modified ions, so that the second initial electrode portion and the first initial electrode portion respectively form the second electrode portion and the first electrode portion.

[0009] In some embodiments, the modified ion includes at least one of nitrogen, boron, phosphorus, sulfur, oxygen, fluorine, and transition metals.

[0010] In some embodiments, the polishing process includes polishing the mask layer and at least a portion of the second electrode portion using a chemical mechanical polishing process until the mask layer is completely removed; wherein, after the polishing process, the second electrode portion is completely removed or partially retained, and the roughness of the surface of the first electrode layer facing away from the substrate is reduced.

[0011] In some embodiments, the concentration of the modified ions in the second electrode portion is 5 at% to 15 at%, and the concentration of the modified ions in the first electrode portion is greater than or equal to 0 and less than 5 at%.

[0012] In some embodiments, it also includes: Before the polishing process, a dielectric layer is formed on both sides of the storage cell layer along a first direction. The dielectric layer includes a first dielectric block and a second dielectric block located on both sides of the storage cell layer, respectively. The first direction is perpendicular to the extension direction of the storage cell layer. The size of the first dielectric block along the first direction is larger than the size of the second dielectric block along the first direction. Before the polishing process, a contact structure is formed in the first dielectric block. During the polishing process, the first dielectric block and the second dielectric block are polished with grooves.

[0013] In some embodiments, the method further includes: forming a conductive layer on the first electrode layer, the first dielectric block, and the second dielectric block, the conductive layer being connected to the contact structure; etching the conductive layer and the memory cell layer to form multiple conductive lines and multiple memory cells, the conductive lines being located on the memory cells and the second dielectric block; forming a third dielectric block on the second dielectric block; and forming a through contact that penetrates the third dielectric block and the second dielectric block.

[0014] This application also provides a semiconductor device formed by the semiconductor device forming method in any of the above embodiments.

[0015] In the semiconductor device formation method of this application embodiment, a mask layer is located on the top surface of the second electrode portion. The roughness of the top surface of the second electrode portion is less than the roughness of the surface of the first electrode portion, that is, the roughness of the top surface of the second electrode portion is reduced, thereby reducing the residue of the mask layer on the surface of the second electrode portion and improving the yield. On the other hand, the mask layer and at least part of the second electrode portion are removed by a grinding process to ensure that the mask layer is completely removed. Since the risk of mask layer residue on the surface of the second electrode portion is reduced, the thickness requirement for removing at least part of the second electrode portion by grinding is reduced, that is, the thickness of the first electrode layer being ground is reduced. Therefore, the grinding time can be reduced, thereby reducing the groove depth caused by the grinding process and improving the yield.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 2 to 10 This is a cross-sectional structural diagram of a semiconductor device provided in some embodiments of this application during its formation process. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0020] During the fabrication of semiconductor devices, when the mask layer on top of the first electrode layer is removed by a polishing process, the polishing process stops at the surface of the first electrode layer. However, due to the large roughness of the top surface of the first electrode layer, the mask layer is easily embedded into the rough surface of the first electrode layer, resulting in silicon nitride residue and ultimately reducing the device yield.

[0021] In one embodiment, the polishing process can be used to continue polishing a portion of the first electrode layer to remove a first electrode layer of a specific thickness, thereby ensuring that the silicon nitride is completely removed. However, as the polishing time increases, the dishing caused by the polishing process becomes more severe due to the structural differences in different regions of the device.

[0022] Based on this, embodiments of this application provide a method for forming a semiconductor device. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor device according to some embodiments of this application. The method for forming the semiconductor device includes: Step S1: Provide a substrate; Step S2: A memory cell layer and a mask layer are formed on the substrate. The memory cell layer includes a first electrode layer, which includes a first electrode portion and a second electrode portion. The second electrode portion is located on the side of the first electrode portion away from the substrate. The mask layer is located on the surface of the second electrode portion away from the substrate. The roughness of the surface of the second electrode portion away from the substrate is less than the roughness of the surface of the first electrode portion. Step S3: Perform a grinding process to remove the mask layer and at least a portion of the second electrode portion.

[0023] In the semiconductor device formation method of this application embodiment, a mask layer is located on the top surface of the second electrode portion. The roughness of the top surface of the second electrode portion is less than the roughness of the surface of the first electrode portion, that is, the roughness of the top surface of the second electrode portion is reduced, thereby reducing the residue of the mask layer on the surface of the second electrode portion and improving the yield. On the other hand, the mask layer and at least part of the second electrode portion are removed by a grinding process to ensure that the mask layer is completely removed. Since the risk of mask layer residue on the surface of the second electrode portion is reduced, the thickness requirement for removing at least part of the second electrode portion by grinding is reduced, that is, the thickness of the first electrode layer being ground is reduced. Therefore, the grinding time can be reduced, thereby reducing the groove depth caused by the grinding process and improving the yield.

[0024] The method for forming a semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0025] Please see Figures 2 to 10 , Figures 2 to 10 This is a cross-sectional structural diagram of a semiconductor device provided in some embodiments of this application during its formation process.

[0026] Step S1: Provide a substrate. See [link / reference] Figure 2 .

[0027] The substrate 10 may include a substrate 11 and a control circuit layer 12, wherein the control circuit layer 12 may include a complementary metal oxide semiconductor (CMOS).

[0028] The substrate 11 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate can also be a substrate including semiconductors of other elements or compound semiconductors, and can also be a stacked structure, such as Si / SiGe.

[0029] Step S2: A memory cell layer 20 and a mask layer 30 are formed on the substrate 10. The memory cell layer 20 includes a first electrode layer 21, which includes a first electrode portion 211 and a second electrode portion 212. The second electrode portion 212 is located on the side of the first electrode portion 211 facing away from the substrate 10. The mask layer 30 is located on the surface 2120 of the second electrode portion 212 facing away from the substrate 10. The roughness of the surface 2120 of the second electrode portion 212 facing away from the substrate 10 is less than the roughness of the surface of the first electrode portion 211. See also Figures 2 to 4 .

[0030] It is understood that the surface 2120 of the second electrode portion 212 facing away from the substrate 10 is the top surface 2120. Since the mask layer 30 is located on the surface 2120 of the second electrode portion 212 facing away from the substrate 10, the first electrode layer 21 is the top electrode layer of the memory cell layer 20.

[0031] See Figure 3 The storage cell layer 20 may also include a second electrode layer 22 and a storage function layer 23. The storage function layer 23 is located on the side of the second electrode layer 22 away from the substrate 10 and between the second electrode layer 22 and the first electrode layer 21. That is, the second electrode layer 22, the storage function layer 23 and the first electrode layer 21 are stacked sequentially on the substrate 10.

[0032] In some embodiments, the storage functional layer 23 includes a gate layer 231, a third electrode layer 232, and a phase change layer 233 stacked sequentially. The materials of the first electrode layer 21, the second electrode layer 22, and the third electrode layer 232 can all include carbon, and the material of the gate layer 231 can include Zn. x Te y 、Ge x Te y 、Nb x O y Si x As y As x Te y At least one of them. The material of the phase change storage layer may include, for example, a chalcogenide-based material, which includes at least one of the four elements forming Group VIA of the periodic table: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).

[0033] In other embodiments, the material of the storage functional layer 23 includes a bidirectional threshold switch (OTS) material, such as a chalcogenide compound, which includes at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, and Ge-As-S.

[0034] See Figure 2 A storage stack 20a is formed on the substrate 10, the storage stack 20a including a first initial electrode layer 21a, the material of the first initial electrode layer 21a including carbon.

[0035] The method for forming the semiconductor device further includes forming a first conductive layer 40 on the substrate 10 between the formation of the memory stack 20a. The first conductive layer 40 is made of tungsten and can be used to form bit lines.

[0036] In some embodiments, the storage stack 20a includes a second initial electrode layer 22a, an initial storage function layer 23a and a first initial electrode layer 21a stacked sequentially, wherein the materials of the first initial electrode layer 21a and the second initial electrode layer 22a include carbon.

[0037] The formation process of the first initial electrode layer 21a, the initial storage function layer 23a and the second initial electrode layer 22a includes a deposition process. The deposition process can be, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering and other methods.

[0038] However, the surface 2120 of the first initial electrode layer 21a formed by the deposition process will have a certain roughness, and this roughness remains on the top surface 2120 of the first electrode layer 21, i.e., the top surface 2120 of the second electrode portion 212. This causes the mask layer 30 subsequently formed on the second electrode portion 212 to embed into the rough top surface 2120 of the second electrode portion 212. During the subsequent removal of the mask layer 30, material residue of the mask layer 30 is caused, ultimately resulting in the top surface 2120 of the first electrode layer 21 not being fully opened and unable to make good contact with the conductive layer above it, thus reducing the yield.

[0039] In some embodiments, the initial storage function layer 23a includes an initial gating layer 231a, a third initial electrode layer 232a, and an initial phase transition layer 233a.

[0040] In other embodiments, the initial storage function layer 23a includes an initial phase change storage layer.

[0041] See Figure 2 Modified ions are incorporated into the first initial electrode layer 21a to form the second electrode portion 212 and the first electrode portion 211. The second electrode portion 212 is doped with the modified ions, while the first electrode portion 211 is not doped with the modified ions, or the concentration of the modified ions in the first electrode portion 211 is less than the concentration of the modified ions in the second electrode portion 212.

[0042] In some embodiments, the modified ions include at least one of nitrogen, boron, phosphorus, sulfur, oxygen, fluorine, and transition metals. Experiments have shown that doping the second electrode portion 212 with these modified ions can reduce the surface roughness of the carbon material.

[0043] Regarding N, since the material of the first initial electrode layer 21a was originally pure carbon, it only has C-C bonds and contains many defects in the crystal. After N is incorporated, N can form C-C bonds with C, reducing the overall defects and thus reducing the roughness. For the other elements mentioned above, the surface roughness can also be reduced, but the principle may be different.

[0044] It should be noted that, since the purpose of this application is to reduce the roughness of the top surface 2120 of the second electrode portion 212, the roughness of the top surface 2120 of the second electrode portion 212 is compared with the roughness of the surface 2120 of the first electrode portion 211 to demonstrate that the roughness of the top surface 2120 of the second electrode portion 212 has been reduced.

[0045] In some embodiments, the modified ions are only incorporated into the first initial electrode layer 21a located in the upper portion, so the second electrode portion 212 is doped with the modified ions, while the first electrode portion 211 is not doped with the modified ions.

[0046] In other embodiments, the modified ions are incorporated into the entire first initial electrode layer 21a, but the concentration is different at different locations. For example, the concentration of modified ions in the first initial electrode layer 21a varies in a gradient, and the concentration of modified ions in the first electrode portion 211 is less than the concentration of modified ions in the second electrode portion 212.

[0047] In some embodiments, the concentration of the modified ions in the second electrode portion 212 is 5 at% to 15 at%. Experimental studies have shown that the modified ions can reduce roughness within this concentration range; that is, outside this concentration range, the effect of reducing roughness is not significant. For example, the concentration of the modified ions in the second electrode portion 212 is 5 at%, 7.5 at%, 10 at%, 12.5 at%, or 15 at%. Furthermore, experimental studies have shown that within the range of 5 at% to 15 at%, the roughness of the top surface 2120 of the second electrode portion 212 first decreases and then increases. For example, within the range of 5 at% to 10 at%, the roughness of the top surface 2120 of the second electrode portion 212 gradually decreases, and within the range of 10 at% to 15 at%, the roughness of the top surface 2120 of the second electrode portion 212 gradually increases.

[0048] Wherein, the concentration of the modified ions in the first electrode portion 212 is greater than or equal to 0 and less than 5 at%. That is, when the modified ions are also incorporated into the first electrode portion 212, the concentration of the modified ions in the first electrode portion 212 is less than 5 at.

[0049] In some embodiments, to further reduce the roughness of the top surface 2120 of the second electrode portion 212, the target concentration of modified ions can be set to 7.5 at% to 12.5 at%, that is, the concentration of modified ions in the second electrode portion 212 is 7.5 at% to 12.5 at%. During the process of incorporating modified ions into the first initial electrode layer 21a, the first electrode portion 211 may also be incorporated with modified ions at a concentration lower than the target concentration. Therefore, the concentration of modified ions in the first electrode portion 211 is less than the concentration of modified ions in the second electrode portion 212. For example, the concentration of modified ions in the first electrode portion 212 is less than 7.5 at%, resulting in a roughness of the top surface 2120 of the second electrode portion 212 that is less than the surface roughness of the first electrode portion 211. The surface roughness of the first electrode portion 211 is also reduced compared to the undoped case.

[0050] In some embodiments, see Figure 2The method for forming the first initial electrode layer 21a and doping the first initial electrode layer 21a with modified ions includes: forming a first initial electrode portion 211a on the substrate 10 (e.g., on the initial storage functional layer 23a); forming a second initial electrode portion 212a on the first initial electrode portion 211a, wherein the first initial electrode portion 211a and the second initial electrode portion 212a form the first initial electrode layer 21a; and during the process of forming the second initial electrode portion 212a, introducing a gas containing the modified ions, so that the second initial electrode portion 212a and the first initial electrode portion 211a respectively form the second electrode portion 212 and the first electrode portion 211.

[0051] In other words, a portion of the first initial electrode 211a can be deposited first, and then a gas containing modified ions (e.g., nitrogen) can be introduced during the deposition of the second initial electrode 212a. After the deposition of the second initial electrode 212a is completed, the first initial electrode 211a becomes the first electrode 211, and the second initial electrode 212a becomes the second electrode 212. In the deposition process of the second initial electrode 212a, the flow rate of nitrogen can be 3 sccm to 7 sccm to form a target concentration of modified ions in the second electrode 212.

[0052] By controlling the deposition thickness of the first initial electrode portion 211a and the second initial electrode portion 212a, the required doping thickness in the first initial electrode layer 21a can be well controlled, that is, the thickness of the first electrode portion 211a and the second electrode portion 212a can be precisely controlled. Furthermore, modified ions are not easily incorporated into the first initial electrode portion 211a.

[0053] Controlling the thickness of the second electrode portion 212 and the first electrode portion 211 is beneficial to improving the grinding rate of the subsequent grinding process, which will be described in detail in the corresponding steps below.

[0054] In other embodiments, the method of forming the first initial electrode layer 21a and doping the first initial electrode layer 21a with modified ions includes: forming a first initial electrode portion 211a on the substrate 10; forming a second initial electrode portion 212a on the first initial electrode portion 211a, the first initial electrode portion 211a and the second initial electrode portion 212a forming the first initial electrode layer 21a; and performing ion implantation on the second initial electrode portion 212a using the modified ions, so that the second initial electrode portion 212a and the first initial electrode portion 211a respectively form the second electrode portion 212 and the first electrode portion 211.

[0055] In other words, after the first initial electrode portion 211a and the second initial electrode portion 212a are deposited, the second initial electrode portion 212a is modified by an ion implantation process. After the ion implantation process, the first initial electrode portion 211a forms the first electrode portion 211, and the second initial electrode portion 212a forms the second electrode portion 212.

[0056] It should be noted that the ion implantation process can enable the modified ions in the second electrode section 212 to reach the target concentration, while the concentration of modified ions in the first electrode section 211 is less than the concentration of modified ions in the second electrode section 212.

[0057] In other embodiments, other suitable processes can be used to make the roughness of the surface 2120 of the second electrode portion 212 facing away from the substrate 10 less than the roughness of the surface of the first electrode portion 211, thereby reducing the residue of the mask layer 30.

[0058] See Figure 3 The mask layer 30 is formed on the second electrode portion 212, and the memory cell layer 20 is formed by etching the memory stack 20a using the mask layer 30 as a mask.

[0059] The method for forming the mask layer 30 includes: forming an initial mask layer 30a on the second electrode portion 212 (see...). Figure 2 The process involves: forming a photoresist layer on the initial mask layer 30a; performing a photolithography process on the photoresist layer using a mask to form a patterned photoresist layer; and etching the initial mask layer 30a using the patterned photoresist layer as a mask to form the mask layer 30.

[0060] The initial mask layer 30a is formed using any of the deposition processes described above.

[0061] Since the roughness of the top surface 2120 of the second initial electrode portion 212a is reduced, when the initial mask layer 30a is formed thereon, the portion of the initial mask layer 30a embedded in the surface 2120 of the second initial electrode portion 212a is reduced. That is, in the process of removing the mask layer 30, the residue of the mask layer 30 on the surface 2120 of the second electrode portion 212a can be reduced, thereby improving the yield.

[0062] The etching process for the memory stack 20a includes self-aligned double patterning (SADP). For example... Figure 3 As shown, the memory cell layer 20 extends along a second direction Y, which is parallel to the upper surface of the substrate 10. During the self-aligned dual patterning process, the first conductive layer 40 is etched to form multiple first conductive lines 40a, such as bit lines, extending along the second direction Y.

[0063] The method for forming the semiconductor device further includes: after forming the memory cell layer 20, forming a protective layer 24 on the sidewalls of adjacent memory cell layers 20; and then forming an isolation layer 25 between adjacent memory cells. The material of the protective layer 24 includes silicon nitride and / or silicon oxide, and the material of the isolation layer 25 includes an organic carbon material.

[0064] See Figure 3 and Figure 4 , Figure 4 It shows the layout structure of semiconductor devices. Figure 3 yes Figure 4 A schematic diagram of the cross-sectional structure at point A-A1.

[0065] like Figure 4 As shown, the semiconductor device includes an array region 101, a via region 102, and a contact region 103. The via region 102 is located on both sides of the array region 101 along a first direction X. The array region 101 includes a first sub-array region 101a and a second sub-array region 101b spaced apart along the first direction X. The contact region 103 is located between the first sub-array region 101a and the second sub-array region 101b.

[0066] The array region 101 is used to form a memory array, which includes memory cells arranged in an array. The contact region 103 is used to form contact structures (e.g., word line contacts) to connect word lines. The via region 102 is used to form through contacts to transmit circuit signals from the control circuit layer 12 to the front side of the semiconductor device.

[0067] Before step S3, after forming the storage cell layer 20, a dielectric layer 50 is formed on both sides of the storage cell layer 20 along the first direction X. The dielectric layer 50 includes a first dielectric block 51 and a second dielectric block 52 located on both sides of the storage cell layer 20, respectively. The first direction X is perpendicular to the extension direction of the storage cell layer 20 (i.e., the second direction Y). Before performing the polishing process, a contact structure 60 is formed in the first dielectric block 51.

[0068] The first dielectric block 51 is located in the contact area 103, so the contact structure 60 is formed within the contact area 103. The second dielectric block 52 is located in the through-hole area 102, and the subsequently formed through contact (described in subsequent corresponding steps) can be formed within the second dielectric block 52 and the through-hole area 102.

[0069] Since the dimension W1 of the contact area 103 along the first direction X is large and larger than the dimension W2 of the through-hole area 102 along the first direction X, the dimension W1 of the first dielectric block 51 along the first direction X is larger than the dimension W2 of the second dielectric block 52 along the first direction X. In other words, the area required for the contact structure 60 is larger than the area required for the through contact.

[0070] Step S3: Perform a grinding process to remove the mask layer 30 and at least a portion of the second electrode portion 212. See also Figure 5 .

[0071] The polishing process includes polishing the mask layer 30 and at least a portion of the second electrode portion 212 using a chemical mechanical polishing process until the mask layer 30 is completely removed. After the polishing process, the second electrode portion 212 is either completely removed or partially retained, and the roughness of the surface 2120 of the first electrode layer 21 facing away from the substrate 10 is reduced.

[0072] Since part of the mask layer 30 is embedded in the top surface 2120 of the second electrode portion 212, the grinding process removes part of the second electrode portion 212, which can further reduce the residue of the mask layer 30.

[0073] like Figure 5 As shown, during the grinding process, the first dielectric block 51 and the second dielectric block 52 are ground. After the grinding process, due to the different sizes of the first dielectric block 51 and the second dielectric block 52, protrusions are formed on the surface of the first dielectric block 51, and grooves 521 are formed on the surface of the second dielectric block 52. Furthermore, the longer the grinding time, the deeper the grooves 521 become, thereby affecting subsequent processes and reducing device yield.

[0074] After grinding, the thickness of the plurality of first electrode layers gradually decreases in the first direction X, from the first dielectric block 51 to the second dielectric block 52 (i.e., from left to right in the diagram). Among them, a portion of the second electrode portion 212 on the left is partially retained, while a portion of the first electrode portion 211 on the right is removed.

[0075] Since the risk of mask layer 30 remaining on the surface 2120 of the second electrode portion 212 is reduced, the thickness requirement for removing at least part of the second electrode portion 212 by grinding is reduced. In other words, the thickness of the first electrode layer 21 being ground is reduced, thus reducing the grinding time and thereby reducing the depth of the groove 521, thereby improving the yield.

[0076] Furthermore, nitrogen is included as a modifying ion, as nitrogen doping typically increases the electrical conductivity of carbon materials. Nitrogen atoms, as N-type dopant, introduce extra electrons, promoting the formation of sp² hybridized carbon structures (graphitization), thereby enhancing carrier mobility. Simultaneously, regarding thermal conductivity, when the nitrogen content reaches a certain value, the thermal conductivity decreases due to structural disorder. Therefore, retaining the N-doped second electrode portion 212 within the semiconductor device is beneficial to the electrical performance of current three-dimensional phase-change memories.

[0077] On the other hand, experimental studies have shown that when the material of the second electrode portion 212 contains modified ions, and the modified ions are at least one of nitrogen, oxygen, and fluorine, CN bonds, CO bonds, and / or CF bonds can be formed. For N, the bond energy of the CC bond (348 kJ / mol) is higher than that of the CN bond (295 kJ / mol). The higher the bond energy, the more stable the bond, and the more stable the chemical bond. Therefore, after N doping, due to the presence of the lower bond energy CN bond, the chemical polishing effect between the second electrode portion 212 and the polishing solution used in the polishing process is enhanced, thus increasing the polishing rate.

[0078] Since the bond energy of a single bond depends heavily on the electronegativity of the element, the higher the electronegativity, the lower the relative bond energy. The electronegativity of C is 2.55, while that of non-metallic elements N (3.04), O (3.44), and F (4) is higher than that of C, so their corresponding bond energies are lower. Theoretically, all of these can enhance the chemical grinding effect and thus increase the grinding rate. Currently, the relatively mature process is N doping.

[0079] It should be noted that elements whose covalent bond energy with C is less than that of C-C bonds are all within the scope of protection of this application, so as to achieve the effect of improving the grinding rate.

[0080] In some embodiments, the thickness (i.e. the total thickness) of the first initial electrode layer 21a is 10nm to 20nm, and one-seventh to one-eighth of the total thickness, such as 2nm, needs to be removed to ensure that the mask layer 30 is not left behind.

[0081] Since doping the second electrode portion 212 with the aforementioned modified ions can increase the polishing rate, the thickness of the second electrode portion 212 can be set according to the thickness of the first electrode layer 21 that needs to be removed. This allows for increased polishing speed while ensuring no residue remains in the mask layer 30. Therefore, a ratio of the thickness of the second electrode portion 212 to the thickness of the first electrode layer 21 of 1:8 to 1:7 ensures no residue remains in the mask layer 30. It should be noted that the thickness of the first electrode layer 21 mentioned here refers to its thickness before polishing.

[0082] The method for forming the semiconductor device further includes the following steps.

[0083] See Figure 6 A conductive layer 70 is formed on the first electrode layer 21, the first dielectric block 51 and the second dielectric block 52, and the conductive layer 70 is connected to the contact structure 60.

[0084] The conductive layer 70 is referred to as the second conductive layer 70. The second conductive layer 70 may include an adhesive layer 71 and a metal layer 72 located on the adhesive layer 71. The material of the adhesive layer 71 includes WSiN, and the material of the metal layer 72 includes W. Figure 6 As shown, the second conductive layer 70 is conformally formed on the surface of the protrusions and grooves 521.

[0085] See Figure 7 , Figure 7 yes Figure 4 A cross-sectional view along line B-B1. The conductive layer 70 and the memory cell layer 20 are etched to form multiple conductive lines 70a and multiple memory cells 20b, respectively. The conductive lines 70a are located on the memory cells 20b and on the second dielectric block 52.

[0086] Corresponding to the section of B-B1, Figure 7 The diagram shows cross-sections of three regions: the left side is a cross-section of the contact region 103 along the YZ direction, the middle side is a cross-section of the array region 101 along the YZ direction, and the right side is a cross-section of the via region 102 along the YZ direction. Therefore, the surface of the first dielectric block 51 remains protruding, and the surface of the second dielectric block 52 remains grooved.

[0087] The method for etching the conductive layer 70 and the memory cell layer 20 includes: forming a mask layer M on the conductive layer 70; and etching the conductive layer 70 and the memory cell layer 20 using the mask layer M as a mask. Figure 3 Etching in different directions; after etching is completed, the mask layer M is removed.

[0088] The mask layer M can be removed by etching. Since the conductive line 70 and the mask layer M on the conductive line 70 are formed on the surface of the groove 521, the mask layer M in the groove 521 cannot be removed during the etching process, that is, the conductive line 70a and the mask layer M remain in the groove 521.

[0089] After etching, multiple memory cells 20b are arrayed along the first direction X and the second direction Y. The second conductive layer 7070 is etched to form multiple conductive lines 70a (which can be called second conductive lines 70a) extending along the first direction X. Among them, the first conductive line 40a can be used as a bit line, and the second conductive line 70a can be used as a word line.

[0090] See Figure 8The method for forming the semiconductor device may further include: after forming the memory cell 20b and the conductive line 70a, forming an isolation layer 25 between adjacent memory cells 20b, between adjacent conductive lines 70a, and within the groove 521.

[0091] The process for forming the isolation layer 25 includes a deposition process and a chemical mechanical polishing process, wherein the chemical mechanical polishing process is applied to the surface of the conductive wire 70a.

[0092] See Figure 9 A third medium block 53 is formed on the second medium block 52.

[0093] The isolation layer 25 located in the groove 521 is removed, and the groove 521 is filled with a third dielectric block 53. In this application, the materials of the first dielectric block 51, the second dielectric block 52, and the third dielectric block 53 all include silicon oxide.

[0094] The process for removing the isolation layer 25 includes dry etching, in which the mask layer M is also removed.

[0095] Because the gap between adjacent conductive lines 70a in the groove 521 is very small, holes V are easily formed between adjacent conductive lines 70a when the third dielectric block 53 is filled, meaning that the third dielectric block 53 has difficulty completely filling the groove 521.

[0096] See Figure 10 This forms a through contact 80 that penetrates the third medium block 53 and the second medium block 52.

[0097] The forming process of the through contact 80 includes an etching process and a deposition process, and the material of the through contact 80 includes tungsten.

[0098] Due to the presence of the hole V, the material penetrating the contact 80 can easily diffuse into the hole V, causing material loss in the contact 80, which in turn leads to yield loss and short circuits between adjacent contact 80s.

[0099] In this embodiment, by reducing the roughness of the top surface 2120 of the second electrode portion 212, the residue of the mask layer 30 is reduced, thus reducing the thickness of the first electrode layer 21 that needs to be ground, thereby reducing the grinding time and consequently reducing the depth of the groove 521. The reduced depth of the groove 521 reduces the size of the hole V, thus reducing material loss through the contact 80 and improving yield.

[0100] In addition, by doping the second electrode portion 212 with modified ions, the grinding rate of the second electrode portion 212 can be increased. From this perspective, the grinding time can also be reduced, thereby reducing the depth of the groove 521 and improving the yield.

[0101] This application also provides a semiconductor device formed by the semiconductor device forming method provided in any of the above embodiments.

[0102] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0103] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0104] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0105] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method of forming a semiconductor device, characterized by, Comprising: providing a substrate, forming a memory cell layer and a mask layer on the substrate, the memory cell layer comprising a first electrode layer, the first electrode layer comprising a first electrode portion and a second electrode portion, the second electrode portion being on a side of the first electrode portion facing away from the substrate, the mask layer being on a surface of the second electrode portion facing away from the substrate, a roughness of the surface of the second electrode portion facing away from the substrate being less than a roughness of a surface of the first electrode portion; performing a polishing process to remove the mask layer and at least part of the second electrode portion.

2. The method of forming a semiconductor device according to claim 1, wherein The method for forming the memory cell layer and the mask layer comprises: forming a memory stack on the substrate, the memory stack comprising a first initial electrode layer, a material of the first initial electrode layer comprising carbon; incorporating modification ions into the first initial electrode layer to form the second electrode portion and the first electrode portion, the second electrode portion being doped with the modification ions, the first electrode portion being free of the modification ions or having a concentration of the modification ions less than a concentration of the modification ions in the second electrode portion; forming a mask layer on the second electrode portion and etching the memory stack with the mask layer as a mask to form the memory cell layer.

3. The method of forming a semiconductor device according to claim 2, wherein The method for forming the first initial electrode layer and incorporating modification ions into the first initial electrode layer comprises: forming a first initial electrode portion on the substrate; forming a second initial electrode portion on the first initial electrode portion, the first initial electrode portion and the second initial electrode portion forming the first initial electrode layer; during a process of forming the second initial electrode portion, introducing a gas containing the modification ions to form the second electrode portion and the first electrode portion from the second initial electrode portion and the first initial electrode portion respectively.

4. The method of forming a semiconductor device according to claim 2, wherein The method for forming the first initial electrode layer and incorporating modification ions into the first initial electrode layer comprises: forming a first initial electrode portion on the substrate; forming a second initial electrode portion on the first initial electrode portion, the first initial electrode portion and the second initial electrode portion forming the first initial electrode layer; performing ion implantation on the second initial electrode portion with the modification ions to form the second electrode portion and the first electrode portion from the second initial electrode portion and the first initial electrode portion respectively.

5. The method of claim 2, wherein The modification ions comprise at least one of nitrogen, boron, phosphorus, sulfur, oxygen, fluorine and transition metal.

6. The method of forming a semiconductor device of claim 1, wherein, The method for performing the polishing process comprises: polishing the mask layer and at least part of the second electrode portion with a chemical mechanical polishing process until the mask layer is completely removed; wherein, after the polishing process, the second electrode portion is completely removed or partially retained, and a roughness of a surface of the first electrode layer facing away from the substrate is reduced.

7. The method of forming a semiconductor device according to claim 2, wherein The concentration of the modification ions in the second electrode portion is 5 at% to 15 at%, and the concentration of the modification ions in the first electrode portion is greater than or equal to 0 and less than 5 at%.

8. The method of forming a semiconductor device of claim 1, wherein, Further comprising: Before the grinding process, a dielectric layer is formed on both sides of the memory cell layer along a first direction, the dielectric layer comprising a first dielectric block and a second dielectric block respectively on both sides of the memory cell layer, the first direction being perpendicular to the extension direction of the memory cell layer, the size of the first dielectric block along the first direction being greater than the size of the second dielectric block along the first direction; Before the grinding process, a contact structure is formed in the first dielectric block; During the grinding process, the first dielectric block and the second dielectric block are ground.

9. The method of forming a semiconductor device according to claim 8, wherein, Further comprising: A conductive layer is formed on the first electrode layer, the first dielectric block and the second dielectric block, the conductive layer being connected with the contact structure; The conductive layer and the memory cell layer are etched to form a plurality of conductive lines and a plurality of memory cells respectively, the conductive lines being on the memory cells and on the second dielectric block; A third dielectric block is formed on the second dielectric block; A through contact is formed through the third dielectric block and the second dielectric block.

10. A semiconductor device, characterized by comprising: Formed by the method of claim 1-9.

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