A two-dimensional material field effect transistor and a method of manufacturing the same

Abstract

The application relates to the technical field of field effect transistor devices, and discloses a two-dimensional material field effect transistor and a preparation method thereof. The two-dimensional material field effect transistor comprises a substrate insulating layer, a gate layer, a gate contact electrode, a vertical electric field shielding structure, a second insulating layer and a conductive channel film which are arranged in a stack. A second step and a third step are formed on the side of the conductive channel film away from the second insulating layer; the second step and the third step are arranged along the stacking direction. A first contact electrode is formed on the second step surface through oblique angle deposition, and a second contact electrode is formed on the third step surface through oblique angle deposition; the side surface of the first contact electrode facing the third step is aligned with the end of the second step surface facing the third step. The first contact electrode and the second contact electrode are deposited through the oblique angle deposition mode, the dependence on a photoetching device and a overlay process precision in the development process of the existing field effect transistor is reduced, and the channel length and the gate length are simultaneously micronized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of field effect transistor devices, in particular to a two-dimensional material field effect transistor and a preparation method thereof. BACKGROUND

[0002] With the continuous development of integrated circuits towards high density and miniaturization, the gate length and channel length of transistors have approached the physical limit of traditional photolithography process. At present, the advanced process of realizing feature size below 10 nm generally relies on extreme ultraviolet lithography (EUV) or electron beam lithography (EBL) technology; however, such technology not only has complex process steps and extremely high requirements for equipment precision, but also has the problem of high preparation cost, which seriously limits the large-scale production and application of high-density miniaturized transistors. In addition, when the device enters the sub-10 nm scale, the problems of short channel effect, increased gate leakage current and poor electrical performance consistency between devices become increasingly prominent, which puts forward more stringent requirements on the structure design, material selection and preparation method of the transistor.

[0003] The two-dimensional material field effect transistor provides a new direction for breaking through the miniaturization bottleneck of traditional transistors, with its atomic-level ultra-thin thickness, excellent charge transport characteristics and flexible electrical control capability. However, the existing research on two-dimensional material field effect transistors still mostly relies on high-precision photolithography process to define the gate length and channel length: although some schemes have realized the miniaturization of gate length (i.e. gate length) or channel length (i.e. channel length), it is difficult to simultaneously achieve the miniaturization of channel length and gate length under the premise of considering low-cost process. Therefore, developing a new process independent of high-precision photolithography to realize the miniaturization of channel length and gate length of two-dimensional material field effect transistors has become a technical requirement to break through the current bottleneck of integrated density of two-dimensional material field effect transistors and promote its industrial application. SUMMARY

[0004] The present application provides a two-dimensional material field effect transistor and a preparation method thereof. In the present application, by using oblique angle deposition technology to deposit the first contact electrode and the second contact electrode on the second step surface of the second step and the third step surface of the third step respectively, the first contact electrode can be aligned with the end of the second step surface facing the third step, thereby realizing the reduction of the channel length; in combination with the connection of the upper surface of the gate layer with the gate contact electrode and the vertical electric field shielding structure, the thickness of the gate can be used to define the gate length of the transistor, so as to realize the purpose of simultaneously reducing the gate length and the channel length in a single field effect transistor. In addition, the present application does not use high-precision photolithography process when depositing the contact electrode, but uses oblique angle deposition technology, thereby reducing the process cost, reducing the dependence on photolithography equipment and overlay process precision in the existing field effect transistor development process, and realizing the synchronous miniaturization of the channel length and the gate length.

[0005] The first aspect of this invention provides a two-dimensional material field-effect transistor, comprising:

[0006] A substrate insulating layer, wherein a first step is formed on one side of the substrate insulating layer, and the first step is formed by splicing a first protrusion and a first recess;

[0007] A gate layer is deposited on one side of the first protrusion, and the thickness S of the gate layer is less than 1 nanometer.

[0008] The gate contact electrode is disposed on the side of the gate layer away from the first protrusion.

[0009] A vertical electric field shielding structure is laid on the side of the gate contact electrode away from the gate layer, and also on the side of the gate layer away from the first protrusion;

[0010] The second insulating layer is laid on the side of the vertical electric field shielding structure away from the gate contact electrode, and is also laid in the first recess.

[0011] A conductive channel film is laid on the side of the second insulating layer away from the vertical electric field shielding structure; a second step and a third step are formed on the side of the conductive channel film away from the second insulating layer; the second step and the third step are arranged along the stacking direction;

[0012] The first contact electrode is formed on the second step surface of the second step by oblique deposition;

[0013] The second contact electrode is formed on the third step surface of the third step by oblique deposition;

[0014] Wherein, the side of the first contact electrode facing the third step is aligned with the end of the second step surface facing the third step.

[0015] According to the two-dimensional material field-effect transistor provided by the present invention, the horizontal spacing L1 between the first contact electrode and the second contact electrode is 0 nanometers to 200 nanometers; the channel length is 5 nanometers to 250 nanometers.

[0016] According to the two-dimensional material field-effect transistor provided by the present invention, the horizontal spacing L1 between the first contact electrode and the second contact electrode is 0 nanometers to 10 nanometers.

[0017] The two-dimensional material field-effect transistor provided by the present invention has a channel length of 5 nanometers to 10 nanometers.

[0018] The two-dimensional material field-effect transistor provided by the present invention has a channel length of 8 nanometers.

[0019] In the two-dimensional material field-effect transistor provided by the present invention, the vertical distance H between the second step surface and the third step surface is 10 nanometers to 50 nanometers.

[0020] In the two-dimensional material field-effect transistor provided by the present invention, the third step surface is lower than the lower side surface of the gate layer.

[0021] According to the two-dimensional material field-effect transistor provided by the present invention, the gate layer comprises a single layer of graphene or a few layers of graphene; the conductive channel film comprises a two-dimensional material film.

[0022] A second aspect of the present invention provides a method for fabricating a two-dimensional material field-effect transistor, for fabricating the field-effect transistor described in any of the preceding claims, comprising:

[0023] A gate layer is deposited on one side of the substrate insulating layer;

[0024] A gate contact electrode is deposited in a portion of the gate layer on the side away from the substrate insulating layer;

[0025] A vertical electric field shielding structure is laid in the remaining area of ​​the gate contact electrode on the side away from the gate layer and on the side of the gate layer away from the substrate insulating layer.

[0026] The vertical electric field shielding structure, the gate layer and the substrate insulating layer are etched to form a first recess on one side of the substrate insulating layer.

[0027] A second insulating layer is laid on the side of the vertical electric field shielding structure away from the gate contact electrode and in the first recess.

[0028] A conductive channel film is laid on the side of the second insulating layer away from the vertical electric field shielding structure. At this time, a second step and a third step are formed on the side of the conductive channel film away from the second insulating layer.

[0029] The first contact electrode and the second contact electrode are deposited on the second step surface of the second step and the third step surface of the third step, respectively, using oblique deposition technology.

[0030] According to the fabrication method of the two-dimensional material field-effect transistor provided by the present invention, the deposition tilt angle α when using the oblique deposition technique is 1° to 89°.

[0031] The two-dimensional field-effect transistor and its fabrication method provided by this invention utilize oblique deposition to deposit the first contact electrode and the second contact electrode on the second step surface of the second step and the third step surface of the third step, respectively. This allows the side of the first contact electrode facing the third step to align with the end of the second step surface facing the third step, thereby reducing the channel length. Furthermore, by connecting the upper side of the gate layer to the gate contact electrode and the vertical electric field shielding structure, the gate length of the transistor can be defined using the gate thickness, achieving the simultaneous reduction of both the gate length and the channel length within a single field-effect transistor. Additionally, this invention does not use high-precision photolithography in the contact electrode fabrication process but instead employs oblique deposition, thus reducing the dependence on photolithography equipment and overlay process precision in existing field-effect transistor development, and enabling simultaneous miniaturization of the channel length and gate length. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of the two-dimensional material field-effect transistor provided by the present invention when the first contact electrode and the second contact electrode are not deposited.

[0034] Figure 2 This is a schematic diagram of the structure of the two-dimensional material field-effect transistor provided by the present invention after the first contact electrode and the second contact electrode are deposited by oblique deposition.

[0035] Figure 3 yes Figure 2 The diagram shows the structure of a two-dimensional material field-effect transistor after removing the photoresist and the electrode layer on the upper side of the photoresist.

[0036] Figure 4 This is a schematic diagram of the structure of the two-dimensional material field-effect transistor provided in Example 1 under a scanning electron microscope.

[0037] Figure 5 yes Figure 4 A schematic diagram of the structure of a two-dimensional material field-effect transistor (FET) under a transmission electron microscope, as shown by the white dashed line in the middle.

[0038] Figure 6 This is a transfer characteristic curve of the two-dimensional material field-effect transistor provided in Example 1.

[0039] Figure 7This is the output characteristic curve of the two-dimensional material field-effect transistor provided in Example 1.

[0040] Figure 8 This is a schematic diagram comparing the transfer characteristic curves of the two-dimensional material field-effect transistors provided in Example 1 and Comparative Example 1.

[0041] Figure label:

[0042] 100, Substrate; 200, Substrate insulating layer; 300, Gate layer; 400, Gate contact electrode; 500, Vertical electric field shielding structure; 510, First insulating layer; 520, Vertical electric field shielding layer; 600, Second insulating layer; 700, Conductive channel thin film; 701, Second step surface; 702, Third step surface; 800, First contact electrode; 900, Second contact electrode. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0044] In the description of this specification, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are used only for the convenience of describing this specification. They do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this specification. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this specification, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this invention based on the specific circumstances.

[0046] In this specification, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0047] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0048] In the embodiments of this specification, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously.

[0049] like Figures 1 to 3 As shown, a specific embodiment of the first aspect of the present invention provides a two-dimensional material field-effect transistor. The two-dimensional material field-effect transistor includes a substrate insulating layer 200, a gate layer 300, a gate contact electrode 400, a vertical electric field shielding structure 500, a second insulating layer 600, a conductive channel thin film 700, a first contact electrode 800, and a second contact electrode 900.

[0050] A first step is formed on one side of the substrate insulating layer 200, and the first step is formed by splicing a first protrusion and a first recess. A gate layer 300 is deposited on one side of the first protrusion, and the thickness S of the gate layer 300 is less than 1 nanometer. A gate contact electrode 400 is deposited on the side of the gate layer 300 away from the first protrusion. A vertical electric field shielding structure 500 is deposited on the side of the gate contact electrode 400 away from the gate layer 300, and also on the side of the gate layer 300 away from the first protrusion. A second insulating layer 600 is deposited on the side of the vertical electric field shielding structure 500 away from the gate contact electrode 400, and also on the first recess. A conductive channel film 700 is deposited on the side of the second insulating layer 600 away from the vertical electric field shielding structure 500; a second step and a third step are formed on the side of the conductive channel film 700 away from the second insulating layer 600; the second step and the third step are arranged along the stacking direction. A first contact electrode 800 and a second contact electrode 900 are deposited at an angle on the second step surface 701 of the second step and the third step surface 702 of the third step, respectively; wherein, the side of the first contact electrode 800 facing the third step is aligned with the end of the second step surface 701 facing the third step.

[0051] In this embodiment, by depositing the first contact electrode 800 and the second contact electrode 900 on the second step surface 701 of the second step and the third step surface 702 of the third step respectively using oblique deposition, the side of the first contact electrode 800 facing the third step (i.e., the right side of the first contact electrode 800) can be aligned with the end of the second step surface 701 facing the third step (i.e., the right end of the second step surface 701), thereby reducing the channel length. In addition, by connecting the upper side of the gate layer 300 to the gate contact electrode 400 and the vertical electric field shielding structure 500, the gate length of the transistor can be defined by the thickness of the gate, thereby achieving the goal of simultaneously reducing the gate length and channel length in a single field-effect transistor.

[0052] In addition, in this embodiment, instead of using traditional high-precision photolithography, oblique deposition is used in the fabrication of the first and second contact electrodes. This reduces the process cost and decreases the dependence on photolithography equipment and overlay process precision in the development of existing field-effect transistors. It also enables the simultaneous miniaturization of the channel length and gate length.

[0053] It should be noted that oblique angle deposition (OAD) is an existing thin film deposition method. OAD is a physical vapor deposition technique that achieves directional growth of thin films by controlling the angle between the incident atomic stream and the substrate. In this embodiment, this existing thin film deposition method is used to deposit the first contact electrode on the second step surface and the second contact electrode on the third step surface.

[0054] Angled deposition involves adjusting the deposition angle of the electron beam evaporation using a customized angle device. The sample, with its defined deposition window, is then firmly attached to the angled sample stage. The placement is precisely adjusted according to the orientation of the sample surface steps or microstructures, ensuring the step sidewalls face upwards to create a directional shadow effect. Finally, the sample and sample stage are placed in a vacuum chamber, where the electron beam power is stabilized under high vacuum. The metal deposition rate and film thickness are monitored and controlled in real time to complete the angled deposition of metals with anisotropic morphology. Because angled deposition is existing technology, the specific process of angled deposition is not described in detail in the specific embodiments of this invention.

[0055] It should be noted that the stacking direction refers to the stacking direction of the functional layers of a two-dimensional material field-effect transistor. In a specific embodiment of the present invention, the stacking direction is the vertical direction.

[0056] Specifically, the two-dimensional material field-effect transistor includes a substrate 100, a substrate insulating layer 200, a gate layer 300, a gate contact electrode 400, a vertical electric field shielding structure 500, a second insulating layer 600, a conductive channel thin film 700, a first contact electrode 800, and a second contact electrode 900.

[0057] A substrate insulating layer 200 is deposited on one side of the substrate 100 along the stacking direction. A first step is formed on the side of the substrate insulating layer 200 away from the substrate 100, and the first step is formed by splicing a first protrusion and a first recess. Specifically, the substrate insulating layer 200 is deposited on the upper side of the substrate 100 along the stacking direction (i.e., the vertical direction), and the upper side of the substrate insulating layer 200 is a stepped surface. The first step is formed by splicing a first protrusion and a first recess. In this embodiment, the substrate 100 is used to provide physical support for the entire field-effect transistor, and the substrate insulating layer 200 is used to electrically isolate the electrical signals of the subsequent gate layer 300. It can also be appropriately etched to realize the gate adjustment function of the gate layer 300 on the conductive channel thin film 700. The design of the first recess and the first protrusion can provide a basis for the formation of the subsequent second step surface 701 and third step surface 702.

[0058] A gate layer 300 is deposited on the side of the first protrusion of the substrate insulating layer 200 away from the substrate 100, and the thickness S of the gate layer 300 is less than 1 nanometer. A gate contact electrode 400 is deposited in a portion of the gate layer 300 on the side away from the substrate insulating layer 200. Specifically, the gate layer 300 is deposited on the upper side of the first protrusion, and the side of the gate layer 300 facing the first recess (i.e., the right side of the gate layer 300) is covered by the second insulating layer 600. A portion of the upper side of the gate layer 300 is provided with the gate contact electrode 400. The gate contact electrode 400 is used to transmit the voltage signal required by the gate layer 300.

[0059] A vertical electric field shielding structure 500 is disposed on the side of the gate contact electrode 400 away from the gate layer 300, and also on the side of the gate layer 300 away from the substrate insulating layer 200. Specifically, the vertical electric field shielding structure 500 is disposed on the upper side of the gate contact electrode 400 and the remaining area of ​​the upper side of the gate layer 300, thus forming a stepped structure on the upper side of the vertical electric field shielding structure 500, which provides a basis for the formation of the second stepped surface 701. The side of the vertical electric field shielding structure 500 facing the first recess (i.e., the right side of the vertical electric field shielding structure 500) is covered by the second insulating layer 600. The vertical electric field shielding structure 500 is used to shield the electric field from the vertical direction of the gate layer 300, thereby enabling the gate length of the transistor to be defined using the gate thickness.

[0060] The second insulating layer 600 is deposited on the side of the vertical electric field shielding structure 500 away from the gate contact electrode 400, and is also deposited in the first recess. Specifically, the upper side of the vertical electric field shielding structure 500 and the first recess are both covered by the second insulating layer 600; the side of the second insulating layer 600 is connected to the substrate insulating layer 200, the gate layer 300, and the side of the vertical electric field shielding structure 500 facing the first recess.

[0061] A conductive channel film 700 is deposited on the side of the second insulating layer 600 away from the vertical electric field shielding structure 500. A second step and a third step are formed on the side of the conductive channel film 700 away from the second insulating layer 600. A first contact electrode 800 and a second contact electrode 900 are deposited using oblique deposition on the second step surface 701 of the second step and the third step surface 702 of the third step, respectively. The side of the first contact electrode 800 facing the third step is aligned with the end of the second step surface 701 facing the third step. Specifically, the conductive channel film 700 is deposited on the upper side of the second insulating layer 600. The upper side of the conductive channel film 700 has a second step with a second step surface 701 and a third step with a third step surface 702, with the third step surface 702 located below the second step surface 701. The first contact electrode 800 and the second contact electrode 900 are deposited using oblique deposition on the second step surface 701 and the third step surface 702, respectively. A field-effect transistor channel is formed within the conductive channel film 700, and the channel length is the length of the conductive channel film 700 located between the first contact electrode 800 and the second contact electrode 900. The first contact electrode 800 and the second contact electrode 900 are used to transmit electrical signals of the field-effect transistor.

[0062] In this embodiment, the first contact electrode 800 is deposited on the second step surface 701 at an angle, while the second contact electrode 900 is deposited on the third step surface 702. This allows the side of the first contact electrode 800 facing the third step (i.e., the right side of the first contact electrode 800) to be aligned with the end of the second step surface 701 facing the third step (i.e., the right end of the second step surface 701). If the first contact electrode 800 and the second contact electrode 900 are fabricated using conventional high-precision photolithography, it is impossible to align the side of the first contact electrode 800 facing the third step (i.e., the right side of the first contact electrode 800) with the end of the second step surface 701 facing the third step (i.e., the right end of the second step surface 701), and it is also difficult to control the distance between the second contact electrode 900 and the right end of the second step surface 701. Since the theoretical channel length is the length of the conductive channel film 700 between the first contact electrode 800 and the second contact electrode 900, in other words, the theoretical channel length L of the two-dimensional material field-effect transistor provided in this embodiment satisfies: L = L1 + H, where L1 is the horizontal distance between the first contact electrode 800 and the second contact electrode 900; and H is the vertical distance between the second step surface 701 and the third step surface 702. However, the first contact electrode formed using traditional high-precision photolithography cannot be aligned with the end of the second step surface, therefore the channel length is greater than the theoretical channel length L of this embodiment. Thus, this embodiment achieves a miniaturization of the theoretical channel length.

[0063] Furthermore, considering that in the actual processing, the included angle β between the sidewall of the conductive channel film 700 of the second step surface 701 and the third step surface 702 and the third step surface 702 will not be exactly equal to 90°, when depositing the first contact electrode using the oblique deposition method, some metal may be deposited on the conductive channel film 700 between the first contact electrode 800 and the second contact electrode 900, which will further reduce the channel length. In other words, the actual channel length in this embodiment is usually less than the theoretical channel length L.

[0064] Optionally, the horizontal distance L1 between the first contact electrode 800 and the second contact electrode 900 is 0 nm to 200 nm, and the channel length is 5 nm to 250 nm. In other words, the horizontal distance between the end of the second contact electrode 900 facing the first contact electrode 800 (i.e., the left end of the second contact electrode 900) and the conductive channel film 700 can be 0. In this case, the horizontal distance L1 between the first contact electrode 800 and the second contact electrode 900 is 0 nm, and the theoretical channel length L is the vertical distance H between the third step surface 702 and the second step surface 701. Alternatively, the horizontal distance between the end of the second contact electrode 900 facing the first contact electrode 800 (i.e., the left end of the second contact electrode 900) and the conductive channel film 700 is greater than 0. In this case, the theoretical channel length L satisfies: L = L1 + H.

[0065] Optionally, the electrode deposition angle α when using oblique deposition can be from 1° to 89°.

[0066] Optionally, the horizontal spacing L1 between the first contact electrode 800 and the second contact electrode 900 is 0 nanometers to 10 nanometers.

[0067] Optionally, the channel length is 5 nanometers to 10 nanometers.

[0068] Preferably, the channel length is 8 nanometers.

[0069] Optionally, the vertical distance H between the second step surface 701 and the third step surface 702 is 10 nanometers to 50 nanometers. This ensures that the two-dimensional material field-effect transistor has a small size while ensuring that the horizontal spacing L1 between the first contact electrode 800 and the second contact electrode 900 is less than 10 nanometers.

[0070] Optionally, the third step surface 702 is lower than the lower side surface of the gate layer 300, thus ensuring the formation of the channel.

[0071] Optionally, the substrate 100 is made of a conductive material. Preferably, the substrate 100 is made of heavily doped p-type silicon.

[0072] Optionally, the substrate insulating layer 200 is made of hafnium dioxide.

[0073] Optionally, the gate layer 300 comprises monolayer graphene or few-layer graphene. The thickness of the monolayer graphene is 0.34 nanometers.

[0074] Optionally, the gate contact electrode 400 may be made of metals or other conductive non-metals. For example, conductive non-metals may include highly doped p-type silicon, highly doped n-type silicon, and germanium semiconductors. Metals may be flexible electrode materials, such as chromium, palladium, gold, silver, and platinum.

[0075] Optionally, the material of the second insulating layer 600 includes metal oxides, two-dimensional insulators, and flexible insulators. For example, the material of the second insulating layer 600 is hafnium dioxide.

[0076] Optionally, the material of the conductive channel film 700 can be a two-dimensional material film or an oxide semiconductor with semiconductor properties. The thickness of the conductive channel film 700 ranges from 0.33 nanometers to 50 nanometers. For example, the material of the conductive channel film 700 is molybdenum disulfide.

[0077] Optionally, the materials of the first contact electrode 800 and the second contact electrode 900 include metals and other conductive non-metals. For example, the materials of the first contact electrode 800 and the second contact electrode 900 can be selected from metals such as bismuth or palladium, or from conductive non-metals such as highly doped p-type silicon, highly doped n-type silicon, and germanium semiconductors.

[0078] It should be noted that the materials of the first contact electrode 800 and the second contact electrode 900 may be the same or different.

[0079] In some embodiments of the present invention, the vertical electric field shielding structure 500 includes a first insulating layer 510 and a vertical electric field shielding layer 520. The first insulating layer 510 is disposed on the side of the gate contact electrode 400 away from the gate layer 300, and also on the remaining portion of the side of the gate layer 300 away from the substrate insulating layer 200. The vertical electric field shielding layer 520 is disposed on the side of the first insulating layer 510 away from the gate contact electrode 400. Specifically, the first insulating layer 510 is disposed on the upper side of the gate contact electrode 400 and the remaining portion of the upper side of the gate layer 300. The side of the gate contact electrode 400 facing the first recess is covered by the first insulating layer 510, and the side of the first insulating layer 510 facing the first recess is covered by a second insulating layer 600. Thus, a stepped structure is formed on the upper side of the first insulating layer 510, laying the foundation for the formation of the second stepped surface 701. The first insulating layer 510 is used to isolate the gate layer 300 from the vertical electric field shielding layer 520. A vertical electric field shielding layer 520 is laid on the upper side of the first insulating layer 510 to shield the electric field from the vertical direction of the gate layer 300.

[0080] Optionally, the material of the first insulating layer 510 is a metal oxide, a two-dimensional insulator, or a flexible insulator.

[0081] For example, the first insulating layer 510 includes an aluminum oxide layer and a hafnium dioxide layer deposited on the upper side of the aluminum oxide layer.

[0082] Optionally, the material of the vertical electric field shielding layer 520 is selected from metals or other conductive non-metals. For example, the material of the vertical electric field shielding layer 520 can be selected from metals such as bismuth or palladium, or from conductive non-metals such as highly doped p-type silicon, highly doped n-type silicon, and germanium semiconductors.

[0083] A second aspect of the present invention provides a method for fabricating a two-dimensional material field-effect transistor. This method is used to fabricate the two-dimensional material field-effect transistor of any of the above embodiments. The method includes:

[0084] S110. Deposit a substrate insulating layer 200 on the substrate 100. Specifically, deposit the substrate insulating layer 200 on the upper side of the substrate 100 using atomic layer deposition.

[0085] S120. A gate layer 300 is deposited on the side of the substrate insulating layer 200 away from the substrate 100. Specifically, the gate layer 300 is transferred to the upper side of the substrate insulating layer 200.

[0086] S130. A gate contact electrode 400 is deposited in a portion of the gate layer 300 on the side away from the substrate insulating layer 200. Specifically, a mask is covered on the upper side of the gate layer 300, and the gate contact electrode 400 is deposited in the non-mask area.

[0087] S140. A vertical electric field shielding structure 500 is deposited on the remaining portion of the gate contact electrode 400 away from the gate layer 300 and on the remaining portion of the gate layer 300 away from the substrate insulating layer 200. Specifically, a first insulating layer 510 is deposited on the upper side of the gate contact electrode 400 and the upper side of the gate layer 300; a vertical electric field shielding layer 520 is deposited on the upper side of the first insulating layer 510.

[0088] S150, the vertical electric field shielding structure 500, the gate layer 300, and the substrate insulating layer 200 are etched to form a first recess on the side of the substrate insulating layer 200 away from the substrate 100. Specifically, the vertical electric field shielding layer 520, the first insulating layer 510, the gate layer 300, and the substrate insulating layer 200 are etched to form a first recess on the upper side of the substrate insulating layer 200.

[0089] S160. A second insulating layer 600 is deposited on the side of the vertical electric field shielding structure 500 away from the gate contact electrode 400 and in the first recess. Specifically, the second insulating layer 600 is deposited on the upper side of the vertical electric field shielding layer 520 and in the first recess.

[0090] S170, a conductive channel film 700 is deposited on the side of the second insulating layer 600 away from the vertical electric field shielding structure 500. At this time, a second step and a third step are formed on the side of the conductive channel film 700 away from the second insulating layer 600. Specifically, the conductive channel film 700 is transferred to the upper side of the second insulating layer 600, and the third step surface 702 is lower than the lower side of the gate layer 300.

[0091] S180. A first contact electrode 800 and a second contact electrode 900 are deposited at an angle on the second step surface 701 of the second step and the third step surface 702 of the third step, respectively. Specifically, contact electrodes are deposited simultaneously on the second step surface 701 and the third step surface 702 using an angled deposition method to form the first contact electrode 800 and the second contact electrode 900. The end of the first contact electrode 800 facing the third step surface 702 is aligned with the end of the second step surface 701.

[0092] In this embodiment, by depositing the first contact electrode 800 and the second contact electrode 900 at an angle on the second step surface 701 of the second step and the third step surface 702 of the third step, respectively, the side of the first contact electrode 800 facing the third step can be aligned with the end of the second step surface 701 facing the third step, thereby reducing the channel length. Furthermore, by connecting the upper side of the gate layer 300 to the gate contact electrode 400 and the vertical electric field shielding structure 500, the gate length of the transistor can be defined by the gate thickness, achieving the goal of simultaneously reducing the gate length and channel length within a single field-effect transistor.

[0093] In addition, in this embodiment, instead of using traditional high-precision photolithography, oblique deposition is used in the fabrication of the first and second contact electrodes. This reduces the process cost, decreases the dependence on photolithography equipment and overlay process precision in the development of existing field-effect transistors, and enables the synchronous miniaturization of the channel length and gate length.

[0094] Example 1

[0095] This embodiment 1 provides a two-dimensional material field-effect transistor. The two-dimensional material field-effect transistor includes a substrate 100, a substrate insulating layer 200, a gate layer 300, a gate contact electrode 400, a first insulating layer 510, a vertical electric field shielding layer 520, a second insulating layer 600, a conductive channel thin film 700, a first contact electrode 800, and a second contact electrode 900.

[0096] Substrate 100 is heavily doped p-type silicon. The substrate insulating layer 200 is 50 nm thick and made of hafnium dioxide (HfO2). The gate layer 300 is a 0.34 nm thick monolayer graphene. The gate contact electrode 400 includes a 3 nm thick chromium layer and a 15 nm thick palladium layer; the chromium layer is disposed on the upper side of the monolayer graphene, and the palladium layer is disposed on the upper side of the chromium layer. The first insulating layer 510 is made of aluminum oxide (Al2O3) and hafnium dioxide (HfO2); a 3 nm thick layer of aluminum metal with its sides self-oxidized to form aluminum oxide is disposed on the upper side of the gate contact electrode 400 and the upper side of the gate layer 300, and then a 10 nm thick hafnium dioxide layer is deposited on the upper side of the aluminum oxide. The vertical electric field shielding layer 520 is 10 nm thick and made of palladium. The second insulating layer 600 is 8 nm thick and made of hafnium dioxide. The conductive channel film 700 has a thickness of 8 nanometers and is made of molybdenum disulfide (MoS2). The first contact electrode 800 includes a 5-nanometer-thick bismuth (Bi) layer and a 30-nanometer-thick palladium (Pd) layer. The bismuth layer is deposited on the second step surface 701, and the palladium layer is deposited on the upper side of the bismuth layer. The second contact electrode 900 has the same material and structure as the first contact electrode 800, and its bismuth layer is deposited on the third step surface 702. The third step surface 702 is lower than the lower side of the gate layer 300 to ensure the formation of the channel. The side of the first contact electrode 800 facing the third step surface 702 is aligned with the end of the second step surface 701 facing the third step surface 702, and the horizontal distance L1 between the first contact electrode 800 and the second contact electrode 900 is less than 10 nanometers.

[0097] The field-effect transistor of Example 1 was characterized using scanning electron microscopy (SEM) and transmission electron microscopy (TEM), respectively, and the results are as follows: Figure 4 and Figure 5 As shown. (Through) Figure 4 and Figure 5 The characterization results show that the actual gate length of the field-effect transistor in Example 1 is sub-1 nanometer and the actual channel length is 8 nanometers. Figure 6 and Figure 7 The transfer characteristic curves and output characteristic curves of the field-effect transistor of Example 1 are further shown.

[0098] Comparative Example 1

[0099] Comparative Example 1 provides a two-dimensional material field-effect transistor. The two-dimensional material field-effect transistor of Comparative Example 1 also includes a substrate 100, a substrate insulating layer 200, a gate layer 300, a gate contact electrode 400, a first insulating layer 510, a vertical electric field shielding layer 520, a second insulating layer 600, a conductive channel thin film 700, a first contact electrode 800, and a second contact electrode 900.

[0100] The substrate 100, substrate insulating layer 200, gate layer 300, gate contact electrode 400, first insulating layer 510, vertical electric field shielding layer 520, second insulating layer 600, and conductive channel film 700 of Comparative Example 1 are all the same as those of Example 1. The structure and material of the first contact electrode 800 and the second contact electrode 900 of Comparative Example 1 are also the same as those of Example 1. However, the first contact electrode 800 and the second contact electrode 900 of Comparative Example 1 are formed using a conventional high-precision photolithography process. Therefore, the side of the first contact electrode 800 facing the third step in Comparative Example 1 is not aligned with the end of the second step surface 701 facing the third step. In other words, the horizontal distance between the side of the first contact electrode 800 facing the third step (i.e., the right side of the first contact electrode 800) and the end of the second step surface 701 facing the third step (i.e., the right end of the second step surface 701) is greater than 0. Therefore, the channel length of Comparative Example 1 is greater than the theoretical channel length of Example 1 and also greater than the actual channel length of Example 1.

[0101] Compared to transistor devices defined by traditional high-precision photolithography (i.e., Comparative Example 1), the two-dimensional material field-effect transistor of Example 1 not only reduces the process difficulty of constructing transistors with extreme dimensions, but also achieves an increase of more than two orders of magnitude in the transistor's on-state current at the same photolithography precision, such as... Figure 8 As shown.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A two-dimensional material field-effect transistor, characterized in that, include: A substrate insulating layer (200) has a first step formed on one side, which is formed by splicing a first protrusion and a first recess. A gate layer (300) is deposited on one side of the first protrusion, and the thickness S of the gate layer (300) is less than 1 nanometer; A gate contact electrode (400) is disposed on the side of the gate layer (300) away from the first protrusion; A vertical electric field shielding structure (500) is laid on the side of the gate contact electrode (400) away from the gate layer (300), and also on the side of the gate layer (300) away from the first protrusion; The second insulating layer (600) is laid on the side of the vertical electric field shielding structure (500) away from the gate contact electrode (400), and is also laid on the first recess; A conductive channel film (700) is laid on the side of the second insulating layer (600) away from the vertical electric field shielding structure (500); a second step and a third step are formed on the side of the conductive channel film (700) away from the second insulating layer (600); the second step and the third step are arranged along the stacking direction; The first contact electrode (800) is formed on the second step surface (701) of the second step by oblique deposition. The second contact electrode (900) is formed on the third step surface (702) of the third step by oblique deposition. Wherein, the side of the first contact electrode (800) facing the third step is aligned with the end of the second step surface (701) facing the third step, and the horizontal distance L1 between the first contact electrode (800) and the second contact electrode (900) is 0 nanometers to 200 nanometers.

2. The two-dimensional material field-effect transistor according to claim 1, characterized in that, The channel length ranges from 5 nanometers to 250 nanometers.

3. The two-dimensional material field-effect transistor according to claim 2, characterized in that, The horizontal distance L1 between the first contact electrode (800) and the second contact electrode (900) is 0 nanometers to 10 nanometers.

4. The two-dimensional material field-effect transistor according to claim 2, characterized in that, The channel length is 5 nanometers to 10 nanometers.

5. The two-dimensional material field-effect transistor according to claim 4, characterized in that, The channel length is 8 nanometers.

6. The two-dimensional material field-effect transistor according to any one of claims 1 to 5, characterized in that, The vertical distance H between the second step surface (701) and the third step surface (702) is 10 nanometers to 50 nanometers.

7. The two-dimensional material field-effect transistor according to any one of claims 1 to 5, characterized in that, The third step surface (702) is lower than the lower side surface of the gate layer (300).

8. The two-dimensional material field-effect transistor according to any one of claims 1 to 5, characterized in that, The gate layer (300) comprises monolayer graphene or few-layer graphene; the conductive channel film (700) comprises a two-dimensional material film.

9. A method for fabricating a two-dimensional material field-effect transistor, characterized in that, For fabricating the two-dimensional material field-effect transistor according to any one of claims 1 to 8, comprising: A gate layer (300) is deposited on one side of the substrate insulating layer (200); A gate contact electrode (400) is deposited in a portion of the gate layer (300) on the side away from the substrate insulating layer (200). A vertical electric field shielding structure (500) is laid on the side of the gate contact electrode (400) away from the gate layer (300) and the remaining area of ​​the gate layer (300) away from the substrate insulating layer (200). The vertical electric field shielding structure (500), the gate layer (300) and the substrate insulating layer (200) are etched to form a first recess on one side of the substrate insulating layer (200); A second insulating layer (600) is laid on the side of the vertical electric field shielding structure (500) away from the gate contact electrode (400) and the first recess. A conductive channel film (700) is laid on the side of the second insulating layer (600) away from the vertical electric field shielding structure (500). At this time, a second step and a third step are formed on the side of the conductive channel film (700) away from the second insulating layer (600). The first contact electrode (800) and the second contact electrode (900) are deposited on the second step surface (701) of the second step and the third step surface (702) of the third step, respectively, by oblique deposition.

10. The method for fabricating a two-dimensional material field-effect transistor according to claim 9, characterized in that, The deposition dip angle α for oblique deposition ranges from 1° to 89°.

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