Longitudinal conduction normally-off type diamond power transistor and preparation method thereof

Abstract

The invention discloses a longitudinal conduction normally-off type diamond power transistor and a preparation method thereof, and relates to the technical field of semiconductor power devices. The device comprises the following structures: a p-type low-resistance diamond single crystal substrate; the first p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond single crystal substrate; the p-type low-resistance diamond insertion layer is located on the upper surface of the first p-type high-resistance diamond drift layer; the second p-type high-resistance diamond drift layer is located on the upper surface of the p-type low-resistance diamond insertion layer; and the p-type low-resistance diamond cap layer is located on the upper surface of the second p-type high-resistance diamond drift layer. The transistor provided by the invention is provided with the composite epitaxial layer with a multi-layer structure, wherein the on resistance of the diamond power transistor can be reduced and the threshold voltage can be improved by the high-concentration doped low-resistance insertion layer; meanwhile, the low-concentration doped high-resistance drift layer can enable the device to bear higher voltage.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor power devices, and particularly relates to a vertical conduction normally-on diamond power transistor and a preparation method thereof. BACKGROUND

[0002] Diamond power devices include diodes and transistors, and are mainly divided into two technical routes of lateral and vertical conduction. The vertical conduction type device can improve the withstand voltage by changing the drift layer thickness while keeping the device size unchanged, and relieve the premature breakdown caused by the edge effect of the gate edge electric field in the lateral device. The electric field peak position of the vertical device is far away from the device surface, which effectively suppresses the effect of trap states and reduces the dynamic on-resistance. Compared with the lateral device, the current flows out along the vertical direction, which can withstand higher power density, the electric field distribution is relatively more uniform, and the current distribution can be more extended, so that the vertical conduction device has better heat dissipation characteristics than the lateral device. Therefore, exploring a new type of vertical conduction device is expected to overcome the challenges of the power handling capability of the lateral device, and is an important topic in the academic and industrial fields.

[0003] In recent years, diamond field effect transistors (FETs) including metal semiconductor field effect transistors (MESFETs), metal-oxide-semiconductor field effect transistors (MOSFETs), and junction field effect transistors (JFETs) have been widely studied. Due to the lack of breakthrough in n-type doping of diamond materials, there are currently two types of devices: MOSFETs with a hydrogen-terminated surface two-dimensional hole gas as a channel and MESFETs with a p-type doped diamond as a channel. Among them, with the breakthrough of a series of key technologies such as highly stable Al2O3 gate dielectric layer, MOSFETs based on hydrogen-terminated surface two-dimensional hole gas channel have low gate leakage current and thermal stability, but the devices are mainly used in the fields of high fT / fmax and high power density microwave electronics and diamond logic circuits.

[0004] Diamond MESFETs and JFETs are mainly used as power switching devices. The metal or heterojunction gate controls the current between the drain and source electrodes by regulating the on-off of the semiconductor channel layer below the gate through the depletion layer under the action of bias voltage. In 1989, Shiomi et al. first confirmed the current modulation effect of an Al Schottky gate on a boron-doped p-type channel layer. However, the gate electrode does not achieve complete depletion of the channel and presents a normally-on working mode. In 2009, Pt was used as a Schottky gate to achieve a 1E 15 cm -3Diamond-based MESFETs exhibit good electrical characteristics over a temperature range of 200°C to 500°C. However, the threshold voltage remains at 2.1 V, indicating a normally-on operating mode. But the fail-safe aspect of power electronic circuits requires power switching devices to operate in a normally-off mode (channel is off at zero gate voltage). Threshold voltage regulation of MESFET devices faces significant challenges. On one hand, achieving lower forward on-resistance requires a thicker channel layer and a relatively high doping concentration. On the other hand, the high interface state density on the oxygen-terminated boron-doped diamond surface causes the Fermi level to be pinned at the metal / semiconductor interface (approximately 1.2 eV), and even with metals of different work functions, only similar Schottky barrier heights can be obtained. Therefore, the metal gate's ability to regulate the device's threshold voltage is relatively weak. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a longitudinally conducting normally-off diamond power transistor and its fabrication method. The longitudinally conducting normally-off diamond transistor is fabricated using a MOS structure depletion channel, thus avoiding the challenges faced in fabricating n-type doped diamond. Simultaneously, to reduce the on-resistance of the diamond power transistor and increase the threshold voltage, a highly doped low-resistance diamond layer is inserted into the high-resistance drift layer, while the low-doped high-resistance drift layer allows the device to withstand higher voltages.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a longitudinally conductive normally off diamond power transistor, comprising a p-type low-resistivity diamond single crystal substrate;

[0008] p-type high-resistivity diamond drift layer one is located on the upper surface of the p-type low-resistivity diamond single crystal substrate;

[0009] The p-type low-resistivity diamond insertion layer is located on the upper surface of the p-type high-resistivity diamond drift layer.

[0010] p-type high-resistivity diamond drift layer 2 is located on the upper surface of the p-type low-resistivity diamond insertion layer;

[0011] The p-type low-resistivity diamond cap layer is located on the upper surface of the p-type high-resistivity diamond drift layer 2.

[0012] Ohmic contact electrodes are located on the upper surface of the p-type low-resistivity diamond cap layer and the lower surface of the p-type low-resistivity diamond single crystal substrate.

[0013] A gate dielectric layer is located on the upper surface of the groove structure, which is formed by the two sides of the p-type low-resistivity diamond insertion layer, the p-type high-resistivity diamond drift layer II, the p-type low-resistivity diamond cap layer and the upper surface of the p-type high-resistivity diamond drift layer I.

[0014] The Schottky gate electrode is located on the surface of the gate dielectric layer.

[0015] Furthermore, the structure of a longitudinally conductive normally-off diamond power transistor provided by the present invention can also be: including a p-type low-resistivity diamond single crystal substrate;

[0016] p-type high-resistivity diamond drift layer one is located on the upper surface of the p-type low-resistivity diamond single crystal substrate;

[0017] The p-type low-resistivity diamond insertion layer and the low-concentration doped p-type high-resistivity drift layer are arranged alternately on top of each other. The upper surface of the p-type high-resistivity diamond drift layer is provided with the p-type low-resistivity diamond insertion layer, and the uppermost layer arranged alternately on top of each other is the p-type high-resistivity diamond drift layer.

[0018] The p-type low-resistivity diamond cap layer is located on the upper surface of the p-type high-resistivity diamond drift layer 2.

[0019] Ohmic contact electrodes are located on the upper surface of the p-type low-resistivity diamond cap layer and the lower surface of the p-type low-resistivity diamond single crystal substrate.

[0020] A gate dielectric layer is located on the upper surface of the groove structure, which is formed by the two sides of the p-type low-resistivity diamond insertion layer, the p-type high-resistivity diamond drift layer II, the p-type low-resistivity diamond cap layer and the upper surface of the p-type high-resistivity diamond drift layer I.

[0021] The Schottky gate electrode is located on the surface of the gate dielectric layer.

[0022] Secondly, the present invention provides a method for fabricating the above-mentioned longitudinally conductive normally-off diamond power transistor, comprising the following steps:

[0023] S1. Grow p-type high-resistivity diamond drift layer one, p-type low-resistivity diamond insertion layer, p-type high-resistivity diamond drift layer two, and p-type low-resistivity diamond cap layer sequentially on a p-type low-resistivity diamond single crystal substrate; or grow p-type high-resistivity diamond drift layer one on a p-type low-resistivity diamond single crystal substrate, then alternately grow p-type low-resistivity diamond insertion layer and p-type high-resistivity diamond drift layer two, and finally grow p-type low-resistivity diamond cap layer on the upper surface of p-type high-resistivity diamond drift layer two.

[0024] S2. A dielectric layer is deposited on the upper surface of the p-type low-resistivity diamond cap layer, and a pattern mask is formed by photolithography.

[0025] S3. Dry etching is performed on both sides of the structure obtained in step S2 to the upper surface of the p-type high-resistivity diamond drift layer to form a groove structure.

[0026] S4. A gate dielectric layer is deposited in the groove structure obtained in step S3, and the mask is removed at the same time;

[0027] S5. Deposit metal on the lower surface of the p-type low-resistivity diamond single crystal substrate and the upper surface of the p-type low-resistivity diamond cap layer to form an ohmic contact electrode.

[0028] S6. Deposit metal on the gate dielectric layer obtained in step S4 to form a Schottky gate electrode.

[0029] As a preferred embodiment of the technical solution of the present invention, in step S1, the p-type low-resistivity diamond single crystal substrate is a single crystal diamond or polycrystalline diamond obtained by homogeneous or heterogeneous epitaxy, and the boron doping concentration is 10. 19 ~10 21 cm -3 .

[0030] As a preferred embodiment of the technical solution of the present invention, in step S1, both the first p-type high-resistivity diamond drift layer and the second p-type high-resistivity diamond drift layer are boron-doped diamond epitaxial layers with a thickness of 10 nm to 20 μm, and low-concentration doping is used, with a boron doping concentration of 10 nm. 14 ~10 18 cm -3 10 preferred 14 ~10 16 cm -3 A low-concentration doped high-resistivity drift layer can enable the device to withstand higher voltages, thereby increasing the threshold voltage of the transistor.

[0031] As a preferred embodiment of the technical solution of the present invention, in step S1, the p-type low-resistivity diamond insertion layer is a single-layer or multi-layer boron-doped diamond epitaxial layer with a thickness of 10 nm to 20 μm, and the boron doping concentration can be 10 nm to 20 μm. 16 ~10 19 cm -3 Inserting a highly doped, low-resistivity diamond layer into a low-doped, high-resistivity drift layer can reduce the on-resistance of diamond power transistors.

[0032] As a preferred embodiment of the technical solution of the present invention, in step S1, the growth is carried out using one of microwave plasma chemical vapor deposition, DC plasma jet chemical vapor deposition, or pyrolysis chemical vapor deposition.

[0033] As a preferred embodiment of the technical solution of the present invention, in step S4, the gate dielectric layer is at least one of aluminum oxide, silicon oxide, and silicon nitride, and the thickness is 1 nm to 10 μm.

[0034] As a preferred embodiment of the present invention, in step S5, the ohmic contact electrode is made of one of Ti / Pt / Au alloy, Ti / Ni / Au alloy, or Ti / Mo / Au alloy; and the Schottky gate electrode is made of one of Zr / Au alloy, Pt / Au alloy, or W / Au alloy.

[0035] As a preferred embodiment of the technical solution of the present invention, in steps S5 and S6, the ohmic contact electrode and the Schottky gate electrode are formed by one of electron beam evaporation, physical vapor deposition or magnetron sputtering.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] This invention provides a high-performance longitudinally conducting diamond transistor and its fabrication method. The high-concentration doped low-resistance insertion layer in the multilayer composite epitaxial layer can reduce the on-resistance and increase the threshold voltage, while the low-concentration doped high-resistance drift layer can withstand higher voltages, thereby improving the lifespan of the transistor. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the device structure fabrication in step S1 of Embodiment 1 of the present invention;

[0039] Figure 2 This is a schematic diagram of the device structure fabrication in step S2 of Embodiment 1 of the present invention;

[0040] Figure 3 This is a schematic diagram of the device structure fabrication in step S3 of Embodiment 1 of the present invention;

[0041] Figure 4 This is a schematic diagram of the device structure fabrication in step S4 of Embodiment 1 of the present invention;

[0042] Figure 5 This is a schematic diagram of the device structure fabrication in step S5 of Embodiment 1 of the present invention;

[0043] Figure 6 This is a schematic diagram of the device structure fabrication in step S6 of Embodiment 1 of the present invention;

[0044] Figure 7 This is a schematic diagram of the device structure provided in Embodiment 2 of the present invention.

[0045] Among them, 1. p-type low-resistivity diamond single crystal substrate; 2. p-type high-resistivity diamond drift layer one; 3. p-type low-resistivity diamond insertion layer; 4. p-type high-resistivity diamond drift layer two; 5. p-type low-resistivity diamond cap layer; 6. gate dielectric layer; 7. ohmic contact electrode; 8. Schottky gate electrode. Detailed Implementation

[0046] The present invention will now be described in detail with reference to specific accompanying drawings and embodiments. The examples described below are merely preferred embodiments of the present invention. It should be noted that the following description is only for explaining the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.

[0047] This invention provides a method for fabricating a longitudinally conductive normally-off diamond power transistor, which generally includes the following steps:

[0048] S1. Provide a p-type low-resistivity diamond single crystal substrate 1, and grow a multilayer composite epitaxial layer on its surface;

[0049] S2. Using photolithography, the area outside the ohmic contact is exposed on the mask layer;

[0050] S3. A groove structure is formed by dry etching with the aid of a mask pattern;

[0051] S4, Deposited gate dielectric layer 6;

[0052] S5. Deposit metal to form ohmic contact electrode 7;

[0053] S6. Deposit metal to form Schottky gate electrode 8.

[0054] In the above technical solution, in step S2, the photoresist is a positive or negative photoresist; in step S3, the groove etching is inductively coupled plasma (ICP) or reactive ion etching (RIE), and the reactive gas is Cl2, BCl3, O2, or a mixture thereof.

[0055] More specifically, see Figures 1-6 The above preparation method includes the following steps:

[0056] S1. On a p-type low-resistivity diamond single crystal substrate 1, a p-type high-resistivity diamond drift layer 1 2, a p-type low-resistivity diamond insertion layer 3, a p-type high-resistivity diamond drift layer 2 4, and a p-type low-resistivity diamond cap layer 5 are grown sequentially; or, after growing a p-type high-resistivity diamond drift layer 1 2 on a p-type low-resistivity diamond single crystal substrate 1, a p-type low-resistivity diamond insertion layer 3 and a p-type high-resistivity diamond drift layer 2 4 are grown alternately, and finally a p-type low-resistivity diamond cap layer 5 is grown on the upper surface of the p-type high-resistivity diamond drift layer 2 4.

[0057] S2. A dielectric layer is deposited on the surface of the p-type low-resistivity diamond cap layer 5, and a pattern mask is formed by photolithography.

[0058] S3. Dry etching is performed on both sides of the structure obtained in step S2 to the upper surface of the p-type high-resistivity diamond drift layer 2 to form a groove structure.

[0059] S4. Deposit a gate dielectric layer 6 in the groove structure obtained in step S3, and remove the mask at the same time.

[0060] S5. Deposit metal on the lower surface of the p-type low-resistivity diamond single crystal substrate 1 and the p-type low-resistivity diamond cap layer 5 to form an ohmic contact electrode 7.

[0061] S6. Deposit metal on the gate dielectric layer 6 obtained in step S4 to form a Schottky gate electrode 8.

[0062] In the above technical solution, the low-resistivity diamond intercalation layer is used to increase the threshold voltage of the device and reduce the on-resistance to a certain extent. Combined with the high-resistivity drift layer, it is beneficial to achieve high withstand voltage capability of the device. In the above preparation method, the p-type low-resistivity diamond intercalation layer 3 does not need to interrupt the epitaxial growth, its spatial position is adjustable, and multiple layers can be added as needed. That is, in step S1, when both the p-type low-resistivity diamond intercalation layer 3 and the p-type high-resistivity diamond drift layer 4 are single layers, only one growth is required; when both the p-type low-resistivity diamond intercalation layer 3 and the p-type high-resistivity diamond drift layer 4 are multiple layers, multiple epitaxial growths are required.

[0063] Based on the above preparation method, when both the p-type low-resistivity diamond insertion layer 3 and the p-type high-resistivity diamond drift layer 4 are single layers, the structure of the obtained longitudinally conductive conventional diamond power transistor is as follows: Figure 6 This is illustrated, specifically including a p-type low-resistivity diamond single-crystal substrate 1;

[0064] p-type high-resistivity diamond drift layer 2 is located on the upper surface of the p-type low-resistivity diamond single crystal substrate 1;

[0065] p-type low-resistivity diamond insertion layer 3 is located on the upper surface of the p-type high-resistivity diamond drift layer 2;

[0066] p-type high-resistivity diamond drift layer 4 is located on the upper surface of p-type low-resistivity diamond insertion layer 3;

[0067] p-type low-resistivity diamond cap layer 5 is located on the upper surface of the p-type high-resistivity diamond drift layer 4;

[0068] Ohmic contact electrode 7 is located on the upper surface of the p-type low-resistivity diamond cap layer 5 and the lower surface of the p-type low-resistivity diamond single crystal substrate 1.

[0069] The gate dielectric layer 6 is located on the upper surface of the groove structure, which is formed by the two sides of the p-type low-resistivity diamond insertion layer 3, the p-type high-resistivity diamond drift layer 2 4, the p-type low-resistivity diamond cap layer 5 and the upper surface of the p-type high-resistivity diamond drift layer 2.

[0070] Schottky gate electrode 8 is located on the surface of the gate dielectric layer 6.

[0071] Based on the above preparation method, when both the p-type low-resistivity diamond insertion layer 3 and the p-type high-resistivity diamond drift layer 4 are multilayered, the structure of the obtained longitudinally conductive conventional diamond power transistor is as follows: Figure 7 The illustration includes a p-type low-resistivity diamond single crystal substrate 1;

[0072] p-type high-resistivity diamond drift layer 2 is located on the upper surface of the p-type low-resistivity diamond single crystal substrate 1;

[0073] The p-type low-resistivity diamond insertion layer 3 and the p-type high-resistivity diamond drift layer 4 are arranged alternately on top of each other. The p-type low-resistivity diamond insertion layer 3 is arranged on the upper surface of the p-type high-resistivity diamond drift layer 2, and the p-type high-resistivity diamond drift layer 4 is arranged alternately on top of each other.

[0074] p-type low-resistivity diamond cap layer 5 is located on the upper surface of the p-type high-resistivity diamond drift layer 4;

[0075] Ohmic contact electrode 7 is located on the upper surface of the p-type low-resistivity diamond cap layer 5 and the lower surface of the p-type low-resistivity diamond single crystal substrate 1.

[0076] The gate dielectric layer 6 is located on the upper surface of the groove structure, which is formed by the two sides of the p-type low-resistivity diamond insertion layer 3, the p-type high-resistivity diamond drift layer 2 4, the p-type low-resistivity diamond cap layer 5 and the upper surface of the p-type high-resistivity diamond drift layer 2.

[0077] Schottky gate electrode 8 is located on the surface of the gate dielectric layer 6.

[0078] That is, multiple layers of p-type low-resistivity diamond insertion layer 3 and p-type high-resistivity diamond drift layer 4 are alternately arranged, with the bottom layer being p-type low-resistivity diamond insertion layer 3 and the top layer being p-type high-resistivity diamond drift layer 4, and the number of both is the same.

[0079] In some embodiments, in step S1, the p-type low-resistivity diamond single-crystal substrate 1 is a single-crystal diamond or polycrystalline diamond obtained by homo- or hetero-epitaxial growth, with a thickness of 10 nm to 50 μm and a boron doping concentration of 10. 19 ~10 21 cm -3 .

[0080] In some embodiments, in step S1, both the p-type high-resistivity diamond drift layer 2 and the p-type high-resistivity diamond drift layer 4 are boron-doped diamond epitaxial layers with a thickness of 10 nm to 20 μm and a boron doping concentration of 10. 14 ~10 16 cm -3.

[0081] In some embodiments, in step S1, the p-type low-resistivity diamond insertion layer 3 is a single-layer or multi-layer boron-doped diamond epitaxial layer with a thickness of 10 nm to 20 μm, and the boron doping concentration can be 10 nm. 16 ~10 19 cm -3 .

[0082] In some embodiments, in step S1, the thickness of the p-type low-resistivity diamond cap layer 5 is 10 nm to 10 μm, and the boron doping concentration is 10. 16 ~10 19 cm -3 .

[0083] In some embodiments, the thickness of the gate dielectric layer 6 is 1 nm to 10 μm.

[0084] In some embodiments, step S1 involves growth using one of microwave plasma chemical vapor deposition (MPCVD), direct current plasma jet chemical vapor deposition (DC-PCVD), or pyrolysis chemical vapor deposition (TVCD). MPCVD utilizes microwave plasma to activate reactive gases, promoting chemical reactions on or near the surface of a substrate to form a solid film. DC-PCVD uses a high-voltage DC negative bias (-1~-5kV) to induce glow discharge in low-pressure reactive gases, generating plasma which bombards the workpiece under an electric field, depositing a film on the workpiece surface. TVCD uses high temperature to activate chemical reactions for vapor phase growth. All of these methods are prior art, and this invention does not describe or limit their specific processes or procedures; the methods described are intended to be feasible for those skilled in the art.

[0085] In some embodiments, in step S1, the p-type low-resistivity diamond single crystal substrate 1 can be a single crystal or polycrystalline diamond substrate synthesized by high temperature and high pressure or chemical vapor deposition.

[0086] In some embodiments, in step S4, the gate dielectric layer 6 is at least one of aluminum oxide, silicon oxide, and silicon nitride, with a thickness of 1 nm to 10 μm.

[0087] In some embodiments, in step S5, the ohmic contact electrode 7 is made of one of Ti / Pt / Au alloy, Ti / Ni / Au alloy, or Ti / Mo / Au alloy; and the Schottky gate electrode 8 is made of one of Zr / Au alloy, Pt / Au alloy, or W / Au alloy.

[0088] In some embodiments, in steps S5 and S6, the ohmic contact electrode 7 and the Schottky gate electrode 8 are formed using one of electron beam evaporation, physical vapor deposition, or magnetron sputtering.

[0089] Example 1

[0090] See Figures 1-6 A method for fabricating a longitudinally conductive, normally closed diamond power transistor includes the following steps:

[0091] S1. Using microwave plasma chemical vapor deposition, a p-type high-resistivity diamond drift layer 1, a p-type low-resistivity diamond insertion layer 3, a p-type high-resistivity diamond drift layer 2, and a p-type low-resistivity diamond cap layer 5 are sequentially grown on a p-type low-resistivity diamond single crystal substrate 1.

[0092] S2. Photoresist is spin-coated onto the upper surface of the p-type low-resistivity diamond cap layer 5, and a pattern mask is formed by photolithography.

[0093] S3. Perform oxygen plasma dry etching on both sides of the structure obtained in step S2 to the upper surface of the p-type high-resistivity diamond drift layer 2 to form a groove structure.

[0094] S4. A silicon oxide gate dielectric layer 6 is deposited in the groove structure obtained in step S3, and the mask is removed at the same time.

[0095] S5. Using physical vapor deposition, metal is deposited on the lower surface of the p-type low-resistivity diamond single crystal substrate 1 and the upper surface of the p-type low-resistivity diamond cap layer 5 to form an ohmic contact electrode 7 (material is Ti / Pt / Au alloy).

[0096] S6. Using physical vapor deposition, metal is deposited on the gate dielectric layer 6 obtained in step S4 to form a Schottky gate electrode 8 (material is W / Au alloy).

[0097] Example 2

[0098] Compared with Example 1, in this example, both the p-type low-resistivity diamond insertion layer 3 and the p-type high-resistivity diamond drift layer 4 are multilayered, while the rest are the same. For the specific structure, please refer to [link to specific details]. Figure 7 As shown.

[0099] Finally, it should be noted that the above embodiments do not limit the present invention in any way. Those skilled in the art can make modifications and improvements based on the present invention. Therefore, any modifications or improvements made without departing from the spirit of the present invention are within the scope of protection claimed by the present invention.

Claims

1. A longitudinally conductive normally-off diamond power transistor, characterized in that, From bottom to top, the layers are: p-type low-resistivity diamond single crystal substrate (1), p-type high-resistivity diamond drift layer one (2), p-type low-resistivity diamond insertion layer (3), p-type high-resistivity diamond drift layer two (4), p-type low-resistivity diamond cap layer (5), gate dielectric layer (6), ohmic contact electrode (7), and Schottky gate electrode (8).

2. The longitudinally conductive normally-off diamond power transistor according to claim 1, characterized in that, The p-type low-resistivity diamond insert layer (3) is a single-layer or multi-layer structure.

3. A method for fabricating a longitudinally conductive normally-off diamond power transistor as described in claim 1 or 2, characterized in that, Includes the following steps: S1. On a p-type low-resistivity diamond single crystal substrate (1), a p-type high-resistivity diamond drift layer 1 (2), a p-type low-resistivity diamond insertion layer (3), a low-concentration doped p-type high-resistivity drift layer 2 (4), and a p-type low-resistivity diamond cap layer (5) are grown sequentially; or, after growing a p-type high-resistivity diamond drift layer 1 (2) on a p-type low-resistivity diamond single crystal substrate (1), the p-type low-resistivity diamond insertion layer (3) and the low-concentration doped p-type high-resistivity drift layer 2 (4) are grown again, and finally a p-type low-resistivity diamond cap layer (5) is grown on the surface of the low-concentration doped p-type high-resistivity drift layer 2 (4). S2. A dielectric layer is deposited on the upper surface of the p-type low-resistivity diamond cap layer (5), and a pattern mask is formed by photolithography. S3. Dry etching is performed on both sides of the structure obtained in step S2 to the upper surface of the p-type high-resistivity diamond drift layer (2) to form a groove structure. S4. A gate dielectric layer (6) is deposited in the groove structure obtained in step S3, and the mask is removed at the same time. S5. Deposit metal on the lower surface of the p-type low-resistivity diamond single crystal substrate (1) and the upper surface of the p-type low-resistivity diamond cap layer (5) to form an ohmic contact electrode (7). S6. Deposit metal on the gate dielectric layer (6) obtained in step S4 to form a Schottky gate electrode (8).

4. The preparation method according to claim 3, characterized in that, In step S1, the p-type low-resistivity diamond single crystal substrate (1) is a single crystal diamond or polycrystalline diamond obtained by homo- or hetero-epitaxial growth, with a boron doping concentration of 10. 19 ~10 21 cm -3 .

5. The preparation method according to claim 3, characterized in that, In step S1, both the first p-type high-resistivity diamond drift layer (2) and the second low-concentration doped p-type high-resistivity drift layer (4) are boron-doped diamond epitaxial layers with a thickness of 10 nm to 20 μm and a boron doping concentration of 10. 14 ~10 18 cm -3 .

6. The preparation method according to claim 3, characterized in that, In step S1, the p-type low-resistivity diamond insertion layer (3) is a single-layer or multi-layer boron-doped diamond epitaxial layer with a thickness of 10 nm to 20 μm and a boron doping concentration of up to 10 nm. 16 ~10 19 cm -3 .

7. The preparation method according to claim 3, characterized in that, In step S1, the growth is performed using one of the following methods: microwave plasma chemical vapor deposition, direct current plasma jet chemical vapor deposition, or pyrolysis chemical vapor deposition.

8. The preparation method according to claim 3, characterized in that, In step S4, the gate dielectric layer (6) is at least one of aluminum oxide, silicon oxide, and silicon nitride, with a thickness of 1 nm to 10 μm.

9. The preparation method according to claim 3, characterized in that, In step S5, the ohmic contact electrode (7) is made of one of Ti / Pt / Au alloy, Ti / Ni / Au alloy or Ti / Mo / Au alloy; the Schottky gate electrode (8) is made of one of Zr / Au alloy, Pt / Au alloy or W / Au alloy.

10. The preparation method according to claim 3, characterized in that, In steps S5 and S6, the ohmic contact electrode (7) and the Schottky gate electrode (8) are formed by one of electron beam evaporation, physical vapor deposition or magnetron sputtering.

Images