Semiconductor device and preparation method thereof, and electronic equipment
By introducing a high-k dielectric layer surrounding the gate electrode of the transistor in the 2T0C structure memory device, the problem of insufficient data storage capacity is solved, parasitic capacitance is improved, and the reliability and stability of the device are guaranteed.
Patent Information
- Application Number
- CN202411045905.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2026-02-06
AI Technical Summary
The lack of independent capacitors in existing 2T0C structure memory devices leads to insufficient data storage capacity, and shortening the gate-source spacing to increase parasitic capacitance will reduce the long-term stability and reliability of the device.
In semiconductor devices, a high-k dielectric layer is introduced to surround the gate electrode of the transistor and increase parasitic capacitance without changing the physical spacing. This is achieved by depositing high-k dielectric material in the trench and performing planarization to form a high-k dielectric layer surrounding the gate to enhance parasitic capacitance.
This improves the data storage capability of semiconductor devices while maintaining their long-term stability and reliability, thus enhancing their performance.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to, but is not limited to, semiconductor structure and processing technology, in particular to a semiconductor device and a preparation method thereof, and an electronic device. BACKGROUND
[0002] With the development of integrated circuit technology, the critical dimension of the device is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that a slight difference in process production may affect the performance of the device.
[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY
[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
[0005] The present application provides a semiconductor device and a preparation method thereof, and an electronic device, which can improve the data storage capacity of the semiconductor device and ensure the reliability of the device.
[0006] The embodiment of the present application provides a preparation method of a semiconductor device, comprising:
[0007] forming a first structure provided with a second conductive layer on a substrate;
[0008] generating an initial first high-K dielectric layer at a position corresponding to a first transistor on the first structure to form a second structure;
[0009] etching the second structure to form a first transistor, so that the initial first high-K dielectric layer after etching is arranged between a first gate electrode of the first transistor and the second conductive layer as a first high-K dielectric layer, and the first high-K dielectric layer surrounds a first semiconductor layer of the first transistor;
[0010] forming a second transistor.
[0011] In an exemplary example, the etching the second structure to form a first transistor further comprises:
[0012] arranging a second high-K dielectric layer surrounding the first gate electrode to form a third structure.
[0013] In an exemplary example, the generating an initial first high-K dielectric layer comprises:
[0014] forming an isolation layer on the first structure; performing selective etching on the formed isolation layer to obtain a trench at a position corresponding to a position where the first transistor is to be disposed; and depositing a high-K dielectric material in the etched trench to form the initial first high-K dielectric layer.
[0015] In an example embodiment, a radius of the trench is greater than a target size of the radius of the trench, and a difference between the radius of the trench and the target size is within a preset range relative to the target size.
[0016] In an example embodiment, the forming of the initial first high-K dielectric layer comprises:
[0017] depositing a high-K dielectric layer on the position corresponding to the first transistor, and performing etching on the formed high-K dielectric layer to reserve a portion of the high-K dielectric layer as the initial first high-K dielectric layer at the position corresponding to the first transistor; and then depositing an isolation layer and performing planarization.
[0018] In an example embodiment, a radius of the reserved portion of the high-K dielectric layer is greater than a target size of the radius of the initial first high-K dielectric layer, and a difference between the radius of the reserved portion of the high-K dielectric layer and the target size is within a preset range relative to the target size.
[0019] In an example embodiment, the disposing of the second high-K dielectric layer surrounding the first gate electrode comprises:
[0020] performing patterned etching on the isolation layer around the first gate electrode, with the first high-K dielectric layer as a boundary away from an edge of the first semiconductor layer, to form an annular groove surrounding the first gate electrode;
[0021] depositing a high-K dielectric material in the etched annular groove to form the second high-K dielectric layer, and performing planarization to obtain the third structure.
[0022] In an example embodiment, the forming of the first structure with the second conductive layer disposed on the substrate comprises:
[0023] depositing an isolation layer on the substrate, depositing a first conductive layer on the isolation layer and performing patterned etching, and continuing to grow the isolation layer on the first conductive layer and performing surface planarization;
[0024] growing the second conductive layer on the planarized isolation layer and performing patterned etching;
[0025] forming the first structure.
[0026] In an example embodiment, the forming of the second transistor comprises:
[0027] forming a third conductive layer on the structure of the first transistor or the third structure and growing an isolation layer to form a fourth structure;
[0028] forming the second transistor on the fourth structure at a position corresponding to the first transistor, the second transistor being vertically arranged and connected with the first transistor.
[0029] In an exemplary example, the high-K dielectric material includes hafnium dioxide HfO2, or at least one of aluminum oxide Al2O3, titanium oxide TiO2, and zirconium oxide ZrO2.
[0030] Embodiments of the present application also provide a semiconductor device, including a memory cell array composed of at least one memory cell; each memory cell including a first transistor and a second transistor;
[0031] The first transistor includes a first semiconductor layer, a first gate electrode, and a second conductive layer, a first high-K dielectric layer being arranged between the first gate electrode and the second conductive layer, the first high-K dielectric layer surrounding the first semiconductor layer.
[0032] The second transistor includes a second semiconductor layer, the second semiconductor layer being connected with the first gate electrode.
[0033] In an exemplary example, each memory cell further includes a second high-K dielectric layer arranged to surround the first gate electrode.
[0034] In an exemplary example, the second conductive layer is connected with the first semiconductor layer, the connection forming a second source / drain of the first transistor.
[0035] The memory cell further includes:
[0036] A first conductive layer, connected with the first semiconductor layer, the connection forming a first source / drain of the first transistor.
[0037] The second conductive layer is located between the first gate electrode and the first conductive layer.
[0038] A third conductive layer, connected with the second semiconductor layer.
[0039] In an exemplary example, in a direction parallel to the substrate, the first conductive layer and the second conductive layer are connected with a plurality of the first transistors arranged at intervals.
[0040] The third conductive layer is connected with a plurality of the second transistors arranged at intervals.
[0041] The embodiment of the present application further provides an electronic device comprising the semiconductor device formed by the preparation method of any one of the semiconductor devices or the semiconductor device of any one of the semiconductor devices.
[0042] The semiconductor device provided by the embodiment of the present application comprises a memory cell array composed of at least one memory cell; each memory cell comprises a first transistor and a second transistor; the first transistor comprises a first semiconductor layer, a first gate electrode and a second conductive layer, a first high-K dielectric layer is arranged between the first gate electrode and the second conductive layer, and the first high-K dielectric layer surrounds the first semiconductor layer; the second transistor comprises a second semiconductor layer, and the second semiconductor layer is connected with the first gate electrode. The embodiment of the present application increases the parasitic capacitance between the gate electrode of the first transistor and the second conductive layer by improving the dielectric constant between the first gate electrode and the second conductive layer of the first transistor, thereby improving the data storage capacity of the semiconductor device and ensuring the reliability of the device.
[0043] Further, the first transistor in the embodiment of the present application further comprises a second high-K dielectric layer arranged around the first gate electrode of the first transistor. The high-K dielectric layer is made around the gate electrode to make the space from the first gate electrode to the second conductive layer of the first transistor be high-K dielectric, and the K value of the dielectric layer around the gate electrode of the first transistor is improved without changing the physical distance between the gate electrode of the first transistor and the second conductive layer, thereby increasing the parasitic capacitance between the gate electrode of the first transistor and the second conductive layer, and further improving the storage charge of the semiconductor device.
[0044] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by means of the structures particularly pointed out in the description, the claims and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS
[0045] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used to explain the technical scheme of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical scheme of the present application.
[0046] Figure 1 It is a typical circuit schematic diagram of a 2T0C memory cell;
[0047] Figure 2 It is a flowchart of the preparation method of the semiconductor device in the embodiment of the present application;
[0048] Fig. 3(a) is a schematic diagram of process one in the preparation process of the semiconductor device in the embodiment of the present application;
[0049] Figure 3(b) is a schematic diagram of process two in the preparation of the semiconductor device according to an embodiment of the application;
[0050] Figure 3(c) is a schematic diagram of process three in the preparation of the semiconductor device according to an embodiment of the application;
[0051] Figure 3(d) is a schematic diagram of process four in the preparation of the semiconductor device according to an embodiment of the application;
[0052] Figure 3(e) is a schematic diagram of process five in the preparation of the semiconductor device according to an embodiment of the application;
[0053] Figure 3(f) is a schematic diagram of process six in the preparation of the semiconductor device according to an embodiment of the application;
[0054] Figure 3(g1) is a schematic diagram of one implementation of process seven in the preparation of the semiconductor device according to an embodiment of the application;
[0055] Figure 3(h1) is a schematic diagram of one implementation of process eight in the preparation of the semiconductor device according to an embodiment of the application;
[0056] Figure 3(i1) is a schematic diagram of one implementation of process nine in the preparation of the semiconductor device according to an embodiment of the application;
[0057] Figure 3(g2) is a schematic diagram of another implementation of process seven in the preparation of the semiconductor device according to an embodiment of the application;
[0058] Figure 3(h2) is a schematic diagram of another implementation of process eight in the preparation of the semiconductor device according to an embodiment of the application;
[0059] Figure 3(j) is a schematic diagram of process ten in the preparation of the semiconductor device according to an embodiment of the application;
[0060] Figure 3(k) is a schematic diagram of process eleven in the preparation of the semiconductor device according to an embodiment of the application;
[0061] Figure 3(l) is a schematic diagram of process twelve in the preparation of the semiconductor device according to an embodiment of the application;
[0062] Figure 3(m) is a schematic diagram of process thirteen in the preparation of the semiconductor device according to an embodiment of the application;
[0063] Figure 3(n) is a schematic diagram of process fourteen in the preparation of the semiconductor device according to an embodiment of the application;
[0064] Figure 3(o) is a schematic diagram of process fifteen in the preparation of the semiconductor device according to an embodiment of the application;
[0065] Figure 3(p) is a schematic diagram of process sixteen in the preparation of the semiconductor device according to an embodiment of the application;
[0066] Fig. 3(q) is a schematic view of process seventeen in the preparation of a semiconductor device according to embodiments of the present application;
[0067] Fig. 3(r) is a schematic view of process eighteen in the preparation of a semiconductor device according to embodiments of the present application;
[0068] Fig. 3(s) is a schematic view of process nineteen in the preparation of a semiconductor device according to embodiments of the present application;
[0069] Fig. 3(t) is a schematic view of process twenty in the preparation of a semiconductor device according to embodiments of the present application;
[0070] Fig. 3(u) is a schematic view of process twenty-one in the preparation of a semiconductor device according to embodiments of the present application;
[0071] Fig. 3(v) is a schematic view of process twenty-two in the preparation of a semiconductor device according to embodiments of the present application;
[0072] Fig. 3(w) is a schematic view of process twenty-three in the preparation of a semiconductor device according to embodiments of the present application;
[0073] Fig. 3(x) is a schematic view of process twenty-four in the preparation of a semiconductor device according to embodiments of the present application;
[0074] Fig. 3(y) is a schematic view of process twenty-five in the preparation of a semiconductor device according to embodiments of the present application;
[0075] Figure 4 Fig. 4 is another schematic view of a process flow for the preparation of a semiconductor device according to embodiments of the present application;
[0076] Fig. 5(a) is a schematic view of the principle of parasitic capacitance improvement according to embodiments of the present application;
[0077] Fig. 5(b) is a schematic view of the principle of parasitic capacitance improvement according to embodiments of the present application. DETAILED DESCRIPTION
[0078] The embodiments of the present application will be described in detail with reference to the drawings. The features of the embodiments of the present application and the embodiments can be combined with each other unless they conflict.
[0079] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the commonly understood meanings by those skilled in the art to which the present application belongs.
[0080] The embodiments of the present application are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values shown in the drawings.
[0081] The ordinal numbers "first", "second", "third" and the like in the present application are set in order to avoid confusion of the components, and do not indicate any order, number, or importance.
[0082] In the present application, the words of indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings in order to facilitate the description of the present specification and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.
[0083] In the present application, unless explicitly specified and limited, the terms "mount", "connect", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. The specific meaning of the above terms in the present disclosure can be understood by the person skilled in the art according to the specific situation.
[0084] In the present application, the transistor refers to an element including at least three terminals of gate electrode, drain electrode and source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region and the source electrode. In the present disclosure, the channel region refers to the region through which the current mainly flows.
[0085] In the present application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is -10° or more and 10° or less, so it also includes the state that the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is 80° or more and 100° or less, so it also includes the state that the angle is 85° or more and 95° or less.
[0086] As used herein, "A and B are disposed in the same layer" means that A and B are formed at the same time by the same patterning process. "The orthographic projection of B is within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.
[0087] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as breaks or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.
[0088] In 2TOC memory devices, two transistors serve as write and read transistors, respectively. Since there are no independent capacitors in the 2TOC structure, data storage relies on the parasitic capacitance formed by the transistors and their interconnection structure. Therefore, improving the data storage capacity of 2TOC memory is a pressing technical problem that needs to be solved.
[0089] The 2T0C structure consists of two transistors (2T) and no capacitor (0C). In a 2T0C memory device, the two transistors serve as the write transistor and the read transistor, respectively. The write transistor is used to write data to the memory node. It controls the data writing process by turning its gate voltage on or off. The read transistor is used to read data from the memory node. It retrieves data by reading changes in the gate voltage. 2T0C memory devices are suitable for applications such as cache, embedded memory, mobile devices like smartphones and tablets, graphics processing unit (GPU) memory, IoT devices, high-performance computing and servers, neural networks, and AI accelerators.
[0090] Figure 1 This is a circuit diagram of a typical 2T0C memory cell, such as... Figure 1 As shown, transistor T2 controls the write operation and is connected to the write bit line (WBL) and write word line (WWL). Transistor T1 controls the read operation and is connected to the read bit line (RBL) and read word line (RWL). The storage node is the connection point between transistors T2 and T1, used to store charge, representing the stored data bits. During a write operation, WWL is activated, turning on transistor T2. Data (high or low level) is applied through WBL, and charge is stored in the storage node through transistor T2. After the write operation is complete, WWL is turned off, transistor T2 is turned off, and the storage node retains the written data. During a read operation, RWL is activated, turning on transistor T1. The charge state of the storage node is read through RBL to obtain the stored data bits (high or low level). After the read operation is complete, RWL is turned off, transistor T1 is turned off, and the storage node continues to retain the data.
[0091] 2T0C structure does not have an independent capacitor, and relies on the parasitic capacitor formed by the transistor and its interconnection structure to store data. On the one hand, due to the absence of an independent capacitor, the 2T0C structure can achieve higher integration, which is suitable for very large scale integrated circuit (VLSI) design, and, on the other hand, the process of reducing the charging and discharging of the capacitor helps to reduce power consumption, which is suitable for mobile devices and other energy-sensitive applications; on the other hand, two transistors are respectively independently controlled in the read and write processes, which can realize fast data read and write operation, and improve the performance of the memory. Compared with the traditional memory structure (such as the 1T1C structure in DRAM) which needs an independent capacitor, the device of the 2T0C structure is simpler and has lower manufacturing cost.
[0092] In practical applications, in order to improve the data storage capacity, it is necessary to increase the parasitic capacitance at the storage node. Generally, the method of increasing the parasitic capacitance is to shorten the physical distance between the gate and the source of the read transistor, which will continuously reduce the height of the dielectric layer between the gate and the read transistor, and the lower height of the dielectric layer will cause a higher electric field strength, thereby increasing the risk of leakage current and dielectric breakdown, thereby reducing the long-term stability and performance of the device, and affecting the reliability of the device.
[0093] In order to improve the data storage capacity of the semiconductor device and maintain the long-term stability and performance of the device, ensure the reliability of the device, the embodiments of the present application propose a preparation method of a semiconductor device, as shown in Figure 2 The preparation method can include:
[0094] Step 200: forming a first structure provided with a second conductive layer on a substrate.
[0095] In an exemplary example, step 200 can include:
[0096] Depositing an isolation layer on the substrate, depositing a first conductive layer on the isolation layer and performing patterned etching, and continuing to grow the isolation layer above the first conductive layer and performing surface planarization treatment;
[0097] Growth of a second conductive layer on the planarized isolation layer and patterned etching to form a first structure.
[0098] In an exemplary example, the first conductive layer can be a read bit line layer or a read word line layer, and the second conductive layer can be a read word line layer or a read bit line layer accordingly.
[0099] In an exemplary example, step 200 can include:
[0100] As shown in Figures 3(a)-3(c) , an isolation layer 31 is deposited on a substrate 30, a first conductive layer 321 is deposited on the isolation layer 31 and patterned etching is performed, and the isolation layer 31 is continued to grow above the first conductive layer 321 and surface planarization treatment is performed.
[0101] In one embodiment, the substrate 30 serves as a support component for a semiconductor device, supporting other components disposed thereon. The substrate 30 can be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other III-V group compounds. Taking Si as an example, an oxide layer, such as silicon oxide (SiO2), can be grown on the Si substrate 30 using methods such as thermal oxidation or chemical vapor deposition (CVD) to form an isolation layer 31. This oxide layer provides electrical insulation and isolation.
[0102] In one embodiment, a first conductive layer 321 can be grown on an oxide layer using physical vapor deposition (PVD) or CVD methods. The first conductive layer 321 can be a metallic material such as tungsten (W), aluminum (Al), titanium nitride (TiN), molybdenum (Mo), or molybdenum nitride (MoN). Subsequently, the first conductive layer 321 can be patterned using photolithography and etching processes. Taking a read line layer as an example, the metal layer is etched according to the designed read line pattern.
[0103] In one embodiment, an oxide layer, such as silicon oxide (SiO2), is grown over the first conductive layer 321 to form a new insulating layer 31. This oxide layer is used to isolate electrical connections between the conductive layers. Subsequently, this oxide layer can be planarized using chemical mechanical planarization (CMP) technology to ensure a smooth and flat surface.
[0104] like Figures 3(d)-3(f) As shown, a second conductive layer 322 can be grown on a planarized oxide layer using PVD or CVD methods and then patterned and etched. The second conductive layer 322 can be made of a metallic material such as tungsten, aluminum, titanium nitride, molybdenum, or molybdenum nitride. Subsequently, a photolithographic pattern can be formed on the second conductive layer 322 using a photolithography process. Taking the second conductive layer as a readout line layer as an example, the position and shape of the readout lines are defined. As shown in Figure 3(d), in one embodiment, a hard mask (HM) and an intermediate layer such as silicon oxynitride (SION) photoresist are deposited sequentially upwards on the second conductive layer; this will not be elaborated further here. The second conductive layer 322 is then patterned using an etching process (such as dry etching or wet etching), etching the metal layer into the designed readout line pattern. As shown in Figure 3(f), an isolation layer, such as an oxide layer, is continued to grow, and the surface height of the isolation layer, such as the oxide layer, is controlled to be flush with the surface of the second conductive layer to form the first structure.
[0105] Step 201: On the first structure, at a position corresponding to the first transistor, an initial first high-K dielectric layer is formed to form a second structure.
[0106] In an exemplary embodiment, forming the initial first high-K dielectric layer on the first structure at a position corresponding to the first transistor can include:
[0107] The initial first high-K dielectric layer can be formed by a Damascene fill high-K dielectric material approach, such as Figures 3(g1)-3(i1) As shown in FIG. 3(i1), on the first structure, a layer of isolation layer, such as a layer of oxide 31, is continued to grow; at a position corresponding to the first transistor hole, the formed oxide layer is selectively etched to obtain a trench 32a; and in the etched trench 32a, a high-K dielectric material is deposited to form an initial first high-K dielectric layer 34.
[0108] In an embodiment, a layer of oxide, such as SiO2, is continued to grow on the first structure to form a new isolation layer 31 for electrical insulation and isolation. Then, the layer of oxide can be planarized by using a CMP technique to ensure smoothness of the surface.
[0109] In an exemplary embodiment, the trench 32a can be etched on the planarized oxide layer at a position corresponding to the first transistor by a selective etching technique. In order to improve the parasitic capacitance without affecting the density of the memory array, the radius of the trench 32a is slightly larger than the initial design etching size (IZ1 etch CD), that is, the radius of the trench 32a is greater than the target size of the trench 32a given in the initial design, and the difference between the radius of the trench 32a and the initial design etching size is within a preset range compared to the initial design etching size. In an embodiment, the range of CD increase is within a preset range of greater than or equal to 5% and less than or equal to 36%, denoted as [5%, 36%], that is, the actual etched trench 32a has a radius of 5% to 36% larger than the design size. Assuming the design size radius is 100 nanometers, the actual etched trench 32a can have a radius of 105 nanometers to 136 nanometers.
[0110] In an embodiment, as shown in FIG. 3(i1), the high-k material can be deposited in the etched trench 32a by CVD or atomic layer deposition (ALD) method to form the initial first high-K dielectric layer 34. In an embodiment, the high-k material can include but is not limited to hafnium dioxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), zirconium oxide (ZrO2), etc. Then, the initial first high-K dielectric layer 34 can be planarized by using a CMP technique to ensure smoothness of the surface.
[0111] In this embodiment of the application, by filling the trench 32a with high-k dielectric material to form an initial first high-k dielectric layer 34, the dielectric constant between the gate of the first transistor and the second conductive layer can be increased, thereby increasing the data storage capability of the semiconductor device by increasing parasitic capacitance, and thus optimizing the electrical performance of the semiconductor device.
[0112] In one exemplary instance, generating an initial first high-k dielectric layer on the first structure at the location corresponding to the first transistor may include:
[0113] An initial first high-k dielectric layer 34 can be generated by depositing a planar high-k dielectric material and using a patterned etching technique, as shown in Figures 3(g2) and 3(h2). A high-k dielectric layer is deposited on the second conductive layer at the location where the first transistor is set. The formed high-k dielectric layer is etched to retain a portion of the high-k dielectric layer at the location corresponding to the first transistor as the initial first high-k dielectric layer 34. After that, an isolation layer such as an oxide layer is deposited and planarized.
[0114] In one embodiment, an oxide layer, such as SiO2, can be deposited on the first structure by CVD or ALD methods, and excess oxide material can be removed using a CMP process. During this process, the surface height of the oxide layer is made flush with the surface height of the second conductive layer 322 by controlling the amount of oxide recess in the isolation layer, such as the oxide layer.
[0115] In one embodiment, as shown in FIG3(h2), a high-k dielectric material, such as HfO2, Al2O3, TiO2, or ZrO2, can be grown on a flat oxide surface using CVD or ALD methods to form a high-k dielectric layer. Then, the formed high-k dielectric layer is etched using dry etching (such as reactive ion etching (RIE)) or wet etching techniques to retain the initial first high-k dielectric layer 34 at the location corresponding to the first transistor. Here, the radius of the retained initial first high-k dielectric layer 34 is slightly larger than the initially designed etching size. That is, the radius of the retained portion of the high-k dielectric layer is larger than the target size of the initial first high-k dielectric layer radius given in the initial design, and the ratio of the difference between the radius of the retained portion of the high-k dielectric layer and the initially designed etching size to the initially designed etching size is within a preset range. In one embodiment, the increase in CD ranges from 5% to 36%, meaning that the radius of the actual retained initial first high-k dielectric layer 34 is 5% to 36% larger than the design size. Assuming the design size radius is 100 nanometers, the radius of the retained initial first high-k dielectric layer 34 may be between 105 nanometers and 136 nanometers.
[0116] In one embodiment, on the structure of the reserved initial first high-K dielectric layer 34 at the position corresponding to the first transistor, a separation layer such as an oxide layer such as SiO2may be re-deposited by a CVD or ALD method, and then the deposited oxide layer is planarized by using a CMP process again to form a second structure.
[0117] Step 202: etching the second structure to form the first transistor, so that the etched initial first high-K dielectric layer is arranged between the first gate electrode of the first transistor and the second conductive layer as the first high-K dielectric layer, and the first high-K dielectric layer surrounds the first semiconductor layer of the first transistor; and the second transistor is formed.
[0118] The preparation method of the semiconductor device provided by the embodiments of the present application improves the parasitic capacitance between the second conductive layer of the first transistor and the gate electrode of the first transistor without changing the physical distance between the gate electrode of the reading transistor and the second conductive layer, thereby improving the data storage capacity of the semiconductor device such as a 2T0C structure memory, and optimizing the electrical performance of the device. At the same time, the long-term stability and performance of the device are maintained, and the reliability of the device is ensured.
[0119] In one exemplary embodiment, the etching the second structure to form the first transistor in step 202 can include:
[0120] At the position of the first transistor hole in the second structure, the first transistor hole for preparing the first transistor is opened, and the second conductive layer and the first conductive layer are exposed; different metal oxides are deposited in the first transistor hole to form a metal oxide stack and are patterned; and a separation layer is deposited on the patterned first metal oxide stack structure and is planarized.
[0121] In one embodiment, as shown in FIG. 3(j) and FIG. 3(k), the initial first high-K dielectric layer 34, the second conductive layer 322 and the first conductive layer 321 at the first transistor hole can be etched by using a physical etching process to open the first transistor hole 32 for preparing the first transistor, the bottom wall of the first transistor hole 32 exposes the first conductive layer 321, and the sidewall exposes the second conductive layer 322; then, different metal oxides are sequentially deposited to form a first metal oxide stack 323. As shown in FIG. 3(j), the etched initial first high-K dielectric layer 34 becomes a first high-K dielectric layer 341.
[0122] In one embodiment, as shown in FIG. 3(k), different metal oxides such as IGZO channel material, high-K dielectric material and ITO material can be sequentially deposited by atomic layer deposition process to form a metal oxide stack. In one embodiment, as shown in FIG. 3(k), the sequentially deposited different metal oxides can include indium gallium zinc oxide 3231, aluminum oxide 3232 and indium tin oxide 3233. After forming the metal oxide stack, surface planarization process is performed using CMP technique to remove the excess indium gallium zinc oxide 3231, aluminum oxide 3232 and indium tin oxide 3233 thin films on the structure surface, as shown in FIG. 3(l), and the remaining thin films form a first metal oxide stack 323 composed of a first semiconductor layer 3234, a first gate dielectric layer 3235 and a first gate electrode 3236, respectively. It is to be noted that in other embodiments, the first semiconductor layer, the first gate dielectric layer and the first gate electrode can also use other semiconductor, insulating or conductive materials, which are not limited in the present application. A first high-K dielectric layer 341 is disposed between the first gate electrode 3236 of the first transistor and the second conductive layer 322, and the first high-K dielectric layer 341 surrounds the first semiconductor layer 3234 of the first transistor.
[0123] In one embodiment, as shown in FIG. 3(l) and FIG. 3(m), the first metal oxide stack 323 is patterned by photolithography and etching process; and a new isolation layer 31 such as SiO2 is grown on the patterned first metal oxide stack 323 structure and planarized by CMP technique.
[0124] In one exemplary embodiment, as shown in FIG. 3(l) and FIG. 3(m), the preparation method of the semiconductor device provided by the embodiments of the present application can further include: Figure 4
[0125] Step 203: In the process of etching the second structure to form the first transistor, a second high-K dielectric layer surrounding the first gate electrode of the first transistor is disposed to form a third structure.
[0126] In one embodiment, disposing the second high-K dielectric layer surrounding the first gate electrode of the first transistor, i.e. disposing the second high-K dielectric layer in the ring gate region of the first transistor, can include:
[0127] The isolation layer in the periphery of the ring gate of the first transistor is patterned and etched with the edge of the first high-K dielectric layer away from the first semiconductor layer of the first transistor as the boundary to form an annular groove surrounding the first gate electrode of the first transistor;
[0128] In the etched annular groove, a high-K dielectric material is deposited to form a second high-K dielectric layer, and after planarization treatment, a third structure is obtained.
[0129] In an embodiment, the oxide layer around the gate of the first transistor can be patterned and etched using photolithography and etching techniques, and in an embodiment, the etching process can be performed using the mask process of the damascene technology route in step 201. Here, since the etching formula of the oxide has a high selectivity ratio to the IGZO material, the structure of the annular groove as shown in Fig. 3(n) can be accurately formed.
[0130] The preparation method of the semiconductor device provided in the embodiments of the present application further fills high-k material in the annular groove (shown as 32b, 32c in the cross-sectional view shown in Fig. 3(n)) to form a second high-k dielectric layer 342 (shown as 3421, 3422 in the cross-sectional view shown in Fig. 3(o)), and a high-k dielectric ring is made around the gate of the first transistor (i.e., the reading transistor), so that the space from the gate of the reading transistor to the second conductive layer of the reading transistor is all high-k dielectric. Without changing the physical distance between the gate and the second conductive layer of the reading transistor, the K value of the dielectric around the gate of the reading transistor is improved, thereby increasing the parasitic capacitance from the gate of the reading transistor to the second conductive layer, and further improving the storage charge amount of the semiconductor device such as the 2T0C storage node. In particular, in the embodiments of the present application, the high-k dielectric ring of the gate is located at the position above the second conductive layer of the reading transistor, which better ensures the performance improvement of the entire device.
[0131] The calculation formula of the parasitic capacitance C is Wherein, k is the dielectric constant, indicating the influence of the dielectric material on the electric field; S is the effective area of the two conductors, i.e., the part of their relative overlap; d is the distance between the two conductors. In the embodiments of the present application, S is constant, and the distance d is about 64 nm in the related art CAA, and in the embodiments of the present application, as shown in Fig. 5(a), the parasitic capacitance C mainly consists of two parts, the first parasitic capacitance C1 and the second parasitic capacitance C2.
[0132] In the embodiments of the present application, the specific position distribution of the high-k dielectric material is shown in Fig. 3(o), and in combination with Fig. 3(o), as shown in Fig. 5(a), for the second parasitic capacitance C2 part, the electrolyte between the capacitor plates is all high-k dielectric material, so the improvement rate of this part of the capacitor is the multiple of the dielectric constant of the high-k dielectric material and the silicon oxide. Taking Al2O3 as an example of the high-k dielectric material, the improvement rate is about 2.5 times, and taking HfO2 as an example of the high-k dielectric material, the improvement rate is about 5.1 times.
[0133] The improvement of the first parasitic capacitance C1 can be referred to Fig. 5(b), and the first parasitic capacitance C1 is a series connection of three capacitors, which are the gate oxide layer capacitor C gate oxide , the channel capacitor C channeland the dielectric capacitance C dielectric , for the gate oxide layer capacitance C gate oxide , the channel capacitance C channel The 2T0C structure memory preparation method provided by the embodiments of the present application is not changed, and the change is the dielectric capacitance C dielectric The dielectric capacitance C dielectric After the dielectric uses high-K dielectric material, the capacitance value is improved. Because S and d in the calculation formula of the parasitic capacitance C are fixed values, therefore, the improvement of the first parasitic capacitance C1 depends on the dielectric capacitance C dielectric According to the formula calculation, it can be obtained that, by taking Al2O3 as an example, the first parasitic capacitance C1 can be improved to 1.55 times of the original, and by taking HfO2 as an example, the first parasitic capacitance C1 can be improved to 2.03 times of the original.
[0134] In summary, by the preparation method of the semiconductor device provided by the embodiments of the present application, under the premise of not changing the physical distance between the gate and the source of the reading transistor, by improving the K value of the dielectric surrounding the gate of the reading transistor, the parasitic capacitance is improved to more than 1.55 times of the original.
[0135] In an exemplary example, after step 202, or after step 203, further comprising step 204: forming a second transistor.
[0136] In an exemplary example, forming the second transistor can comprise:
[0137] forming a third conductive layer on the structure of the first transistor or the third structure and growing an isolation layer to form a fourth structure;
[0138] forming the second transistor corresponding to the position of the first transistor on the fourth structure, and the second transistor is vertically arranged and connected with the first transistor.
[0139] In an exemplary example, the third conductive layer is a write bit line layer.
[0140] In an embodiment, taking the second transistor formed based on the third structure, the second transistor vertically arranged and located above the first transistor as an example, as shown in Figures 3(p)-3(r) , a third conductive layer 331 can be deposited on the third structure and patterned etched, and after the fourth structure is formed by continuing to grow an isolation layer 31 above the third conductive layer 331 and performing surface planarization processing.
[0141] As shown in Figures 3(p)-3(r)As shown, a third conductive layer 331 can be grown on the oxide layer using a PVD or CVD method. The third conductive layer 331 can use a metal material such as tungsten, aluminum, titanium nitride, molybdenum, or molybdenum nitride, etc. Thereafter, the third conductive layer 331 can be patterned by a photolithography and etching process, i.e. the metal layer is etched into the designed pattern of the bit line. After the metal is patterned, an oxide layer such as SiO2is grown on the third conductive layer 331 to form a new isolation layer 31, which is used to isolate the electrical connection between the conductive layers. Thereafter, the oxide layer can be planarized using a CMP technique to obtain a fourth structure, ensuring a smooth and flat surface.
[0142] In one embodiment, forming a second transistor in a position corresponding to the first transistor on the fourth structure can include:
[0143] In one embodiment, opening a second transistor hole for preparing the second transistor in a position corresponding to the first transistor on the fourth structure, the bottom and side of the second transistor hole respectively expose the first gate electrode and the third conductive layer of the first transistor; depositing different metal oxides in the second transistor hole to form a second metal oxide stack and patterning; depositing an isolation layer on the patterned second metal oxide stack structure and planarizing.
[0144] In one embodiment, as shown in FIG. 3(s), FIG. 3(t), a physical etching process can be used to etch the isolation layer 31, the third conductive layer 331 and part of the indium tin oxide in the first metal oxide stack 323, i.e. part of the first gate electrode 3236, at the position corresponding to the first transistor hole, to open a second transistor hole 33 for preparing the second transistor, the bottom and side of the second transistor hole respectively expose the first gate electrode and the third conductive layer 331 of the first transistor; then, different metal oxides are deposited in sequence to form a metal oxide stack.
[0145] In one embodiment, as shown in FIG. 3(t), different metal oxides such as IGZO channel material, high-K dielectric material and ITO material can be sequentially deposited by atomic layer deposition process to form a metal oxide stack. In one embodiment, as shown in FIG. 3(t), the sequentially deposited different metal oxides can include indium gallium zinc oxide 3331, aluminum oxide 3332 and indium tin oxide 3333. After the formation of the metal oxide stack, a surface planarization process is performed using CMP technique to remove the excess indium gallium zinc oxide 3331, aluminum oxide 3332 and indium tin oxide 3333 thin films on the structure surface, and the remaining thin films form a second metal oxide stack 333 composed of a second semiconductor layer 3334, a second gate dielectric layer 3335 and a second gate electrode 3336. It is noted that in other embodiments, the second semiconductor layer 3334 can also use other semiconductor materials such as polysilicon material; the second gate dielectric layer 3335 and the second gate electrode 3336 can also use other insulating dielectric materials or conductive materials, which are not limited by the present disclosure.
[0146] In one embodiment, as shown in FIG. 3(u), FIG. 3(v), the second metal oxide stack 333 is patterned by photolithography and etching process; a layer of oxide such as SiO2 is grown on the patterned second metal oxide stack 333 structure to form a new isolation layer 31, and a planarization process is performed using CMP technique.
[0147] In one exemplary embodiment, after the formation of the second transistor, the process further includes forming a via and completing metal interconnection, which can include:
[0148] A via is formed on the oxide layer 31 grown on the second metal oxide stack 333 structure; and a metal is filled in the via to form an electrical connection.
[0149] In one embodiment, as shown in FIG. 3(w), a via can be formed on the oxide layer 31 grown on the second metal oxide stack 333 structure using photolithography and etching technique to expose the underlying conductive layer. As shown in FIG. 3(w), the second conductive layer 322 is exposed through the via 351, the third conductive layer 331 is exposed through the via 352, the second gate electrode 3336 is exposed through the via 353, and the first conductive layer 321 is exposed through the via 354.
[0150] In one embodiment, as shown in Fig. 3(x), the formed via hole 351, via hole 352, via hole 353 and via hole 354 are filled with metal to form electrical connection 35. In one embodiment, the filled metal can use metal conductive material such as W or Cu or other conductive material. As shown in Fig. 3(y), by using photolithography and etching technology, the pattern of metal pad on the surface of the structure is made to obtain pad 3511 (source of the first transistor, i.e. read transistor), pad 3521 (source of the second transistor, i.e. write transistor), pad 3531 (gate of the second transistor, i.e. write transistor) and pad 3541 (drain of the first transistor, i.e. read transistor) for external electrical connection. In other embodiments, pad 3511 can also be the drain of the first transistor, i.e. read transistor, and pad 3541 can also be the source of the first transistor, i.e. read transistor.
[0151] The embodiment of the present application also provides a semiconductor device, comprising a memory cell array composed of at least one memory cell; each memory cell comprising a first transistor and a second transistor;
[0152] The first transistor comprises a first semiconductor layer 3234, a first gate electrode 3236 and a second conductive layer 322, a first high-K dielectric layer 341 is arranged between the first gate electrode 3236 and the second conductive layer 322, and the first high-K dielectric layer 341 surrounds the first semiconductor layer 3234.
[0153] The second transistor comprises a second semiconductor layer 3334, and the second semiconductor layer 3334 is connected with the first gate electrode 3236.
[0154] In one exemplary instance, each memory cell further comprises a second high-K dielectric layer 342 arranged around the first gate electrode 3236.
[0155] In one exemplary instance, the second conductive layer 322 is connected with the first semiconductor layer 3234, and the connection forms a second source / drain electrode of the first transistor; the memory cell further comprises:
[0156] The first conductive layer 321 is connected with the first semiconductor layer 3234, and the connection forms a first source / drain electrode of the first transistor.
[0157] The second conductive layer 322 is located between the first gate electrode 3236 and the first conductive layer 321.
[0158] The third conductive layer 331 is connected with the second semiconductor layer 3334.
[0159] In one exemplary instance, the first conductive layer 321 is a read bit line layer or a read word line layer; the second conductive layer 322 is a read bit line layer or a read word line layer; and the third conductive layer 331 is a write bit line layer.
[0160] In an example, the first conductive layer 321 and the second conductive layer 322 are connected with the plurality of first transistors which are arranged at intervals in a direction parallel to the substrate 30.
[0161] The third conductive layer 331 is connected with the plurality of second transistors which are arranged at intervals.
[0162] In an embodiment, the semiconductor device further comprises n write word lines, n read word lines, m write bit lines and m read bit lines.
[0163] The first transistor in each memory cell is a read transistor, and the second transistor is a write transistor.
[0164] The source end of the first transistor is connected to the read word line, the drain end of the first transistor is connected to the read bit line, the gate end of the first transistor is connected to the drain end of the second transistor, the gate end of the second transistor is connected to the write word line, and the source end of the second transistor is connected to the write bit line.
[0165] The semiconductor device provided by the embodiment of the present application improves the dielectric constant between the first gate electrode of the first transistor and the second conductive layer by filling the high-K dielectric material in the dielectric layer between the first gate electrode of the first transistor and the second conductive layer, increases the parasitic capacitance between the first gate electrode and the second conductive layer, and improves the data storage capacity of the semiconductor device, thereby optimizing the electrical performance of the device.
[0166] Further, in the semiconductor device provided by the embodiment of the present application, the second high-K dielectric layer in the ring gate is arranged around the gate of the first transistor, so that the high-K dielectric is arranged between the first gate electrode and the second conductive layer of the first transistor. Without changing the physical distance between the first gate electrode and the second conductive layer, the K value of the dielectric around the first gate electrode is improved, thereby increasing the parasitic capacitance between the first gate electrode and the second conductive layer, and further improving the storage charge of the storage node of the semiconductor device. In particular, in the embodiment of the present application, the high-K dielectric in the ring gate is located at the position above the gate flush position to the read word line of the first transistor, which better ensures the performance improvement of the entire device.
[0167] In an example, the semiconductor device can include but is not limited to a 2T0C structure memory.
[0168] In an example, the 2T0C structure memory is a DRAM.
[0169] The embodiment of the present application further provides an electronic device comprising the semiconductor device formed by the preparation method of the semiconductor device according to any one of the embodiments of the present application, or the semiconductor device according to any one of the embodiments of the present application.
[0170] In some embodiments, the electronic device can include, but is not limited to, a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc.
[0171] Although the embodiments disclosed in the present application are as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art to which the present application belongs can make any modification and change in the form and details without departing from the spirit and scope of the present application. The patent protection scope of the present application shall be subject to the scope defined by the appended claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A first structure having a second conductive layer formed on a substrate; A first high-k dielectric layer is generated at the location of the first transistor on the first structure to form the second structure; The second structure is etched to form a first transistor, such that the etched initial first high-k dielectric layer is disposed between the first gate electrode and the second conductive layer of the first transistor as a first high-k dielectric layer, and the first high-k dielectric layer surrounds the first semiconductor layer of the first transistor. A second transistor is formed.
2. The fabrication method according to claim 1, wherein the process of etching the second structure to form the first transistor further includes: A second high-k dielectric layer is disposed around the first gate electrode to form a third structure.
3. The preparation method according to claim 1 or 2, wherein, The generation of the initial first high-k dielectric layer includes: An isolation layer is grown on the first structure; at the location where the first transistor is disposed, the formed isolation layer is selectively etched to obtain a trench; a high-k dielectric material is deposited in the etched trench to form the initial first high-k dielectric layer.
4. The preparation method according to claim 3, wherein, The radius of the groove is greater than the target size of the groove radius, and the ratio of the difference between the groove radius and the target size to the target size is within a preset range.
5. The preparation method according to claim 1 or 2, wherein, The generation of the initial first high-k dielectric layer includes: A high-k dielectric layer is deposited at the location corresponding to the first transistor. The formed high-k dielectric layer is etched to retain a portion of the high-k dielectric layer at the location where the first transistor is located as the initial first high-k dielectric layer. Then, an isolation layer is deposited and planarized.
6. The preparation method according to claim 5, wherein, The radius of the reserved portion of the high-k dielectric layer is larger than the target size of the radius of the initial first high-k dielectric layer, and the ratio of the difference between the radius of the reserved portion of the high-k dielectric layer and the target size to the target size is within a preset range.
7. The preparation method according to claim 2, wherein, The provision of a second high-k dielectric layer surrounding the first gate electrode includes: In the isolation layer surrounding the first gate electrode, a patterned etching is performed with the edge of the first high-k dielectric layer away from the first semiconductor layer as the boundary to form an annular groove around the first gate electrode. Within the etched annular groove, a high-k dielectric material is deposited to form the second high-k dielectric layer, and after planarization, the third structure is obtained.
8. The preparation method according to claim 1 or 2, wherein, The first structure having a second conductive layer formed on a substrate includes: An isolation layer is deposited on the substrate, a first conductive layer is deposited on the isolation layer and patterned and etched, and an isolation layer is grown on top of the first conductive layer and surface planarization is performed. The second conductive layer is grown on the planarized isolation layer and then patterned and etched. The first structure is formed.
9. The preparation method according to claim 1 or 2, wherein, The formation of the second transistor includes: A third conductive layer is formed on the structure in which the first transistor is formed or the third structure, and an isolation layer is grown to form a fourth structure; The second transistor is formed on the fourth structure at the position corresponding to the first transistor, and the second transistor is arranged perpendicularly to and connected to the first transistor.
10. The preparation method according to claim 3, 5 or 7, wherein, The high-k dielectric material includes hafnium dioxide (HfO2), or at least one of aluminum oxide (Al2O3), titanium dioxide (TiO2), and zirconium oxide (ZrO2).
11. A semiconductor device, characterized in that, It includes a memory cell array consisting of at least one memory cell; each memory cell includes a first transistor and a second transistor; The first transistor includes a first semiconductor layer, a first gate electrode and a second conductive layer, and a first high-k dielectric layer is disposed between the first gate electrode and the second conductive layer, the first high-k dielectric layer surrounding the first semiconductor layer. The second transistor includes a second semiconductor layer, which is connected to the first gate electrode.
12. The semiconductor device of claim 11, wherein each memory cell further comprises: A second high-k dielectric layer is disposed around the first gate electrode.
13. The semiconductor device according to claim 11 or 12, wherein, The second conductive layer is connected to the first semiconductor layer, and the connection point forms the second source and drain of the first transistor; The storage unit further includes: A first conductive layer is connected to the first semiconductor layer, and the connection point forms the first source and drain of the first transistor. The second conductive layer is located between the first gate electrode and the first conductive layer; The third conductive layer is connected to the second semiconductor layer.
14. The semiconductor device according to claim 13, wherein, In a direction parallel to the substrate, the first conductive layer and the second conductive layer are connected to a plurality of first transistors disposed at intervals; The third conductive layer is connected to a plurality of second transistors spaced apart.
15. An electronic device, characterized in that, The semiconductor device includes a semiconductor device formed by the method of fabrication of a semiconductor device as described in any one of claims 1-10, or a semiconductor device as described in any one of claims 11-14.