Semiconductor device and forming method thereof

Abstract

In an embodiment, a method includes: forming a multilayer stack including alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, where a lower of the semiconductor nanostructures extends between the lower source / drain regions; forming an upper source / drain region over the lower source / drain region, with an upper semiconductor nanostructure of the semiconductor nanostructures extending between the upper source / drain regions; removing the dummy nanostructures to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; forming a gate dielectric layer around the lower semiconductor nanostructure and the upper semiconductor nanostructure; forming a lower gate electrode around the lower semiconductor nanostructure and in the first opening; selectively depositing a dummy layer over a top surface of the lower gate electrode, the dummy layer including a first polymer; and forming an upper gate electrode around the upper semiconductor nanostructure and in the second opening. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers over a semiconductor substrate and patterning each of the material layers using photolithography to form electrical circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the size of the smallest component that can be fabricated, allowing more components to be integrated into a given area. However, as the smallest component size decreases, additional problems arise that should be addressed. SUMMARY

[0004] Some embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating semiconductor nanostructures and dummy nanostructures; forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming upper source / drain regions over the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; removing the dummy nanostructures to form first openings between the lower semiconductor nanostructures and second openings between the upper semiconductor nanostructures; forming a gate dielectric layer around the lower semiconductor nanostructures and the upper semiconductor nanostructures; forming a lower gate electrode around the lower semiconductor nanostructures and in the first openings; selectively depositing a dummy layer over a top surface of the lower gate electrode, the dummy layer comprising a first polymer; and forming an upper gate electrode around the upper semiconductor nanostructures and in the second openings, wherein a sidewall of the upper gate electrode is in contact with a gate spacer, wherein a dielectric constant of the gate dielectric layer is greater than a dielectric constant of the gate spacer, wherein the upper gate electrode comprises a titanium-containing material.

[0005] Another embodiment of the present application provides a method of forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack comprising alternating semiconductor layers and dummy layers; patterning the multilayer stack to form fins, wherein the fins comprise alternating semiconductor nanostructures and dummy nanostructures, the semiconductor nanostructures being defined by the semiconductor layers, and the dummy nanostructures being defined by the dummy layers; forming lower source / drain regions, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming upper source / drain regions over the lower source / drain regions, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; removing the dummy nanostructures to form first openings between the lower semiconductor nanostructures, and second openings between the upper semiconductor nanostructures; forming a lower gate electrode around the lower semiconductor nanostructures and in the first openings; selectively depositing a polymer layer over a top surface of the lower gate electrode, wherein the polymer layer comprises a first polymer; selectively forming a first metal-containing layer around the upper semiconductor nanostructures and in the second openings; replacing the polymer layer with a dielectric layer; and depositing an upper gate electrode layer over the first metal-containing layer, the dielectric layer, and the lower gate electrode.

[0006] Yet another embodiment of the present application provides a semiconductor device, comprising: a plurality of first nanostructures extending between first source / drain regions; a plurality of second nanostructures located over the plurality of first nanostructures, the plurality of second nanostructures extending between second source / drain regions; an isolation structure located between the plurality of first nanostructures and the plurality of second nanostructures; a first gate stack located around the plurality of first nanostructures; an isolation layer disposed on a top surface of the first gate stack and adjacent to sidewalls of the isolation structure; and a second gate stack located over the isolation layer, the isolation structure, and the first gate stack, the second gate stack disposed around the plurality of second nanostructures, wherein the second gate stack comprises: a first metal-containing layer located around a second nanostructure of the plurality of second nanostructures; a second metal-containing layer located over the first metal-containing layer and around the second nanostructure of the plurality of second nanostructures; and a first gate electrode layer located over the first metal-containing layer and the second metal-containing layer, wherein bottom surfaces of the first metal-containing layer and the second metal-containing layer are in contact with the isolation layer. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the present disclosure embodiments can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be noted that various components were not drawn to scale. Rather, the dimensions of the various components can have been arbitrarily increased or decreased for the sake of discussion. It is emphasized that, according to well-known industrial practice, components can be combined or separated into further components. In addition, some of the components can be used exclusively or can be used in common. Consequently, the designations of these components do not limit their functionality.

[0008] Figure 1 An exemplary schematic diagram of a stacked transistor, such as a complementary field effect transistor (CFET), in a three-dimensional view is shown, in accordance with some embodiments.

[0009] Figures 2-22B A view of an intermediate stage in the manufacture of a CFET, in accordance with some embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure embodiments. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first component over or on a second component can include embodiments in which the first component and the second component are formed in direct contact, and where there can be embodiments in which additional components can be formed between the first component and the second component, such that the first component and the second component can not be in direct contact. In addition, the present disclosure embodiments can refer to a number of functional units to perform certain steps. This implies that the embodiments can be implemented using one or more computer programs or components that, functional units that are integrated with those computer programs or components, or both; the computer programs can be stored in any apparatus-readable medium, implemented in hardware logic, or a combination thereof. The computer programs can be software or firmware. For instance, and without limitation, as a non-limiting example, the described embodiments can be implemented in hardware using a combination of logic gates in a logic array, such as an application specific integrated circuit, or field programmable gate array, or using transistors and logic gates in a combination of components. Further, the present disclosure embodiments can be repeated with variations in the reference numerals and / or characters in various instances. Such repetition is for the sake of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Moreover, spatial or directional terms, such as "below", "under", "lower", "above", "upper" and the like, can be used in this specification to describe one element's or component's relationship to another element or component as illustrated in the figures. Spatial and directional terms are used with respect to the orientation of the device illustrated in the figures. The device can be otherwise oriented (rotated 90° or at other orientations) and the spatial and directional descriptions can be interpreted accordingly.

[0012] According to various embodiments, a semiconductor device including a CFET can be formed. The CFET includes a lower nanosheet FET and an upper nanosheet FET disposed above the lower nanosheet FET. Forming the semiconductor device can include forming an upper channel region of the upper nanosheet FET and a lower channel region of the lower nanosheet FET, the upper channel region and the lower channel region disposed above a fin. A gate dielectric layer is formed around the upper channel region and the lower channel region and above the fin. A lower gate electrode is then formed above the gate dielectric layer and around the lower channel region. A dummy layer can be selectively deposited on exposed surfaces (e.g., top surfaces) of the lower gate electrode, such that the dummy layer is not formed on surfaces of the gate dielectric layer disposed around the upper channel region. The dummy layer can include an anionic polymer, such as polyacrylic acid (PAA), polyvinyl alcohol (PVA), etc. The dummy layer can be formed using a spin-on process, etc., which is used to deposit a solution having an anionic polymer concentration in a range from 10% to 40% by weight. In some embodiments, the dummy layer can also include a non-ionic polymer, such as polyacrylamide, polyethylene glycol (polyethylene oxide), polystyrene sulfonate, polyvinylpyrrolidone, etc. After forming the dummy layer, a first metal-containing material layer (which can also be referred to as a first conductive layer) can be selectively formed above the gate dielectric layer and around the upper channel region, such that the first metal-containing layer is not formed on surfaces (e.g., top surfaces) of the dummy layer. A second metal-containing material layer (which can also be referred to as a second conductive layer) is then selectively formed around the first metal-containing layer and around the upper channel region, such that the second metal-containing layer is not formed on surfaces (e.g., top surfaces) of the dummy layer. The dummy layer can then be removed using water or a water-based solution. An isolation layer (e.g., including a dielectric material) is then formed above the lower gate electrode (e.g., on top surfaces of the lower gate electrode). An upper gate electrode is then formed above the isolation layer and on surfaces of the second metal-containing layer and the first metal-containing layer around the upper channel region. The isolation layer can electrically isolate the lower gate electrode and the upper gate electrode from each other, and the combination of the lower gate electrode and the upper gate electrode can be subsequently referred to as a split metal gate.

[0013] Advantageous features of one or more embodiments disclosed herein can allow for formation of an isolation layer disposed between a lower gate electrode and an upper gate electrode, and the isolation layer electrically isolates the lower gate electrode from the upper gate electrode. A dummy layer (e.g., including an anionic polymer such as polyacrylic acid (PAA), polyvinyl alcohol (PVA), etc.) is selectively formed on an exposed surface (e.g., a top surface) of the lower gate electrode, such that the dummy layer is not formed on a surface of a gate dielectric layer disposed around the upper channel region. This allows for a subsequent selective formation of a first metal-containing layer and a second metal-containing layer on the surface of the gate dielectric layer and around the upper channel region, such that the first metal-containing layer and the second metal-containing layer are not formed on a surface (e.g., a top surface) of the dummy layer. The dummy layer can then be removed using water or a water-based solution, and then an isolation layer (e.g., including a dielectric material) is formed over the lower gate electrode. The upper gate electrode can then be formed over the isolation layer and on surfaces of the second metal-containing layer and the first metal-containing layer around the upper channel region. Thus, the number of patterning steps (e.g., including masking and etching processes) for forming the isolation layer disposed between the upper gate electrode and the lower gate electrode can be reduced. Moreover, the water-based removal process of the dummy layer can reduce the risk of damage to the underlying device structure compared to other etching processes (e.g., dry etching processes). This can result in improved device reliability, improved manufacturing yield, and simplification of the overall device manufacturing process.

[0014] Figure 1 An exemplary schematic diagram of a stacked transistor, such as a complementary field effect transistor (CFET), is shown in accordance with some embodiments. Figure 1 is a three-dimensional view in which some components of the CFET are omitted for clarity of illustration.

[0015] The CFET includes a plurality of vertically stacked nanoscale FETs (e.g., nanowire FETs, nanosheet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, etc.). For example, the CFET can include a lower nanoscale FET of a first device type (e.g., n-type / p-type) and an upper nanoscale FET of a second device type (e.g., p-type / n-type) opposite the first device type. Specifically, the CFET can include a lower PMOS transistor and an upper NMOS transistor, or the CFET can include a lower NMOS transistor and an upper PMOS transistor. Each of the nanoscale FETs includes a semiconductor nanoscale structure 66 (including a lower semiconductor nanoscale structure 66L and an upper semiconductor nanoscale structure 66U), where the semiconductor nanoscale structure 66 serves as a channel region for the nanoscale FET. The semiconductor nanoscale structure 66 can be a nanosheet, a nanowire, etc. The lower semiconductor nanoscale structure 66L is for the lower nanoscale FET, and the upper semiconductor nanoscale structure 66U is for the upper nanoscale FET. A channel isolation material (e.g., a dielectric material) can be used to separate the lower semiconductor nanoscale structure 66L from the upper semiconductor nanoscale structure 66U.Figure 1 Not explicitly stated in the text, see Figure 20 This is used to separate and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L.

[0016] Gate dielectric 132 extends along the top, sidewalls, and bottom of semiconductor nanostructure 66. Gate electrode 134 (including lower gate electrode 134L and upper gate electrode 134U) is located above gate dielectric 132 and around semiconductor nanostructure 66. Source / drain regions 108 (including lower epitaxial source / drain region 108L and upper epitaxial source / drain region 108U) are disposed on opposite sides of gate dielectric 132 and gate electrode 134. Source / drain region 108 may refer to a source or a drain, individually or collectively, depending on the context. Isolation components may be formed to separate desired source / drain regions 108 and / or desired gate electrode 134. For example, lower gate electrode 134L may optionally be separated from upper gate electrode 134U by an isolation layer 168 disposed between lower gate electrode 134L and upper gate electrode 134U. Optionally, the lower gate electrode 134L can be coupled to the upper gate electrode 134U. Furthermore, the upper epitaxial source / drain region 108U can be separated from the lower epitaxial source / drain region 108L by one or more dielectric layers. Figure 1 Not explicitly stated in the text, see Figure 20 The isolation components between the channel region, gate, and source / drain regions allow for vertically stacked transistors, thereby improving device density. Due to the vertical stacking characteristics of CFETs, the schematic diagram can also be referred to as a stacked transistor or a folded transistor.

[0017] Figure 1 Reference cross sections used in later figures are also shown. Cross section A-A' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and in the direction of current, for example, between the source / drain regions 108 of the CFET. Cross section B-B' is perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 134 of the CFET. For clarity, the following figures refer to these reference cross sections.

[0018] Figures 2-22B This is a view of an intermediate stage in the fabrication of a CFET according to some embodiments. Figure 2 , Figure 3A and Figure 4 It is shown that... Figure 1 A similar three-dimensional view. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 11A , Figure 20 , Figure 21 andFigure 22A It shows the line and Figure 1 A cross-sectional view of a section similar to the reference section A-A' in the diagram. Figure 3B , Figure 10B , Figure 11B , Figure 12 , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 14C , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 22B It shows the line and Figure 1 A cross-sectional view of a section similar to the reference section B-B' in the diagram.

[0019] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0020] A multilayer stack 52 is formed over a substrate 50. The multilayer stack 52 includes alternating dummy layers 54 (including a first dummy layer 54A and a second dummy layer 54B) and semiconductor layers 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U). A subset of the lower semiconductor layer 56L and the first dummy layer 54A is disposed below the second dummy layer 54B. Another subset of the upper semiconductor layer 56U and the first dummy layer 54A is disposed above the second dummy layer 54B. As will be described in more detail later, the dummy layers 54 will be removed, and the semiconductor layers 56 will be patterned to form the channel region of the CFET. Specifically, the lower semiconductor layer 56L will be patterned to form the channel region of the lower nanostructure FET of the CFET, and the upper semiconductor layer 56U will be patterned to form the channel region of the upper nanostructure FET of the CFET.

[0021] The multilayer stack 52 is shown as including a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0022] The first dummy layer 54A and the second dummy layer 54B may be formed of a first semiconductor material. The first semiconductor material may be selected from candidate semiconductor materials of the substrate 50. In some embodiments, the dummy layer 54 (e.g., the first dummy layer 54A and the second dummy layer 54B) is formed of or includes silicon germanium, and the second dummy layer 54B may be formed of germanium or silicon germanium having a higher percentage of germanium atoms than the first dummy layer 54A. The first dummy layer 54A and the second dummy layer 54B have high etch selectivity to each other, thereby allowing the second dummy layer 54B to be removed at a faster rate than the first dummy layer 54A in subsequent processing. The semiconductor layer 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U) is formed of a second semiconductor material different from the first semiconductor material. The second semiconductor material may be selected from candidate semiconductor materials of the substrate 50. In some embodiments, the semiconductor layer 56 is formed of silicon. Semiconductor layer 56 and dummy layer 54 have high etch selectivity to each other, which allows dummy layer 54 (e.g., first dummy layer 54A and second dummy layer 54B) to be removed at a faster rate in subsequent processing than semiconductor layer 56 (e.g., lower semiconductor layer 56L and upper semiconductor layer 56U).

[0023] exist Figure 3A and Figure 3BIn this process, fins 62 are formed in the substrate 50, and nanostructures 64 and 66 (including a first pseudo-nanostructure 64A, a second pseudo-nanostructure 64B, a lower semiconductor nanostructure 66L, an intermediate semiconductor nanostructure 66M, and an upper semiconductor nanostructure 66U) are formed in the multilayer stack 52. In some embodiments, nanostructures 64 and 66 and fins 62 can be formed in the multilayer stack 52 and the substrate 50, respectively, by etching trenches in the multilayer stack 52 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic. Nanostructures 64 and 66 formed by etching multilayer stack 52 can define a first pseudo-nanostructure 64A from a first pseudo-layer 54A, a second pseudo-nanostructure 64B from a second pseudo-layer 54B, a lower semiconductor nanostructure 66L from some of the lower semiconductor layer 56L, an upper semiconductor nanostructure 66U from some of the upper semiconductor layer 56U, and an intermediate semiconductor nanostructure 66M from some of the lower semiconductor layer 56L and some of the upper semiconductor layer 56U. The first pseudo-nanostructure 64A and the second pseudo-nanostructure 64B can be further collectively referred to as pseudo-nanostructure 64. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U can be further collectively referred to as semiconductor nanostructure 66.

[0024] As will be described in more detail later, each of the nanostructures 64, 66 will be removed to form the channel region of the CFET. Specifically, the lower semiconductor nanostructure 66L will be used as the channel region of the lower nanostructure FET for the CFET. Furthermore, the upper semiconductor nanostructure 66U will be used as the channel region of the upper nanostructure FET for the CFET.

[0025] The intermediate semiconductor nanostructure 66M is a semiconductor nanostructure 66 located directly above / below (e.g., in contact with) the second pseudo-nanostructure 64B. Depending on the height of the subsequently formed source / drain regions, the intermediate semiconductor nanostructure 66M may or may not be adjacent to any source / drain regions and may or may not be used as a functional channel region for the CFET. Subsequently, the second pseudo-nanostructure 64B will be replaced with an isolation structure. The isolation structure and the intermediate semiconductor nanostructure 66M can define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0026] Fins 62 and nanostructures 64, 66 can be patterned using any suitable method. For example, fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a spacing smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained on nanostructures 64, 66.

[0027] Although each of the fins 62 and nanostructures 64, 66 is shown to always have a constant width, in other embodiments, the fins 62 and / or nanostructures 64, 66 may have tapered sidewalls, such that the width of each of the fins 62 and / or nanostructures 64, 66 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have a different width and be trapezoidal in shape.

[0028] Furthermore, an isolation region 70 is formed above the substrate 50 and between adjacent semiconductor fins 62. The isolation region 70 may include a pad and a filler material above the pad. Each of the pad and filler material may include a dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof. Forming the isolation region 70 may include: depositing a dielectric material; and performing a planarization process, such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc., to remove excess portions of the dielectric material, such as those above the nanostructures 64, 66. The deposition process may include ALD, high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or a combination thereof. In some embodiments, the isolation region 70 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric material is then recessed to define the isolation region 70. The dielectric material may be recessed such that the upper portions of the semiconductor fins 62 and nanostructures 64, 66 extend above the isolation region 70.

[0029] The previously described process is merely one example of how fins 62 and nanostructures 64, 66 can be formed. In some embodiments, fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form fins 62 and / or nanostructures 64, 66. The epitaxial structure can include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the material being epitaxially grown can be doped in situ during growth, which avoids prior and / or subsequent implantation, but in-situ doping and implantation doping can be used together.

[0030] exist Figure 4 In this process, a pseudo-dielectric layer 72 is formed on fins 62 and / or nanostructures 64, 66. The pseudo-dielectric layer 72 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A pseudo-gate layer 74 is formed above the pseudo-dielectric layer 72, and a mask layer 76 is formed above the pseudo-gate layer 74. The pseudo-gate layer 74 can be deposited above the pseudo-dielectric layer 72 and then planarized, for example, by CMP. The mask layer 76 can be deposited above the pseudo-gate layer 74. The pseudo-gate layer 74 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The pseudo-gate layer 74 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The pseudo-gate layer 74 can be formed from other materials that have high etch selectivity to insulating materials. The mask layer 76 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70, thereby extending the dummy dielectric layer 72 between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and / or the nanostructures 64, 66.

[0031] exist Figure 5In this process, mask layer 76 can be patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to dummy gate layer 74 and dummy dielectric layer 72 to form dummy gate 84 and dummy dielectric 82, respectively. The dummy gate 84 covers the corresponding channel regions of nanostructures 64, 66. The pattern of mask 86 can be used to physically separate each of the dummy gate 84 from its adjacent counterpart. The dummy gate 84 can also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the corresponding fin 62. After patterning, mask 86 can optionally be removed, such as by any acceptable etching technique.

[0032] exist Figure 6 In this process, gate spacers 90 are formed over nanostructures 64 and 66 and on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacers 90 can be formed by conformally forming one or more dielectric materials and subsequently etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to pattern the dielectric material. Etching can be anisotropic. The dielectric material (when etched) has portions remaining on the sidewalls of the dummy gate 84 (thus forming gate spacers 90). In some embodiments, the dielectric material (when etched) may also have portions remaining on the sidewalls of fins 62 and / or nanostructures 64 and 66.

[0033] It should be noted that the previous disclosures generally described the process for forming the spacers. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used, additional spacers can be formed and removed, etc.

[0034] Source / drain recesses 94 are formed in fins 62, nanostructures 64, 66, and substrate 50. Epitaxial source / drain regions are subsequently formed in the source / drain recesses 94. The source / drain recesses 94 may extend through nanostructures 64, 66 and into substrate 50. Fins 62 may be etched such that the bottom surface of the source / drain recesses 94 is positioned above, below, or flush with the top surface of isolation region 70. In the illustrated example, the top surface of isolation region 70 is positioned above the bottom surface of the source / drain recesses 94. The source / drain recesses 94 can be formed by etching fins 62, nanostructures 64, 66, and substrate 50 using anisotropic etching processes (such as RIE, NBE, etc.). Gate spacers 90 and dummy gates 84 mask portions of fins 62, nanostructures 64, 66, and substrate 50 during the etching process used to form the source / drain recesses 94. Each layer of nanostructures 64, 66 and / or fins 62 can be etched using a single etching process or multiple etching processes. After the source / drain trenches 94 have reached the desired depth, a timed etching process can be used to stop the etching of the source / drain trenches 94.

[0035] exist Figure 7 In this process, the sidewalls of the first pseudo-nanostructure 64A, exposed by the source / drain trench 94, are recessed to form a sidewall trench 96A. Furthermore, the second pseudo-nanostructure 64B is removed to form an opening 96B between the lower semiconductor nanostructure 66L (collectively referred to as the lower semiconductor nanostructure 66L) and the upper semiconductor nanostructure 66U (collectively referred to as the upper semiconductor nanostructure 66U). The sidewall trench 96A is then filled with a spacer. The opening 96B is then filled with an isolation structure.

[0036] The sidewall recess 96A can be formed by recessing the sidewalls of the first pseudo-nanostructure 64A using any acceptable etching process. The etching is selective for the first pseudo-nanostructure 64A (e.g., selectively etching the material of the first pseudo-nanostructure 64A at a rate faster than that of the semiconductor nanostructure 66). The etching can be isotropic. Although the sidewalls of the first pseudo-nanostructure 64A are shown as being straight after etching, the sidewalls can be concave or convex.

[0037] The opening 96B can be formed by removing the second pseudo-nanostructure 64B using any acceptable etching process. The etching is selective for the second pseudo-nanostructure 64B (e.g., selectively etching the material of the second pseudo-nanostructure 64B at a rate faster than that of the semiconductor nanostructure 66). The etching can be isotropic. The pseudo-gate 84 can be bonded to and support the upper semiconductor nanostructure 66U such that the upper semiconductor nanostructure 66U does not collapse after the opening 96B is formed.

[0038] In some embodiments, the same etching process is used to recess the sidewalls of the first pseudo-nanostructure 64A and to remove the second pseudo-nanostructure 64B. For example, the second pseudo-nanostructure 64B can be completely removed without completely removing the first pseudo-nanostructure 64A, and the first pseudo-nanostructure 64A can be recessed without significantly recessing the semiconductor nanostructure 66. The etching process is selective among the materials of the first pseudo-nanostructure 64A, the second pseudo-nanostructure 64B, and the semiconductor nanostructure 66. Specifically, the etching process selectively etches the material of the first pseudo-nanostructure 64A at a rate faster than the material of the semiconductor nanostructure 66, and also selectively etches the material of the second pseudo-nanostructure 64B at a rate faster than the material of the first pseudo-nanostructure 64A. Therefore, the etching rate of the first pseudo-nanostructure 64A is less than the etching rate of the second pseudo-nanostructure 64B, and greater than the etching rate of the semiconductor nanostructure 66. In some embodiments, the second pseudo-nanostructure 64B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the first pseudo-nanostructure 64A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 66 is formed of germanium-free silicon. The etching process may include a dry etching process using chlorine gas, with or without plasma.

[0039] The intermediate semiconductor nanostructure 66M is exposed by an opening 96B. In some embodiments, an etching process thins the intermediate semiconductor nanostructure 66M. Therefore, the thickness of the intermediate semiconductor nanostructure 66M can differ from (e.g., less than) the thickness of the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U. In some embodiments, after the etching process, the intermediate semiconductor nanostructure 66M is 0% to 20% thinner than the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U.

[0040] exist Figure 8 In this process, an internal spacer 98 is formed in the sidewall recess 96A and on the sidewall of the remaining portion of the first pseudo-nanostructure 64A. As described in more detail later, a source / drain region will subsequently be formed in the source / drain recess 94, and the first pseudo-nanostructure 64A will be replaced with a corresponding gate structure. The internal spacer 98 serves as an isolation member between the subsequently formed source / drain region and the subsequently formed gate structure. Furthermore, the internal spacer 98 can be used to prevent damage to the subsequently formed source / drain region by subsequent etching processes (such as etching processes used to form the gate structure). Additionally, an isolation structure 100 is formed in the opening 96B and between the intermediate semiconductor nanostructure 66M. The isolation structure 100 and the intermediate semiconductor nanostructure 66M will define the boundaries between the lower nanostructure FET and the upper nanostructure FET.

[0041] The internal spacer 98 and the isolation structure 100 can be formed by conformally forming an insulating material in the source / drain recess 94, the sidewall recess 96A, and the opening 96B, and then subsequently etching the insulating material. The insulating material can be a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic. For example, the etching process can be dry etching, such as RIE, NBE, etc. The insulating material (when etched) has a portion retained in the sidewall recess 96A (thus forming the internal spacer 98) and a portion retained in the opening 96B (thus forming the isolation structure 100).

[0042] Although the outer walls of the internal spacer 98 and the isolation structure 100 are shown flush with the sidewalls of the semiconductor nanostructure 66, the outer walls of the internal spacer 98 and the isolation structure 100 may extend beyond the sidewalls of the semiconductor nanostructure 66 or be recessed relative to the sidewalls of the semiconductor nanostructure 66. Therefore, the internal spacer 98 and the isolation structure 100 may partially fill, fully fill, or overfill the sidewall recesses 96A and openings 96B, respectively. Furthermore, although the sidewalls of the internal spacer 98 and the isolation structure 100 are shown as straight, those sidewalls may be concave or convex.

[0043] The isolation structures 100 have similar dimensions to the second pseudo-nanostructures 64B that they replace. Therefore, the isolation structures 100 can have a large thickness, such as a thickness greater than that of the semiconductor nanostructures 66 and the first pseudo-nanostructure 64A, or the isolation structures 100 can have a small thickness, such as a thickness smaller than that of the semiconductor nanostructures 66 and the first pseudo-nanostructure 64A. In some embodiments, the isolation structures 100 are 60% to 90% thinner than the semiconductor nanostructure 66, and 40% to 90% thinner than the first pseudo-nanostructure 64A.

[0044] exist Figure 9In the source / drain trench 94, a lower epitaxial source / drain region 108L and an upper epitaxial source / drain region 108U are formed. A first contact etch stop layer (CESL) 112 and / or a first interlayer dielectric (ILD) 114 may also be formed in the source / drain trench 94. The first ILD 114 is located between the upper epitaxial source / drain region 108U and the lower epitaxial source / drain region 108L. The lower epitaxial source / drain region 108L serves as the lower nanostructure FET of the CFET, and the upper epitaxial source / drain region 108U serves as the upper nanostructure FET of the CFET. Therefore, the first ILD 114 serves as an isolation region to prevent short circuits between the lower and upper nanostructure FETs. Furthermore, a second CESL 122 and / or a second ILD 124 may be formed on the upper epitaxial source / drain region 108U.

[0045] The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L but not the upper semiconductor nanostructure 66U. In some embodiments, the lower epitaxial source / drain region 108L applies stress to the corresponding channel region of the lower semiconductor nanostructure 66L to improve performance. The lower epitaxial source / drain region 108L is formed in a source / drain recess 94, such that each stack of the lower semiconductor nanostructure 66L is disposed between corresponding adjacent pairs of the lower epitaxial source / drain regions 108L. In some embodiments, an internal spacer 98 is used to separate the lower epitaxial source / drain region 108L from a first pseudo-nanostructure 64A, which will be replaced with a gate structure in a subsequent process.

[0046] The lower epitaxial source / drain region 108L is epitaxially grown in the lower portion of the source / drain recess 94. For example, the lower epitaxial source / drain region 108L can be grown laterally from the exposed sidewalls of the lower semiconductor nanostructure 66L and the bottom surface of the fin 62 / substrate 50 in the source / drain recess 94. During the epitaxy of the lower epitaxial source / drain region 108L, the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can be masked to prevent undesirable epitaxial growth on the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U. After the lower epitaxial source / drain region 108L is grown, the mask on the intermediate semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can then be removed. The lower epitaxial source / drain region 108L has a conductivity type suitable for the device type of the lower nanostructure FET. In some embodiments, the lower epitaxial source / drain region 108L is an n-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon, the lower epitaxial source / drain region 108L may include a material on which tensile strain is applied to the lower semiconductor nanostructure 66L, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the lower epitaxial source / drain region 108L is a p-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon-germanium, the lower epitaxial source / drain region 108L may include a material on which compressive strain is applied to the lower semiconductor nanostructure 66L, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, germanium-tin, etc. The lower epitaxial source / drain region 108L may have a surface protruding from the corresponding upper surface of the lower semiconductor nanostructure 66L, and may have a small facet.

[0047] The lower epitaxial source / drain region 108L can be implanted with dopant to form the source / drain region, followed by annealing. The source / drain region can have a density of 10... 19 atoms / cm 3 and 10 21 atoms / cm 3 The impurity concentration is within a certain range. For example, n-type impurity implantation or p-type impurity implantation can be performed. n-type impurities can be phosphorus, arsenic, antimony, etc. p-type impurities can be boron, boron fluoride, indium, etc. In some embodiments, the lower epitaxial source / drain region 108L is in-situ doped during growth.

[0048] Due to the epitaxial process used to form the lower epitaxial source / drain regions 108L, the upper surface of the lower epitaxial source / drain regions 108L has small planes that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent lower epitaxial source / drain regions 108L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 108L of the same nanostructure FET to merge.

[0049] The first ILD 114 is formed above the lower epitaxial source / drain region 108L. The first ILD 114 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process can be used.

[0050] The first CESL 112 can be formed between the first ILD 114 and the lower epitaxial source / drain region 108L. The first CESL 112 can be formed from a dielectric material that has high etch selectivity to the dielectric material of the first ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0051] The first CESL 112 and / or the first ILD 114 can be formed by depositing material for the first CESL 112 and material for the first ILD 114, followed by a subsequent etch-back process. In some embodiments, the first ILD 114 is initially etched, leaving the first CESL 112 unetched. An anisotropic etch process is then performed to remove the portion of the first CESL 112 above the first ILD 114. After recessing, the sidewalls of the upper semiconductor nanostructure 66U are exposed.

[0052] The upper epitaxial source / drain region 108U contacts the upper semiconductor nanostructure 66U but not the lower semiconductor nanostructure 66L. In some embodiments, the upper epitaxial source / drain region 108U applies stress to the corresponding channel region of the upper semiconductor nanostructure 66U to improve performance. The upper epitaxial source / drain region 108U is formed in a source / drain recess 94, such that each stack of the upper semiconductor nanostructure 66U is disposed between corresponding adjacent pairs of the upper epitaxial source / drain regions 108U. In some embodiments, an internal spacer 98 is used to separate the upper epitaxial source / drain region 108U from a first pseudo-nanostructure 64A, which will be replaced with a gate structure in a subsequent process.

[0053] The upper epitaxial source / drain region 108U is epitaxially grown in the upper portion of the source / drain recess 94. For example, the upper epitaxial source / drain region 108U can be laterally grown from the exposed sidewalls of the upper semiconductor nanostructure 66U. The upper epitaxial source / drain region 108U has a conductivity type suitable for the device type of the upper nanostructure FET. The conductivity type of the upper epitaxial source / drain region 108U can be opposite to that of the lower epitaxial source / drain region 108L. In other words, the upper epitaxial source / drain region 108U can be doped in the opposite way to the lower epitaxial source / drain region 108L. In some embodiments, the upper epitaxial source / drain region 108U is an n-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon, the upper epitaxial source / drain region 108U may include a material on which tensile strain is applied to the upper semiconductor nanostructure 66U, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the upper epitaxial source / drain region 108U is a p-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon-germanium, the upper epitaxial source / drain region 108U may include a material on which compressive strain is applied to the upper semiconductor nanostructure 66U, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, germanium-tin, etc. The upper epitaxial source / drain region 108U may have a surface protruding from the corresponding upper surface of the upper semiconductor nanostructure 66U, and may have a small facet.

[0054] The upper epitaxial source / drain region 108U can be implanted with dopant to form the source / drain region, followed by annealing. The source / drain region can have a 10... 19 atoms / cm 3 and 10 21 atoms / cm 3The impurity concentration is within a certain range. For example, n-type impurity implantation or p-type impurity implantation can be performed. n-type impurities can be phosphorus, arsenic, antimony, etc. p-type impurities can be boron, boron fluoride, indium, etc. In some embodiments, the upper epitaxial source / drain region 108U is in-situ doped during growth.

[0055] Due to the epitaxial process used to form the upper epitaxial source / drain regions 108U, the upper surface of the upper epitaxial source / drain regions 108U has small planes that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent upper epitaxial source / drain regions 108U remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent upper epitaxial source / drain regions 108U of the same nanostructure FET to merge.

[0056] The second ILD 124 is deposited above the upper epitaxial source / drain region 108U. The second ILD 124 can be formed of a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process can be used.

[0057] The second CESL 122 can be formed between the second ILD 124 and the upper epitaxial source / drain region 108U. The second CESL 122 can be formed from a dielectric material with high etch selectivity to the dielectric material of the second ILD 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which can be formed by any suitable deposition process, such as CVD, ALD, etc.

[0058] The second CESL 122 and / or the second ILD 124 can be formed by depositing material for the second CESL 122 and material for the second ILD 124. A removal process is then performed to make the top surface of the second ILD 124 flush with the top surface of the gate spacer 90 and the mask 86 (if present) or dummy gate 84. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, can be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the second ILD 124, the gate spacer 90, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Therefore, the top surface of the mask 86 (if present) or dummy gate 84 is exposed through the second ILD 124. In the illustrated embodiment, the mask 86 is retained after the removal process. In other embodiments, mask 86 is removed, thereby exposing the top surface of dummy gate 84 through second ILD 124.

[0059] exist Figure 10A and Figure 10B In one or more etching steps, the dummy gate 84 is removed, thereby forming a recess 67 between the gate spacers 90. A portion of the dummy dielectric 82 located in the recess 67 is also removed. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a rate faster than the materials of the second ILD 124, the isolation structure 100, the internal spacers 98, and the gate spacers 90. Each recess 67 between the gate spacers 90 exposes a portion of the nanostructures 64, 66 that serves as a channel region in the resulting device and / or is located above the portion of the nanostructures 64, 66 that serves as a channel region in the resulting device. The portions of the nanostructures 64, 66 that serve as channel regions are disposed between adjacent pairs of the lower epitaxial source / drain regions 108L or between adjacent pairs of the upper epitaxial source / drain regions 108U. During removal, the dummy dielectric 82 may be used as an etch stop layer when the dummy gate 84 is etched. Then, after removing the dummy gate 84, the dummy dielectric 82 can be removed.

[0060] The remaining portion of the first pseudo-nanostructure 64A is then removed to extend the groove 67 and form openings in the region between the semiconductor nanostructures 66. The remaining portion of the first pseudo-nanostructure 64A can be removed by any acceptable etching process that selectively etches the material of the first pseudo-nanostructure 64A at a rate faster than that of the materials of the semiconductor nanostructure 66, the internal spacer 98, and the isolation structure 100. The etching can be isotropic. For example, when the first pseudo-nanostructure 64A is formed of silicon germanium, the semiconductor nanostructure 66 is formed of silicon, the internal spacer 98 is formed of silicon carbonitride, and the isolation structure 100 is formed of silicon carbonitride, the etching process can be wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the semiconductor nanostructure 66 and to extend the openings between the semiconductor nanostructures 66.

[0061] exist Figure 11A and Figure 11B In this process, a gate dielectric 132 can be deposited in a recess 67, such as between an opening between the gate spacer 90 and the semiconductor nanostructure 66. The gate dielectric 132 can also be deposited on the top surface of the second ILD 124 and the gate spacer 90. The gate dielectric 132 may include one or more gate dielectric layers disposed around the lower semiconductor nanostructure 66L, the upper semiconductor nanostructure 66U, and the isolation structure 100. Specifically, the gate dielectric 132 is disposed on the top surface of the fin 62; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 66; and on the sidewalls of the gate spacer 90. The gate dielectric 132 encloses all (e.g., four) sides of the semiconductor nanostructure 66. The gate dielectric 132 can be formed of oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. Additionally or optionally, the gate dielectric 132 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In embodiments, the gate dielectric 132 may include a dielectric material having a dielectric constant greater than that of the dielectric material of the gate spacer 90. The dielectric material of the gate dielectric 132 may be formed by molecular beam deposition (MBD), ALD, PECVD, etc. Although a single-layer gate dielectric 132 is shown, the gate dielectric 132 may include any number of interface layers and any number of main layers. For example, the gate dielectric 132 may include an interface layer and an overlying high-k dielectric layer.

[0062] Figure 12The formation of a lower gate electrode 134L is illustrated. The lower gate electrode 134L may include one or more lower gate electrode layers disposed above the gate dielectric 132 and around the lower semiconductor nanostructure 66L. The lower gate electrode 134L is disposed in the lower portion of the recess 67 between the gate spacers 90 and between the lower semiconductor nanostructures 66L, and in the opening between the bottommost lower semiconductor nanostructure 66L and the fin 62. In an embodiment, the top surface of the lower gate electrode 134L is located below the top surface of the isolation structure 100. The lower gate electrode 134L may be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 134L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0063] The lower gate electrode 134L is formed of a material suitable for the device type of a lower nanostructure FET. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of a work function adjustment metal suitable for the device type of a lower nanostructure FET. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of a p-type work function adjustment metal, such as titanium nitride, tantalum nitride, combinations thereof, etc. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. Additionally or optionally, the lower gate electrode 134L may include a dipole inducing element suitable for the device type of a lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0064] As an example of forming the lower gate electrode 134L, one or more lower gate electrode layers are formed above the gate dielectric 132 and in the remainder of the recess 67 between the gate spacers 90 and the semiconductor nanostructures 66. The lower gate electrode layers can be formed, for example, using a suitable deposition process, such as CVD, ALD, etc. The lower gate electrode layers can then be recessed. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to recess the lower gate electrode layers. The etching can be isotropic, such as an etch-back process that removes the lower gate electrode layers from the upper portion of the recess 67 between the gate spacers 90, thereby leaving the lower gate electrode layers in the opening between the lower semiconductor nanostructures 66L.

[0065] Figure 13A and Figure 13BOptional steps for forming the masking structure 160 are shown to fill the openings between the upper semiconductor nanostructures 66U, and to fill the openings between the intermediate semiconductor nanostructure 66M above the isolation structure 100 and the adjacent upper semiconductor nanostructure 66U. The masking structure 160 can be in the dummy layer 162 (subsequently in...) Figure 14B (As shown in the diagram) is used as a deposition mask during formation. In some embodiments, this can be omitted. Figure 13A and Figure 13B The steps are shown in the figure.

[0066] As an example of how the masking structure 160 is formed, such as Figure 13A As shown, it can be in the groove 67 and previously in Figure 12 A dielectric layer 159 is deposited over the structure shown, such as over the gate dielectric 132 and the lower gate electrode 134L, and around the upper semiconductor nanostructure 66U, to fill the openings between the upper semiconductor nanostructures 66U. Furthermore, the dielectric layer 159 fills the openings between the intermediate semiconductor nanostructure 66M and the adjacent upper semiconductor nanostructure 66U above the isolation structure 100. Additionally, the dielectric layer 159 may be formed over the top surface and sidewalls of the gate spacer 90 and over the top surface of the second ILD 124.

[0067] The dielectric layer 159 may include materials such as alumina, lanthanum oxide, tantalum oxide, etc., which are conformally deposited using suitable processes such as ALD, CVD, etc. Figure 13B As shown, after the dielectric layer 159 is formed, an etching process (e.g., which may include reactive ion etching (RIE), neutral beam etching (NBE), chemical etching, free radical etching, etc.) can be performed to remove portions of the dielectric layer 159 disposed above the lower gate electrode 134L, on the sidewalls of the upper semiconductor nanostructure 66U, and above the topmost upper semiconductor nanostructure 66U. In an embodiment, the etching process can also remove portions of the dielectric layer 159 disposed on the top surface and sidewalls of the gate spacer 90 and on the top surface of the second ILD 124. In an embodiment, additional trimming processes (e.g., using a suitable wet etching process) can also be performed to remove end portions of the dielectric layer 159 between the upper semiconductor nanostructures 66U. In an embodiment, after performing the etching and trimming processes, the remaining portion of the dielectric layer 159 forms a masking structure 160 disposed between the upper semiconductor nanostructures 66U and above the isolation structure 100, between the intermediate semiconductor nanostructure 66M and the adjacent upper semiconductor nanostructure 66U. Although the outer wall of the masking structure 160 is shown flush with the sidewall of the gate dielectric 132, the outer wall of the masking structure 160 may extend beyond the sidewall of the gate dielectric 132 or be recessed relative to the sidewall of the gate dielectric 132.

[0068] exist Figure 14A In the middle, in the previous Figure 12 A dummy layer 162 is selectively deposited on the exposed surface (e.g., the top surface) of the lower gate electrode 134L in the recess 67 of the structure shown. Figure 14A In the embodiment shown, previously in Figure 13A and Figure 13B The optional masking structure 160 described herein is not present. The dummy layer 162 may also be referred to hereinafter as the polymer layer. In embodiments, the dummy layer 162 may comprise anionic polymers, such as, for example, polyacrylic acid (PAA), polyvinyl alcohol (PVA), etc. The dummy layer 162 may be formed using a spin-coating process, etc., for depositing a spin-coating solution having an anionic polymer concentration in the range of 10% to 40% by weight. The spin-coating solution may also comprise solvents such as water, isopropanol (IPA), methanol, ethanol, glycerol, etc. In embodiments, the thickness T1 of the dummy layer 162 may be in the range of 5 nm to 50 nm. The thickness T1 of the dummy layer 162 can be controlled by adjusting the anionic polymer concentration in the spin-coating solution and / or by adjusting the number of spin-coating cycles in the implemented spin-coating process. For example, increasing the concentration of the anionic polymer in the spin coating solution or increasing the number of spin coating cycles can produce a larger thickness T1 of the pseudo layer 162, while decreasing the concentration of the anionic polymer in the spin coating solution or decreasing the number of spin coating cycles can produce a smaller thickness T1 of the pseudo layer 162.

[0069] Anionic polymers are compounds comprising long-chain carbon atoms having negatively charged functional groups attached along the chain. During the deposition of the dummy layer 162, surface charge interactions occur between the negatively charged functional groups of the anionic polymer and the underlying material. These charged functional groups preferentially interact with positively charged surface sites present on the surface (e.g., the top surface) of the lower gate electrode 134L (e.g., including titanium nitride, etc.), while exhibiting minimal interaction with neutral or negatively charged surface sites on the surface of the gate dielectric 132. Therefore, the dummy layer 162 is selectively formed on the top surface of the lower gate electrode 134L, and the formation of the dummy layer 162 on the surface of the gate dielectric 132 is suppressed.

[0070] Advantages can be achieved by selectively forming a dummy layer 162 on the exposed surface (e.g., top surface) of the lower gate electrode 134L in the recess 67, wherein the dummy layer 162 comprises an anionic polymer, such as, for example, polyacrylic acid (PAA), polyvinyl alcohol (PVA), etc. The dummy layer 162 can be formed using a spin-coating process, etc., for depositing a spin-coating solution having an anionic polymer concentration in the range of 10% to 40% by weight. These advantages include using a spin-coating process to form the dummy layer 162, wherein the anionic polymer concentration in the spin-coating solution is in the range of 10% to 40% by weight, such that the dummy layer 162 is formed only on the surface of the lower gate electrode 134L and not on the surface of the gate dielectric 132 surrounding the semiconductor nanostructure 66. Therefore, the semiconductor nanostructure 66 (which is subsequently located above the gate dielectric 132 and in the recess 67) can then be deposited. Figure 15 The conductive layers 164 and 166 are formed around the semiconductor nanostructure 66 without the need for additional masking or etching steps to remove any portion of the dummy layer 162 around the semiconductor nanostructure 66. Furthermore, the dummy layer 162 is formed over the lower gate electrode 134L using a spin-coating process, which deposits a spin-coating solution having an anionic polymer concentration ranging from 10% to 40% by weight, allowing the subsequent formation of the conductive layer 164 (as described in the text) over the gate dielectric 132 and around the semiconductor nanostructure 66 in the recess 67. Figure 15 (as described in the text) and conductive layer 166 ( Figure 15 (As described in the text) will be selective. For example, the presence of polymer compounds in dummy layer 162 creates a surface lacking the reaction sites required for the formation of conductive layers 164 and 166, and thus inhibits the formation of conductive layers 164 and 166 on the surface of dummy layer 162. This results in improved control over the placement of conductive layers 164 and 166 and reduces the need for subsequent patterning or removal steps, thereby simplifying the overall manufacturing process and improving manufacturing yield.

[0071] In some embodiments, the dummy layer 162 may also comprise a nonionic polymer. For example, in addition to anionic polymers, the spin-coating solution used to form the dummy layer 162 may also comprise a nonionic polymer, such as polyacrylamide, polyethylene glycol (also known as polyethylene oxide), polystyrene sulfonate, polyvinylpyrrolidone, etc. A nonionic polymer is a compound comprising a large molecule that does not contain ionic bonds, ions, or functional groups that would ionize in aqueous solution. In embodiments, when a nonionic polymer is added to an anionic polymer (e.g., in a spin-coating solution), an insoluble molecular structure (e.g., also known as a complex) is formed through hydrogen bonding or other non-covalent interactions. In embodiments, the spin-coating solution may have a first percentage concentration of solvent, a second percentage concentration of anionic polymer, and a third percentage concentration of nonionic polymer by weight, wherein the first percentage concentration is greater than the second percentage concentration, and the second percentage concentration is greater than the third percentage concentration.

[0072] In the embodiments, when a nonionic polymer is added to an anionic polymer (e.g., in a spin-coating solution), the anionic and nonionic polymers can interact through hydrogen bonds or other non-covalent interactions to form a molecular structure (also referred to as a complex) with different solubility properties than the individual polymers. After forming the dummy layer 162 using a spin-coating process, the solubility of the molecular structure in the dummy layer 162 can be adjusted by modifying the exposure of the dummy layer 162 therein and can subsequently be used to remove the dummy layer 162 (e.g., as...). Figure 16 The pH level of the water or water-based solution (as shown in the figure) is controlled by the pH level of the solution.

[0073] Advantages can be achieved by forming a pseudo-layer 162, which comprises both nonionic and anionic polymers. A spin-coating process is performed to form the pseudo-layer 162 using a spin-coating solution comprising both anionic and nonionic polymers, wherein the nonionic polymers include polyacrylamide, polyethylene glycol (also known as polyethylene oxide), polystyrene sulfonate, polyvinylpyrrolidone, etc. These advantages include the interaction between the anionic and nonionic polymers to form a molecular structure (also known as a complex) with different solubility properties than the individual polymers (e.g., anionic or nonionic polymers). This allows the solubility of the pseudo-layer 162 in water or a water-based solution to be controlled by adjusting the pH level of the water or water-based solution. For example, as subsequently... Figure 16 As described, when the pH level of the water or water-based solution is equal to or higher than 7, the solubility of the dummy layer 162 (e.g., comprising anionic and nonionic polymers) increases in the water or water-based solution. This allows for the selective removal of the dummy layer 162 without the need for the use of materials that could potentially damage the conductive layer 164 (subsequently used in...). Figure 15 (as described in the text) and conductive layer 166 (subsequently in...) Figure 15Other etching processes (e.g., dry etching, etc.) can be used to etch the device structure as described in the description or other methods described below. Therefore, device reliability can be improved, and improved manufacturing yield can be achieved.

[0074] Figure 14B and Figure 14C An alternative embodiment is shown, wherein there is a previously known embodiment. Figure 13A and Figure 13B The optional masking structure 160 is described in [the text]. Figure 14B In the middle, pseudo-layer 162 uses the same as previously in Figure 14A Similar processes and material selective deposition described in [the text] have been previously [used in] [the text]. Figure 13B The lower gate electrode 134L is exposed on the surface (e.g., the top surface) of the recess 67 in the structure shown. During this selective deposition process, the masking structure 160 can be used as a deposition mask. Figure 14C It is shown that after the formation of the dummy layer 162, the masking structure 160 can be removed using an etching process. In an embodiment, the etching process can be an isotropic etching process, such as wet etching, which uses ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), etc., as etchants.

[0075] exist Figure 15 In this process, conductive layers 164 and 166 can be selectively deposited over the gate dielectric 132 and previously deposited on... Figure 14A or Figure 14C The structure shown in the diagram surrounds the semiconductor nanostructure 66 in the groove 67, thereby preventing the conductive layers 164 and 166 from forming on the surface (e.g., top surface) of the dummy layer 162. In an embodiment, the conductive layer 164 (which may also be referred to as a metal-containing layer) and the conductive layer 166 (which may also be referred to as a metal-containing layer) are deposited sequentially. The conductive layer 164 may include titanium, aluminum, etc., which are conformally deposited using a suitable deposition process such as CVD, ALD, etc. In an embodiment, the conductive layer 164 may be deposited over the gate dielectric 132 and around the upper semiconductor nanostructure 66U. The conductive layer 164 may also be formed over the top surface of the intermediate semiconductor nanostructure 66M and on the sidewalls of the intermediate semiconductor nanostructure 66M. In some embodiments, the conductive layer 164 may also be formed on the sidewalls of the isolation structure 100. During the deposition process for forming the conductive layer 164, the formation of the conductive layer 164 on the surface of the dummy layer 162 is suppressed due to the presence of polymer compounds in the dummy layer 162, creating a surface lacking the reaction sites required for the formation of the conductive layer 164.

[0076] The conductive layer 166 may include titanium nitride, tantalum nitride, tantalum oxide, titanium silicon nitride, titanium aluminum carbide, etc., and is conformally deposited using a suitable deposition process such as CVD, ALD, etc. In an embodiment, the conductive layer 166 may be deposited over the conductive layer 164, the gate dielectric 132, and around the upper semiconductor nanostructure 66U to fill the openings between the upper semiconductor nanostructures 66U. The conductive layer 166 may also be formed over the top surface of the intermediate semiconductor nanostructure 66M and on the sidewalls of the intermediate semiconductor nanostructure 66M. Furthermore, the conductive layer 166 may also be formed on the sidewalls of the isolation structure 100. During the deposition process for forming the conductive layer 166, the presence of polymer compounds in the dummy layer 162 inhibits the formation of the conductive layer 166 on the surface of the dummy layer 162, creating a surface lacking the reaction sites required for the formation of the conductive layer 166.

[0077] exist Figure 16 In this process, the dummy layer 162 can be removed by exposing its surface to water or an aqueous solution with a controlled pH level. For example, in an embodiment, during the formation of the dummy layer 162 (previously in... Figure 14A As described in [the text], anionic and nonionic polymers can interact through hydrogen bonds or other non-covalent interactions to form a pseudo-layer 162 having a molecular structure (also referred to as a complex) with different solubility properties than the individual polymers (e.g., anionic or nonionic polymers). In embodiments where the pseudo-layer 162 comprises anionic and nonionic polymers, exposing the pseudo-layer 162 to water or an aqueous solution having a pH level equal to or greater than 7 can increase the solubility of the pseudo-layer 162 in the water or aqueous solution. Therefore, exposing the pseudo-layer 162 to water or an aqueous solution will promote the removal of the pseudo-layer 162.

[0078] For example, pseudolayer 162 may comprise anionic and nonionic polymers that interact to form a molecular structure (also known as a complex), wherein the anionic polymer is polyacrylic acid (PAA) and the nonionic polymer is polyethylene glycol. Polyacrylic acid (PAA) may comprise polymer chains having repeating units, wherein each repeating unit of the polymer chain contains a carboxyl group (-COOH), and wherein the carboxyl group (-COOH) comprises a carbon atom with a double bond to an oxygen atom and a single bond to a hydroxyl group (-OH). When polyethylene glycol is present, polyacrylic acid interacts with polyethylene glycol to form a molecular structure stable at pH levels below 7. However, when the pH level of the water or aqueous solution used to remove pseudolayer 162 is equal to or higher than 7 (e.g., becoming more alkaline), the hydrogen atom (also known as a proton) from the hydroxyl group (-OH) of the carboxyl group is removed (also known as deprotonation), thereby converting the carboxyl group (-COOH) into a negatively charged carboxylate ion (-COO-). This conversion to a carboxylate ion increases the negative charge density along the polymer chain, making polyacrylic acid more hydrophilic and increasing its solubility. The increased negative charge density of the polymer chains also disrupts the hydrogen bonds between polyacrylic acid (PAA) and polyethylene glycol, which promotes the decomposition of the molecular structure and allows for the removal of pseudo-layer 162.

[0079] exist Figure 17 In the process, conformal deposition processes (such as CVD, ALD, etc.) are used in groove 67 and Figure 16 A dielectric layer 167 is deposited over the structure shown. The dielectric layer 167 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc. The dielectric layer 167 may be formed over the lower gate electrode 134L, the upper semiconductor nanostructure 66U, the conductive layer 164, the conductive layer 166, the gate dielectric 132, and the isolation structure 100. For example, the dielectric layer 167 may be disposed on the top surface of the lower gate electrode 134L, the top surface, sidewalls, and bottom surface of the conductive layer 166, the bottom surface of the conductive layer 164, and the sidewalls of the gate dielectric 132. In an embodiment, the dielectric layer 167 fills the gap between the bottom surfaces of the conductive layers 164 and 166 and the top surface of the lower gate electrode 134L (e.g., previously filled by materials such as...). Figure 16 The pseudo-layer 162 described in the document is occupied by [the layer].

[0080] exist Figure 18In this process, after the dielectric layer 167 is formed, an etching process (e.g., which may include reactive ion etching (RIE), neutral beam etching (NBE), etc.) can be performed to remove portions of the dielectric layer 167 disposed on the top surface and sidewalls of the conductive layer 166. Furthermore, during the etching process, the thickness of the portion of the dielectric layer 167 disposed above the lower gate electrode 134L can be reduced. In an embodiment, after the etching process, the remaining portion of the dielectric layer 167 forms an isolation layer 168. The isolation layer 168 serves as a junction between the lower gate electrode 134L and the subsequently formed upper gate electrode 134U (which is then...). Figure 19 The isolation components between the upper gate electrode 134U and the lower gate electrode 134L are described in the text. The isolation layer 168 and the isolation structure 100 together physically and electrically isolate the upper gate electrode 134U from the lower gate electrode 134L. Furthermore, the upper nanostructure FET can be isolated from the lower nanostructure FET via the isolation structure 100.

[0081] exist Figure 19In this structure, one or more upper gate electrode layers 174 are formed in a groove 67 above the isolation layer 168, the lower gate electrode 134L, the conductive layer 166, the gate dielectric 132, and the upper semiconductor nanostructure 66U. The one or more upper gate electrode layers 174 may contact the top surface and sidewalls of the conductive layer 166 and the top surface of the isolation layer 168. In an embodiment, the bottom surface of the one or more upper gate electrode layers 174 may be higher than the bottom surface of the isolation structure 100, and the bottom surface of the one or more upper gate electrode layers 174 may be located below the top surface of the isolation structure 100. In an embodiment, the bottom surfaces of the conductive layers 166 and 164 may be higher than the bottom surface of the isolation structure 100, and the bottom surfaces of the conductive layers 166 and 164 may be located below the top surface of the isolation structure 100. In an embodiment, the sidewalls of the conductive layers 166 and 164 are disposed adjacent to the sidewalls of the isolation structure 100. In an embodiment, conductive layer 166, conductive layer 164, and one or more upper gate electrode layers 174 together form an upper gate electrode 134U disposed above the gate dielectric 132 and around the upper semiconductor nanostructure 66U. The upper gate electrode 134U is disposed in the upper portion of the recess 67 between the gate spacers 90 and in the opening between the upper semiconductor nanostructure 66U. The one or more upper gate electrode layers 174 may be formed of a metal-containing material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. For example, in an embodiment, the upper semiconductor nanostructure 66U may form a channel region for a subsequently formed upper nanostructure FET. In embodiments where the subsequently formed upper nanostructure FET is an n-type device, the one or more gate electrode layers 174 may be formed of a metal-containing material such as titanium nitride. In an embodiment, the upper gate electrode 134U may include any number of power function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0082] In an embodiment, the upper gate electrode 134U may include a dipole-inducing element suitable for the device type of the upper nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The dipole-inducing element of the upper gate electrode 134U may differ from that of the lower gate electrode 134L. In an embodiment, the isolation layer 168 and the isolation structure 100 together electrically isolate the upper gate electrode 134U from the lower gate electrode 134L. Furthermore, the upper nanostructure FET may be isolated from the lower nanostructure FET via the isolation structure 100.

[0083] As an example of forming one or more upper gate electrode layers 174, one or more upper gate electrode layers 174 are formed in a recess 67 above the isolation layer 168, the lower gate electrode 134L, the conductive layer 166, the gate dielectric 132, and the upper semiconductor nanostructure 66U. For example, a suitable conformal deposition process (such as CVD, ALD, etc.) is used to form one or more upper gate electrode layers 174 in the upper portion of the recess 67 and above the lower gate electrode 134L and the isolation layer 168. The conductive layers 166 and 164 of the upper gate electrode 134U and the one or more upper gate electrode layers 174 may not be shown separately in the following figures, but may be collectively shown as the upper gate electrode 134U.

[0084] exist Figure 20 In this process, a removal process can be implemented to remove excess portions of one or more upper gate electrode layers 174 and / or gate dielectric 132 located above the top surfaces of gate spacer 90 and second ILD 124. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., can be utilized. When a planarization process is used, the top surfaces of gate spacer 90, second ILD 124, gate dielectric 132, and upper gate electrode 134U are coplanar (within process variations).

[0085] Gate dielectric 132 and gate electrode 134 (including lower gate electrode 134L and upper gate electrode 134U) form an alternative gate. Each corresponding pair of gate dielectric 132 and gate electrode 134 (including upper gate electrode 134U and / or lower gate electrode 134L) may be collectively referred to as a "gate structure" or "gate stack". Each gate structure extends along at least three sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of semiconductor nanostructure 66. The gate structure may also extend along the sidewalls and / or top surface of semiconductor fin 62.

[0086] exist Figure 21 In the second ILD 124, a source / drain contact 144 is formed to electrically couple to the upper epitaxial source / drain region 108U and / or the lower epitaxial source / drain region 108L. As an example of forming the source / drain contact 144, an opening for the source / drain contact 144 is formed through the second ILD 124 and the second CESL 122. The opening can be formed using acceptable photolithography and etching techniques. In the illustrated embodiment, the opening is formed using a self-aligned contact (SAC) process. A pad (not shown separately), such as a diffusion barrier layer or adhesive layer, and a conductive material are formed in the opening. The pad may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process can be implemented to remove the material from the gate spacer 90, the second ILD 124 (see...).Figure 20 Excess material is removed from the top surface of the gate electrode 134U and the upper gate electrode 134U. The remaining pads and conductive material form the source / drain contacts 144 in the opening. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof, are utilized. After the planarization process, the gate spacer 90, the second ILD 124 (see...) Figure 20 The top surfaces of the upper gate electrode 134U and the source / drain contact 144 are substantially coplanar (within the process variation).

[0087] Optionally, a metal-semiconductor alloy region 142 is formed at the interface between the source / drain region 108 and the source / drain contact 144. The metal-semiconductor alloy region 142 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 142 can be formed prior to the material of the source / drain contact 144 by depositing metal in the opening for the source / drain contact 144 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 108 (e.g., silicon, silicon-germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metals can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from openings used for the source / drain contacts 144 (such as from the surface of the metal-semiconductor alloy region 142). The material for the source / drain contacts 144 can then be formed on the metal-semiconductor alloy region 142.

[0088] exist Figure 22A and Figure 22B In this process, a third ILD 154 is deposited over the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contact 144. In some embodiments, the third ILD 154 is a flowable film formed by a flowable CVD method, followed by curing of the flowable film. In some embodiments, the third ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., which can be deposited by any suitable method, such as CVD, PECVD, etc.

[0089] In some embodiments, an etch stop layer (ESL) 152 is formed between the third ILD 154 and the gate spacer 90, the second ILD 124, the upper gate electrode 134U, and the source / drain contact 144. The ESL 152 may include a dielectric material that has high etch selectivity to the dielectric material of the third ILD 154, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0090] A gate contact 156 and a source / drain via 158 are formed through the third ILD 154 to electrically couple to the upper gate electrode 134U and the source / drain contact 144, respectively. As an example of forming the gate contact 156 and the source / drain via 158, openings for the gate contact 156 and the source / drain via 158 are formed through the third ILD 154 and ESL 152. These openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers and adhesive layers, as well as conductive material, are formed within the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the third ILD 154. The remaining pads and conductive material form the gate contact 156 and the source / drain via 158 within the openings. The gate contact 156 and the source / drain via 158 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 156 and the source / drain via 158 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0091] The active devices shown are collectively referred to as device layers. In some embodiments, the contacts to the lower gate electrode 134L and the lower epitaxial source / drain region 108L can be formed on the back side of the device layer (e.g., the side opposite to the source / drain contact 144).

[0092] The embodiments of this disclosure have several advantageous features. The embodiments include forming a semiconductor device comprising a complementary field-effect transistor (CFET), wherein forming the semiconductor device may include forming an upper channel region of an upper nanostructure FET and a lower channel region of a lower nanostructure FET, the upper and lower channel regions being disposed above the fin. A gate dielectric layer is formed around the upper and lower channel regions and above the fin. A lower gate electrode is then formed above the gate dielectric layer and around the lower channel region. A dummy layer may be selectively deposited on the exposed surface (e.g., top surface) of the lower gate electrode, such that the dummy layer does not form on the surface of the gate dielectric layer disposed around the upper channel region. The dummy layer may comprise an anionic polymer, such as polyacrylic acid (PAA), polyvinyl alcohol (PVA), etc. The dummy layer may be formed using a spin-coating process, etc., for depositing a solution having an anionic polymer concentration in the range of 10% to 40% by weight. In some embodiments, the dummy layer may also comprise a nonionic polymer, such as polyacrylamide, polyethylene glycol (also known as polyethylene oxide), polystyrene sulfonate, polyvinylpyrrolidone, etc. After forming the dummy layer, a first metallized material layer may be selectively formed over the gate dielectric layer and around the upper channel region, such that the first metallized layer is not formed on the surface (e.g., the top surface) of the dummy layer. A second metallized material layer is then selectively formed around the first metallized layer and around the upper channel region, such that the second metallized layer is not formed on the surface (e.g., the top surface) of the dummy layer. The dummy layer can then be removed using water or an aqueous solution. An isolation layer (e.g., comprising a dielectric material) is then formed over the lower gate electrode (e.g., on the top surface of the lower gate electrode). An upper gate electrode is then formed over the isolation layer and on the surfaces of the second metallized layer and the first metallized layer around the upper channel region. The isolation layer electrically isolates the lower gate electrode and the upper gate electrode from each other, and the combination of the lower gate electrode and the upper gate electrode may subsequently be referred to as a split metal gate.

[0093] One or more embodiments disclosed herein can allow the formation of an isolation layer disposed between a lower gate electrode and an upper gate electrode, electrically isolating the lower gate electrode from the upper gate electrode. A dummy layer (e.g., comprising an anionic polymer such as polyacrylic acid (PAA), polyvinyl alcohol (PVA), etc.) is selectively formed on the exposed surface (e.g., top surface) of the lower gate electrode, such that the dummy layer is not formed on the surface of the gate dielectric layer disposed around the upper channel region. This allows for the subsequent selective formation of a first metal-containing layer and a second metal-containing layer on the surface of the gate dielectric layer and around the upper channel region, such that the first and second metal-containing layers are not formed on the surface (e.g., top surface) of the dummy layer. The dummy layer can then be removed using water or an aqueous solution, and then an isolation layer (e.g., comprising a dielectric material) is formed over the lower gate electrode. The upper gate electrode can then be formed over the isolation layer and on the surfaces of the second and first metal-containing layers around the upper channel region. Therefore, the number of patterning steps (e.g., including masking and etching processes) used to form the isolation layer disposed between the upper and lower gate electrodes can be reduced. Furthermore, the water-based removal process for the dummy layer reduces the risk of damage to the underlying device structure compared to other etching processes (e.g., dry etching). This can result in improved device reliability, improved manufacturing yield, and a simplified overall device fabrication process.

[0094] According to an embodiment, the method includes: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming a lower source / drain region, wherein lower semiconductor nanostructures of the semiconductor nanostructures extend between the lower source / drain regions; forming an upper source / drain region above the lower source / drain region, wherein upper semiconductor nanostructures of the semiconductor nanostructures extend between the upper source / drain regions; removing the pseudo-nanostructures to form a first opening between the lower semiconductor nanostructures, and in the upper... A second opening is formed between semiconductor nanostructures; a gate dielectric layer is formed around the lower and upper semiconductor nanostructures; a lower gate electrode is formed around the lower semiconductor nanostructure and in the first opening; a dummy layer, comprising a first polymer, is selectively deposited over the top surface of the lower gate electrode; and an upper gate electrode is formed around the upper semiconductor nanostructure and in the second opening, wherein the sidewalls of the upper gate electrode are in contact with the gate spacer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein the upper gate electrode comprises a titanium-containing material. In an embodiment, the first polymer is an anionic polymer. In an embodiment, the anionic polymer includes polyacrylic acid (PAA) or polyvinyl alcohol (PVA). In an embodiment, the dummy layer also includes a second polymer, and wherein the second polymer is a nonionic polymer. In an embodiment, the nonionic polymer includes polyacrylamide, polyethylene glycol, polystyrene sulfonate, or polyvinylpyrrolidone. In an embodiment, forming the upper gate electrode further includes: forming a first metal-containing layer around the upper semiconductor nanostructure and in the second opening; forming a second metal-containing layer around the first metal-containing layer and in the second opening; and depositing an upper gate electrode layer over the lower gate electrode, the first metal-containing layer, and the second metal-containing layer. In an embodiment, the method further includes: removing the dummy layer by exposing the surface of the dummy layer to water or an aqueous solution having a pH level equal to or higher than 7; and forming a dielectric layer over the top surface of the lower gate electrode. In an embodiment, the first metal-containing layer comprises titanium aluminum, and the second metal-containing layer comprises titanium nitride.

[0095] According to an embodiment, the method includes: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor layers and dummy layers; patterning the multilayer stack to form fins, wherein the fins include alternating semiconductor nanostructures and dummy nanostructures, the semiconductor nanostructures being defined by semiconductor layers and the dummy nanostructures being defined by dummy layers; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; and forming an upper source / drain region above the lower source / drain region, wherein the upper semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions. The structure extends between upper source / drain regions; pseudo-nanostructures are removed to form a first opening between lower semiconductor nanostructures and a second opening between upper semiconductor nanostructures; a lower gate electrode is formed around the lower semiconductor nanostructures and in the first opening; a polymer layer is selectively deposited over the top surface of the lower gate electrode, wherein the polymer layer comprises a first polymer; a first metal-containing layer is selectively formed around the upper semiconductor nanostructures and in the second opening; the polymer layer is replaced with a dielectric layer; and an upper gate electrode layer is deposited over the first metal-containing layer, the dielectric layer, and the lower gate electrode. In an embodiment, the first polymer is an anionic polymer comprising polyacrylic acid (PAA) or polyvinyl alcohol (PVA). In an embodiment, the polymer layer also comprises a second polymer, wherein the second polymer is a nonionic polymer. In an embodiment, the nonionic polymer comprises polyacrylamide, polyethylene glycol, polystyrene sulfonate, or polyvinylpyrrolidone. In an embodiment, the method further includes selectively forming a second metal-containing layer around the first metal-containing layer, around the upper semiconductor nanostructure, and in the second opening. In an embodiment, the first metal-containing layer comprises titanium aluminum, and the second metal-containing layer comprises titanium nitride. In an embodiment, replacing the polymer layer with a dielectric layer includes: removing the polymer layer by exposing the surface of the polymer layer to water or an aqueous solution having a pH level equal to or higher than 7; and forming a dielectric layer over the top surface of the lower gate electrode.

[0096] According to an embodiment, the semiconductor device includes: a plurality of first nanostructures extending between first source / drain regions; a plurality of second nanostructures located above the plurality of first nanostructures extending between second source / drain regions; an isolation structure located between the plurality of first nanostructures and the plurality of second nanostructures; a first gate stack located around the plurality of first nanostructures; an isolation layer disposed on the top surface of the first gate stack and adjacent to the sidewalls of the isolation structure; and a second gate stack located above the isolation layer, the isolation structure, and the first gate stack, the second gate stack being disposed around the plurality of second nanostructures, wherein the second gate stack includes: a first metal-containing layer located around the second nanostructures of the plurality of second nanostructures; a second metal-containing layer located above the first metal-containing layer and around the second nanostructures of the plurality of second nanostructures; and a first gate electrode layer located above the first metal-containing layer and the second metal-containing layer, wherein the bottom surfaces of the first metal-containing layer and the second metal-containing layer are in contact with the isolation layer. In an embodiment, the first metal-containing layer includes titanium aluminum, and the second metal-containing layer includes titanium nitride. In an embodiment, the isolation layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. In an embodiment, the isolation layer electrically isolates the first gate stack from the second gate stack. In an embodiment, the device further includes a gate dielectric layer disposed between a first sidewall of the isolation layer and a second sidewall of the isolation structure.

[0097] Some embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack above a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and pseudo-nanostructures; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; forming an upper source / drain region above the lower source / drain regions, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; removing the pseudo-nanostructure to form a first opening between the lower semiconductor nanostructures, and A second opening is formed between the upper semiconductor nanostructures; a gate dielectric layer is formed around the lower semiconductor nanostructure and the upper semiconductor nanostructure; a lower gate electrode is formed around the lower semiconductor nanostructure and in the first opening; a dummy layer comprising a first polymer is selectively deposited over the top surface of the lower gate electrode; and an upper gate electrode is formed around the upper semiconductor nanostructure and in the second opening, wherein the sidewalls of the upper gate electrode are in contact with a gate spacer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein the upper gate electrode comprises a titanium-containing material.

[0098] In some embodiments, the first polymer is an anionic polymer. In some embodiments, the anionic polymer includes polyacrylic acid (PAA) or polyvinyl alcohol (PVA). In some embodiments, the dummy layer also includes a second polymer, wherein the second polymer is a nonionic polymer. In some embodiments, the nonionic polymer includes polyacrylamide, polyethylene glycol, polystyrene sulfonate, or polyvinylpyrrolidone. In some embodiments, forming the upper gate electrode further includes: forming a first metal-containing layer around the upper semiconductor nanostructure and in the second opening; forming a second metal-containing layer around the first metal-containing layer and in the second opening; and depositing an upper gate electrode layer over the lower gate electrode, the first metal-containing layer, and the second metal-containing layer. In some embodiments, the method further includes: removing the dummy layer by exposing the surface of the dummy layer to water or an aqueous solution having a pH level equal to or greater than 7; and forming a dielectric layer over the top surface of the lower gate electrode. In some embodiments, the first metal-containing layer includes titanium aluminum, and the second metal-containing layer includes titanium nitride.

[0099] Some other embodiments of this application provide a method for forming a semiconductor device, comprising: forming a multilayer stack over a semiconductor substrate, the multilayer stack including alternating semiconductor layers and dummy layers; patterning the multilayer stack to form fins, wherein the fins include alternating semiconductor nanostructures and dummy nanostructures, the semiconductor nanostructures being defined by the semiconductor layers and the dummy nanostructures being defined by the dummy layers; forming a lower source / drain region, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; and forming an upper source / drain region over the lower source / drain regions, wherein the upper semiconductor nanostructure... A semiconductor nanostructure extends between the upper source / drain regions; the pseudo-nanostructure is removed to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; a lower gate electrode is formed around the lower semiconductor nanostructures and in the first opening; a polymer layer is selectively deposited over the top surface of the lower gate electrode, wherein the polymer layer comprises a first polymer; a first metal-containing layer is selectively formed around the upper semiconductor nanostructures and in the second opening; the polymer layer is replaced with a dielectric layer; and an upper gate electrode layer is deposited over the first metal-containing layer, the dielectric layer, and the lower gate electrode.

[0100] In some embodiments, the first polymer is an anionic polymer comprising polyacrylic acid (PAA) or polyvinyl alcohol (PVA). In some embodiments, the polymer layer also comprises a second polymer, wherein the second polymer is a nonionic polymer. In some embodiments, the nonionic polymer comprises polyacrylamide, polyethylene glycol, polystyrene sulfonate, or polyvinylpyrrolidone. In some embodiments, the method further comprises selectively forming a second metal-containing layer around the first metal-containing layer, around the upper semiconductor nanostructure, and in the second opening. In some embodiments, the first metal-containing layer comprises titanium aluminum, and the second metal-containing layer comprises titanium nitride. In some embodiments, replacing the polymer layer with the dielectric layer comprises removing the polymer layer by exposing the surface of the polymer layer to water or an aqueous solution having a pH level equal to or greater than 7; and forming the dielectric layer over the top surface of the lower gate electrode.

[0101] Some embodiments of this application provide a semiconductor device comprising: a plurality of first nanostructures extending between first source / drain regions; a plurality of second nanostructures extending between second source / drain regions above the plurality of first nanostructures; an isolation structure between the plurality of first nanostructures and the plurality of second nanostructures; a first gate stack surrounding the plurality of first nanostructures; an isolation layer disposed on the top surface of the first gate stack and adjacent to the sidewall of the isolation structure; and a second gate stack surrounding the plurality of second nanostructures, wherein the second gate stack comprises: a first metal-containing layer surrounding the second nanostructures of the plurality of second nanostructures; a second metal-containing layer surrounding the first metal-containing layer and the second nanostructures of the plurality of second nanostructures; and a first gate electrode layer surrounding the first metal-containing layer and the second metal-containing layer, wherein the bottom surfaces of the first metal-containing layer and the second metal-containing layer are in contact with the isolation layer.

[0102] In some embodiments, the first metal-containing layer comprises titanium aluminum, and the second metal-containing layer comprises titanium nitride. In some embodiments, the isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. In some embodiments, the isolation layer electrically isolates the first gate stack from the second gate stack. In some embodiments, the semiconductor device further includes a gate dielectric layer disposed between a first sidewall of the isolation layer and a second sidewall of the isolation structure.

[0103] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A multilayer stack is formed on a semiconductor substrate, the multilayer stack comprising alternating semiconductor nanostructures and pseudo-nanostructures; A lower source / drain region is formed, wherein the lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; An upper source / drain region is formed above the lower source / drain region, wherein the upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; The pseudo-nanostructure is removed to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; A gate dielectric layer is formed around the lower semiconductor nanostructure and the upper semiconductor nanostructure; A lower gate electrode is formed around the lower semiconductor nanostructure and in the first opening; A dummy layer is selectively deposited above the top surface of the lower gate electrode, the dummy layer comprising a first polymer; and An upper gate electrode is formed around the upper semiconductor nanostructure and in the second opening, wherein the sidewall of the upper gate electrode is in contact with the gate spacer, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer, and wherein the upper gate electrode comprises a titanium-containing material.

2. The method according to claim 1, wherein, The first polymer is an anionic polymer.

3. The method according to claim 2, wherein, The anionic polymer includes polyacrylic acid (PAA) or polyvinyl alcohol (PVA).

4. The method according to claim 2, wherein, The pseudo-layer also includes a second polymer, wherein the second polymer is a nonionic polymer.

5. The method according to claim 4, wherein, The nonionic polymer includes polyacrylamide, polyethylene glycol, polystyrene sulfonate, or polyvinylpyrrolidone.

6. The method according to claim 1, wherein, The formation of the upper gate electrode further includes: A first metal-containing layer is formed around the upper semiconductor nanostructure and in the second opening; A second metal-containing layer is formed around the first metal-containing layer and in the second opening; and An upper gate electrode layer is deposited above the lower gate electrode, the first metal-containing layer, and the second metal-containing layer.

7. The method according to claim 6, further comprising: The dummy layer is removed by exposing its surface to water or an aqueous solution with a pH level equal to or higher than 7. as well as A dielectric layer is formed above the top surface of the lower gate electrode.

8. The method according to claim 7, wherein, The first metal-containing layer comprises titanium aluminum, and the second metal-containing layer comprises titanium nitride.

9. A method for forming a semiconductor device, comprising: A multilayer stack is formed over a semiconductor substrate, the multilayer stack comprising alternating semiconductor layers and dummy layers; The multilayer stack is patterned to form a fin, wherein the fin comprises alternating semiconductor nanostructures and pseudo-nanostructures, the semiconductor nanostructures being defined by the semiconductor layers and the pseudo-nanostructures being defined by the pseudo layers; A lower source / drain region is formed, wherein the lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions; An upper source / drain region is formed above the lower source / drain region, wherein the upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions; The pseudo-nanostructure is removed to form a first opening between the lower semiconductor nanostructures and a second opening between the upper semiconductor nanostructures; A lower gate electrode is formed around the lower semiconductor nanostructure and in the first opening; A polymer layer is selectively deposited over the top surface of the lower gate electrode, wherein the polymer layer comprises a first polymer; A first metal-containing layer is selectively formed around the upper semiconductor nanostructure and in the second opening; Replace the polymer layer with a dielectric layer; and An upper gate electrode layer is deposited above the first metal layer, the dielectric layer, and the lower gate electrode.

10. A semiconductor device, comprising: Multiple first nanostructures extend between first source / drain regions; Multiple second nanostructures are located above the multiple first nanostructures, and the multiple second nanostructures extend between the second source / drain regions; An isolation structure is located between the plurality of first nanostructures and the plurality of second nanostructures; A first gate stack is located around the plurality of first nanostructures; An isolation layer is disposed on the top surface of the first gate stack and adjacent to the sidewall of the isolation structure; as well as A second gate stack is located above the isolation layer, the isolation structure, and the first gate stack, and is disposed around the plurality of second nanostructures, wherein the second gate stack includes: A first metal-containing layer is located around the plurality of second nanostructures; A second metal-containing layer is located above the first metal-containing layer and around the second nanostructures of the plurality of second nanostructures; and A first gate electrode layer is located above the first metal-containing layer and the second metal-containing layer, wherein the bottom surfaces of the first metal-containing layer and the second metal-containing layer are in contact with the isolation layer.

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