Display substrate and display device

Abstract

A display substrate (910) includes a substrate (10) and a gate drive circuit disposed on the substrate (10). The gate drive circuit comprises a plurality of cascaded shift register circuits (GOA). A shift register circuit (GOA) includes a plurality of oxide transistors. The plurality of oxide transistors includes a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors including at least one oxide transistor. The bottom gate and the top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and the top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal; and the bottom gate and the top gate of each oxide transistor in the second group of oxide transistors are mutually independent.

Description

Display substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202410544894.4, filed on April 30, 2024, and entitled “Shift register unit and driving method thereof, gate drive circuit, and display device”, the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0003] With the progress of display technology, a gate drive circuit is usually arranged on a display substrate by using an array substrate row driving technology to facilitate a narrow frame design. The gate drive circuit is connected with multiple rows of pixels on the display substrate, and is used to transmit a gate drive signal to the multiple rows of pixels row by row to light up the pixels row by row, i.e., to realize row-by-row scanning and refreshing, so that the display substrate can display a picture.

[0004] SUMMARY

[0005] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0006] The present embodiments provide a display substrate and a display device.

[0007] In one aspect, the present embodiments provide a display substrate, comprising: a substrate and a gate drive circuit arranged on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, each shift register circuit comprising: a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors comprising at least one oxide transistor. The bottom gate and the top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and the top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal. The bottom gate and the top gate of each oxide transistor in the second group of oxide transistors are independent of each other.

[0008] In some example embodiments, the second group of oxide transistors comprises: a plurality of oxide transistors, and the bottom gates of the plurality of oxide transistors in the second group of oxide transistors are connected to the same voltage line.

[0009] In some example embodiments, the second group of oxide transistors includes an oxide output transistor and a plurality of oxide switch transistors; the oxide output transistor is directly connected to an output terminal of the shift register circuit. Bottom gates of the oxide output transistor and the plurality of oxide switch transistors are independently arranged. Bottom gates of at least some oxide switch transistors in the plurality of oxide switch transistors are connected to the same voltage line.

[0010] In some example embodiments, the plurality of oxide switch transistors in the second group of oxide transistors are divided into a first group of oxide switch transistors and a second group of oxide switch transistors, each group of oxide switch transistors including at least one oxide switch transistor; in a frame duration, a duty cycle of a first potential of a top gate voltage signal of an oxide switch transistor in the first group of oxide switch transistors is greater than a duty cycle of a first potential of a top gate voltage signal of an oxide switch transistor in the second group of oxide switch transistors. A bottom gate of at least one oxide switch transistor in the first group of oxide switch transistors is connected to a first voltage line; a bottom gate of at least one oxide switch transistor in the second group of oxide switch transistors is connected to a second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals.

[0011] In some example embodiments, each group of oxide switch transistors includes a plurality of oxide switch transistors; bottom gates of at least some oxide switch transistors in the plurality of oxide switch transistors in the first group of oxide switch transistors are in a unitary structure, and bottom gates of the plurality of oxide switch transistors in the second group of oxide switch transistors are in a unitary structure.

[0012] In some example embodiments, in a direction perpendicular to the display substrate, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged on the base. Top gates of the plurality of oxide transistors are located in the third conductive layer, active layers of the plurality of oxide transistors are located in the second semiconductor layer, and bottom gates of the plurality of oxide transistors are located in the second conductive layer.

[0013] In some example embodiments, the shift register circuit comprises an input shift circuit, a transmission control circuit and a driving enhancement circuit. The input shift circuit is connected with a first clock terminal, a second clock terminal, a third clock terminal, a fourth clock terminal, an input terminal of the shift register circuit, a reset control terminal, a first intermediate node and a second intermediate node respectively, and is configured to control potentials of the first intermediate node and the second intermediate node under control of the first clock terminal, the second clock terminal, the third clock terminal, the fourth clock terminal, the input terminal and the reset control terminal. The transmission control circuit is connected with the first intermediate node, the second intermediate node, an enable control terminal and the driving enhancement circuit respectively, and is configured to provide an output signal to the driving enhancement circuit under control of the first intermediate node, the second intermediate node and the enable control terminal. The driving enhancement circuit is connected between the transmission control circuit and an output terminal of the shift register circuit, and is configured to output the output signal provided by the transmission control circuit after at least one inversion processing. The input shift circuit, the transmission control circuit and the driving enhancement circuit are arranged in sequence along a first direction in a projection of the substrate.

[0014] In some example embodiments, the input shift circuit comprises a first NOR gate circuit, a first NOT gate circuit, a first transmission gate circuit and a second transmission gate circuit. The first transmission gate circuit is connected with the first clock terminal, the second clock terminal, the input terminal of the shift register circuit and an input node, and is configured to control continuity of the input terminal and the input node under control of the first clock terminal and the second clock terminal. The second transmission gate circuit is connected with the third clock terminal, the fourth clock terminal, the input node and the second intermediate node, and is configured to control continuity of the input node and the second intermediate node under control of the third clock terminal and the fourth clock terminal. The first NOR gate circuit is connected with the input node, the reset control terminal and the first intermediate node, and is configured to control the potential of the first intermediate node under control of the input node and the reset control terminal. The first NOT gate circuit is connected between the first intermediate node and the second intermediate node. The first transmission gate circuit, the second transmission gate circuit and the first NOT gate circuit are arranged in sequence along a second direction in a projection of the substrate, and are located between the first NOR gate circuit and the transmission control circuit in the projection of the substrate in the first direction; the second direction intersects the first direction.

[0015] In some example embodiments, the first transmission gate circuit comprises a first P-type transistor and a first N-type transistor; a gate of the first P-type transistor is connected with the second clock end; a top gate and a bottom gate of the first N-type transistor are connected and connected with the first clock end; a first pole of the first P-type transistor and a first pole of the first N-type transistor are both connected with an input end of the shift register circuit, and a second pole of the first P-type transistor and a second pole of the first N-type transistor are both connected with the input node. The second transmission gate circuit comprises a fifth P-type transistor and a fifth N-type transistor; a gate of the fifth P-type transistor is connected with the fourth clock end; a top gate and a bottom gate of the fifth N-type transistor are connected and connected with the third clock end; a first pole of the fifth P-type transistor and a first pole of the fifth N-type transistor are both connected with the input node, and a second pole of the fifth P-type transistor and a second pole of the fifth N-type transistor are both connected with the second intermediate node. The first P-type transistor and the first N-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate; the fifth P-type transistor and the fifth N-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate. The first P-type transistor and the fifth P-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate; the first N-type transistor and the fifth N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate.

[0016] In some example embodiments, the transmission control circuit comprises a second NOR gate circuit, a third transmission gate circuit and a capacitor. The third transmission gate circuit is connected with the first intermediate node, the second intermediate node, the enable control end, a first input end of the second NOR gate circuit and the capacitor, and is configured to control the on-off of the enable control end and the first input end of the second NOR gate circuit under the control of the first intermediate node and the second intermediate node. A second input end of the second NOR gate circuit is connected with the second intermediate node, and an output end of the second NOR gate circuit is connected with the drive enhancement circuit. The second NOR gate circuit and the third transmission gate circuit are arranged in sequence along the second direction in the orthographic projection of the substrate, and the third transmission gate circuit is located between the capacitor and the first NOR gate circuit in the orthographic projection of the substrate in the first direction.

[0017] In some example embodiments, the driving enhancement circuit includes: a second NOT gate circuit, a third NOT gate circuit and a fourth NOT gate circuit connected in series; the second NOT gate circuit, the third NOT gate circuit and the fourth NOT gate circuit are arranged in sequence along the first direction in the orthographic projection of the substrate. The orthographic projection of the second NOT gate circuit in the substrate is adjacent to the orthographic projection of the capacitor in the second direction, and the orthographic projection of the capacitor in the substrate is located between the orthographic projections of the third transmission gate circuit and the third NOT gate circuit in the first direction.

[0018] In some example embodiments, the first or NOT gate circuit comprises a second P-type transistor, a third P-type transistor, a second N-type transistor and a third N-type transistor; the gate of the third P-type transistor and the top gate of the third N-type transistor are connected with the reset control end, the gate of the second P-type transistor and the top gate of the second N-type transistor are connected with the input node, the first pole of the third P-type transistor is connected with the first power supply end, the second pole of the third P-type transistor is connected with the first pole of the second P-type transistor, the second pole of the second P-type transistor, the second pole of the second N-type transistor and the second pole of the third N-type transistor are connected with the first intermediate node, the first pole of the second N-type transistor and the first pole of the third N-type transistor are connected with the second power supply end. The second or NOT gate circuit comprises a seventh P-type transistor, an eighth P-type transistor, a seventh N-type transistor and an eighth N-type transistor; the gate of the eighth P-type transistor and the top gate of the eighth N-type transistor are connected with the third transmission gate circuit, the gate of the seventh P-type transistor and the top gate of the seventh N-type transistor are connected with the second intermediate node, the first pole of the eighth P-type transistor is connected with the first power supply end, the second pole of the eighth P-type transistor is connected with the first pole of the seventh P-type transistor, the second pole of the seventh P-type transistor, the second pole of the seventh N-type transistor and the second pole of the eighth N-type transistor are connected, serving as the output end of the second or NOT gate circuit, the first pole of the seventh N-type transistor and the first pole of the eighth N-type transistor are both connected with the second power supply end. The third transmission gate circuit comprises a sixth P-type transistor and a sixth N-type transistor, the gate of the sixth P-type transistor is connected with the second intermediate node, the top gate of the sixth N-type transistor is connected with the first intermediate node, the first pole of the sixth P-type transistor and the first pole of the sixth N-type transistor are connected with the enable control end, the second pole of the sixth P-type transistor and the second pole of the sixth N-type transistor are connected with the gate of the eighth P-type transistor of the second or NOT gate circuit. The first NOT gate circuit comprises a fourth P-type transistor and a fourth N-type transistor, the gate of the fourth P-type transistor and the top gate of the fourth N-type transistor are connected with the first intermediate node, the first pole of the fourth P-type transistor is connected with the first power supply end, the second pole of the fourth P-type transistor and the second pole of the fourth N-type transistor are connected with the second intermediate node, the first pole of the fourth N-type transistor is connected with the second power supply end.The second NOT gate circuit comprises a ninth P-type transistor and a ninth N-type transistor, the gate of the ninth P-type transistor and the top gate of the ninth N-type transistor are connected with the output terminal of the second NOT gate circuit, the first pole of the ninth P-type transistor is connected with the first power supply terminal, the first pole of the ninth N-type transistor is connected with the second power supply terminal, the second pole of the ninth P-type transistor and the second pole of the ninth N-type transistor are connected as the output terminal of the second NOT gate circuit. The third NOT gate circuit comprises a tenth P-type transistor and a tenth N-type transistor, the gate of the tenth P-type transistor and the top gate of the tenth N-type transistor are connected with the output terminal of the second NOT gate circuit, the first pole of the tenth P-type transistor is connected with the first power supply terminal, the first pole of the tenth N-type transistor is connected with the second power supply terminal, the second pole of the tenth P-type transistor and the second pole of the tenth N-type transistor are connected as the output terminal of the third NOT gate circuit. The bottom gates of the second N-type transistor, the seventh N-type transistor, the eighth N-type transistor and the tenth N-type transistor are connected with the first voltage line. The bottom gates of the third N-type transistor, the fourth N-type transistor, the sixth N-type transistor and the ninth N-type transistor are connected with the second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals.

[0019] In some example embodiments, the bottom gates of the second N-type transistor, the seventh N-type transistor and the eighth N-type transistor of any stage of the shift register circuit are in one structure.

[0020] In some example embodiments, the bottom gate of the tenth N-type transistor of the n-th stage of the shift register circuit is connected with the bottom gates of the second N-type transistor, the seventh N-type transistor and the eighth N-type transistor of the n+1-th stage of the shift register circuit through a first bottom gate connecting line; the first bottom gate connecting line is in a polyline shape extending along the first direction in the orthographic projection of the substrate, and is located between the orthographic projections of the n-th stage of the shift register circuit and the n+1-th stage of the shift register circuit.

[0021] In some example embodiments, the bottom gates of the third N-type transistor and the fourth N-type transistor of any stage of the shift register circuit are in one structure, and the one structure is connected with the bottom gates of the sixth N-type transistor and the ninth N-type transistor of the shift register circuit through a third bottom gate connecting line. The third bottom gate connecting line is in a polyline shape extending along the first direction in the orthographic projection of the substrate, and is located between the orthographic projections of the third transmission gate circuit and the second NOT gate circuit of the shift register circuit, and is located between the orthographic projections of the second transmission gate circuit and the first NOT gate circuit.

[0022] In some example embodiments, the third P-type transistor, the second P-type transistor and the second N-type transistor are arranged in a stepped manner along the second direction in the orthographic projection of the substrate, and the second N-type transistor and the third N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate. The third N-type transistor and the fourth N-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate; and the fourth P-type transistor is located on the side of the fourth N-type transistor away from the orthographic projection of the third N-type transistor in the first direction in the orthographic projection of the substrate.

[0023] In some example embodiments, the sixth N-type transistor and the sixth P-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate. The seventh N-type transistor and the eighth N-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate. The sixth N-type transistor and the seventh N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate, and the sixth P-type transistor and the eighth N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate. The seventh P-type transistor and the eighth P-type transistor are arranged in sequence along the first direction in the orthographic projection of the substrate.

[0024] In some example embodiments, the ninth P-type transistor and the tenth N-type transistor are arranged in sequence along the first direction in the orthographic projection of the substrate. The ninth N-type transistor and the ninth P-type transistor are arranged in misalignment along the second direction in the orthographic projection of the substrate. The tenth N-type transistor and the tenth P-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate.

[0025] In some example embodiments, the fourth non-gate circuit comprises an eleventh N-type transistor and an eleventh P-type transistor; the gate of the eleventh P-type transistor and the top gate of the eleventh N-type transistor are connected to the output terminal of the third non-gate circuit, the first pole of the eleventh P-type transistor is connected to the first power supply terminal, the first pole of the eleventh N-type transistor is connected to the second power supply terminal, the second pole of the eleventh P-type transistor and the second pole of the eleventh N-type transistor are connected to the output terminal of the shift register circuit; and the bottom gate of the eleventh N-type transistor is connected to the third voltage line. The eleventh N-type transistor and the eleventh P-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate; the eleventh N-type transistor and the tenth P-type transistor are adjacent in the first direction in the orthographic projection of the substrate, and the eleventh P-type transistor and the tenth N-type transistor are adjacent in the first direction in the orthographic projection of the substrate.

[0026] In some example embodiments, the first voltage line, the second voltage line and the third voltage line are located in the same conductive layer; the third voltage line is located on a side of the eleventh N-type transistor away from the tenth P-type transistor in the first direction in the orthographic projection of the substrate; the first voltage line and the second voltage line are located on a side of the input shift circuit away from the transmission control circuit in the first direction in the orthographic projection of the substrate.

[0027] In another aspect, the embodiments provide a display device including the display substrate as described above.

[0028] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings.

[0029] SUMMARY

[0030] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0031] FIG. 1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0032] FIG. 2 is a schematic diagram of a gate-level circuit of a shift register circuit according to at least one embodiment of the present disclosure;

[0033] FIG. 3 is an equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0034] FIG. 4 is a local brush driving timing diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0035] FIG. 5 is another equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0036] FIG. 6 is another equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0037] FIG. 7 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0038] FIG. 8 is a schematic diagram of a partial cross-sectional view of a display area of a display substrate according to at least one embodiment of the present disclosure;

[0039] FIG. 9 is a schematic diagram of a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0040] FIG. 10 is a schematic diagram of the display substrate after forming a first semiconductor layer in FIG. 9;

[0041] FIG. 11A is a schematic diagram of the display substrate after forming a first conductive layer in FIG. 9;

[0042] FIG. 11B is a schematic view of the first conductive layer in FIG. 11A;

[0043] FIG. 12A is a schematic view of the display substrate after forming the second conductive layer in FIG. 9;

[0044] FIG. 12B is a schematic view of the second conductive layer in FIG. 12A;

[0045] FIG. 13A is a schematic view of the display substrate after forming the second semiconductor layer in FIG. 9;

[0046] FIG. 13B is a schematic view of the second semiconductor layer in FIG. 13A;

[0047] FIG. 14A is a schematic view of the display substrate after forming the third conductive layer in FIG. 9;

[0048] FIG. 14B is a schematic view of the third conductive layer in FIG. 14A;

[0049] FIGS. 15A and 15B are schematic views of the display substrate after forming the fifth insulating layer in FIG. 9;

[0050] FIG. 16A is a schematic view of the display substrate after forming the fourth conductive layer in FIG. 9;

[0051] FIG. 16B is a schematic view of the fourth conductive layer in FIG. 16A;

[0052] FIG. 17 is a schematic view of the display substrate after forming the seventh insulating layer in at least one embodiment of the present disclosure;

[0053] FIG. 18A is a schematic view of the display substrate after forming the fifth conductive layer in at least one embodiment of the present disclosure;

[0054] FIG. 18B is a schematic view of the fifth conductive layer in FIG. 18A;

[0055] FIG. 19 is a schematic view of a display device in at least one embodiment of the present disclosure.

[0056] DETAILED DESCRIPTION

[0057] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. Embodiments can be implemented in a variety of different forms. It is readily apparent to one of ordinary skill in the art that the embodiments and features of the embodiments can be freely combined with each other and can be implemented in other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the embodiments described below. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other without departing from the scope of the present disclosure.

[0058] In the drawings, the size, the thickness, or the region of one or a plurality of components is sometimes exaggerated for the sake of clarity. Thus, one embodiment of the present disclosure is not necessarily limited to such a scale. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to shapes or values shown in the drawings.

[0059] The ordinal numbers such as "first", "second", and "third" in this specification are used for the purpose of avoiding confusion among components, and are not for the purpose of numbering the components in the order of their importance. "A plurality of" in the present disclosure indicates a number of two or more.

[0060] In this specification, terms of "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship are used to describe the positional relationship of components with reference to the drawings, for the convenience of the description of this specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relationship of components is appropriately changed according to the direction of the components described. Therefore, it is not limited to the terms described in the specification, and can be appropriately changed depending on the situation.

[0061] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements. Among them, "connection" includes "electrical connection". "Electrical connection" includes the case where the components are connected together through elements having certain electrical effects. "Elements having certain electrical effects" are not particularly limited as long as they can transmit electrical signals between the connected components. Examples of "elements having certain electrical effects" include not only electrodes and wires, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like. The meaning of the above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0062] In this specification, a transistor refers to an element including at least a gate (gate electrode), a drain, and a source. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. Among them, the channel region refers to a region where current mainly flows.

[0063] In this specification, the first electrode can be a drain electrode, the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In addition, the gate electrode can also be referred to as a control electrode. The functions of the "source" and "drain" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the current direction is changed in circuit operation. Thus, the "source" and "drain" can be interchanged with each other in this specification.

[0064] In this specification, "parallel" means a state where the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus also includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus also includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0065] In this specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, or an approximate hexagon, and can include some small deformations due to a tolerance, such as a fillet, a rounded corner, and a deformation.

[0066] In this specification, "approximately" and "substantially" mean that a limit is not strictly defined and a range of process and measurement errors is allowed. In this disclosure, "the same" and "substantially the same" mean a case where the difference between the values is within 10%.

[0067] In this specification, A extends along the direction of B means that A can include a main portion and a sub portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction of B, and the length of the main portion extending along the direction of B is greater than the length of the sub portion extending along another direction. In this specification, "A extends along the direction of B" means "the main portion of A extends along the direction of B".

[0068] With the rapid development of OLED display technology, various requirements such as high resolution, narrow frame, and low power consumption are put forward for display products. Local refresh technology (for example, a part of the screen displays high-frequency refresh, and another part displays low-frequency refresh) has considerable benefits in reducing power consumption, and therefore is highly concerned. In display products using local refresh technology, the structure of the gate driving circuit is relatively complex, and how to achieve better driving stability is a problem to be solved.

[0069] The embodiment provides a display substrate, comprising: a substrate and a gate drive circuit arranged on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits (also referred to as shift register circuits or shift register units), each shift register circuit comprising: a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors comprising at least one oxide transistor. The bottom gate and the top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and the top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal; the bottom gate and the top gate of each oxide transistor in the second group of oxide transistors are independent of each other.

[0070] The display substrate provided by the embodiment can distinguish and connect the bottom gates of the plurality of oxide transistors in the shift register circuit, so as to reduce the influence of the long-time bias of the gate of the oxide transistor on the threshold voltage drift of the transistor, thereby improving the driving capability and stability of the shift register circuit.

[0071] In some example embodiments, the second group of oxide transistors can comprise: a plurality of oxide transistors, the bottom gates of the plurality of oxide transistors in the second group of oxide transistors being connected to the same voltage line. The bottom gates of the plurality of oxide transistors in the second group of oxide transistors can be configured to receive the same voltage signal. The example interconnects the bottom gates of all the oxide transistors in the second group of oxide transistors, which not only ensures the driving capability and stability of the shift register circuit, but also reduces the additional wiring.

[0072] In some example embodiments, the second group of oxide transistors can comprise: an oxide output transistor and a plurality of oxide switch transistors; the oxide output transistor is directly connected to the output end of the shift register circuit. The bottom gate of the oxide output transistor and the bottom gates of the plurality of oxide switch transistors are independently arranged; the bottom gates of at least some oxide switch transistors in the plurality of oxide switch transistors are connected to the same voltage line. The bottom gates of the at least some oxide switch transistors in the second group of oxide transistors can be configured to receive the same voltage signal. The example can separately control the bottom gates of the oxide output transistor and the plurality of oxide switch transistors in the second group of oxide transistors, so as to independently adjust the threshold voltage, which is conducive to improving the output stability of the shift register circuit.

[0073] In some example embodiments, the plurality of oxide switch transistors within the second group of oxide transistors can be divided into a first group of oxide switch transistors and a second group of oxide switch transistors, each group of oxide switch transistors including at least one oxide switch transistor. A duty cycle of the first potential of the top gate voltage signal of the oxide switch transistors within the first group of oxide switch transistors over a frame duration is greater than a duty cycle of the first potential of the top gate voltage signal of the oxide switch transistors within the second group of oxide switch transistors over the frame duration. The duty cycle of the first potential of the top gate voltage signal of the oxide switch transistors over the frame duration can refer to a ratio of a duration of the first potential of the top gate voltage signal over the frame duration, i.e., a proportion of the duration of the first potential of the top gate voltage signal over the frame duration. For example, the first potential can be a high potential or a low potential; the high potential can be represented by binary "1", and the low potential can be represented by binary "0". The bottom gate of the at least one oxide switch transistor within the first group of oxide switch transistors is connected to the first voltage line; the bottom gate of the at least one oxide switch transistor within the second group of oxide switch transistors is connected to the second voltage line; and the first voltage line and the second voltage line are configured to provide different voltage signals. The present example can further precisely adjust the threshold voltage of the oxide switch transistors by further grouping control of the bottom gates of the plurality of oxide switch transistors within the second group of oxide transistors.

[0074] The scheme of the present embodiments is exemplified below by some examples.

[0075] In some examples, the display substrate can include a display region and a non-display region. For example, the non-display region can be a peripheral region located at a periphery of the display region. However, the present embodiments are not limited thereto. For example, the non-display region can be located between adjacent display regions.

[0076] In some examples, the display region can include a plurality of light emitting units. One pixel within the display region can include three light emitting units (which can also be referred to as sub-pixels), and the three sub-pixels can be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the present embodiments are not limited thereto. In some examples, one pixel can include four sub-pixels, and the four sub-pixels can be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0077] In some examples, the sub-pixel can include a pixel circuit and a light emitting element connected to the pixel circuit. The shape of the light emitting element can be rectangular, rhombic, pentagonal or hexagonal. When one pixel includes three sub-pixels, the light emitting elements of the three sub-pixels can be arranged in a horizontal parallel, vertical parallel or triangular manner. When one pixel includes four sub-pixels, the light emitting elements of the four sub-pixels can be arranged in a horizontal parallel, vertical parallel or square manner. However, the present embodiment is not limited in this regard.

[0078] In some examples, the display area can include at least: a plurality of pixel circuits arranged in an array, a plurality of gate lines (e.g., including scan lines, reset signal lines, light emitting control lines) extending in a first direction, a plurality of data lines and a power line extending in a second direction. The plurality of rows of pixel circuits can be arranged in the second direction, and each row of pixel circuits can include a plurality of pixel circuits arranged in the first direction. The first direction and the second direction can be in the same plane, and the first direction can intersect the second direction, for example, the first direction can be perpendicular to the second direction. For example, the first direction can include a horizontal direction, and the second direction can include a vertical direction.

[0079] In some examples, the pixel circuit can be configured to drive the connected light emitting element. For example, the pixel circuit can be configured to provide a drive current to drive the light emitting element to emit light. The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, and the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0080] In some examples, the pixel circuit can include P-type transistors and N-type transistors. The P-type transistor is turned on when the gate is at a low potential and is turned off when the gate is at a high potential. The N-type transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential. The N-type transistor can be an oxide thin film transistor, and the P-type transistor can be a low temperature poly-silicon thin film transistor. The active layer of the low temperature poly-silicon thin film transistor uses low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-oxide (LTPO+Oxide) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption and improve display quality.

[0081] In some examples, the non-display region can be provided with a timing controller, a data driving circuit, and a gate driving circuit. The gate driving circuit can be provided on opposite sides of the display region, for example, on the left and right sides of the display region (such as the left and right bezel regions included in the peripheral region). The timing controller and the data driving circuit can be provided on one side of the display region, for example, on the lower side of the display region (such as the lower bezel region included in the peripheral region). However, the present embodiment is not limited thereto. In some examples, the gate driving circuit can be located in the display region.

[0082] In some examples, the data driving circuit can provide a data signal to the sub-pixels of the display region through the data line. The timing controller can provide a driving signal to the data driving circuit and the gate driving circuit. The actions of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide a gray scale data to the data driving circuit, which specifies the gray scale to be displayed by the sub-pixel. The data driving circuit can provide a data signal corresponding to the potential of the gray scale data of the sub-pixel to the sub-pixels of the row selected by the gate driving circuit through the data line.

[0083] In some examples, the display substrate can include a plurality of gate driving circuits, such as a gate driving circuit for providing a gate driving signal to a P-type transistor in the pixel circuit, a gate driving circuit for providing a gate driving signal to an N-type transistor in the pixel circuit, and the like. Each gate driving circuit can include a plurality of cascaded shift register circuits. The output end of each shift register circuit can be connected to a plurality of pixel circuits in a corresponding row of pixel circuits, respectively, and configured to provide a gate driving signal to the row of pixel circuits.

[0084] FIG. 1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the shift register circuit provided by the present embodiment can include an input shift circuit 11, a transmission control circuit 12, and a driving enhancement circuit 13.

[0085] In some examples, the input shift circuit 11 can be connected to a first clock end CKn, a second clock end CB, a third clock end CBn, a fourth clock end CK, an input end IN_n of the shift register circuit, a reset control end Trst, a first intermediate node Q1_n, and a second intermediate node Q2_n, and configured to control the potentials of the first intermediate node Q1_n (or marked as GNc_n) and the second intermediate node Q2_n (or marked as GPc_n) under the control of the first clock end CKn, the second clock end CB, the third clock end CBn, the fourth clock end CK, the input end IN_n, and the reset control end Trst.

[0086] In some examples, the input shift circuit 11 can include an input control circuit 111, a first control circuit 112 and a latch circuit 113. The input control circuit 111 can be connected with the first clock terminal CKn, the second clock terminal CB, the input terminal IN_n and the input node Q_n, and configured to control the on-off of the input terminal IN_n and the input node Q_n in response to the first clock signal provided by the first clock terminal CKn and the second clock signal provided by the second clock terminal CB. The first control circuit 112 can be connected with the reset control terminal Trst, the input node Q_n and the first intermediate node Q1_n, and configured to control the potential of the first intermediate node Q1_n based on the potential of the input node Q_n and the reset signal provided by the reset control terminal Trst. The latch circuit 113 can be connected with the third clock terminal CBn, the fourth clock terminal CK, the input node Q_n, the first intermediate node Q1_n and the second intermediate node Q2_n, and configured to control the on-off of the second intermediate node Q2_n and the input node Q_n in response to the third clock signal provided by the third clock terminal CBn and the fourth clock signal provided by the fourth clock terminal CK, and transmit the potential of the first intermediate node Q1_n to the input node Q_n after being inverted.

[0087] In some examples, the transmission control circuit 12 can be connected with the first intermediate node Q1_n, the second intermediate node Q2_n, the enable control terminal GEN and the drive enhancement circuit 13, and configured to provide the output signal to the drive enhancement circuit 13 under the control of the first intermediate node Q1_n, the second intermediate node Q2_n and the enable control terminal GEN.

[0088] In some examples, the transmission control circuit 12 can include a second control circuit 121 and a switch circuit 122. The second control circuit 121 can be connected with the second intermediate node Q2_n, the switch circuit 122 and the drive enhancement circuit 13, and configured to control the potential of the output signal provided to the drive enhancement circuit 13 based on the potential of the second intermediate node Q2_n and the signal output by the switch circuit 122. The switch circuit 122 is connected between the enable control terminal GEN and the second control circuit 121, and also connected with the first intermediate node Q1_n and the second intermediate node Q2_n, and configured to control the on-off of the enable control terminal GEN and the second control circuit 121 based on the potentials of the first intermediate node Q1_n and the second intermediate node Q2_n.

[0089] In some examples, the driving enhancement circuit 13 is connected between the transmission control circuit 12 and the output end OUT_n (or marked as GP_n) of the shift register circuit, and is configured to output the potential of the output signal provided by the transmission control circuit 12 to the output end OUT_n of the shift register circuit after at least one inversion processing. The driving enhancement circuit 13 can be configured to output the potential of the output signal of the second control circuit 121 to the output end OUT_n of the shift register circuit after at least one (for example, odd times) inversion processing.

[0090] FIG. 2 is a schematic diagram of a gate-level circuit of the shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 2, the input control circuit 111 can include a first transmission gate circuit (also referred to as a first transmission gate) Tg1. The first transmission gate circuit Tg1 can be connected between the input end IN_n of the shift register circuit and the input node Q_n, and can be connected with the first clock end CKn and the second clock end CB, respectively.

[0091] In some examples, the first control circuit 112 can include a first NOR gate circuit (also referred to as a first NOR gate) NOR1. The first input end of the first NOR gate circuit NOR1 is connected with the reset control end Trst, the second input end of the first NOR gate circuit NOR1 is connected with the input node Q_n, and the output end of the first NOR gate circuit NOR1 is connected with the first intermediate node Q1_n.

[0092] In some examples, the latch circuit 113 can include a second transmission gate circuit (also referred to as a second transmission gate) Tg2 and a first NOT gate circuit (also referred to as a first NOT gate) INV1. The second transmission gate circuit Tg2 and the first NOT gate circuit INV1 are connected in series between the input node Q_n and the first intermediate node Q1_n. The second transmission gate circuit Tg2 can be connected between the input node Q_n and the second intermediate node Q2_n, and can be connected with the third clock end CBn and the fourth clock end CK. The input end of the first NOT gate circuit INV1 can be connected with the first intermediate node Q1_n, and the output end of the first NOT gate circuit INV1 can be connected with the second intermediate node Q2_n.

[0093] In some examples, the second control circuit 121 can include a second NOR gate circuit (also referred to as a second NOR gate) NOR2. The first input end of the second NOR gate circuit NOR2 can be connected with the second intermediate node Q2_n, the second input end of the second NOR gate circuit NOR2 can be connected with the output end of the switch circuit 122, and the output end of the second NOR gate circuit NOR2 can be connected with the driving enhancement circuit 13.

[0094] In some examples, the switch circuit 122 can include a third transmission gate circuit (may also be referred to as a third transmission gate) Tg3. The third transmission gate circuit Tg3 can be connected between the enable control end GEN and the second input end of the second NOR gate circuit NOR2, and can also be connected with the first intermediate node Q1_n and the second intermediate node Q2_n.

[0095] In some examples, the drive enhancement circuit 13 can include a plurality of (for example, an odd number of) NOR gate circuits connected in series, such as the second NOR gate circuit INV2, the third NOR gate circuit INV3, and the fourth NOR gate circuit INV4. The input end of the second NOR gate circuit INV2 is connected with the output end of the second NOR gate circuit NOR2, the output end of the second NOR gate circuit INV2 is connected with the input end of the third NOR gate circuit INV3, the output end of the third NOR gate circuit INV3 is connected with the input end of the fourth NOR gate circuit INV4, and the output end of the fourth NOR gate circuit INV4 is connected with the output end OUT_n of the shift register circuit.

[0096] In the present example, the logic operation principle of the NOR gate circuit is that all 0s output 1, and 1 outputs 0; that is, when the potentials of all the received signals are low potentials 0, the potential of the output signal can be controlled to be a high potential 1; otherwise, as long as the potential of a certain received signal is a high potential 1, the potential of the output signal is controlled to be a low potential 0.

[0097] In the present example, the NOR gate circuit can be a complementary metal oxide semiconductor (CMOS) tube formed by a pair of P-type transistor and N-type transistor that appear and work complementarily.

[0098] In the present example, the input node Q_n, the first intermediate node Q1_n, and the second intermediate node Q2_n are not actual components, but are nodes equivalent to the convergence points of the relevant electrical connections in the circuit diagram. In other words, these nodes are nodes equivalent to the convergence points of the relevant electrical connections in the circuit diagram.

[0099] FIG. 3 is an equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure. FIG. 3 can be an equivalent circuit diagram of the nth stage shift register circuit. Wherein n can be an integer greater than 0.

[0100] In some examples, as shown in FIG. 3, the first transmission gate circuit Tg1 can include a first N-type transistor Tn_1 and a first P-type transistor Tp_1. The gate of the first P-type transistor Tp_1 is connected with the second clock end CB, the first pole of the first P-type transistor Tp_1 is connected with the input end IN_n of the shift register circuit, and the second pole of the first P-type transistor Tp_1 is connected with the input node Q_n. The top gate and the bottom gate of the first N-type transistor Tn_1 are connected, and both are connected with the first clock end CKn. The first pole of the first N-type transistor Tn_1 is connected with the input end IN_n of the shift register circuit, and the second pole of the first N-type transistor Tn_1 is connected with the input node Q_n.

[0101] In some examples, the first NOR gate circuit NOR1 can include a second N-type transistor Tn_2, a third N-type transistor Tn_3, a second P-type transistor Tp_2 and a third P-type transistor Tp_3. The gate of the third P-type transistor Tp_3 is connected with the reset control end Trst, the first pole of the third P-type transistor Tp_3 is connected with the first power supply end VGH1, and the second pole of the third P-type transistor Tp_3 is connected with the first pole of the second P-type transistor Tp_2. The gate of the second P-type transistor Tp_2 is connected with the input node Q_n, and the second pole of the second P-type transistor Tp_2 is connected with the first intermediate node Q1_n. The top gate of the second N-type transistor Tn_2 is connected with the input node Q_n, the first pole of the second N-type transistor Tn_2 is connected with the second power supply end VGL1, and the second pole of the second N-type transistor Tn_2 is connected with the first intermediate node Q1_n. The top gate of the third N-type transistor Tn_3 is connected with the reset control end Trst, the first pole of the third N-type transistor Tn_3 is connected with the second power supply end VGL1, and the second pole of the third N-type transistor Tn_3 is connected with the first intermediate node Q1_n. The bottom gate of the second N-type transistor Tn_2 and the bottom gate of the third N-type transistor Tn_3 are both connected with the fifth voltage line BG5.

[0102] In some examples, the first NOR gate circuit INV1 can include a fourth N-type transistor Tn_4 and a fourth P-type transistor Tp_4. The gate of the fourth P-type transistor Tp_4 is connected with the first intermediate node Q1_n, the first pole of the fourth P-type transistor Tp_4 is connected with the first power supply end VGH1, and the second pole of the fourth P-type transistor Tp_4 is connected with the second intermediate node Q2_n. The top gate of the fourth N-type transistor Tn_4 is connected with the first intermediate node Q1_n, the first pole of the fourth N-type transistor Tn_4 is connected with the second power supply end VGL1, and the second pole of the fourth N-type transistor Tn_4 is connected with the second intermediate node Q2_n. The bottom gate of the fourth N-type transistor Tn_4 is connected with the fifth voltage line BG5.

[0103] In some examples, the second transmission gate circuit Tg2 can include a fifth N-type transistor Tn_5 and a fifth P-type transistor Tp_5. The gate of the fifth P-type transistor Tp_5 is connected with the fourth clock end CK, the first pole of the fifth P-type transistor Tp_5 is connected with the input node Q_n, and the second pole of the fifth P-type transistor Tp_5 is connected with the second intermediate node Q2_n. The top gate and the bottom gate of the fifth N-type transistor Tn_5 are connected, and both are connected with the third clock end CBn, the first pole of the fifth N-type transistor Tn_5 is connected with the input node Q_n, and the second pole of the fifth N-type transistor Tn_5 is connected with the second intermediate node Q2_n.

[0104] In some examples, the third transmission gate circuit Tg3 can include a sixth N-type transistor Tn_6 and a sixth P-type transistor Tp_6. The gate of the sixth P-type transistor Tp_6 is connected with the second intermediate node Q2_n, the first pole of the sixth P-type transistor Tp_6 is connected with the enable control end GEN, and the second pole of the sixth P-type transistor Tp_6 is connected with the second pole of the sixth N-type transistor Tn_6. The top gate of the sixth N-type transistor Tn_6 is connected with the first intermediate node Q1_n, the bottom gate of the sixth N-type transistor Tn_6 is connected with the fifth voltage line BG5, and the first pole of the sixth N-type transistor Tn_6 is connected with the enable control end GEN.

[0105] In some examples, the second or non gate circuit NOR2 can include a seventh N-type transistor Tn_7, an eighth N-type transistor Tn_8, a seventh P-type transistor Tp_7 and an eighth P-type transistor Tp_8. The gate of the eighth P-type transistor Tp_8 is connected with the second pole of the sixth P-type transistor Tp_6 and the second pole of the sixth N-type transistor Tn_6, the first pole of the eighth P-type transistor Tp_8 is connected with the first power end VGH1, and the second pole of the eighth P-type transistor Tp_8 is connected with the first pole of the seventh P-type transistor Tp_7. The gate of the seventh P-type transistor Tp_7 is connected with the second intermediate node Q2_n, and the second pole of the seventh P-type transistor Tp_7 is connected with the second pole of the seventh N-type transistor Tn_7. The top gate of the seventh N-type transistor Tn_7 is connected with the second intermediate node Q2_n, the bottom gate of the seventh N-type transistor Tn_7 is connected with the fifth voltage line BG5, and the first pole of the seventh N-type transistor Tn_7 is connected with the second power end VGL1. The top gate of the eighth N-type transistor Tn_8 is connected with the gate of the eighth P-type transistor Tp_8, the bottom gate of the eighth N-type transistor Tn_8 is connected with the fifth voltage line BG5, the first pole of the eighth N-type transistor Tn_8 is connected with the second power end VGL1, and the second pole of the eighth N-type transistor Tn_8 is connected with the second pole of the seventh N-type transistor Tn_7 and the second pole of the seventh P-type transistor Tp_7.

[0106] In some examples, the second NOT gate circuit INV2 can include a ninth N-type transistor Tn_9 and a ninth P-type transistor Tp_9. The gate of the ninth P-type transistor Tp_9 is connected with the second pole of the seventh P-type transistor Tp_7, the second pole of the seventh N-type transistor Tn_7 and the second pole of the eighth N-type transistor Tn_8, the first pole of the ninth P-type transistor Tp_9 is connected with the first power supply end VGH1, and the second pole of the ninth P-type transistor Tp_9 is connected with the second pole of the ninth N-type transistor Tn_9. The top gate of the ninth N-type transistor Tn_9 is connected with the gate of the ninth P-type transistor Tp_9, the bottom gate of the ninth N-type transistor Tn_9 is connected with the fifth voltage line BG5, and the first pole of the ninth N-type transistor Tn_9 is connected with the second power supply end VGL1.

[0107] In some examples, the third NOT gate circuit INV3 can include a tenth N-type transistor Tn_10 and a tenth P-type transistor Tp_10. The gate of the tenth P-type transistor Tp_10 is connected with the second pole of the ninth P-type transistor Tp_9 and the second pole of the ninth N-type transistor Tn_9, the first pole of the tenth P-type transistor Tp_10 is connected with the first power supply end VGH1, and the second pole of the tenth P-type transistor Tp_10 is connected with the second pole of the tenth N-type transistor Tn_10. The top gate of the tenth N-type transistor Tn_10 is connected with the gate of the tenth P-type transistor Tp_10, the bottom gate of the tenth N-type transistor Tn_10 is connected with the fifth voltage line BG5, and the first pole of the tenth N-type transistor Tn_10 is connected with the second power supply end VGL1.

[0108] In some examples, the fourth NOT gate circuit INV4 can include an eleventh N-type transistor Tn_11 and an eleventh P-type transistor Tp_11. The gate of the eleventh P-type transistor Tp_11 is connected with the second pole of the tenth P-type transistor Tp_10 and the second pole of the tenth N-type transistor Tn_10, the first pole of the eleventh P-type transistor Tp_11 is connected with the first power supply end VGH2, and the second pole of the eleventh P-type transistor Tp_11 is connected with the second pole of the eleventh N-type transistor Tn_11. The top gate of the eleventh N-type transistor Tn_11 is connected with the gate of the eleventh P-type transistor Tp_11, the bottom gate of the eleventh N-type transistor Tn_11 is connected with the fifth voltage line BG5, and the first pole of the eleventh N-type transistor Tn_11 is connected with the second power supply end VGL2.

[0109] In some examples, the second control circuit 121 can further include a capacitor C. The first pole of the capacitor C can be connected with the gate of the eighth P-type transistor Tp_8, and the second pole of the capacitor C can be connected with the second power supply end VGL1.

[0110] In some examples, the first power signal provided by the first power terminal (including the first power terminal VGH1 and VGH2) can have a higher potential than the second power signal provided by the second power terminal (including the second power terminal VGL1 and VGL2). The first power signal provided by the first power terminal VGH1 can be the same as or different from the first power signal provided by the first power terminal VGH2. For example, the first power signal provided by the first power terminal VGH2 can have a higher potential than or equal to the first power signal provided by the first power terminal VGH1. The second power signal provided by the second power terminal VGL1 can be the same as or different from the second power signal provided by the second power terminal VGL2. For example, the second power signal provided by the second power terminal VGL2 can have a lower potential than or equal to the second power signal provided by the second power terminal VGL1.

[0111] In some examples, the fourth inverter INV4 receives a second power signal having a lower potential than the second power signal received by the third inverter INV3 and the second inverter INV2, which can ensure that the N-type transistor in the fourth inverter INV4 can be completely turned off, so that the shift register circuit can reliably control the potential of the output terminal OUT_n to be high. The fourth inverter INV4 receives a first power signal having a higher potential than the first power signal received by the third inverter INV3 and the second inverter INV2, which can ensure that the P-type transistor in the fourth inverter INV4 can be completely turned off, so that the shift register circuit can reliably control the potential of the output terminal OUT_n to be low. The present example can accelerate the charging and discharging speed of the fourth inverter INV4 directly connected to the output terminal OUT_n of the shift register circuit, thereby further improving the driving ability of the shift register circuit and reducing power consumption.

[0112] In the present example, the first N-type transistor Tn_1 to the eleventh N-type transistor Tn_11 are all oxide transistors. The first group of oxide transistors can include the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5. The second group of oxide transistors can include the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11.

[0113] In the present example, the top gate of the first N-type transistor Tn_1 and the top gate of the fifth N-type transistor Tn_5 are configured to receive a clock signal, and no long-time bias is applied to the transistors, and there is no need to adjust the threshold voltage separately. By connecting the top gate and the bottom gate of the first N-type transistor Tn_1 and connecting the top gate and the bottom gate of the fifth N-type transistor Tn_5, the additional wiring can be reduced.

[0114] In the present example, the top gates and the bottom gates of the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10 and the eleventh N-type transistor Tn_11 are controlled individually, and the bottom gates of these N-type transistors are all connected with the fifth voltage line BG5 and configured to receive the same voltage signal, so as to adjust the threshold voltage of the N-type transistors in the shift register circuit, thereby optimizing the output signal of the shift register circuit.

[0115] FIG. 4 is a local brush driving timing diagram of the shift register circuit according to at least one embodiment of the present disclosure. The local brush driving timing diagram shown in FIG. 4 can include the timing of the high brush area and the low brush area.

[0116] In some examples, the enable control end GEN can be connected with the first enable control line EN1 or the second enable control line EN2. For example, the enable control end GEN connected with the shift register circuit for connecting the odd row sub-pixels can be connected with the first enable control line EN1, and the enable control end GEN connected with the shift register circuit for connecting the even row sub-pixels can be connected with the second enable control line EN2.

[0117] In some examples, the four clock ends (the first clock end CKn, the second clock end CB, the third clock end CBn and the fourth clock end CK) can provide four groups of clock signals. The period of the four groups of clock signals can be 2H (1H can be one row period), and the clock signal provided by the clock end CK and the clock signal provided by the clock end CB can be different by 1H, the clock signal provided by the clock end CKn and the clock signal provided by the clock end CB can be inverse signals, and the clock signal provided by the clock end CBn and the clock signal provided by the clock end CK can be inverse signals. In addition, the pulse width of the low voltage 0 of the clock signal provided by the clock end CK and the clock signal provided by the clock end CB is generally smaller than 1H by about 0 to 2 microseconds (μs), and can be selected according to the load resistance RC. The setting mode of the present example can eliminate the influence of clock delay, avoid the simultaneous opening of the first transmission gate circuit Tg1 and the second transmission gate circuit Tg2, and avoid the risk of competition between the first NOR gate circuit NOR1 and the first inverter circuit INV1 when the input state is switched.

[0118] In some examples, in the high brush area, the enable control signal provided by the first enable control line EN1 connected to the shift register circuit of the odd row sub-pixels can be the same phase as the clock signal provided by the clock terminal CK; the enable control signal provided by the second enable control line EN2 connected to the shift register circuit of the even row sub-pixels can be the same phase as the clock signal provided by the clock terminal CB. In other examples, the enable control signal provided by the first enable control line EN1 can be interchanged with the enable control signal provided by the second enable control line EN2. That is, the enable control signal provided by the first enable control line EN1 connected to the shift register circuit of the odd row sub-pixels can be the same phase as the clock signal provided by the clock terminal CB; the enable control signal provided by the second enable control line EN2 connected to the shift register circuit of the even row sub-pixels can be the same phase as the clock signal provided by the clock terminal CK.

[0119] In some examples, in the low brush area, the enable control signals provided by the first enable control line EN1 and the second enable control line EN2, that is, the control enable control signal, can be controlled to be high potential to achieve output reset.

[0120] The working timing of the nth stage shift register circuit of the present example is described below with reference to FIG. 3 and FIG. 4.

[0121] In the first stage t01, a high potential first clock signal can be provided to the first clock terminal CKn, and a low potential second clock signal can be provided to the second clock terminal CB, so that the first transmission gate circuit Tg1 is turned on; and then the input terminal IN_n and the input node Q_n are turned on, the input terminal IN_n (i.e., the second intermediate node Q2_n-1 of the nth stage shift register circuit) can output an input signal to the input node Q_n, at this time the potential of the output input signal can be high potential. A high potential reset control signal can be provided to the reset control terminal Trst, and then after the first NOR gate circuit NOR1, the potential of the first intermediate node Q1_n can be controlled to be low potential, and then after the first inverter circuit INV1, the potential of the second intermediate node Q2_n can be controlled to be high potential. Because the potential of the first intermediate node Q1_n is low potential and the potential of the second intermediate node Q2_n is high potential, the third transmission gate Tg3 can be turned off, and a low potential signal output by the second NOR gate circuit NOR2 can be output, which after the second inverter circuit INV2, the third inverter circuit INV3 and the fourth inverter circuit INV4 can make the potential of the output terminal OUT_n be high potential. And in the first stage t01, a low potential third clock signal can be provided to the third clock terminal CBn, and a high potential fourth clock signal can be provided to the fourth clock terminal CK, so that the second transmission gate circuit Tg2 is turned off, and then the second intermediate node Q2_n and the input node Q_n are disconnected.

[0122] In the second stage t02, the first clock signal with low potential can be provided to the first clock terminal CKn, and the second clock signal with high potential can be provided to the second clock terminal CB, so that the first transmission gate circuit Tg1 is turned off, and then the input terminal IN_n is disconnected from the input node Q_n. The third clock signal with high potential can be provided to the third clock terminal CBn, and the fourth clock signal with low potential can be provided to the fourth clock terminal CK, so that the second transmission gate circuit Tg2 is turned on, and then the second intermediate node Q2_n is connected to the input node Q_n, thereby latching the potential of the input node Q_n as the high potential of the second intermediate node Q2_n. In addition, the reset control signal with low potential can be provided to the reset control terminal Trst, so that the potential of the first intermediate node Q1_n is controlled as low potential after the first NOR gate circuit NOR1, and the potential of the second intermediate node Q2_n is controlled as high potential after the first inverter circuit INV1. Since the potential of the first intermediate node Q1_n is low, and the potential of the second intermediate node Q2_n is high, the third transmission gate Tg3 can be turned off, and the signal with low potential output by the second NOR gate NOR2 can be provided, which can make the potential of the output terminal OUT_n high after the second inverter circuit INV2, the third inverter circuit INV3 and the fourth inverter circuit INV4.

[0123] In the third stage t03, the first clock signal with a high level can be provided to the first clock terminal CKn, and the second clock signal with a low level can be provided to the second clock terminal CB, so that the first transmission gate circuit Tg1 is turned on, and then the input terminal IN_n is conducted with the input node Q_n. The input terminal IN_n can provide the input signal to the input node Q_n, and the potential of the input signal can be a low level. In addition, the reset control signal with a low level can be provided to the reset control terminal Trst, and then the potential of the first intermediate node Q1_n can be controlled to be a high level through the first NOR gate circuit NOR1, and the potential of the second intermediate node Q2_n can be controlled to be a low level through the first inverter circuit INV1. Because the potential of the first intermediate node Q1_n is a high level, and the potential of the second intermediate node Q2_n is a low level, the third transmission gate circuit Tg3 can be turned on, that is, the enable control signal provided by the enable control terminal GEN is transmitted to the second NOR gate circuit NOR2. For example, the potential of the enable control signal can be a high level. Thus, the signal with a low level can be output through the second NOR gate NOR2, and the potential of the output terminal OUT_n can be a high level through the second inverter circuit INV2, the third inverter circuit INV3 and the fourth inverter circuit INV4. Moreover, in the third stage t03, the third clock signal with a low level can be provided to the third clock terminal CBn, and the fourth clock signal with a high level can be provided to the fourth clock terminal CK, so that the second transmission gate circuit Tg2 is turned off, and then the second intermediate node Q2_n is disconnected with the input node Q_n.

[0124] In the fourth stage t04, the first clock signal with low potential can be provided to the first clock terminal CKn, and the second clock signal with high potential can be provided to the second clock terminal CB, so that the first transmission gate circuit Tg1 is turned off, and then the input terminal IN_n is disconnected from the input node Q_n. The third clock signal with high potential can be provided to the third clock terminal CBn, and the fourth clock signal with low potential can be provided to the fourth clock terminal CK, so that the second transmission gate circuit Tg2 is turned on, and then the second intermediate node Q2_n is connected to the input node Q_n, thereby latching the potential of the input node Q_n as the low potential of the second intermediate node Q2_n. In addition, the reset control signal with low potential can be provided to the reset control terminal Trst, so that the potential of the first intermediate node Q1_n is controlled as high potential after the first NOR gate circuit NOR1, and then the potential of the second intermediate node Q2_n is controlled as low potential after the first inverter circuit INV1. Since the potential of the first intermediate node Q1_n is high, and the potential of the second intermediate node Q2_n is low, the third transmission gate circuit Tg3 can be turned on, i.e., the enable control signal provided by the enable control terminal GEN is transmitted to the second NOR gate circuit NOR2. For example, the potential of the enable control signal can be low. Thus, the signal with high potential can be output after the second NOR gate circuit NOR2, and then the potential of the output terminal OUT_n can be low after the second inverter circuit INV2, the third inverter circuit INV3 and the fourth inverter circuit INV4.

[0125] In the present example, the low potential of the output signal provided by the output terminal OUT_n occupies a smaller proportion of the frame duration, i.e. the output signal provided by the output terminal OUT_n is a P-type output (i.e. the duty cycle of the low potential is small). In order to ensure that the output terminal OUT_n provides an output signal with a small duty cycle of the low potential, the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7 and the second N-type transistor Tn_2 are in an open state for a relatively long time within the frame duration, and the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6 and the ninth N-type transistor Tn_9 are in a closed state for a relatively long time within the frame duration. In other words, the duty cycle of the high potential of the top gate voltage signal of the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7 and the second N-type transistor Tn_2 (i.e. the ratio of the duration of the high potential of the top gate voltage signal within the frame duration to the frame duration) is relatively large; the duty cycle of the low potential of the top gate voltage signal of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6 and the ninth N-type transistor Tn_9 (i.e. the ratio of the duration of the low potential of the top gate voltage signal within the frame duration to the frame duration) is relatively large. The top gate voltage signal of the second N-type transistor Tn_2 is controlled by the input node Q_n, the top gate voltage signal of the third N-type transistor Tn_3 is controlled by the reset control terminal Trst, the top gate voltage signals of the fourth N-type transistor Tn_4 and the sixth N-type transistor Tn_6 are controlled by the first intermediate node Q1_n, the top gate voltage signal of the seventh N-type transistor Tn_7 is controlled by the second intermediate node Q2_n, the top gate voltage signal of the eighth N-type transistor Tn_8 is controlled by the output terminal of the third transmission gate circuit, the top gate voltage signal of the ninth N-type transistor Tn_9 is controlled by the output terminal of the second NOR gate circuit, and the top gate voltage signal of the tenth N-type transistor Tn_10 is controlled by the output terminal of the second NAND gate circuit.

[0126] In some examples, the duty cycle of the high potential of the top gate voltage signal of the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7 and the second N-type transistor Tn_2 can be greater than the duty cycle of the high potential of the top gate voltage signal of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6 and the ninth N-type transistor Tn_9; and the duty cycle of the low potential of the top gate voltage signal of the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7 and the second N-type transistor Tn_2 can be less than the duty cycle of the low potential of the top gate voltage signal of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6 and the ninth N-type transistor Tn_9.

[0127] The shift register circuit provided in the example can not only better match the timing requirements of the P-type transistor in the pixel circuit, but also can realize local refresh of the pixel, reliably reset the output signal, and has good driving flexibility and driving effect.

[0128] FIG. 5 is another equivalent circuit diagram of the shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 5, the top gate and the bottom gate of the first N-type transistor Tn_1 are connected and connected with the first clock end CKn configured to receive a clock signal. The top gate and the bottom gate of the fifth N-type transistor Tn_5 are connected and connected with the third clock end CBn configured to receive a clock signal.

[0129] In some examples, the top gate and the bottom gate of the eleventh N-type transistor Tn_11 are controlled separately, and the bottom gate of the eleventh N-type transistor Tn_11 is connected with the third voltage line BG3. The top gate and the bottom gate of each of the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10 are controlled separately, and the bottom gates of these N-type transistors are all connected with the fourth voltage line BG4. The fourth voltage signal provided by the fourth voltage line BG4 can be different from the third voltage signal provided by the third voltage line BG3.

[0130] In the example, the first N-type transistor Tn_1 to the eleventh N-type transistor Tn_11 are all oxide transistors. The first group of oxide transistors can include the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5, and the second group of oxide transistors can include the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11. The eleventh N-type transistor Tn_11 in the second group of oxide transistors is an oxide output transistor, and the remaining N-type transistors are oxide switch transistors.

[0131] In the present example, the eleventh N-type transistor Tn_11 is used as an output transistor, and the received second power signal can be different from the second power signal received by the rest of the N-type transistors. Therefore, the gate voltage requirements for adjusting the threshold voltages of the eleventh N-type transistor and the rest of the N-type transistors (including the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10) are different. By separately controlling the bottom gates of the eleventh N-type transistor and the rest of the N-type transistors, the threshold voltages of the transistors can be independently adjusted. The remaining description of the shift register circuit of the present example can refer to the description of the foregoing embodiments, and will not be described here again.

[0132] FIG. 6 is another equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 6, the top gate and the bottom gate of the first N-type transistor Tn_1 are connected and connected to the first clock terminal CKn. The top gate and the bottom gate of the fifth N-type transistor Tn_5 are connected and connected to the third clock terminal CBn.

[0133] In some examples, the top gate and the bottom gate of the eleventh N-type transistor Tn_11 are separately controlled, and the bottom gate of the eleventh N-type transistor Tn_11 is connected to the third voltage line BG3. The top gate and the bottom gate of each of the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10 are separately controlled. The bottom gates of the second N-type transistor Tn_2, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, and the tenth N-type transistor Tn_10 are all connected to the first voltage line BG1; the bottom gates of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9 are all connected to the second voltage line BG2. The first voltage signal provided by the first voltage line BG1, the second voltage signal provided by the second voltage line BG2, and the third voltage signal provided by the third voltage line BG3 can be different.

[0134] In the present example, the first N-type transistor Tn_1 to the eleventh N-type transistor Tn_11 are all oxide transistors. The first group of oxide transistors can include the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5; the second group of oxide transistors can include the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11. The eleventh N-type transistor Tn_11 in the second group of oxide transistors is an oxide output transistor, and the rest of the N-type transistors are oxide switch transistors.

[0135] In the present example, during the driving process of a frame duration, according to the duty cycle difference between the high and low potentials of the top gate voltage of the N-type switch transistor, the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10 can be divided into two groups. The first group of N-type switch transistors (corresponding to the first group of oxide switch transistors described above) includes the second N-type transistor Tn_2, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, and the tenth N-type transistor Tn_10; the second group of N-type switch transistors (corresponding to the second group of oxide switch transistors described above) includes the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9. In some examples, the first group of N-type switch transistors is in an open state for a longer time within a frame duration, and the duty cycle of the high potential of the gate voltage is large; the second group of N-type switch transistors is in a closed state for a longer time within a frame duration, and the duty cycle of the low potential of the gate voltage is large. For example, when the output signal of the output end OUT_n of the shift register circuit is configured to drive the P-type transistor in the pixel circuit, i.e., the duty cycle of the low potential of the output signal is small, the duty cycle of the high potential of the gate voltage of the tenth N-type transistor Tn_10 is large, i.e., the tenth N-type transistor Tn_10 is in an open state for a long time.

[0136] In the present example, according to the duty cycle difference between the high and low potentials of the gate voltage of the N-type switch transistor, different voltages are used to control the bottom gate of the plurality of N-type switch transistors, which can further accurately adjust the threshold voltage of the N-type transistor. The remaining description of the shift register circuit of the present example can refer to the description of the foregoing embodiments, and thus will not be described here.

[0137] FIG. 7 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 7, the gate driving circuit can include a plurality of shift register circuits cascaded (e.g., including a first stage shift register circuit GOA(1), a second stage shift register circuit GOA(2), an (n-1)th stage shift register circuit GOA(n-1), and an nth stage shift register circuit GOA(n)). The second intermediate node Q2_n-1 of the (n-1)th stage shift register circuit GOA(n-1) is connected to the input end IN_n of the nth stage shift register circuit GOA(n). The second intermediate node of each stage shift register circuit can provide an input signal to the input end of the next stage shift register circuit, except for the last stage shift register circuit. n can be an integer greater than 0. The input end IN_1 of the first stage shift register circuit GOA(1) can be connected to a start signal line STV.

[0138] In some examples, the first clock end CKn of the 2i-1th stage shift register circuit can be connected to a first clock signal line CL1, the second clock end CB can be connected to a second clock signal line CL2, the third clock end CBn can be connected to a third clock signal line CL3, and the fourth clock end CK can be connected to a fourth clock signal line CL4. The first clock end CKn of the 2ith stage shift register circuit can be connected to the third clock signal line CL3, the second clock end CB can be connected to the fourth clock signal line CL4, the third clock end CBn can be connected to the first clock signal line CL1, and the fourth clock end CK can be connected to the second clock signal line CL2. i can be an integer greater than 0.

[0139] In some examples, the enable control end GEN of the 2i-1th stage shift register circuit can be connected to a first enable control line EN1, and the enable control end GEN of the 2ith stage shift register circuit can be connected to a second enable control line EN2.

[0140] In some examples, the first power supply end VGH1 of each stage shift register circuit can be connected to a first power supply line VH1, the first power supply end VGH2 can be connected to a second power supply line VH2, the second power supply end VGL1 can be connected to a first ground line VL1, and the second power supply end VGL2 can be connected to a second ground line VL2. The reset control end Trst of each stage shift register circuit can be connected to a reset control line RST.

[0141] FIG. 8 is a partial cross-sectional schematic diagram of a display area of a display substrate according to at least one embodiment of the present disclosure. The film layer stacking order of the display substrate is shown in FIG. 8. In some examples, as shown in FIG. 8, in a direction perpendicular to the display substrate, the display substrate can include a substrate 10, and a circuit structure layer 20, a light emitting structure layer 30, and an encapsulation structure layer 40 disposed on the substrate 10 in sequence.

[0142] In some examples, the circuit structure layer 20 can include, in sequence, a buffer layer BF, a first semiconductor layer PY1, a first insulating layer (may also be referred to as a first gate insulating layer) GI1, a first conductive layer (may also be referred to as a first gate metal layer) GT1, a second insulating layer (may also be referred to as a second gate insulating layer) GI2, a second conductive layer (may also be referred to as a second gate metal layer) GT2, a third insulating layer (may also be referred to as a third gate insulating layer) GI3, a second semiconductor layer PY2, a fourth insulating layer (may also be referred to as a fourth gate insulating layer) GI4, a third conductive layer (may also be referred to as a third gate metal layer) GT3, a fifth insulating layer (may also be referred to as an interlayer insulating layer) ILD, a fourth conductive layer (may also be referred to as a first source-drain metal layer) SD1, a sixth insulating layer (may also be referred to as a passivation layer) PVX, a seventh insulating layer (may also be referred to as a first planarization layer) PLN1, a fifth conductive layer (may also be referred to as a second source-drain metal layer) SD2, and an eighth insulating layer (may also be referred to as a second planarization layer) PLN2. However, the present embodiment is not limited thereto. In other examples, the sixth insulating layer PVX can be omitted, or the sixth insulating layer PVX can be located between the seventh insulating layer and the fifth conductive layer.

[0143] In some examples, the light-emitting structure layer 30 can include an anode layer ANO, a pixel definition layer PDL, a light-emitting functional layer EL, and a cathode layer CATH. The anode layer ANO can include anodes of light-emitting elements, the pixel definition layer PDL can be formed with a plurality of pixel openings exposing the anode layer ANO, the light-emitting functional layer EL can be disposed within the pixel openings and connected with the anodes in the anode layer ANO. The cathode layer CATH can be connected with the light-emitting functional layer EL.

[0144] In some examples, the encapsulation structure layer 40 can include a first encapsulation layer CVD1, a second encapsulation layer IJP, and a third encapsulation layer CVD2. The first encapsulation layer CVD1 and the third encapsulation layer CVD2 can be made of inorganic materials, and the second encapsulation layer IJP can be made of an organic material. The second encapsulation layer IJP can be disposed between the first encapsulation layer CVD1 and the third encapsulation layer CVD2 to form an inorganic material / organic material / inorganic material laminated structure, which can prevent external water vapor from entering the light-emitting structure layer 30. In some possible implementations, the display substrate can further include other film layers, such as a touch structure layer, a color filter layer, and the like, which are not limited herein.

[0145] FIG. 9 is a partial top view of a display substrate according to at least one embodiment of the present disclosure. FIG. 9 schematically shows the top views of two shift register circuits (for example, an n-level shift register circuit GOA(n) and an n+1-level shift register circuit GOA(n+1)) of the display substrate. The equivalent circuit of the shift register circuit of the present example can be as shown in FIG. 6.

[0146] In some examples, as shown in FIG. 9, in a plane parallel to the display substrate, the outer contour of the single shift register circuit can be substantially rectangular. The input shift circuit can include a first transmission gate circuit Tg1, a second transmission gate circuit Tg2, a first NOR gate circuit NOR1, and a first inverter circuit INV1; the transmission control circuit can include a second NOR gate circuit NOR2, a third transmission gate circuit Tg3, and a capacitor C; the drive enhancement circuit can include a second inverter circuit INV2, a third inverter circuit INV3, and a fourth inverter circuit INV4. In the first direction D1, the input shift circuit, the transmission control circuit, and the drive enhancement circuit can be arranged in sequence.

[0147] In some examples, the first transmission gate circuit Tg1, the second transmission gate circuit Tg2, and the first inverter circuit INV1 can be arranged in sequence along the second direction D2 in the orthographic projection of the substrate; the orthographic projection of the first NOR gate circuit NOR1 in the first direction D1 can be located on the same side of the orthographic projection of the first transmission gate circuit Tg1, the second transmission gate circuit Tg2, and the first inverter circuit INV1 in the substrate, and the orthographic projection of the first NOR gate circuit NOR1 in the first direction D1 can be located on the side of the orthographic projection of the first transmission gate circuit Tg1, the second transmission gate circuit Tg2, and the first inverter circuit INV1 in the substrate away from the orthographic projection of the transmission control circuit in the substrate. The orthographic projection of the second NOR gate circuit NOR2 and the third transmission gate circuit Tg3 can be arranged in sequence along the second direction D2. The orthographic projection of the second NOR gate circuit NOR2 in the first direction D1 can be adjacent to the orthographic projection of the first transmission gate circuit Tg1 and the second transmission gate circuit Tg2 in the substrate, and the orthographic projection of the third transmission gate circuit Tg3 in the first direction D1 can be adjacent to the orthographic projection of the first inverter circuit INV1 in the substrate. The orthographic projection of the second inverter circuit INV2, the third inverter circuit INV3, and the fourth inverter circuit INV4 in the substrate can be arranged in sequence along the first direction D1. The orthographic projection of the second inverter circuit INV2 in the first direction D1 can be adjacent to the orthographic projection of the second NOR gate circuit NOR2 in the substrate. The orthographic projection of the capacitor C in the first direction D1 can be located between the orthographic projection of the third transmission gate circuit Tg3 and the third inverter circuit INV3 in the substrate. The orthographic projection of the second inverter circuit INV2 and the capacitor C in the substrate can be adjacent in the second direction D2. The arrangement of the shift register circuit of the present example can effectively reduce the wiring length, thereby saving the occupied space and facilitating the realization of narrow frame.

[0148] In some examples, the second N-type transistor Tn_2, the second P-type transistor Tp_2 and the third N-type transistor Tn_3 of the first NOR gate circuit NOR1 can be arranged in a stepped manner along the second direction D2 in the projection on the substrate. The third P-type transistor Tp_3 can be located on the side of the projection on the substrate of the second P-type transistor Tp_2 away from the projection on the substrate of the second transmission gate circuit Tg2 in the first direction D1. The projections on the substrate of the second N-type transistor Tn_2 and the third N-type transistor Tn_3 can be arranged in alignment along the second direction D2. The projection on the substrate of the third N-type transistor Tn_3 can be arranged in sequence with the projections on the substrate of the fourth N-type transistor Tn_4 and the fourth P-type transistor Tp_4 of the first inverter circuit INV1 along the first direction D1.

[0149] In some examples, the first P-type transistor Tp_1 and the first N-type transistor Tn_1 of the first transmission gate circuit Tg1 can be arranged in alignment along the first direction D1 in the projection on the substrate. The fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 of the second transmission gate circuit Tg2 can be arranged in alignment along the first direction D1 in the projection on the substrate. The projections on the substrate of the fifth P-type transistor Tp_5 and the first P-type transistor Tp_1 can be arranged in alignment along the second direction D2, and the projections on the substrate of the fifth N-type transistor Tn_5 and the first N-type transistor Tn_1 can be arranged in alignment along the second direction D2.

[0150] In some examples, the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 of the second NOR gate circuit NOR2 can be arranged in alignment along the first direction D1 in the projection on the substrate, and the seventh P-type transistor Tp_7 and the eighth P-type transistor Tp_8 can be located on the side of the projections on the substrate of the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 away from the third transmission gate circuit Tg3 in the second direction D2. The projections on the substrate of the seventh P-type transistor Tp_7 and the eighth P-type transistor Tp_8 can be arranged in sequence along the first direction D1. The projections on the substrate of the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7 can be arranged in misalignment along the second direction D2, and the projections on the substrate of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 can be arranged in misalignment along the second direction D2.

[0151] In some examples, the sixth N-type transistor Tn_6 and the sixth P-type transistor Tp_6 of the third transmission gate circuit Tg3 can be arranged in alignment along the first direction D1 in the projection on the substrate. The projections on the substrate of the sixth N-type transistor Tn_6 and the seventh N-type transistor Tn_7 can be arranged in alignment along the second direction D2, and the projections on the substrate of the sixth P-type transistor Tp_6 and the eighth N-type transistor Tn_8 can be arranged in alignment along the second direction D2.

[0152] In some examples, the footprint of the capacitor C on the substrate in the first direction D1 can be between the footprint of the sixth P-type transistor Tp_6 on the substrate and the footprint of the tenth N-type transistor Tn_10 on the substrate, and in the second direction D2 can be adjacent to the footprint of the ninth N-type transistor Tn_9 on the substrate.

[0153] In some examples, the footprint of the ninth N-type transistor Tn_9 of the second NOT gate circuit INV2 on the substrate in the first direction D1 can be aligned with the footprint of the eighth N-type transistor Tn_9 on the substrate, and the footprint of the ninth P-type transistor Tp_9 on the substrate in the second direction D2 can be misaligned with the footprint of the ninth N-type transistor Tn_9 on the substrate.

[0154] In some examples, the footprint of the tenth N-type transistor Tn_10 and the tenth P-type transistor Tp_10 of the third NOT gate circuit INV3 on the substrate can be aligned along the second direction D2. The footprint of the tenth P-type transistor Tp_10 on the substrate in the first direction D1 can be adjacent to the footprint of the ninth P-type transistor Tp_9 on the substrate.

[0155] In some examples, the footprint of the eleventh N-type transistor Tn_11 and the eleventh P-type transistor Tp_11 of the fourth NOT gate circuit INV4 on the substrate can be aligned along the second direction D2. The footprint of the eleventh P-type transistor Tp_11 on the substrate in the first direction D1 can be adjacent to the footprint of the tenth N-type transistor Tn_10 on the substrate, and the footprint of the eleventh N-type transistor Tn_11 on the substrate in the first direction D1 can be adjacent to the footprint of the tenth P-type transistor Tp_10 on the substrate.

[0156] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes.

[0157] The "A and B are arranged in the same layer" in the present disclosure refers to that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer refers to the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the projection of A contains the projection of B" refers to that the boundary of the projection of B falls within the boundary of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0158] The preparation process of the display substrate of the present exemplary embodiment can include the following steps. The following will be described by way of example with the preparation process of the circuit structure layer.

[0159] (1) providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass, quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl acid ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer and a second inorganic material layer stacked together, the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface treated polymer soft film, etc., and the materials of the first and second inorganic material layers can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., for improving the water and oxygen resistance of the substrate.

[0160] (2) forming a first semiconductor layer. In some examples, a buffer film and a first semiconductor film are sequentially deposited on the substrate, the first semiconductor film is patterned by a patterning process to form a buffer layer and a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathienyl or polythiophene, etc.

[0161] FIG. 10 is a schematic view of the display substrate after the first semiconductor layer is formed in FIG. 9. In some examples, as shown in FIG. 10, the first semiconductor layer of the display substrate can include the active layers of the plurality of P-type transistors of the shift register circuit, such as the active layer 201 of the first P-type transistor, the active layer 202 of the second P-type transistor, the active layer 203 of the third P-type transistor, the active layer 204 of the fourth P-type transistor, the active layer 205 of the fifth P-type transistor, the active layer 206 of the sixth P-type transistor, the active layer 207 of the seventh P-type transistor, the active layer 208 of the eighth P-type transistor, the active layer 209 of the ninth P-type transistor, the active layer 210 of the tenth P-type transistor, and the active layers 211a and 211b of the eleventh P-type transistor.

[0162] In some examples, the active layer of each transistor can include a first region, a second region, and a channel region between the first region and the second region. The material of the first semiconductor layer may, for example, include polysilicon. The channel region of the first type of transistor can be undoped and have semiconductor properties. The first region and the second region can be doped regions on both sides of the channel region and doped with impurities and thus have electrical conductivity. The impurities can vary according to the type of transistor. In some examples, the doped regions of the active layer can be interpreted as the source electrode or the drain electrode of the transistor. For example, the first region of the active layer can be interpreted as the first electrode of the transistor, and the second region of the active layer can be interpreted as the second electrode of the transistor. The part of the active layer between the transistors can be interpreted as a wiring doped with impurities and can be used to electrically connect the transistors. The present embodiment is not limited in this regard.

[0163] In some examples, the active layer 202 of the second P-type transistor can extend along the first direction D1, and the active layer 203 of the third P-type transistor can extend along the second direction D2. The active layer 202 of the second P-type transistor and the active layer 203 of the third P-type transistor can be an integral structure, and the integral structure can have a substantially L-shaped footprint on the substrate. The first region 202-1 of the active layer 202 of the second P-type transistor can simultaneously serve as the second region of the active layer 203 of the third P-type transistor; the second region 202-2 of the active layer 202 of the second P-type transistor and the first region 203-1 of the active layer 203 of the third P-type transistor can be independently provided.

[0164] In some examples, the active layer 201 of the first P-type transistor and the active layer 205 of the fifth P-type transistor can extend along the second direction D2. The active layer 205 of the fifth P-type transistor can be adjacent to the active layer 202 of the second P-type transistor in the first direction D1. The active layer 201 of the first P-type transistor and the active layer 205 of the fifth P-type transistor can be an integral structure, and the integral structure can have a substantially I-shaped footprint on the substrate. The second region 201-2 of the active layer 201 of the first P-type transistor can simultaneously serve as the first region of the active layer 205 of the fifth P-type transistor; the first region 201-1 of the active layer 201 of the first P-type transistor and the second region 205-2 of the active layer 205 of the fifth P-type transistor can be independently provided.

[0165] In some examples, the active layer 204 of the fourth P-type transistor can have a dumbbell shape extending along the first direction D1 in the footprint on the substrate. The first region 204-1 and the second region 204-2 of the active layer 204 of the fourth P-type transistor can be located on both sides of the channel region of the active layer 204 of the fourth P-type transistor in the first direction D1.

[0166] In some examples, the active layer 206 of the sixth P-type transistor can have a positive projection on the substrate in a dumbbell shape extending along the second direction D2. The first region 206-1 and the second region 206-2 of the active layer 206 of the sixth P-type transistor can be located on both sides of the channel region of the active layer 206 of the sixth P-type transistor along the second direction D2.

[0167] In some examples, the active layer 207 of the seventh P-type transistor can extend along the second direction D2, and the active layer 208 of the eighth P-type transistor and the active layer 209 of the ninth P-type transistor can extend along the first direction D1. The active layer 207 of the seventh P-type transistor, the active layer 208 of the eighth P-type transistor and the active layer 209 of the ninth P-type transistor can be an integrated structure, and the positive projection of the integrated structure on the substrate can be substantially L-shaped. The active layer 208 of the eighth P-type transistor can be connected between the active layer 207 of the seventh P-type transistor and the active layer 209 of the ninth P-type transistor. The first region 208-1 of the active layer 208 of the eighth P-type transistor can simultaneously serve as the first region of the active layer 209 of the ninth P-type transistor, and the second region 208-2 of the active layer 208 of the eighth P-type transistor can simultaneously serve as the first region of the active layer 207 of the seventh P-type transistor; the second region 207-2 of the active layer 207 of the seventh P-type transistor and the second region 209-2 of the active layer 209 of the ninth P-type transistor can be independently arranged.

[0168] In some examples, the active layer 210 of the tenth P-type transistor can extend along the second direction D2, and the positive projection of the active layer 210 of the tenth P-type transistor on the substrate can be substantially rectangular, such as a rounded rectangular shape, extending along the second direction D2. The first region 210-1 and the second region 210-2 of the active layer 210 of the tenth P-type transistor can be located on both sides of the channel region of the active layer 210 of the tenth P-type transistor along the second direction D2.

[0169] In some examples, the active layers 211a and 211b of the eleventh P-type transistor can be arranged in alignment along the first direction D1 on the substrate, and both extend along the first direction D1. The positive projection of the active layers 211a and 211b of the eleventh P-type transistor on the substrate can be substantially rectangular, such as a rounded rectangular shape. The first region 211a-1 and the second region 211a-2 of the active layer 211a of the eleventh P-type transistor can be located on both sides of the channel region of the active layer 211a of the eleventh P-type transistor along the second direction D2; the first region 211b-1 and the second region 211b-2 of the active layer 211b of the eleventh P-type transistor can be located on both sides of the channel region of the active layer 211b of the eleventh P-type transistor along the second direction D2.

[0170] The present examples can effectively utilize the arrangement space and reduce the space waste of the display substrate by reasonably arranging the positions of the active layers of the plurality of P-type transistors.

[0171] (3) forming a first conductive layer. In some examples, on the substrate of the foregoing structure, a first insulating thin film and a first conductive thin film are sequentially deposited, the first conductive thin film is patterned by a patterning process, and a first insulating layer and a first conductive layer disposed on the first insulating layer are formed.

[0172] FIG. 11A is a schematic view of the display substrate after the first conductive layer is formed in FIG. 9; and FIG. 11B is a schematic view of the first conductive layer in FIG. 11A. In some examples, as shown in FIGS. 11A and 11B, the first conductive layer of the display substrate can include the first plate C01 of the capacitor of the shift register circuit and the gates of the plurality of P-type transistors, for example, including the gate 301 of the first P-type transistor Tp_1, the gate 302 of the second P-type transistor Tp_2, the gate 303 of the third P-type transistor Tp_3, the gate 304 of the fourth P-type transistor Tp_4, the gate 305 of the fifth P-type transistor Tp_5, the gate 306 of the sixth P-type transistor Tp_6, the gate 307 of the seventh P-type transistor Tp_7, the gate 308 of the eighth P-type transistor Tp_8, the gate 309 of the ninth P-type transistor Tp_9, the gate 310 of the tenth P-type transistor Tp_10, and the gate 311 of the eleventh P-type transistor Tp_11.

[0173] In some examples, the gate 302 of the second P-type transistor Tp_2 and the gate 303 of the third P-type transistor Tp_3 are adjacent in the second direction D2. The orthographic projection of the gate 302 of the second P-type transistor Tp_2 on the substrate can be substantially a strip extending along the second direction D2. The orthographic projection of the gate 303 of the third P-type transistor Tp_3 on the substrate can be substantially a strip extending along the first direction D1.

[0174] In some examples, the gate 301 of the first P-type transistor Tp_1 and the gate 305 of the fifth P-type transistor Tp_5 can be substantially aligned in the second direction D2. The orthographic projection of the gate 301 of the first P-type transistor Tp_1 on the substrate can be substantially a strip extending along the first direction D1. The orthographic projection of the gate 305 of the fifth P-type transistor Tp_5 on the substrate can be substantially a strip extending along the first direction D1.

[0175] In some examples, the orthographic projection of the gate 304 of the fourth P-type transistor Tp_4 on the substrate can be substantially a T shape. The gate 306 of the sixth P-type transistor Tp_6 can be located between the gate 304 of the fourth P-type transistor Tp_4 and the first plate C01 of the capacitor in the first direction D1. The orthographic projection of the gate 306 of the sixth P-type transistor Tp_6 on the substrate can be substantially a ladder shape extending along the second direction D2. The orthographic projection of the first plate C01 of the capacitor on the substrate can be substantially a kitchen knife shape.

[0176] In some examples, the gate 307 of the seventh P-type transistor Tp_7 can have a footprint on the substrate that is substantially strip-shaped extending along the first direction D1. The gate 308 of the eighth P-type transistor Tp_8 and the gate 309 of the ninth P-type transistor Tp_9 can have a footprint on the substrate that is substantially strip-shaped extending along the second direction D2. The gate 310 of the tenth P-type transistor Tp_10 can have a footprint on the substrate that is substantially U-shaped, and the opening of the U-shaped can face away from the gate 309 of the ninth P-type transistor Tp_9. The gate 311 of the eleventh P-type transistor Tp_11 can have a footprint on the substrate that is substantially straight line-shaped extending along the first direction D1.

[0177] (4) forming a second conductive layer. In some examples, on the substrate with the foregoing structure, a second insulating thin film and a second conductive thin film are sequentially deposited, the second conductive thin film is patterned by a patterning process, and a second insulating layer and a second conductive layer disposed on the second insulating layer are formed.

[0178] FIG. 12A is a schematic view of the display substrate after the second conductive layer is formed in FIG. 9; and FIG. 12B is a schematic view of the second conductive layer in FIG. 12A. In some examples, as shown in FIG. 12A and FIG. 12B, the second conductive layer of the display substrate can include: a second plate C02 of a capacitor of a shift register circuit, a plurality of bottom gates of N-type transistors (for example, including: a bottom gate 341 of a first N-type transistor, a bottom gate 342 of a second N-type transistor, a bottom gate 343 of a third N-type transistor, a bottom gate 344 of a fourth N-type transistor, a bottom gate 345 of a fifth N-type transistor, a bottom gate 346 of a sixth N-type transistor, a bottom gate 347 of a seventh N-type transistor, a bottom gate 348 of an eighth N-type transistor, a bottom gate 349 of a ninth N-type transistor, a bottom gate 350 of a tenth N-type transistor, and a bottom gate 351 of an eleventh N-type transistor), and a plurality of bottom gate connection lines (for example, including a first bottom gate connection line 51, a second bottom gate connection line 52, and a third bottom gate connection line 53).

[0179] In some examples, the second plate C02 of the capacitor can have a footprint on the substrate that is substantially rectangular, for example, can be a rounded rectangular. The footprint on the substrate of the second plate C02 of the capacitor and the footprint on the substrate of the first plate C01 can partially overlap.

[0180] In some examples, the bottom gate 341 of the first N-type transistor and the bottom gate 345 of the fifth N-type transistor can each extend along the first direction D1 and be aligned along the second direction D2. The bottom gate 341 of the first N-type transistor and the bottom gate 345 of the fifth N-type transistor can have a footprint on the substrate that is substantially L-shaped.

[0181] In some examples, the bottom gate 342 of the second N-type transistor can have a projection on the substrate that is substantially a rectangle extending along the first direction D1. The bottom gate 343 of the third N-type transistor can have a projection on the substrate that is substantially a rectangle extending along the first direction D1. The bottom gate 342 of the second N-type transistor and the bottom gate 343 of the third N-type transistor can be arranged in alignment along the second direction D2. The bottom gate 344 of the fourth N-type transistor can have a projection on the substrate that is substantially an n-shape. The bottom gate 343 of the third N-type transistor and the bottom gate 344 of the fourth N-type transistor can be adjacent and connected along the second direction D2.

[0182] In some examples, the bottom gate 346 of the sixth N-type transistor can have a projection on the substrate that is substantially a rectangle extending along the first direction D1. The bottom gate 347 of the seventh N-type transistor and the bottom gate 346 of the sixth N-type transistor can be arranged in alignment along the second direction D2. The bottom gate 347 of the seventh N-type transistor and the bottom gate 348 of the eighth N-type transistor can have a projection on the substrate that is substantially a rectangle extending along the first direction D1. The bottom gate 347 of the seventh N-type transistor and the bottom gate 348 of the eighth N-type transistor can be adjacent and connected along the second direction D2.

[0183] In some examples, the bottom gate 349 of the ninth N-type transistor can have a projection on the substrate that is substantially a rectangle extending along the second direction D2. The bottom gate 349 of the ninth N-type transistor can be arranged in alignment with the second plate C02 of the capacitor along the second direction D2. The bottom gate 350 of the tenth N-type transistor can have a projection on the substrate that is substantially a U-shape, and the opening of the U-shape faces away from the second plate of the capacitor. The bottom gate 351 of the eleventh N-type transistor can have a projection on the substrate that is substantially a mountain-shape, and the opening of the mountain-shape faces away from the bottom gate 350 of the tenth N-type transistor.

[0184] In some examples, the bottom gate 350 of the tenth N-type transistor of the current stage of the shift register circuit (e.g., the n-th stage of the shift register circuit GOA(n)) can be connected to the bottom gate 342 of the second N-type transistor, the bottom gate 347 of the seventh N-type transistor, and the bottom gate 348 of the eighth N-type transistor of the next stage of the shift register circuit (e.g., the n+1-th stage of the shift register circuit GOA(n+1)) through the first bottom gate connection line 51. For example, the bottom gate 350 of the tenth N-type transistor of the current stage of the shift register circuit (e.g., the n-th stage of the shift register circuit GOA(n)), the bottom gate 342 of the second N-type transistor, the bottom gate 347 of the seventh N-type transistor, and the bottom gate 348 of the eighth N-type transistor of the next stage of the shift register circuit (e.g., the n+1-th stage of the shift register circuit GOA(n+1)), and the first bottom gate connection line 51 can be an integrated structure.

[0185] In some examples, the first bottom gate connection line 51 can include a first trace segment 510 extending along the first direction D1, a first connection segment 511 extending along the second direction D2, and a second connection segment 512. The first trace segment 510 is a broken line segment extending along the first direction D1 in the orthographic projection of the substrate. One end of the first trace segment 510 can be connected with the first voltage line, and the other end can be connected with the bottom gate 350 of the tenth N-type transistor of the current stage shift register circuit (e.g., the n-th stage shift register circuit GOA(n)). The first trace segment 510 can be located within the interval of the adjacent two stage shift register circuits. The first connection segment 511 and the second connection segment 512 are connected on the same side of the first trace segment 510 along the second direction D2. The first connection segment 511 and the second connection segment 512 are strips extending along the second direction D2 in the orthographic projection of the substrate. The first connection segment 511 is connected with the bottom gate 342 of the second N-type transistor of the next stage shift register circuit (e.g., the n+1-th stage shift register circuit GOA(n+1)), and the second connection segment 512 is connected with the bottom gate 347 of the seventh N-type transistor and the bottom gate 348 of the eighth N-type transistor of the next stage shift register circuit.

[0186] In some examples, the bottom gate 343 of the third N-type transistor, the bottom gate 344 of the fourth N-type transistor, the bottom gate 346 of the sixth N-type transistor, and the bottom gate 349 of the ninth N-type transistor of the current stage shift register circuit, and the connected second bottom gate connection line 52 and third bottom gate connection line 53 can be an integrated structure.

[0187] In some examples, the second bottom gate connection line 52 is substantially U-shaped in the orthographic projection of the substrate. One end of the second bottom gate connection line 52 can be connected with the second voltage line, and the other end can be connected with the bottom gate 343 of the third N-type transistor. The bottom gate 344 of the fourth N-type transistor can be connected between the bottom gate 343 of the third N-type transistor and the third bottom gate connection line 53.

[0188] In some examples, the third bottom gate connection line 53 can include a second trace segment 530 extending along the first direction D1, and a third connection segment 531 extending along the second direction D2. The second trace segment 530 is a broken line segment extending along the first direction D1 in the orthographic projection of the substrate. One end of the second trace segment 530 is connected with the bottom gate 344 of the fourth N-type transistor, and the other end is connected with the bottom gate 349 of the ninth N-type transistor. The third connection segment 531 is a strip extending along the second direction D2 in the orthographic projection of the substrate. The third connection segment 531 is connected with the bottom gate 346 of the sixth N-type transistor. The orthographic projection of the second trace segment 530 in the substrate can be located between the orthographic projection of the second or NOT gate circuit and the third transmission gate circuit in the substrate, and between the orthographic projection of the second transmission gate circuit and the first NOT gate circuit.

[0189] The example can realize the bottom gate connection of the corresponding multiple N-type transistors by setting multiple bottom gate connection lines, and facilitate to reduce the layout difficulty of the shift register circuit.

[0190] In some examples, the second conductive layer can have no overlap with the first semiconductor layer and the first conductive layer in the orthographic projection of the substrate, thereby reducing the influence on the P-type transistor.

[0191] (5) Forming a second semiconductor layer. In some examples, on the substrate formed with the foregoing pattern, a third insulating film and a second semiconductor film are sequentially deposited, the second semiconductor film is patterned by a patterning process, and a third insulating layer and a second semiconductor layer disposed on the third insulating layer are formed. In some examples, the material of the second semiconductor layer can include indium gallium zinc oxide (IGZO).

[0192] FIG. 13A is a schematic view of the display substrate after the second semiconductor layer is formed in FIG. 9; and FIG. 13B is a schematic view of the second semiconductor layer in FIG. 13A. In some examples, as shown in FIGS. 13A and 13B, the second semiconductor layer of the display substrate can include the active layers of the multiple N-type transistors of the shift register circuit, for example, including the active layer 221 of the first N-type transistor Tn_1, the active layer 222 of the second N-type transistor Tn_2, the active layer 223 of the third N-type transistor Tn_3, the active layer 224 of the fourth N-type transistor Tn_4, the active layer 225 of the fifth N-type transistor Tn_5, the active layer 226 of the sixth N-type transistor Tn_6, the active layer 227 of the seventh N-type transistor Tn_7, the active layer 228 of the eighth N-type transistor Tn_8, the active layer 229 of the ninth N-type transistor Tn_9, the active layer 230 of the tenth N-type transistor Tn_10, and the active layers 231a and 231b of the eleventh N-type transistor Tn_11.

[0193] In some examples, the active layer 222 of the second N-type transistor Tn_2 can have a dumbbell shape extending along the second direction D2 in the orthographic projection of the substrate. The first region 222-1 and the second region 222-2 of the active layer 222 of the second N-type transistor Tn_2 are located on both sides of the channel region along the second direction D2.

[0194] In some examples, the active layer 223 of the third N-type transistor Tn_3 can extend along the second direction D2, and the active layer 224 of the fourth N-type transistor Tn_4 can extend along the first direction D1. The active layer 223 of the third N-type transistor Tn_3 and the active layer 224 of the fourth N-type transistor Tn_4 can be an integrated structure, and the orthographic projection of the integrated structure on the substrate can be substantially L-shaped. The first region 223-1 of the active layer 223 of the third N-type transistor Tn_3 can simultaneously serve as the first region of the active layer 224 of the fourth N-type transistor Tn_4, and the second region 223-2 of the active layer 223 of the third N-type transistor Tn_3 and the second region 224-2 of the active layer 224 of the fourth N-type transistor Tn_4 can be independently arranged.

[0195] In some examples, the active layer 221 of the first N-type transistor Tn_1 and the active layer 225 of the fifth N-type transistor Tn_5 can both extend along the second direction D2. The active layer 221 of the first N-type transistor Tn_1 and the active layer 225 of the fifth N-type transistor Tn_5 can be an integrated structure, and the orthographic projection of the integrated structure on the substrate can be substantially I-shaped. The second region 221-2 of the active layer 221 of the first N-type transistor Tn_1 can simultaneously serve as the first region of the active layer 225 of the fifth N-type transistor Tn_5, and the first region 221-1 of the active layer 221 of the first N-type transistor Tn_1 and the second region 225-2 of the active layer 225 of the fifth N-type transistor Tn_5 can be independently arranged.

[0196] In some examples, the active layer 226 of the sixth N-type transistor Tn_6, the active layer 227 of the seventh N-type transistor Tn_7, and the active layer 228 of the eighth N-type transistor Tn_8 can have an orthographic projection on the substrate that is substantially dumbbell-shaped extending along the second direction D2. The active layer 227 of the seventh N-type transistor Tn_7 and the active layer 228 of the eighth N-type transistor Tn_8 can be arranged in alignment along the first direction D1, and the active layer 227 of the seventh N-type transistor Tn_7 and the active layer 226 of the sixth N-type transistor Tn_6 can be arranged in alignment along the second direction D2. The first region 226-1 and the second region 226-2 of the active layer 226 of the sixth N-type transistor Tn_6 can be located on both sides of the channel region of the sixth N-type transistor Tn_6 along the second direction D2. The first region 227-1 and the second region 227-2 of the active layer 227 of the seventh N-type transistor Tn_7 can be located on both sides of the channel region of the seventh N-type transistor Tn_7 along the second direction D2. The first region 228-1 and the second region 228-2 of the active layer 228 of the eighth N-type transistor Tn_8 can be located on both sides of the channel region of the eighth N-type transistor Tn_8 along the second direction D2.

[0197] In some examples, the active layer 229 of the ninth N-type transistor Tn_9 and the active layer 228 of the eighth N-type transistor Tn_8 can be arranged in alignment along the first direction D1. The active layer 229 of the ninth N-type transistor Tn_9 can extend along the first direction D1, and a footprint of the active layer 229 of the ninth N-type transistor Tn_9 on the substrate can be substantially rectangular. The first region 229-1 and the second region 229-2 of the active layer 229 of the ninth N-type transistor Tn_9 can be located on two sides of a channel region of the ninth N-type transistor Tn_9 along the first direction D1.

[0198] In some examples, the active layer 230 of the tenth N-type transistor Tn_10 can extend along the second direction D2, and a footprint of the active layer 230 of the tenth N-type transistor Tn_10 on the substrate can be substantially rectangular. The active layers 231a and 231b of the eleventh N-type transistor Tn_11 can be arranged in alignment along the first direction D1, and a footprint of the active layers 231a and 231b of the eleventh N-type transistor Tn_11 on the substrate can be substantially rectangular.

[0199] (6) Forming a third conductive layer. In some examples, on the substrate with the aforementioned pattern, a fourth insulating thin film and a third conductive thin film are sequentially deposited, the third conductive thin film is patterned by a patterning process, and a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer are formed.

[0200] FIG. 14A is a schematic view of the display substrate after the third conductive layer is formed in FIG. 9, and FIG. 14B is a schematic view of the third conductive layer in FIG. 14A. In some examples, as shown in FIG. 14A and FIG. 14B, the third conductive layer of the display substrate can include top gates of the plurality of N-type transistors of the shift register circuit, for example, can include the top gate 321 of the first N-type transistor Tn_1, the top gate 322 of the second N-type transistor Tn_2, the top gate 323 of the third N-type transistor Tn_3, the top gate 324 of the fourth N-type transistor Tn_4, the top gate 325 of the fifth N-type transistor Tn_5, the top gate 326 of the sixth N-type transistor Tn_6, the top gate 327 of the seventh N-type transistor Tn_7, the top gate 328 of the eighth N-type transistor Tn_8, the top gate 329 of the ninth N-type transistor Tn_9, the top gate 330 of the tenth N-type transistor Tn_10, and the top gate 331 of the eleventh N-type transistor Tn_11.

[0201] In some examples, the top gate 321 of the first N-type transistor Tn_1, the top gate 322 of the second N-type transistor Tn_2, the top gate 323 of the third N-type transistor Tn_3, the top gate 325 of the fifth N-type transistor Tn_5, the top gate 326 of the sixth N-type transistor Tn_6, the top gate 327 of the seventh N-type transistor Tn_7, and the top gate 328 of the eighth N-type transistor Tn_8 can all extend along the first direction D1, for example, the orthographic projection on the substrate can be a strip extending along the first direction D1. The top gate 329 of the ninth N-type transistor Tn_9 can extend along the second direction D2, for example, the orthographic projection on the substrate is a strip extending along the second direction D2. The orthographic projection of the top gate 324 of the fourth N-type transistor Tn_4 on the substrate can be substantially n-shaped. The orthographic projection of the top gate 330 of the tenth N-type transistor Tn_10 on the substrate can be substantially U-shaped, and the opening of the U shape faces the top gate 331b of the eleventh N-type transistor Tn_11. The orthographic projection of the top gate 331a of the eleventh N-type transistor Tn_11 on the substrate is a long strip extending along the first direction D1, and the orthographic projection of the top gate 331b of the eleventh N-type transistor Tn_11 on the substrate is substantially U-shaped, and the opening of the U shape faces away from the top gate 330 of the tenth N-type transistor Tn_10.

[0202] In some examples, the top gate 322 of the second N-type transistor Tn_2 and the top gate 323 of the third N-type transistor Tn_3 can be arranged in alignment along the second direction D2. The top gate 321 of the first N-type transistor Tn_1 and the top gate 325 of the fifth N-type transistor Tn_5 can be arranged in alignment along the second direction D2. The top gate 326 of the sixth N-type transistor Tn_6 and the top gate 327 of the seventh N-type transistor Tn_7 can be arranged in alignment along the second direction D2. The top gate 327 of the seventh N-type transistor Tn_7 and the top gate 328 of the eighth N-type transistor Tn_8 can be arranged in alignment along the first direction D1.

[0203] In some examples, the orthographic projection on the substrate of the overlapping area between the top gate of an N-type transistor and the active layer can be located within the orthographic projection on the substrate of the overlapping area between the bottom gate of the N-type transistor and the active layer. This example can adjust the characteristics of the N-type transistor by setting the bottom gate of the N-type transistor, thereby achieving better transistor performance.

[0204] (7), forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate with the aforementioned patterns formed thereon, and the fifth insulating film is patterned by a patterning process to form the fifth insulating layer. In some examples, the fifth insulating film can be patterned by two patterning processes. The first set of vias can be formed in the fifth insulating layer by the first patterning process, and the second set of vias can be formed in the fifth insulating layer by the second patterning process. For example, the first set of vias can expose part of the surfaces of the first semiconductor layer, the first conductive layer, and the second conductive layer, and the second set of vias can expose part of the surfaces of the second semiconductor layer and the third conductive layer.

[0205] FIGS. 15A and 15B are schematic diagrams of the display substrate after the fifth insulating layer is formed in FIG. 9. The first set of vias of the fifth insulating layer is illustrated in FIG. 15A, and the second set of vias of the fifth insulating layer is illustrated in FIG. 15B.

[0206] In some examples, as shown in FIG. 15A, the first set of vias of the fifth insulating layer of the display substrate can include the first via V1 to the twentieth via V20, the twenty-first via V21 to the thirty-third via V33, and the thirty-fourth via V34 to the fortieth via V40. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via V1 to the twentieth via V20 can be removed to expose part of the surface of the first semiconductor layer; the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-first via V21 to the thirty-third via V33 can be removed to expose part of the surface of the first conductive layer; and the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the thirty-fourth via V34 to the fortieth via V40 can be removed to expose part of the surface of the second conductive layer.

[0207] In some examples, as shown in FIG. 15B, the second set of vias of the fifth insulating layer of the display substrate can include the forty-first via V41 to the sixty-seventh via V67, and the sixty-eighth via V68 to the seventy-ninth via V79. The fifth insulating layer and the fourth insulating layer in the forty-first via V41 to the sixty-seventh via V67 can be removed to expose part of the surface of the second semiconductor layer; and the fifth insulating layer in the sixty-eighth via V68 to the seventy-ninth via V79 can be removed to expose part of the surface of the third conductive layer.

[0208] (8), forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate with the aforementioned patterns formed thereon, and the fourth conductive film is patterned by a patterning process to form the fourth conductive layer on the fifth insulating layer.

[0209] FIG. 16A is a schematic view of the display substrate after forming the fourth conductive layer in FIG. 9; FIG. 16B is a schematic view of the fourth conductive layer in FIG. 16A. In some examples, as shown in FIGS. 16A and 16B, the fourth conductive layer of the display substrate can include a plurality of connection electrodes (e.g., including the first connection electrode 401 to the thirty-first connection electrode 431).

[0210] In some examples, the first connection electrode 401 can have a rectangular shape in the orthographic projection of the substrate. The first connection electrode 401 can be connected to the first region 222-1 of the active layer 222 of the second N-type transistor Tn_2 through the forty-first via V41.

[0211] In some examples, the second connection electrode 402 can have a rectangular shape in the orthographic projection of the substrate. The second connection electrode 402 can be connected to the first region 223-1 of the active layer 223 of the third N-type transistor Tn_3 through the forty-fourth via V44. The second connection electrode 402 and the first connection electrode 401 can be arranged in alignment along the second direction D2. The first connection electrode 401 and the second connection electrode 402 can be subsequently connected to the second power supply line VL1a located in the fifth conductive layer.

[0212] In some examples, the third connection electrode 403 can have a substantially rectangular shape in the orthographic projection of the substrate. The third connection electrode 403 can be connected to the first region 203-1 of the active layer 203 of the third P-type transistor Tp_3 through the second via V2. The third connection electrode 403 can be subsequently connected to the first power supply line VH1a located in the fifth conductive layer.

[0213] In some examples, the fourth connection electrode 404 can have a substantially rectangular shape extending along the second direction D2 in the orthographic projection of the substrate. The fourth connection electrode 404 can be connected to the gate 303 of the third P-type transistor Tp_3 through the twenty-second via V22, and can be connected to the top gate 323 of the third N-type transistor Tn_3 through the sixty-ninth via V69. The fourth connection electrode 404 can be subsequently connected to the reset control line RST located in the fifth conductive layer.

[0214] In some examples, the fifth connection electrode 405 can have a substantially rectangular shape in the orthographic projection of the substrate. The fifth connection electrode 405 can be connected to the gate 305 of the fifth P-type transistor Tp_5 through the twenty-third via V23. The fifth connection electrode 405 of the nth-stage shift register circuit GOA(n) can be subsequently connected to the fourth clock signal line CL4 located in the fifth conductive layer.

[0215] In some examples, the sixth connection electrode 406 can have a substantially rectangular footprint on the substrate. The sixth connection electrode 406 can be connected to the gate 301 of the first P-type transistor Tp_1 through the twenty-fourth via V24. The sixth connection electrode 406 of the nth-stage shift register circuit GOA(n) can be subsequently connected to the second clock signal line CL2 located in the fifth conductive layer.

[0216] In some examples, the seventh connection electrode 407 can have a substantially rectangular footprint on the substrate. The seventh connection electrode 407 can be connected to the bottom gate 341 of the first N-type transistor Tn_1 through the thirty-eighth via V38, and can be connected to the top gate 321 of the first N-type transistor Tn_1 through the seventy-first via V71. The seventh connection electrode 407 of the nth-stage shift register circuit GOA(n) can be subsequently connected to the first clock signal line CL1 located in the fifth conductive layer.

[0217] In some examples, the eighth connection electrode 408 can have a substantially L-shaped footprint on the substrate. The eighth connection electrode 408 can be connected to the bottom gate 345 of the fifth N-type transistor Tn_5 through the thirty-ninth via V39, and can be connected to the top gate 325 of the fifth N-type transistor Tn_5 through the seventy-second via V72. The eighth connection electrode 408 of the nth-stage shift register circuit GOA(n) can be subsequently connected to the third clock signal line CL3 located in the fifth conductive layer.

[0218] In some examples, the ninth connection electrode 409 can have a substantially rectangular footprint on the substrate. The ninth connection electrode 409 can be connected to the second region 208-2 of the active layer 208 of the eighth P-type transistor Tp_8 through the ninth via V9.

[0219] In some examples, the tenth connection electrode 410 can have a substantially rectangular footprint on the substrate. The tenth connection electrode 410 can be connected to the first region 227-1 of the active layer 227 of the seventh N-type transistor Tn_7 through the fifty-first via V51, and can be connected to the first region 228-1 of the active layer 228 of the eighth N-type transistor Tn_8 through the fifty-second via V52. The tenth connection electrode 410 can be subsequently connected to the second power supply line VL1b located in the fifth conductive layer.

[0220] In some examples, the eleventh connection electrode 411 can have a substantially L-shaped footprint on the substrate. The eleventh connection electrode 411 can be connected to the first region 208-1 of the active layer 208 of the eighth P-type transistor Tp_8 through the tenth via V10. The eleventh connection electrode 411 can be subsequently connected to the first power supply line VH1c located in the fifth conductive layer.

[0221] In some examples, the twelfth connection electrode 412 can have a substantially rectangular shape in the orthogonal projection on the substrate. The twelfth connection electrode 412 can be connected to the conductorized region between two channel regions of the active layer 210 of the tenth P-type transistor Tp_10 through a plurality (e.g., three) of fifteenth vias V15 arranged in alignment along the first direction D1. The twelfth connection electrode 412 can be subsequently connected to the first power supply line VH1d located in the fifth conductive layer.

[0222] In some examples, the thirteenth connection electrode 413 can have a substantially L-shape in the orthogonal projection on the substrate. The thirteenth connection electrode 413 can be connected to the first region 204-1 of the active layer 204 of the fourth P-type transistor Tp_4 through the seventh via V7. The thirteenth connection electrode 413 can be subsequently connected to the first power supply line VH1b located in the fifth conductive layer.

[0223] In some examples, the fourteenth connection electrode 414 can have a substantially L-shape in the orthogonal projection on the substrate. The fourteenth connection electrode 414 can be connected to the first region 206-1 of the active layer 206 of the sixth P-type transistor Tp_6 through the thirteenth via V13, and can be connected to the first region 226-1 of the active layer 226 of the sixth N-type transistor Tn_6 through the fifty-fourth via V54. The fourteenth connection electrode 414 of the nth-stage shift register circuit GOA(n) can be subsequently connected to the first enable control line EN1 located in the fifth conductive layer.

[0224] In some examples, the fifteenth connection electrode 415 can have a strip shape extending along the first direction D1 in the orthogonal projection on the substrate. The fifteenth connection electrode 415 can be connected to the active layer 231a of the eleventh N-type transistor Tn_11 through a plurality (e.g., seven) of sixtieth vias V60 arranged in alignment along the first direction D1, and can be connected to the active layer 231b of the eleventh N-type transistor Tn_11 through a plurality (e.g., seven) of sixty-fourth vias V64 arranged in alignment along the first direction D1. The fifteenth connection electrode 415 can be subsequently connected to the second power supply line VL2 located in the fifth conductive layer.

[0225] In some examples, the sixteenth connection electrode 416 can have a U-shaped projection on the substrate, and the opening of the U-shaped projection faces the tenth P-type transistor Tp_10. The sixteenth connection electrode 416 can be connected to the active layer 231a of the eleventh N-type transistor Tn_11 through a plurality of (e.g., seven) sixty-first vias V61 aligned in the first direction D1 and a plurality of (e.g., seven) sixty-third vias V63 aligned in the first direction D1, can be connected to the active layer 231b of the eleventh N-type transistor Tn_11 through a plurality of (e.g., seven) sixty-fifth vias V65 aligned in the first direction D1 and a plurality of (e.g., seven) sixty-seventh vias V67 aligned in the first direction D1, can be connected to the second region 211a-2 of the active layer 211a of the eleventh P-type transistor Tp_11 through a plurality of (e.g., seven) seventeenth vias V17 aligned in the first direction D1, and can be connected to the second region 211b-2 of the active layer 211b of the eleventh P-type transistor Tp_11 through a plurality of (e.g., seven) nineteenth vias V19 aligned in the first direction D1. The sixteenth connection electrode 416 can serve as an output terminal of the shift register circuit.

[0226] In some examples, the seventeenth connection electrode 417 can have a strip-shaped projection on the substrate extending in the first direction D1. The seventeenth connection electrode 417 can be located in the U-shaped opening of the sixteenth connection electrode 416. The seventeenth connection electrode 417 can be connected to the active layer 231a of the eleventh N-type transistor Tn_11 through a plurality of (e.g., seven) sixty-second vias V62 aligned in the first direction D1, and can be connected to the active layer 231b of the eleventh N-type transistor Tn_11 through a plurality of (e.g., seven) sixty-sixth vias V66 aligned in the first direction D1. The seventeenth connection electrode 417 can be subsequently connected to the second power line VL2 located in the fifth conductive layer.

[0227] In some examples, the eighteenth connection electrode 418 can have a projection on the substrate extending in the second direction D2. The eighteenth connection electrode 418 can be connected to the second region 209-2 of the active layer 209 of the ninth P-type transistor Tp_9 through the eleventh via V11, can be connected to the gate 310 of the tenth P-type transistor Tp_10 through the thirty-first via V31, can be connected to the second region 229-2 of the active layer 229 of the ninth N-type transistor Tn_9 through the fifty-sixth via V56, and can be connected to the top gate 330 of the tenth N-type transistor Tn_10 through the seventy-sixth via V76.

[0228] In some examples, the nineteenth connection electrode 419 can have a rectangular footprint on the substrate. The nineteenth connection electrode 419 can be connected to the bottom gate 351 of the eleventh N-type transistor Tn_11 through a thirty-fifth via hole V35. The nineteenth connection electrode 419 can be subsequently connected to a third voltage line BG3 located in the fifth conductive layer, so as to realize electrical connection between the bottom gate 351 of the eleventh N-type transistor Tn_11 and the third voltage line BG3.

[0229] In some examples, the twentieth connection electrode 420 can have a substantially L-shaped footprint on the substrate. The twentieth connection electrode 420 can be connected to the first region 201-1 of the active layer 201 of the first P-type transistor Tp_1 through a third via hole V3, and can also be connected to the first region 221-1 of the active layer 221 of the first N-type transistor Tn_1 through a forty-sixth via hole V46. The twentieth connection electrode 420 can serve as an input terminal of the shift register circuit at the current stage.

[0230] In some examples, the twenty-first connection electrode 421 can have a footprint on the substrate which is substantially a broken line extending in the first direction D1. The twenty-first connection electrode 421 can be connected to the gate 302 of the second P-type transistor Tp_2 through a twenty-first via hole V21, and can also be connected to the top gate 322 of the second N-type transistor Tn_2 through a sixty-eighth via hole V68. The twenty-first connection electrode 421 can also be connected to the second region 201-2 of the active layer 201 of the first P-type transistor Tp_1 through a fourth via hole V4, and can also be connected to the second region 221-2 of the active layer 221 of the first N-type transistor Tn_1 through a forty-seventh via hole V47. Since the second region of the active layer of the first P-type transistor Tp_1 also serves as the second region of the active layer of the fifth P-type transistor Tp_5, and the second region of the active layer of the first N-type transistor Tn_1 also serves as the second region of the active layer of the fifth N-type transistor Tn_5, the twenty-first connection electrode 421 can serve as an input node, realizing connection of the first transmission gate circuit, the first NAND gate circuit, and the second transmission gate circuit.

[0231] In some examples, the second twenty-two connection electrode 422 can have a substantially fold line shape extending along the first direction D1 in the orthographic projection of the substrate. The second twenty-two connection electrode 422 can be connected to the second region of the active layer of the second P-type transistor Tp_2 through the first via V1, to the second region 222-2 of the active layer 222 of the second N-type transistor Tn_2 through the forty-second via V42, to the second region 223-2 of the active layer 223 of the third N-type transistor Tn_3 through the forty-third via V43, to the top gate 324 of the fourth N-type transistor Tn_4 through the seventy via V70, and to the gate 304 of the fourth P-type transistor Tp_4 through the twenty-fifth via V25. The second twenty-two connection electrode 422 can realize the connection of the first OR gate circuit and the first NOT gate circuit.

[0232] In some examples, the second twenty-three connection electrode 423 can have a substantially L shape in the orthographic projection of the substrate. The second twenty-three connection electrode 423 can be connected to the gate 304 of the fourth P-type transistor Tp_4 through the twenty-sixth via V26, and to the top gate 326 of the sixth N-type transistor Tn_6 through the seventy-fifth via V75. In this example, the second twenty-two connection electrode 422, the gate 304 of the fourth P-type transistor Tp_4, and the second twenty-three connection electrode 423 can be connected as a first intermediate node.

[0233] In some examples, the second twenty-four connection electrode 424 can have a substantially ladder shape extending along the second direction D2 in the orthographic projection of the substrate. The second twenty-four connection electrode 424 can be connected to the second region 205-2 of the active layer 205 of the fifth P-type transistor Tp_5 through the fifth via V5, to the second region 204-2 of the active layer 204 of the fourth P-type transistor Tp_4 through the sixth via V6, to the second region 225-2 of the active layer 225 of the fifth N-type transistor Tn_5 through the forty-eighth via V48, to the second region 224-2 of the active layer 224 of the fourth N-type transistor Tn_4 through the forty-fifth via V45, to the gate 306 of the sixth P-type transistor Tp_6 through the twenty-seventh via V27, to the gate 307 of the seventh P-type transistor Tp_7 through the twenty-eighth via V28, and to the top gate 327 of the seventh N-type transistor Tn_7 through the seventy-third via V73. The second twenty-four connection electrode 424 can realize the connection of the second transmission gate circuit, the first NOT gate circuit, the second OR gate circuit, and the third transmission gate circuit as a second intermediate node. The second twenty-four connection electrode 424 of the present stage shift register circuit (e.g., the n-th stage shift register circuit GOA(n)) and the second ten connection electrode 420 of the next stage shift register circuit (e.g., the (n+1)-th stage shift register circuit GOA(n+1)) can be an integrated structure.

[0234] In some examples, the twenty-fifth connection electrode 425 can have a footprint on the substrate that is generally a broken line extending along the first direction D1. The twenty-fifth connection electrode 425 can be connected to the second region 207-2 of the active layer 207 of the seventh P-type transistor Tp_7 through the eighth via V8, to the gate 309 of the ninth P-type transistor Tp_9 through the thirtieth via V30, to the second region 227-2 of the active layer 227 of the seventh N-type transistor Tn_7 through the forty-ninth via V49, to the second region 228-2 of the active layer 228 of the eighth N-type transistor Tn_8 through the fiftieth via V50, and to the top gate 329 of the ninth N-type transistor Tn_9 through the seventy-ninth via V79.

[0235] In some examples, the twenty-sixth connection electrode 426 can have a footprint on the substrate that is generally L-shaped. The twenty-sixth connection electrode 426 can be connected to the gate 308 of the eighth P-type transistor Tp_8 through the twenty-ninth via V29, to the first plate C01 of the capacitor through the thirty-second via V32, to the second region 206-2 of the active layer 206 of the sixth P-type transistor Tp_6 through the twelfth via V12, to the top gate 328 of the eighth N-type transistor Tn_8 through the seventy-fourth via V74, and to the second region 226-2 of the active layer 226 of the sixth N-type transistor Tn_6 through the fifty-third via V53.

[0236] In some examples, the twenty-seventh connection electrode 427 can have a footprint on the substrate that is generally L-shaped. The twenty-seventh connection electrode 427 can be connected to the second plate C02 of the capacitor through two fourthieth vias V40 aligned along the second direction D2, to the first region 229-1 of the active layer 229 of the ninth N-type transistor Tn_9 through the fifty-fifth via V55, and to the active layer 230 of the tenth N-type transistor Tn_10 through three fifty-eighth vias V58 aligned along the first direction D1. The twenty-seventh connection electrode 427 can be subsequently connected to the second power line VL1c in the fifth conductive layer.

[0237] In some examples, the twenty-eighth connection electrode 428 can have a substantially E-shaped footprint on the substrate. The twenty-eighth connection electrode 428 can be connected to the active layer 210 of the tenth P-type transistor Tp_10 through three fourteenth vias V14 aligned along the first direction D1 and three sixteenth vias V16 aligned along the first direction D1, to the bottom gate 351 of the eleventh N-type transistor Tn_11 through a thirty-fourth via V34, to the gate 311 of the eleventh P-type transistor Tp_11 through a thirty-third via V33, to the active layer 230 of the tenth N-type transistor Tn_10 through three fifty-seventh vias V57 aligned along the first direction D1 and three fifty-ninth vias V59 aligned along the first direction D1, to the top gate 331a of the eleventh N-type transistor Tn_11 through a seventy-seventh via V77, and to the top gate 331b of the eleventh N-type transistor Tn_11 through a seventy-eighth via V78.

[0238] In some examples, the twenty-ninth connection electrode 429 can have a substantially strip-shaped footprint on the substrate extending along the second direction D2. The twenty-ninth connection electrode 429 can be connected to the second bottom gate connection line 52 through two thirty-sixth vias V36 aligned along the second direction D2. The twenty-ninth connection electrode 429 can be subsequently connected to the second voltage line BG2 on the fifth conductive layer.

[0239] In some examples, the thirtieth connection electrode 430 can have a substantially strip-shaped footprint on the substrate extending along the second direction D2. The thirtieth connection electrode 430 can be connected to the first bottom gate connection line 51 through two thirty-seventh vias V37 aligned along the second direction D2. The thirtieth connection electrode 430 can be subsequently connected to the first voltage line BG1 on the fifth conductive layer.

[0240] In some examples, the thirty-first connection electrode 431 can have a substantially strip-shaped footprint on the substrate extending along the first direction D1. The thirty-first connection electrode 431 can be connected to the active layer 211a of the eleventh P-type transistor Tp_11 through a plurality (e.g., seven) of eighteenth vias V18 aligned along the first direction D1, and to the active layer 211b of the eleventh P-type transistor Tp_11 through a plurality (e.g., seven) of twentieth vias V20 aligned along the first direction D1. The thirty-first connection electrode 431 can be subsequently connected to the first power line VH2 on the fifth conductive layer.

[0241] (9), forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating thin film is deposited on the substrate formed with the foregoing pattern, the sixth insulating thin film is patterned by a patterning process to form the sixth insulating layer, then a seventh insulating thin film is coated, the seventh insulating thin film is patterned by a patterning process to form the seventh insulating layer.

[0242] FIG. 17 is a schematic view of a display substrate after forming a seventh insulating layer in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 17, the seventh insulating layer of the display substrate is provided with a plurality of vias, which can include, for example, eighty-first to one hundredth vias V81-V100. The seventh insulating layer and the sixth insulating layer in the eighty-first to one hundredth vias V81-V100 can be removed to expose part of the surface of the fourth conductive layer.

[0243] (10), forming a fifth conductive layer. In some examples, a fifth conductive thin film is deposited on the substrate formed with the foregoing pattern, the fifth conductive thin film is patterned by a patterning process to form the fifth conductive layer on the seventh insulating layer.

[0244] FIG. 18A is a schematic view of a display substrate after forming a fifth conductive layer in at least one embodiment of the present disclosure. FIG. 18B is a schematic view of the fifth conductive layer in FIG. 18A. In some examples, as shown in FIGS. 18A and 18B, the fifth conductive layer of the display substrate can include a plurality of signal lines, such as first to third voltage lines BG1-BG3, first to fourth clock signal lines CL1-CL4, a reset control line RST, first and second enable control lines EN1-EN2, a plurality of first power lines (such as first power lines VH1a-VH1d, VH2), a plurality of second power lines (such as second power lines VL1a-VL1b and VL2), and a start signal line STV.

[0245] In some examples, the plurality of signal lines extend along a second direction D2. Along a first direction D1, the first voltage line BG1, the second voltage line BG2, the first power line VH1a, the reset control line RST, the second power line VL1a, the fourth clock signal line CL4, the second clock signal line CL2, the third clock signal line CL3, the first clock signal line CL1, the first power line VH1b, the second power line VL1b, the first enable control line EN1, the second enable control line EN2, the first power line VH1c, the second power line VL1c, the first power line VH1d, the first power line VH2, the second power line VL2, the start signal line STV, and the third voltage line BG3 can be arranged in sequence.

[0246] In some examples, the first voltage line BG1 can be connected with the first bottom gate connecting line through two eighty-first vias V81 arranged in alignment along the second direction D2 and the thirtieth connecting electrode 430. The second voltage line BG2 can be connected with the second bottom gate connecting line through two eighty-second vias V82 arranged in alignment along the second direction D2 and the twenty-ninth connecting electrode 429. The first power line VH1a can be connected with the third P-type transistor Tp_3 through an eighty-third via V83 and the third connecting electrode 403. The reset control line RST can be electrically connected with the third P-type transistor Tp_3 and the third N-type transistor Tn-3 through an eighty-fourth via V84 and the fourth connecting electrode 404. The second power line VL1a can be electrically connected with the second N-type transistor Tn_2 and the third N-type transistor Tn_3 through an eighty-fifth via V85 and the second connecting electrode 402, and through an eighty-sixth via V86 and the first connecting electrode 401.

[0247] In some examples, the fourth clock signal line CL4 can be connected with the fifth connecting electrode 405 of the n-th stage shift register circuit GOA(n) and the sixth connecting electrode of the (n+1)-th stage shift register circuit GOA(n+1) through an eighty-eighth via V88. The second clock signal line CL2 can be connected with the sixth connecting electrode 406 of the n-th stage shift register circuit GOA(n) and the fifth connecting electrode of the (n+1)-th stage shift register circuit GOA(n+1) through an eighty-seventh via V87. The third clock signal line CL3 can be connected with the eighth connecting electrode 408 of the n-th stage shift register circuit GOA(n) and the seventh connecting electrode of the (n+1)-th stage shift register circuit GOA(n+1) through a ninetieth via V90. The first clock signal line CL1 can be connected with the seventh connecting electrode 407 of the n-th stage shift register circuit GOA(n) and the eighth connecting electrode of the (n+1)-th stage shift register circuit GOA(n+1) through an eighty-ninth via V89.

[0248] In some examples, the first power line VH1b can be electrically connected with the fourth P-type transistor Tp_4 through a ninety-sixth via V96 and the thirteenth connecting electrode 413. The second power line VL1b can be electrically connected with the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 through a ninety-first via V91 and the tenth connecting electrode 410.

[0249] In some examples, the first enable control line EN1 can be connected with the fourteenth connecting electrode 414 of the n-th stage shift register circuit GOA(n) through a ninety-fifth via V95. The second enable control line EN2 can be connected with the fourteenth connecting electrode of the (n+1)-th stage shift register circuit GOA(n+1).

[0250] In some examples, the first power line VH1c can be connected with the eleventh connection electrode 411 through the ninety-second via hole V92, to realize electrical connection with the eighth P-type transistor Tp_8 and the ninth P-type transistor Tp_9. The second power line VL1c can be connected with the twenty-seventh connection electrode 427 through the ninety-fourth via hole V94, to realize electrical connection with the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10 and the capacitor. The first power line VH1d can be connected with the twelfth connection electrode 412 through the ninety-third via hole V93, to realize electrical connection with the tenth P-type transistor Tp_10. The first power line VH2 can be connected with the thirty-first connection electrode 431 through the one-hundredth via hole V100, to realize electrical connection with the eleventh P-type transistor Tp_11. The second power line VL2 can be connected with the fifteenth connection electrode 415 through the ninety-seventh via hole V97, and can also be connected with the seventeenth connection electrode 417 through the ninety-ninth via hole V99, to realize electrical connection with the eleventh N-type transistor Tn_11.

[0251] In some examples, the third voltage line BG3 can be connected with the nineteenth connection electrode 419 through the ninety-eighth via hole V98, to realize electrical connection with the bottom gate 351 of the eleventh N-type transistor Tn_11.

[0252] In some examples, the potentials of the first power signals provided by the first power lines VH1a, VH1b, VH1c, VH1d can be the same, and the potential of the first power signal provided by the first power line VH2 can be different from the potentials of the first power signals provided by the first power lines VH1a, VH1b, VH1c, VH1d; for example, the potential of the first power signal provided by the first power line VH2 can be greater than the potentials of the first power signals provided by the first power lines VH1a, VH1b, VH1c, VH1d.

[0253] In some examples, the potentials of the second power signals provided by the second power lines VL1a, VL1b can be the same, and the potential of the second power signal provided by the second power line VL2 can be different from the potentials of the second power signals provided by the second power lines VL1a, VL1b; for example, the potential of the second power signal provided by the second power line VL2 can be less than the potentials of the second power signals provided by the second power lines VL1a, VL1b.

[0254] In the present example, the eleventh N-type transistor Tn_11 is located at the rightmost region of the shift register circuit, and the bottom gate 351 of the eleventh N-type transistor Tn_11 located in the second conductive layer can be connected with the third voltage line BG3 located at the rightmost side in the fifth conductive layer, and the threshold voltage of the eleventh N-type transistor Tn_11 can be independently adjusted through the third voltage line BG3, so that the output stability can be improved.

[0255] In the present example, the bottom gate of the tenth N-type transistor Tn_10 of the nth stage shift register circuit GOA(n) can be connected with the bottom gates of the second N-type transistor, the seventh N-type transistor and the eighth N-type transistor of the (n+1)th stage shift register circuit GOA(n+1) through a first bottom gate connection line extending along the first direction D1. The first bottom gate connection line can be connected with the first voltage line BG1 located at the leftmost side in the fifth conductive layer. In some examples, the bottom gates of the second N-type transistor, the seventh N-type transistor and the eighth N-type transistor of the first stage shift register circuit can be connected through a first bottom gate connection line. The present example can set the threshold voltage of the oxide transistor which independently affects the long-time-on state through the first voltage line BG1, and can improve the stability of the transistor.

[0256] In the present example, the bottom gates of the ninth N-type transistor Tn_9, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4 and the sixth N-type transistor Tn_6 of any stage shift register circuit are connected through a third bottom gate connection line, and can also be connected with the second voltage line BG2 located in the left area of the fifth conductive layer through a second bottom gate connection line. The third bottom gate connection line can pass through the middle positions of the second NOR gate circuit and the third transmission gate circuit, and can also pass through the middle positions of the second transmission gate circuit and the first NOT gate circuit. The present example can set the threshold voltage of the oxide transistor which independently affects the long-time-off state through the second voltage line BG2, and can improve the stability of the transistor.

[0257] In the present example, the bottom gates of the oxide transistors are arranged in the second conductive layer. On the premise of ensuring that the bottom gates of the corresponding transistors are connected to the same signal, the oxide transistors can be connected through horizontal wiring, which can avoid layer switching connection in the fourth conductive layer, reduce parasitic capacitance between the oxide transistors and other wirings (such as the wirings in the fifth conductive layer), and can also avoid winding and reduce the length of the wirings.

[0258] In some examples, when the display substrate forms the shift register circuit, the pixel circuit can be formed in the display area. For example, the first semiconductor layer of the display area can include the active layer of the P-type transistor of the pixel circuit, the first conductive layer of the display area can include the gate of the P-type transistor of the pixel circuit and the first plate of the storage capacitor, the second conductive layer of the display area can include the second plate of the storage capacitor and the bottom gate of the N-type transistor of the pixel circuit, the second semiconductor layer of the display area can include the active layer of the N-type transistor of the pixel circuit, the third conductive layer of the display area can include the top gate of the N-type transistor of the pixel circuit, the fourth conductive layer of the display area can include at least the connection electrodes of the plurality of transistors of the pixel circuit, and the fifth conductive layer of the display area can include at least the data line and the power line connected with the pixel circuit. The present embodiment is not limited thereto.

[0259] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can be a single-layer structure, or a multi-layer composite structure such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can adopt any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The sixth insulating layer and the seventh insulating layer can adopt an organic material such as polyimide, acrylic or polyethylene terephthalate. However, the present embodiment is not limited thereto.

[0260] The structure shown in the present example embodiment and the preparation process thereof are merely exemplary. In some example embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs. The preparation process of the present example embodiment can be realized by using the currently mature preparation equipment, can be well compatible with the related preparation process, the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.

[0261] The display substrate provided by the present example embodiment can save the space occupied by the shift register circuit through the layout design of the shift register circuit on the basis of realizing local refresh, and is conducive to realizing a narrow-frame display substrate.

[0262] FIG. 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in FIG. 19, the present embodiment provides a display device 91, which comprises a display substrate 910. The display substrate 910 is the display substrate provided by the foregoing embodiments. The display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate or a Mini-LED display substrate. The display device 91 can be an OLED display device, a watch, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator or any product or component having a display function. However, the present embodiment is not limited thereto.

[0263] In the description of the specification, the description using the terms "one embodiment", "some embodiments", "an example", "some examples" or the like means that the particular feature, structure, material or characteristic following the term is included in at least one embodiment or example of the application. The illustrative appearances of the above terms in various places in the specification are not necessarily referred to the same embodiment or example. Also, the particular features, structures, materials or characteristics can be combined in any suitable manner in one or more embodiments or examples. Furthermore, in non-contradictory relation to each other, those skilled in the art can combine and combine the features described in the specification of different embodiments or examples and the features of different embodiments or examples.

[0264] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be interpreted as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above-described embodiments within the scope of the present application.

Claims

1. A display substrate, comprising: A substrate and a gate drive circuit disposed on the substrate, the gate drive circuit comprising a plurality of cascaded shift register circuits, each shift register circuit comprising: a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors comprising at least one oxide transistor; The bottom gate and the top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and the top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal; The bottom gate and the top gate of each oxide transistor in the second group of oxide transistors are independent of each other. 2.The display substrate of claim 1, wherein, The second group of oxide transistors comprises a plurality of oxide transistors, and the bottom gates of the plurality of oxide transistors in the second group of oxide transistors are connected to the same voltage line. 3.The display substrate of claim 1, wherein, The second group of oxide transistors comprises an oxide output transistor and a plurality of oxide switch transistors; the oxide output transistor is directly connected to the output end of the shift register circuit; The bottom gate of the oxide output transistor is independently arranged from the bottom gates of the plurality of oxide switch transistors; The bottom gates of at least some of the plurality of oxide switch transistors are connected to the same voltage line. 4.The display substrate of claim 3, wherein, The plurality of oxide switch transistors in the second group of oxide transistors are divided into a first group of oxide switch transistors and a second group of oxide switch transistors, each group of oxide switch transistors comprising at least one oxide switch transistor; within a frame duration, the duty cycle of the first potential of the top gate voltage signal of the oxide switch transistors in the first group of oxide switch transistors is greater than the duty cycle of the first potential of the top gate voltage signal of the oxide switch transistors in the second group of oxide switch transistors; The bottom gate of at least one oxide switch transistor in the first group of oxide switch transistors is connected to a first voltage line; The bottom gate of at least one oxide switch transistor in the second group of oxide switch transistors is connected to a second voltage line; The first voltage line and the second voltage line are configured to provide different voltage signals. 5.The display substrate of claim 4, wherein, Each group of oxide switch transistors comprises a plurality of oxide switch transistors; the bottom gates of at least some of the plurality of oxide switch transistors in the first group of oxide switch transistors are a unitary structure, and the bottom gates of the plurality of oxide switch transistors in the second group of oxide switch transistors are a unitary structure. 6.The display substrate of claim 1, wherein, In a direction perpendicular to the display substrate, the display substrate comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate; The top gates of the plurality of oxide transistors are located in the third conductive layer, the active layers of the plurality of oxide transistors are located in the second semiconductor layer, and the bottom gates of the plurality of oxide transistors are located in the second conductive layer. 7.The display substrate of claim 1, wherein, The shift register circuit comprises: an input shift circuit, a transmission control circuit, and a drive enhancement circuit; The input shift circuit is connected with the first clock end, the second clock end, the third clock end, the fourth clock end, the input end of the shift register circuit, the reset control end, the first intermediate node and the second intermediate node respectively, and is configured to control the potentials of the first intermediate node and the second intermediate node under the control of the first clock end, the second clock end, the third clock end, the fourth clock end, the input end of the shift register circuit and the reset control end. The transmission control circuit is connected with the first intermediate node, the second intermediate node, the enable control end and the drive enhancement circuit respectively, and is configured to provide an output signal to the drive enhancement circuit under the control of the first intermediate node, the second intermediate node and the enable control end. The drive enhancement circuit is connected between the transmission control circuit and the output end of the shift register circuit, and is configured to output the output signal provided by the transmission control circuit to the output end of the shift register circuit after at least one inversion processing. The input shift circuit, the transmission control circuit and the drive enhancement circuit are arranged in the first direction along the orthographic projection of the substrate in sequence. The input shift circuit comprises a first NOR gate circuit, a first NOT gate circuit, a first transmission gate circuit and a second transmission gate circuit. 8.The display substrate of claim 7, wherein, The first transmission gate circuit is connected with the first clock end, the second clock end, the input end of the shift register circuit and the input node, and is configured to control the on-off of the input end of the shift register circuit and the input node under the control of the first clock end and the second clock end. The second transmission gate circuit is connected with the third clock end, the fourth clock end, the input node and the second intermediate node, and is configured to control the on-off of the input node and the second intermediate node under the control of the third clock end and the fourth clock end. The first NOR gate circuit is connected with the input node, the reset control end and the first intermediate node, and is configured to control the potential of the first intermediate node under the control of the input node and the reset control end. The first NOT gate circuit is connected between the first intermediate node and the second intermediate node. The first transmission gate circuit, the second transmission gate circuit and the first NOT gate circuit are arranged in the second direction along the orthographic projection of the substrate in sequence and are located between the orthographic projection of the first NOR gate circuit and the transmission control circuit in the first direction; the second direction intersects the first direction. The first transmission gate circuit comprises a first P-type transistor and a first N-type transistor; the gate of the first P-type transistor is connected with the second clock end; the top gate and the bottom gate of the first N-type transistor are connected and connected with the first clock end; the first pole of the first P-type transistor and the first pole of the first N-type transistor are connected with the input end of the shift register circuit, and the second pole of the first P-type transistor and the second pole of the first N-type transistor are connected with the input node. 9.The display substrate of claim 8, wherein, ​ The second transmission gate circuit comprises a fifth P-type transistor and a fifth N-type transistor; a gate of the fifth P-type transistor is connected with the fourth clock end; a top gate and a bottom gate of the fifth N-type transistor are connected and connected with the third clock end; a first pole of the fifth P-type transistor and a first pole of the fifth N-type transistor are connected with the input node, and a second pole of the fifth P-type transistor and a second pole of the fifth N-type transistor are connected with the second intermediate node; The first P-type transistor and the first N-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate; the fifth P-type transistor and the fifth N-type transistor are arranged in alignment along the first direction in the orthographic projection of the substrate; The first P-type transistor and the fifth P-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate; the first N-type transistor and the fifth N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate. 10.The display substrate of claim 8, wherein, The transmission control circuit comprises a second NOR gate circuit, a third transmission gate circuit and a capacitor; The third transmission gate circuit is connected with the first intermediate node, the second intermediate node, the enable control end, a first input end of the second NOR gate circuit and the capacitor, and is configured to control the enable control end and the first input end of the second NOR gate circuit in the control of the first intermediate node and the second intermediate node; A second input end of the second NOR gate circuit is connected with the second intermediate node, and an output end of the second NOR gate circuit is connected with the drive enhancement circuit; The second NOR gate circuit and the third transmission gate circuit are arranged in sequence along the second direction in the orthographic projection of the substrate, and the third transmission gate circuit is located between the capacitor and the first NOR gate circuit in the orthographic projection of the substrate in the first direction. 11.The display substrate of claim 10, wherein, The drive enhancement circuit comprises a second NOR gate circuit, a third NOR gate circuit and a fourth NOR gate circuit connected in sequence; the second NOR gate circuit, the third NOR gate circuit and the fourth NOR gate circuit are arranged in sequence along the first direction in the orthographic projection of the substrate; The second NOR gate circuit is adjacent to the capacitor in the orthographic projection of the substrate in the second direction, and the capacitor is located between the third transmission gate circuit and the third NOR gate circuit in the orthographic projection of the substrate in the first direction. 12.The display substrate of claim 11, wherein, The first or non-gate circuit comprises a second P-type transistor, a third P-type transistor, a second N-type transistor and a third N-type transistor; the gate of the third P-type transistor and the top gate of the third N-type transistor are connected with the reset control end, the gate of the second P-type transistor and the top gate of the second N-type transistor are connected with the input node, the first pole of the third P-type transistor is connected with the first power supply end, the second pole of the third P-type transistor is connected with the first pole of the second P-type transistor, the second pole of the second P-type transistor, the second pole of the second N-type transistor and the second pole of the third N-type transistor are connected with the first intermediate node, the first pole of the second N-type transistor and the first pole of the third N-type transistor are connected with the second power supply end; The second or non-gate circuit comprises a seventh P-type transistor, an eighth P-type transistor, a seventh N-type transistor and an eighth N-type transistor; the gate of the eighth P-type transistor and the top gate of the eighth N-type transistor are connected with the third transmission gate circuit, the gate of the seventh P-type transistor and the top gate of the seventh N-type transistor are connected with the second intermediate node, the first pole of the eighth P-type transistor is connected with the first power supply end, the second pole of the eighth P-type transistor is connected with the first pole of the seventh P-type transistor, the second pole of the seventh P-type transistor, the second pole of the seventh N-type transistor and the second pole of the eighth N-type transistor are connected, as the output end of the second or non-gate circuit, the first pole of the seventh N-type transistor and the first pole of the eighth N-type transistor are both connected with the second power supply end; The third transmission gate circuit comprises a sixth P-type transistor and a sixth N-type transistor, the gate of the sixth P-type transistor is connected with the second intermediate node, the top gate of the sixth N-type transistor is connected with the first intermediate node, the first pole of the sixth P-type transistor and the first pole of the sixth N-type transistor are connected with the enable control end, the second pole of the sixth P-type transistor and the second pole of the sixth N-type transistor are connected with the gate of the eighth P-type transistor of the second or non-gate circuit; The first non-gate circuit comprises a fourth P-type transistor and a fourth N-type transistor, the gate of the fourth P-type transistor and the top gate of the fourth N-type transistor are connected with the first intermediate node, the first pole of the fourth P-type transistor is connected with the first power supply end, the second pole of the fourth P-type transistor and the second pole of the fourth N-type transistor are connected with the second intermediate node, the first pole of the fourth N-type transistor is connected with the second power supply end; The second non-gate circuit comprises a ninth P-type transistor and a ninth N-type transistor, the gate of the ninth P-type transistor and the top gate of the ninth N-type transistor are connected with the output end of the second or non-gate circuit, the first pole of the ninth P-type transistor is connected with the first power supply end, the first pole of the ninth N-type transistor is connected with the second power supply end, the second pole of the ninth P-type transistor and the second pole of the ninth N-type transistor are connected, as the output end of the second non-gate circuit; The third NOT gate circuit comprises a tenth P-type transistor and a tenth N-type transistor, a gate of the tenth P-type transistor and a top gate of the tenth N-type transistor are connected with an output end of the second NOT gate circuit, a first pole of the tenth P-type transistor is connected with a first power supply end, a first pole of the tenth N-type transistor is connected with a second power supply end, a second pole of the tenth P-type transistor and a second pole of the tenth N-type transistor are connected, and the second pole of the tenth P-type transistor and the second pole of the tenth N-type transistor are connected as an output end of the third NOT gate circuit. Bottom gates of the second N-type transistor, the seventh N-type transistor, the eighth N-type transistor and the tenth N-type transistor are connected with a first voltage line. Bottom gates of the third N-type transistor, the fourth N-type transistor, the sixth N-type transistor and the ninth N-type transistor are connected with a second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals. 13.The display substrate of claim 12, wherein, The bottom gates of the second N-type transistor, the seventh N-type transistor and the eighth N-type transistor of any stage of the shift register circuit are in an integrated structure. 14.The display substrate of claim 13, wherein, The bottom gate of the tenth N-type transistor of the n-th stage of the shift register circuit is connected with the bottom gates of the second N-type transistor, the seventh N-type transistor and the eighth N-type transistor of the n+1-th stage of the shift register circuit through a first bottom gate connecting line; the first bottom gate connecting line is in a polyline shape extending along the first direction in the orthographic projection of the substrate, and is located between the orthographic projections of the n-th stage of the shift register circuit and the n+1-th stage of the shift register circuit; n is a positive integer. 15.The display substrate of claim 12, wherein, The bottom gates of the third N-type transistor and the fourth N-type transistor of any stage of the shift register circuit are in an integrated structure, and the integrated structure is connected with the bottom gates of the sixth N-type transistor and the ninth N-type transistor of the shift register circuit through a third bottom gate connecting line. The third bottom gate connecting line is in a polyline shape extending along the first direction in the orthographic projection of the substrate, and is located between the orthographic projections of the third transmission gate circuit and the second NOT gate circuit of the shift register circuit, and between the orthographic projections of the second transmission gate circuit and the first NOT gate circuit. 16.The display substrate of claim 12, wherein, The orthographic projections of the third P-type transistor, the second P-type transistor and the second N-type transistor along the second direction are arranged in a stepped shape, and the orthographic projections of the second N-type transistor and the third N-type transistor along the second direction are arranged in alignment. The orthographic projections of the third N-type transistor and the fourth N-type transistor along the first direction are arranged in alignment; the orthographic projection of the fourth P-type transistor in the first direction is located on a side of the fourth N-type transistor away from the orthographic projection of the third N-type transistor in the first direction. 17.The display substrate of claim 12, wherein, The orthographic projections of the sixth N-type transistor and the sixth P-type transistor along the first direction are arranged in alignment. The orthographic projections of the seventh N-type transistor and the eighth N-type transistor along the first direction are arranged in alignment. The sixth N-type transistor and the seventh N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate, and the sixth P-type transistor and the eighth N-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate; The seventh P-type transistor and the eighth P-type transistor are arranged in sequence along the first direction in the orthographic projection of the substrate. 18.The display substrate of claim 12, wherein, The ninth P-type transistor and the tenth N-type transistor are arranged in sequence along the first direction in the orthographic projection of the substrate; The ninth N-type transistor and the ninth P-type transistor are arranged in misalignment along the second direction in the orthographic projection of the substrate; The tenth N-type transistor and the tenth P-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate.

19. The display substrate of claim 12, wherein, The fourth non-gate circuit comprises an eleventh N-type transistor and an eleventh P-type transistor; a gate of the eleventh P-type transistor and a top gate of the eleventh N-type transistor are connected to an output end of the third non-gate circuit, a first pole of the eleventh P-type transistor is connected to a first power supply end, a first pole of the eleventh N-type transistor is connected to a second power supply end, and a second pole of the eleventh P-type transistor and a second pole of the eleventh N-type transistor are connected to an output end of the shift register circuit; A bottom gate of the eleventh N-type transistor is connected to a third voltage line; The eleventh N-type transistor and the eleventh P-type transistor are arranged in alignment along the second direction in the orthographic projection of the substrate; The eleventh N-type transistor and the tenth P-type transistor are adjacent in the first direction in the orthographic projection of the substrate, and the eleventh P-type transistor and the tenth N-type transistor are adjacent in the first direction in the orthographic projection of the substrate. 20.The display substrate of claim 19, wherein, The first voltage line, the second voltage line, and the third voltage line are located in the same conductive layer; The third voltage line is located on a side of the eleventh N-type transistor away from the tenth P-type transistor in the first direction in the orthographic projection of the substrate; The first voltage line and the second voltage line are located on a side of the input shift circuit away from the transmission control circuit in the first direction in the orthographic projection of the substrate.

21. A display device, the display substrate of any one of claims 1 to 20.

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