Spatially tunable deposition to compensate in wafer differential bending

Abstract

A plasma processing chamber for depositing a film on an underside surface of a wafer includes a showerhead susceptor. The showerhead base includes a first partition and a second partition. An upper separator fin is disposed above the top surface of the showerhead base, and a lower separator fin is disposed below the top surface of the showerhead base and aligned with the upper separator fin. The first partition is configured for depositing a first film to an underside surface of the wafer, and the second partition is configured for depositing a second film to the underside surface of the wafer. In another embodiment, the top surface of the showerhead base may be configured to receive a masking plate rather than an upper separator fin. The masking plate is provided with a first region having an opening and a masked second region. The first region is used to provide a process gas to a portion of the underside surface of the wafer for depositing a film.

Description

This application is a divisional application of application number 202080058049.6, filed on August 6, 2020, entitled "Spatial Adjustable Deposition for Compensation in Wafer Differential Bending". Technical Field

[0001] This embodiment relates to semiconductor wafer processing equipment and tools, and more specifically, to a chamber having a nozzle for performing backside deposition to counteract wafer bending caused by layers formed on the top side. Background Technology

[0002] Various thin film layers are deposited onto the top surface of a wafer (i.e., a substrate) to form a semiconductor device. These thin film layers can be formed using known deposition processes such as chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD). CVD is a type of deposition in which the wafer (i.e., the substrate) is exposed to one or more volatile precursors. These volatile precursors react and / or decompose on the substrate surface to form a thin film. PECVD is a type of chemical vapor deposition used to deposit a thin film from a gaseous state (i.e., vapor) onto a solid state on a substrate. In PECVD, liquid precursors are converted into vapor precursors and then transported to a chamber. A PECVD system may include an evaporator that evaporates liquid precursors in a controlled manner to produce vapor precursors.

[0003] Typically, most deposition and other processes for forming semiconductor devices occur on the top surface (i.e., the front side) of the substrate. As thin film layers form, they introduce internal stresses into the substrate. These internal stresses are caused by differences in the chemical properties of the process gases used to form the thin film layers. As more thin film layers are deposited, the internal stresses increase. The cumulative internal stresses of different thin films deposited on the substrate and the mismatch in the coefficients of thermal expansion (CTE) of the different thin film layers can lead to substrate warping (i.e., bending). Substrate warping is widely considered to be convex or concave. However, in some cases, the warp can be saddle-shaped. This warping is detrimental because it makes subsequent substrate processes more difficult.

[0004] Stress compensation is required to mitigate the adverse effects of bending. One method for compensating for stress and mitigating the adverse effects of bending is to deposit a film on the back side of the substrate to counteract the bending caused by the film on the front side (i.e., the top side) and the internal stress in the substrate caused by the different films. Depositing the film on the back side requires flipping the substrate and loading it with the back side facing up. Flipping the wafer can cause additional problems, such as additional handling, potential particle exposure, and / or reduced process yield.

[0005] Traditional techniques use edge shadowing rings to mask edges and prevent exposure to particles. These edge shadowing rings are inherently static and cannot be changed. Furthermore, these edge shadowing rings only target the edge region and do not affect the substrate beyond the outer edge region. Another conventional technique used is standard patterning. However, standard patterning processes are very time-consuming and require numerous operations.

[0006] The invention arose in this context. Summary of the Invention

[0007] Embodiments of this disclosure provide systems and methods for depositing thin films on the underside (i.e., backside) surface of a substrate to counteract substrate warping caused by depositing a thin film on the topside surface of the substrate. The systems and methods disclosed herein include a lower electrode nozzle (or simply referred to herein as a "lower nozzle," "nozzle base," or "ShoPed") with multiple regions disposed at the bottom of a processing chamber. The ShoPed includes masking features to define different regions. Each different region is connected to a separate gas source and interfaces with a different set of outlets defined on the top surface of the ShoPed. Process gases supplied through the different sets of outlets are used to generate different plasmas to deposit thin films in different sectors defined on the underside surface of the wafer, wherein the different sectors correspond to specific areas covered by the respective set of outlets. In an alternative embodiment, a mask plate with a precise, defined shape and coverage area is disposed on the top surface of the ShoPed. The ShoPed with the mask plate disposed thereon can be a zonal showerhead or a conventional nozzle. The mask plate allows for the deposition of different thin films in a defined pattern, covering the different sectors defined on the underside surface of the substrate.

[0008] The use of masking plates and / or partitioned nozzles allows for the deposition of different films in specific predefined regions (i.e., specific sectors) on the underside surface of the wafer. The process gas used for depositing the film on the underside surface of the substrate is selected based on its tensile or compressive properties. The combination of film thickness, gas properties used to form the film (e.g., stress, tensile, or compressive properties), and the order in which different films are applied in different sectors helps to tune the stress on the backside of the substrate to compensate for substrate deformation (i.e., bending) experienced due to film deposition on the top surface of the substrate. Stress tuning helps to improve device yield.

[0009] In one embodiment, a nozzle base (ShoPed) for depositing a film on the underside surface of a wafer in a plasma processing chamber is disclosed. The ShoPed includes a first section and a second section. An upper separator fin is disposed above the top surface of the ShoPed, and a lower separator fin is disposed below the top surface of the ShoPed and aligned with the upper separator fin. The first section is configured to deposit a first film onto the underside surface of the wafer, and the second section is configured to deposit a second film onto the underside surface of the wafer.

[0010] In another embodiment, a nozzle base (ShoPed) for depositing a film on the underside surface of a wafer in a plasma processing chamber is disclosed. The ShoPed includes a chamber (plenum) defined therein for receiving a volume of process gas. An outlet assembly is defined on the top surface of the ShoPed and configured to interface with the internal chamber to provide process gas for film deposition. A mask is disposed on the top surface of the ShoPed. The mask includes a first region with an opening and a masked second region. The first region of the mask is configured to provide process gas to a portion of the underside surface of the wafer for film deposition.

[0011] Other aspects of the invention will become apparent from the following detailed description of the principles of the invention illustrated by way of example and in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1 A simplified block diagram of a wafer processing system configured for back-side wafer deposition according to some embodiments is shown.

[0013] Figure 2 A top view of a multi-station processing tool according to one embodiment is shown, in which four processing stations are provided, each configured for back-side wafer deposition.

[0014] Figure 3 A schematic diagram of an embodiment of a multi-station processing tool having an inbound loading lock and an outbound loading lock is shown.

[0015] Figure 4A A simplified schematic diagram of a nozzle base identifying sectors according to one embodiment is shown, where a sector represents a different partition designed for selectively depositing thin films on different regions defined on the lower surface of a wafer.

[0016] Figure 4B An embodiment is shown. Figure 4A The cross-sectional view of section AA of the nozzle base marked in the middle.

[0017] Figure 4C An embodiment is shown. Figure 4A The cross-sectional view of the nozzle base BB marked in the middle.

[0018] Figure 4D An enlarged view is shown of the geometry of the upper separator fins for defining the various sections on the nozzle base, as provided relative to a substrate, according to one embodiment.

[0019] Figure 4E A cross-sectional view along the upper and lower separator fins defined in the nozzle base is shown according to one embodiment.

[0020] Figure 4F A schematic diagram of the interior of a nozzle base according to one embodiment is shown, illustrating the location of the upper separator fins, the lower separator fins, and the inner plenum defined by the lower separator fins.

[0021] Figure 4G-1 A perspective view of the internal chambers formed in different sections of the nozzle base according to one embodiment is shown.

[0022] Figure 4G-2 A simplified schematic diagram of an internal chamber with a corresponding process gas supply according to one embodiment is shown.

[0023] Figure 4G-3 A schematic diagram is shown of a first internal chamber defined in a first partition according to one embodiment, together with a first gas supply for supplying a first process gas to the first internal chamber.

[0024] Figure 4G-4 A schematic diagram is shown of a second internal chamber defined in a second partition according to one embodiment, together with a second gas supply for supplying a second process gas to the second internal chamber.

[0025] Figure 4H The surface profile of an alternative nozzle base for use in a chamber, according to one embodiment, is shown for performing selective deposition on the underside surface of a substrate.

[0026] Figure 4I An embodiment is shown. Figure 4H The cross-sectional view of section CC marked in the figure.

[0027] Figure 4J An embodiment is shown. Figure 4H The cross-sectional view of section DD as indicated in the figure.

[0028] Figure 4KA top view of the top surface of a nozzle base according to one embodiment is shown, wherein outlets with different outlet densities and outlet sizes are distributed along the top surface to increase hollow cathode discharge (HCD) in different zones.

[0029] Figure 5A A simplified schematic diagram of a plasma processing system with a lower electrode nozzle according to an alternative embodiment is shown. The lower electrode nozzle includes a mask plate having different regions defined thereon for selectively depositing thin films in different portions of the lower surface of a wafer.

[0030] Figure 5B-1 and 5B-2 A top view of a masking plate with different regions is shown according to one embodiment, which are selectively activated or masked when used at two different stations to allow selective film deposition.

[0031] Figure 5C An enlarged view of the edge of a nozzle base with a spacer according to one embodiment is shown, the spacer providing substrate support to receive a carrier ring with a substrate.

[0032] Figure 6 A control module for a control system according to one embodiment is shown. Detailed Implementation

[0033] The embodiments of this disclosure provide embodiments of a processing chamber for processing semiconductor wafers. In one embodiment, the chamber is configured with a lower electrode nozzle configuration such that back-side deposition can counteract wafer bending and / or stress when more layers are formed on the top side of the substrate.

[0034] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially fabricated integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “partially fabricated integrated circuit” can refer to a silicon wafer during any of the many stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 or 300 mm, but substrates with a diameter of 450 mm or greater, or less than 200 mm, are also conceivable. The description herein uses the terms “front” or “top” side and “back” or “bottom” side to describe different sides of a wafer that may be exposed to one or more process gases during deposition or etching. It will be understood that the front side or top side is where most deposition and processing occurs, and where the semiconductor device itself is fabricated. The back side or bottom side is the reverse side of the wafer, which typically undergoes minimal or no processing during fabrication.

[0035] Multi-stage semiconductor processing for manufacturing advanced memory and logic chips has resulted in significant substrate bending in both compression and stretch directions. Deformation of the wafer surface can be attributed to the compressive and / or stretching properties of films deposited on the wafer surface. This substrate bending (moderate to severe) affects processing conditions for various manufacturing processes, leading to process control issues, lithography chuck problems, and overlay issues, which can sometimes result in increased yield losses.

[0036] According to one embodiment, one way to address bending is to deposit one or more sacrificial films on the back side of the wafer to compensate for bending on the front side, resulting in a substantially flat wafer. The amount and type of material used in the sacrificial film, and the location of the sacrificial film deposition on the underside, can vary depending on the amount and type of material and the location of the film deposition on the front side. Conventional PECVD systems have a gas-flowing electrode that can be powered by radio frequency (RF) or grounded. Typically, the gas-flowing electrode (also called the upper electrode nozzle or simply upper electrode 104) is positioned at the top of the PECVD system, causing the reactants to generate plasma on the front or top side of the wafer, resulting in film deposition only on the front or top side of the wafer. However, to address the bending problem, the sacrificial film must be formed on the back or underside surface of the wafer. To form a sacrificial film on the back side of the wafer, plasma for depositing the sacrificial film must be formed on the back side (i.e., the underside surface) of the substrate.

[0037] According to one embodiment, a deposition system (e.g., a PECVD system) is disclosed that addresses this difference by including dual gas flow electrodes. One gas flow electrode is defined at the top of the chamber, and a second gas flow electrode is defined at the bottom and oriented relative to the top gas flow electrode (also referred to herein as the “upper nozzle” or “upper electrode”). Either electrode can be an RF electrode to provide an AC field capable of generating plasma for film (e.g., CVD film) deposition. This dual gas flow electrode PECVD system is configured to selectively deposit films only on the top surface of the wafer, or only on the lower surface, or on both the top and lower surfaces of the wafer. In an exemplary embodiment, the lower gas flow electrode (referred herein to as the “lower electrode nozzle” or simply the “lower nozzle”, “nozzle base”, or “ShoPed”) can be part of a multi-station chamber or a single-station chamber. Thus, the ShoPed includes a wafer support for receiving and holding a carrier ring with the wafer transferred to one station of the chamber or multi-station chamber. The ShoPed is connected to a first process gas source via a first gas supply for receiving a first process gas, and to a second process gas source via a second gas supply for receiving a second process gas. The upper nozzle is connected to a third process gas source via a third gas supply for receiving a third process gas.

[0038] In one implementation, the back-side process gas flow enables PECVD deposition on the back side of the wafer, while the front-side process gas flow enables deposition on the front side of the wafer. The system can be configured to selectively enable the deposition side by turning on and off gas supplies connected to the respective process gas sources that result in film deposition on a particular side. For example, if the back side of the wafer must undergo deposition, the gas supply(s) providing one or more process gases to the back side of the wafer is turned on, and the gas supply providing process gases to the front side of the wafer is turned off. In some implementations, the side not actively treated with plasma can alternatively be treated with a non-reactive gas (e.g., an inert gas). In such an implementation, the gas supply used to supply process gases to the non-processed side during deposition on the treated side can alternatively be connected to a non-reactive gas source (e.g., an inert gas source). In the above example where the back side of the wafer is treated with one or more process gases, the gas supply to the front side of the wafer can be connected to an inert gas source to allow inert gas to be supplied to the front side when process gases are supplied to the back side of the wafer. This prevents byproducts escaping from the front side from reaching the back side and adhering to the back side surface. Another aspect of the system is the ability to control the distance between the substrate side and the reactant flow gas and / or to confine (one or more) process gases within the corresponding plasma processing region. This control enables the achievement of the required deposition profile and film properties for applications such as backside compensation.

[0039] The ShoPed and the upper nozzle include a configuration providing nozzle-like features that allow for proper mixing of reactive gases and appropriate application of suitable hydrodynamics to perform PECVD deposition processes on the back or front side of the wafer. Furthermore, some embodiments implement a controllable gap that can suppress or allow plasma on a desired side (one or both sides) of the wafer for deposition. The controlled gap can include, for example, the gap spacing between the top side of the wafer and the bottom surface of the upper nozzle 104, and the gap spacing between the back side of the wafer and the top surface of the ShoPed 106. For example, when the back side of the wafer is being deposited, the gap between the top side of the wafer and the bottom surface of the upper nozzle can be adjusted to a minimum to prevent plasma formation. For example, this gap can be between approximately 0.5 mm and approximately 2 mm, and in another embodiment, between approximately 0.5 mm and approximately 1 mm (depending on wafer bending constraints).

[0040] ShoPed 106 is also configured to include a nozzle exit pattern and internal chambers for either uniform gas distribution (i.e., allowing process gases to be delivered to the bottom of the wafer) or differential gas distribution. Implementations also allow the gas-flowing pedestal (i.e., ShoPed) to have an active heater to bring the process gases to the appropriate temperature. The combination of ShoPed 106 and nozzle 104 allows both key properties to function simultaneously. In one implementation, ShoPed 106 can still heat the wafer and provide wafer transfer features within the multi-station reaction chamber, or from inside the reaction chamber to outside the reaction chamber, or from outside the reaction chamber to inside the reaction chamber, while the nozzle 104 assembly allows process gases to flow for deposition on the top surface of the wafer. Therefore, the gas-flowing pedestal (i.e., ShoPed) disclosed herein is capable of implementing conventional PECVD processes to selectively deposit on either side of the wafer. These configurations are also configured to selectively RF power the top electrode or the bottom ShoPed and dynamically enable / disable plasma on the wafer side requiring deposition. In addition, ShoPed can be configured to selectively RF power different partitions defined within ShoPed for selective deposition on different portions defined on the underside surface of the wafer.

[0041] In summary, ShoPed offers several advantages over stress and bending problems by depositing films on the back side of the wafer. The back-side film counteracts the stress from the front-side deposition to produce a neutral stress (or essentially neutral stress, e.g., less than about + / - 150 MPa) wafer that does not exhibit bending (or essentially no bending, e.g., bending less than about 150 μm). If the film deposited on the front side is stretched, then the film used for back-side deposition should also be stretched to balance the overall stress. Similarly, if the film on the front side is compressed, then the film on the back side should also be compressed. Back-side films can be deposited through various reaction mechanisms, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), low-pressure chemical vapor deposition (LPCVD), etc. PECVD is used in various cases because a high deposition rate is achieved in this type of reaction.

[0042] Certain deposition parameters can be adjusted to produce a back-side film with the desired stress level. One of these deposition parameters is the thickness of the deposited back-side film. A thicker film will generate greater stress in the wafer, while a thinner film (with the same composition and deposited under the same conditions) will generate less stress in the wafer. Therefore, to minimize the amount of material consumed in forming the back-side layer, the layer can be deposited relatively thinly under conditions that promote the formation of a high-stress film. Another deposition parameter that can be adjusted is the number of different film layers to be deposited. The number of film layers formed on the back side can be equal to or less than the number of films deposited on the front side of the wafer, and these numbers may depend on the type of process gas used, the tensile or compressive properties of the film, the thickness of each film layer, and the overall stress to be alleviated.

[0043] As described above, the stacking of deposited materials can particularly lead to wafer stress and bending. One example stack that may cause these problems is a stack with alternating oxide and nitride layers (e.g., silicon oxide / silicon nitride / silicon oxide / silicon nitride, etc.). Another example stack that may cause bending includes alternating oxide and polysilicon layers (e.g., silicon oxide / polysilicon / silicon oxide / polysilicon, etc.). Other examples of potentially problematic stacking materials include, but are not limited to, tungsten and titanium nitride. Materials in the stack can be deposited using chemical vapor deposition techniques or by methods such as direct metal deposition (DMD), including plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and plasma-enhanced atomic layer deposition (PEALD). These examples are not intended to be limiting. Certain disclosed embodiments may be useful whenever wafer stress and / or bending are caused by materials present on the positive side of the wafer.

[0044] Front-side stacking can be deposited to any number of layers and thickness. In typical examples, the stack comprises approximately 32 to approximately 72 layers and has a total thickness of approximately 2 μm to approximately 4 μm. The stress caused by the stack in the wafer can range from approximately -500 MPa to approximately +500 MPa, resulting in bending typically between approximately 200 and 400 μm (for a 300 mm wafer), and in some cases even greater.

[0045] In some implementations, the back-side layer can be removed after further processing. In this case, the composition of the film deposited on the back side is selected such that it can be easily removed from the substrate at an appropriate time. In this regard, there should be a high selectivity between the material of the back-side layer (e.g., dielectric) and the material of the underlying substrate (e.g., silicon) among the chemicals to be removed.

[0046] The optimal thickness of the back-side layer will depend on the amount of stress caused by deposition on the front side of the wafer, and the deposition conditions of the back-side layer. The back-side layer can be deposited to a thickness where the stress in the wafer becomes negligible (e.g., less than about 150 MPa). The thickness of the deposited back-side layer can be controlled to keep wafer bending within a negligible range (e.g., less than about 150 μm of bending). In some cases, this corresponds to a back-side layer thickness between about 0.1 and 2 μm (e.g., between about 0.3 and 2 μm, or between about 0.1 and 1 μm, or between about 0.3 and 1 μm). In the case of using silicon nitride to form the back-side layer, a film with a thickness of about 0.3 μm is sufficient to mitigate bending of about 50–200 μm. As mentioned above, a higher stress back-side layer can be selected to reduce the required layer thickness. This helps to save material and reduce costs. More information on back-side deposition techniques can be found in U.S. Patent Application No. 14 / 285,554, owned by the same assignee as this application and incorporated herein by reference. For further details regarding the use of dual-flow electrodes and for some reference regarding the composition of the film formed on the lower surface of the substrate, see U.S. Patent Application No. 15 / 692,300, which is assigned to the same assignee as this invention and is incorporated herein by reference.

[0047] It should be understood that this implementation scheme can be implemented in various ways, such as processes, apparatus, systems, equipment, or methods. Several implementation schemes are described below.

[0048] In one embodiment, film deposition is performed in a plasma-enhanced chemical vapor deposition (PECVD) system. PECVD systems can take many different forms. A PECVD system includes one or more plasma processing chambers or "reactors" (sometimes including multiple stations) that contain one or more wafers and are suitable for wafer processing. Each chamber can contain one or more wafers for processing. The one or more chambers hold the wafers in one or more defined locations (with or without movement, such as rotation, vibration, or other agitation). During processing, the wafer undergoing deposition can be transferred from one station to another within the plasma processing chamber. Of course, film deposition can occur entirely at a single station, or any portion of the film can be deposited at any number of stations.

[0049] During processing, each wafer is held in place by a base, wafer chuck, and / or other wafer holding device. For some operations, this device may include a heater, such as a heating plate, to heat the wafer.

[0050] Figure 1 A substrate processing system 100 for processing wafer 101 is shown. The system includes a plasma processing chamber 102. In one embodiment, the plasma processing chamber (or simply "chamber" herein) 102 is a single-station chamber, such as... Figure 1 As shown. In an alternative embodiment, the plasma processing chamber 102 may be a multi-station chamber, as will be referred to Figure 2 and Figure 3 Described. The bottom of chamber 102 includes a base 106. According to the embodiments disclosed herein, base 106 is referred to as a nozzle base (or simply "ShoPed") because the nozzle is defined on the top surface of the base and configured to provide process gas to the underside surface of wafer 101. A central pillar 160 is configured to support ShoPed 106. The outer edge of the top surface of ShoPed 106 includes a support surface, such as a carrier ring support region, to provide support for carrier ring 134 when received within plasma processing chamber 102. Carrier ring 134 is configured to support wafer 101 and for moving the wafer into the processing chamber for deposition and removing the wafer after deposition. Carrier ring 134 exposes the top and underside surfaces of wafer 101 for film deposition, depending on which side of wafer 101 is being processed. An upper nozzle 104 is disposed on top of plasma processing chamber 102 and oriented relative to ShoPed 106. The upper nozzle 104 is connected to a process gas source (e.g., a third process gas source 116) via a corresponding gas supply (e.g., gas supply 116a) to receive process gas (e.g., a third process gas).

[0051] In one embodiment, ShoPed 106 is electrically coupled to a first power source (e.g., a first radio frequency (RF) power source) 122 via a mating network 124, and the upper nozzle 104 is electrically coupled to a second power source (e.g., a second RF power source) 126 via a mating network 128. The first RF power source 122 and the second RF power source 126 are connected to a control module 120 (e.g., a controller) and are controlled by RF power control code defined within the controller 120 to power the upper nozzle 104 and / or ShoPed 106. In some embodiments, the controller 120 may be configured to power only ShoPed 106 instead of the upper nozzle 104 to allow film deposition in different portions of the lower surface of wafer 101. In alternative embodiments, the controller 120 may be configured to power only the upper nozzle 104 to allow film deposition only on the top surface of wafer 101. In another embodiment, the controller 120 can be configured to power both the nozzle 104 and the ShoPed 106, thereby allowing film deposition on both the top and bottom surfaces of the wafer 101.

[0052] Control module 120 is configured to operate substrate processing system 100 by executing process inputs and controlling specific process recipes for depositing films on the top or bottom surface of wafer 101. Regardless of which surface of wafer 101 is receiving the film deposition, controller module 120 sets various operational inputs for the specific process recipe, such as power levels, timing parameters, process gases, mechanical movement of wafer 101, height of wafer 101 away from ShoPed 106, film thickness, etc., and such process recipes can be based on the location where the film is to be deposited, the properties of the process gases used for film deposition (e.g., stretching or compressing properties), etc. In some embodiments, operational inputs for the process recipe for depositing a film on the bottom surface of wafer 101 (i.e., back-side deposition control) can be determined based on the process recipe for depositing a film on the top surface of wafer 101. For example, the process recipe for the top-side film can be used to manually provide operational inputs to manual setup input codes within controller 120 to determine the process recipe for back-side deposition. Alternatively, the process recipe for depositing the top-side film can be used as the setup input for a mathematical model via the model setup input code of controller 120 to determine the process recipe for controlling back-side deposition. The mathematical model can be generated and trained using a machine learning algorithm that takes the process recipe related to top-side deposition in multi-wafer processing as input. The list of operational inputs for the above process recipes is provided as an example only and should not be considered exhaustive or limiting.

[0053] In one implementation, a mathematical model is generated by first running test wafers through various deposition processes and inspecting wafers with bends to determine the factors causing the bend. The deposition processes are used to define different films on different portions of the wafer's top surface to define the device. Metrology tools are used to analyze the properties of the various films and determine the factors causing the bend. For example, this analysis can be used to identify which films cause the bend in which sector or portion, the film thickness, the tensile or compressive properties of the films causing the bend, and the amount of bend due to the deposition of different films. Metrology tools can quantify the bend using microscopes, lasers, or any other tool or method. Data collected by the metrology tools from the wafer inspection is used as input to a machine learning algorithm to generate a mathematical model. The generated model is then trained by running additional test wafers and using data from these additional test wafers. The trained model can identify characteristics of the deposited films to define specific devices (e.g., 3D NAND, memory chips, processors, etc.) and factors (thickness, location, tensile / compressive properties, etc.) that cause the bend. Therefore, in one embodiment, when a wafer is received for forming a specific type of device, a trained model can be used to identify factors causing bending of that specific type of device and perform back-side deposition before deposition on the front side of the wafer to form the device, and the back-side deposition is performed where it is expected that wafer bending will occur on the film used on the top surface. The trained model can be used to identify the type of material to be used, the thickness of the film to be deposited on the back side, the portion of the wafer back side where the film needs to be deposited, the number of film layers, etc., to compensate for bending. In another embodiment, the trained model can be used to determine what type of film needs to be formed on the back side of the wafer after how many layers of film are deposited on the front side, and perform back-side deposition multiple times to compensate for bending as the layers of the device are built on the front side. Thus, data from the model can be used at different stages of the device being built or at the beginning or at a defined period for performing back-side deposition. The model generated by the machine learning algorithm can be trained not only by inspecting a test wafer but also by inspecting a live wafer using in-situ metrology tools.

[0054] In some embodiments, the carrier ring support region on the outer edge of the ShoPed 106 may include spacers 130 uniformly distributed along the support region to allow an end effector of a robot (not shown) in the processing chamber to place a carrier ring 134 carrying a wafer 101 over the spacers 130. The carrier ring 134 includes a step-down bottom extension 134a defined along its inner radius for supporting the wafer 101. A plurality of contact supports may be defined on the bottom extension 134a for placing the wafer 101. Features defined on the spacers 130 are used to reliably receive the carrier ring 134 on the spacers 130. As will be described below, the spacers 130 are sized to provide controlled separation between the lower surface of the wafer 101 received on the carrier ring 134 and the top surface of the ShoPed 106. The dimensions of the spacers 130 further ensure controlled separation between the bottom surface (facing the wafer) of the upper nozzle 104 and the top surface of the wafer 101.

[0055] In an alternative embodiment, the edge of the ShoPed may include a lift pin mechanism (not shown) for placing and retrieving the carrier ring 134 carrying the wafer 101. The lift pin mechanism may be provided instead of the spacer 130. In this arrangement, the lift pin mechanism is used to receive the carrier ring 134 carrying the wafer 101. The lift pin mechanism includes a plurality of lift pins coupled to a lift pin controller. The lift pins may be housed within a housing defined in a peripheral region of the ShoPed 106 and may be configured to extend outward through a hole defined along the peripheral region of the ShoPed 106 to a raised position when the lift pins are activated by the lift pin controller, and to retract into the housing when the lift pins are deactivated. The lift pins may be activated when the carrier ring 134 carrying the wafer 101 is received on the ShoPed 106 and may remain activated while the lower surface of the wafer 101 must undergo deposition. When the carrier ring and wafer 101 are received or removed from the processing chamber, the activated lifting pin provides the necessary support for the end effector to place and retrieve the carrier ring 134 with wafer 101. The retrieved carrier ring 134 with wafer 101 can be moved to the next station or removed out of the processing chamber.

[0056] ShoPed 106 is designed to allow the deposition of different films in different regions on the underside surface of wafer 101. Therefore, ShoPed 106 includes a first partition and a second partition defined within ShoPed 106. The first partition 152 is connected to a first process gas source 112 via a first supply 112a and includes a first internal chamber 206a to receive a volume of first process gas from the first process gas source 112. The first process gas from the first internal chamber 206a is used to deposit a first film in a first region on the underside surface of wafer 101 corresponding to the first partition. For this purpose, the first internal chamber interfaces with a first set of outlets defined on the top surface of ShoPed 106 to allow the supply of first process gas over the first region for the deposition of the first film. The second partition 154 is connected to a second process gas source 114 via a second supply 114a and includes a second internal chamber 206b to receive a volume of second process gas from the second process gas source 114. A second process gas from the second internal chamber 206b is used to deposit a second film in a second region corresponding to the second partition on the lower surface of the wafer 101. For this purpose, the second internal chamber interfaces with a second set of outlets defined on the top surface of the ShoPed 106 to allow the supply of the second process gas over the second region for deposition of the second film.

[0057] Separator fins are provided inside and outside the ShoPed 106 to confine the first and second process gases to specific areas of the wafer 101. For example, a lower separator fin 158 is defined inside the ShoPed 106 to separate a first internal chamber of a first partition from a second internal chamber of a second partition. An upper separator fin 156 is defined on the top surface of the ShoPed 106 facing the wafer 101 and is aligned with the lower separator fin 158. The upper separator fin 156 defines the boundary between the first and second films formed on the wafer 101. (See reference...) Figures 4A-4D The geometry and location of the upper separator fins 156 will be discussed in more detail. Similarly, references will be made to... Figure 4E-4FLet's discuss the details of the separator fin 158 in more detail. The height of the upper separator fin 156 is designed to provide a film of a certain thickness. Furthermore, the height of the upper separator fin 156 is limited such that the lower surface of the wafer 101 is spaced apart from the tip of the upper separator fin 156, while still being able to confine the process gas to each region. As a result, the process gas directed to the lower surface of the wafer 101 is confined by the upper separator fin 156 to regions on the lower surface of the wafer 101 corresponding to the first and second partitions, respectively, allowing the formation of either the first or second film in each region. For example, in one embodiment where the carrier ring 134 with wafer 101 is received on the spacer 130, the height of the upper separator fin 158 can be limited to be shorter than the spacer 130, such that when wafer 101 and carrier ring 134 are received on the spacer 130, the tip of the upper separator fin 156 is below the lower surface of wafer 101, and a separation distance exists between the tip of the upper separator fin 156 and the lower surface of wafer 101. Furthermore, the upper and lower separator fins 156 allow for the simultaneous deposition of different films by providing the partitioning necessary to maintain film separation.

[0058] The support surfaces of spacers 130 provide complementary mating surfaces for any ring extensions defined within the carrier ring 134, thereby preventing the carrier ring 134 from slipping or moving when supported by the spacers 130. In one embodiment, three spacers 130 are provided. However, the embodiment is not limited to three spacers, and any number of spacers can be provided, as long as the carrier ring 134 can be supported substantially parallel to the surface of the ShoPed 106 and the spacers define the spacing to support the wafer 101 in a spaced-apart relationship with the top surface of the ShoPed 106.

[0059] The heights of the spacer 130 and the upper separator fin 156 are defined such that a separation distance exists between the lower surface of the wafer 101 and the tip of the upper separator fin 156. In another embodiment, the height of the upper separator fin 156 is defined to be equal to the height of the spacer 130. In this embodiment, a separation distance still exists between the tip of the upper separator fin 156 and the lower surface of the wafer 101, and this separation distance can be equal to the thickness of the bottom extension 134a of the carrier ring 134 receiving the wafer 101. The spacer 130 and the upper separator fin 156 provide partition separation by limiting film deposition to regions corresponding to the first and second partitions, which is optimized for deposition on the lower surface of the wafer 101. Furthermore, by controlling the operation of the ShoPed 106 and the upper nozzle 104, deposition on the top surface of the wafer 101 can be reduced when deposition occurs on the lower surface of the wafer 101.

[0060] The first gas source 112 and the second gas source 114 connected to the ShoPed 106 can be gaseous chemical supplies and / or inert gases from the facility. Depending on the type of deposition performed on the underside surface of the wafer 101, the controller 120 controls the selection and delivery of process gases from the appropriate process gas sources 112 and 114 via corresponding gas supplies 112a and 114a. The selected process gases are supplied to corresponding first or second internal chambers 206a and 206b, and are supplied from the corresponding first or second internal chambers to the space volume defined between the upper surface of the ShoPed 106 and the underside surface of the wafer 101 when the wafer 101 is resting on the spacer 130 on the ShoPed 106. In some embodiments, the controller 120 can be configured to sequentially control the delivery of the first and second process gases to deposit a first film and a second film in respective regions defined on the underside surface of the substrate. For example, controller 120 can control the delivery of a first process gas to form a first film in a first region corresponding to a first partition of ShoPed 106 on the lower surface of wafer 101. After the first film is deposited, controller 120 can control the delivery of a second process gas to form a second film in a second region corresponding to a second partition of ShoPed 106 on the lower surface of wafer 101. In an alternative embodiment, since the first and second partitions are clearly separated by upper and lower separator fins, the controller can be configured to simultaneously control the delivery of the first and second process gases to form the first and second films in corresponding regions on the lower surface of wafer 101.

[0061] During the deposition of different films on the lower surface of wafer 101, the gas supply 116a to the upper nozzle 104 can be shut off to ensure that no process gas is applied to the top surface of wafer 101 while a film is being deposited on the lower surface of wafer 101. Alternatively, the upper nozzle 104 can be used to supply an inert gas to the top side of wafer 101. The inert gas can be used to push the reactive gas used for deposition on the lower surface away from the top surface, thereby guiding the reactive gas to the lower surface of wafer 101. In this case, the gas supply 116a can be connected to an inert gas source instead of a reactant process gas source. In another embodiment, the upper nozzle can be used to deposit a film on the top side of the surface while ShoPed can be used to deposit one or more films on the lower surface of the substrate. In some embodiments, the process gas used to deposit a film on the lower surface can have the same composition and properties as the process gas used to deposit a film on the top surface. In some other embodiments, the process gas used to deposit a film on the top surface can be different from the process gas used to deposit a film on the lower surface. The operational inputs for the process formulation used to define the number of films, process gas type, film location, and / or film thickness deposited on the underside surface can be driven by the process formulation for depositing various films on the top side of wafer 101 and the characteristics of the films formed on the top side of wafer 101. The configuration of different partitions in ShoPed 106 (including size, shape profile, location, etc.) can be determined by a mathematical model based on inputs obtained from the incoming wafer, and this determination can be accomplished using machine learning algorithms, or it can be predetermined by a production line or equipment capable of in-situ metering.

[0062] Furthermore, the process gases used for depositing films on the top and bottom surfaces may be premixed or not. Appropriate valves and mass flow control mechanisms may be used in the corresponding gas supplies 112a, 114a, 116a to ensure that the correct process gases are delivered for the top and bottom surfaces during the plasma treatment phase (e.g., the deposition phase) of the deposition process. The process gases exit the chamber through an outlet (not shown). A vacuum pump (e.g., a primary or secondary mechanical dry pump and / or a turbomolecular pump) (not shown) extracts the process gases and maintains an appropriate low pressure within the reactor via a closed-loop controlled flow-limiting device (e.g., a throttle valve or swing valve). As previously mentioned, the reactor may be part of a single-station chamber or a multi-station chamber.

[0063] In one embodiment, the end effector used to move the carrier ring 134 carrying the wafer into and out of the chamber or station may be a set of spider forks (not shown). The spider forks include extension arms that are used to support the carrier ring as it moves from one station to another within the processing chamber, or to move the carrier ring into and out of the processing chamber 100.

[0064] Figure 2 A top view of the multi-station machining tool is shown, which provides four machining stations. Figure 1 The implementation scheme shows room 102, which can be Figure 2 and Figure 3 It is implemented in a multi-station processing tool, which has four chamber stations. Figure 2 and Figure 3 A top view of the chamber portion is provided (e.g., the top chamber portion is omitted for illustration), in which the spider fork 132 contacts four stations. Each spider fork 132, or fork, includes a first arm and a second arm, each arm located around a portion of each side of the ShoPed 106. In this figure, the spider forks 132 are drawn in dashed lines to indicate that they are located below the carrier ring 124. The spider forks 132 are configured to simultaneously raise and lift the carrier ring 134 from the stations (i.e., from the lower surface of the carrier ring 134) using the engagement and rotation mechanism 220, and then rotate at least one or more stations to the next position before lowering the carrier ring 134 (where at least one carrier ring supports the wafer 101), thereby allowing further plasma processing, treatment, and / or film deposition on the respective wafer 101. In one embodiment, the spider fork 132 can be used to raise the carrier ring 134 with the wafer 101 to a height such that deposition is possible on the back side of the wafer 101 while substantially preventing deposition on the top side of the wafer 101.

[0065] Figure 3 A schematic diagram of an embodiment of a multi-station processing tool with an inbound loading lock 148 and an outbound loading lock 140 is shown. A robot 142, located within an atmospheric transfer module maintained at atmospheric pressure, is configured to move a wafer 101 from a pod loaded via a pod 150 to the inbound loading lock 148 via an atmospheric port 144. The inbound loading lock 148 is coupled to a vacuum source (not shown) such that it can be evacuated when the atmospheric port 144 is closed. The inbound loading lock 148 also includes a chamber transfer port 146 interfaced with a processing chamber 102. Thus, when the chamber transfer port 146 is open, another robot (not shown) can move a wafer from the inbound loading lock 148 to the ShoPed 106 of the first processing station for processing.

[0066] exist Figure 3 In the illustrated embodiment, the depicted processing chamber 102 includes four processing stations, numbered 1 to 4. In some embodiments, the processing chamber 102 may be configured to maintain a low-pressure environment, thereby allowing the transfer of substrates between processing stations using the carrier ring 134 without experiencing vacuum disruption and / or air exposure. Figure 3Each processing station depicted is a ShoPed 106, which is configured to deliver process gas to the underside surface of wafer 101 when backside deposition is about to occur. During backside deposition, whether the wafer is lifted away from ShoPed 106 using spacers, spider forks, lifting pins, or paddles, in some embodiments, nozzle 104 may be configured to supply inert gas above the top surface of the substrate to prevent or reduce deposition on the top surface of wafer 101.

[0067] Figure 3 A spider fork 132 is also depicted for transferring wafers within processing chamber 102 and lifting wafer 101 during backside deposition. As will be described in more detail below, the spider fork 132 can also rotate and is capable of transferring wafers from one station to another. Transfer occurs by enabling the spider fork 132 to lift carrier ring 134 from its outer lower surface (carrier ring 134 then lifts the wafer), and then rotating the wafer and carrier ring 134 together to the next station. In one configuration, the spider fork 132 is made of a ceramic material to withstand high levels of heat during processing.

[0068] In other embodiments, instead of using a spider fork 132 to lift and transfer the wafer, a paddle-shaped structure can also serve the purpose of lifting and transferring the wafer. The paddles can be positioned between stations in a manner similar to that of the spider fork 132 and can function in the same way. Therefore, for ease of understanding, the reference to the spider fork 132 should be understood to also apply to the paddle configuration, which can provide controlled lifting of the wafer during back-side wafer deposition and during transfer between stations.

[0069] It should be understood that Figure 3 The illustrated implementation can also be extended to different processing tool configurations, including processing tools in which multiple multi-station processing chambers are distributed along different sides of the vacuum transfer module. In addition to the multi-station processing chambers located on different sides, the vacuum transfer module also includes one side interfaced with the inbound loading lock 148 and the other side interfaced with the outbound loading lock 140. A robotic module within the vacuum transfer module can be used to move the wafer from the inbound loading lock 148 to the processing chamber and from the processing chamber to the outbound loading lock 140. A spider fork located within the processing chamber can be used to move the wafer from one station to another within the processing chamber. It can be seen that... Figure 3 The configuration of the machining tool described is just an example, and other configurations can be envisioned to implement ShoPed as defined in various implementation schemes.

[0070] In summary, the embodiments disclosed herein are systems for depositing PECVD films on selective sides (front and / or back sides) of a wafer, featuring dynamic control for selecting the side of the wafer to undergo deposition. One embodiment includes dual-flow electrodes for defining a capacitively coupled PECVD system. The dual-flow system will include a flow nozzle 104 and a flow ShoPed 106. In one embodiment, the flow ShoPed is a combination of a nozzle and a base that enables deposition on the back side of the wafer. The ShoPed geometry combines features of the nozzle (e.g., gas mixing chamber, outlet, outlet pattern, gas jet preventing baffle) and features of the base (e.g., embedded controlled heater, lifting pin mechanism, ability to retain a plasma suppression ring, and mobility). This allows for the transfer of wafer and processing gas regardless of the presence or absence of RF power.

[0071] In the case where a lifting pin mechanism is used in the ShoPed to lift the carrier ring with the chip 101, the height to which the lifting pin can extend can depend on the amount of gap between the upper nozzle 104 and the ShoPed 106, as well as the thickness of the carrier ring 134. The lifting pin mechanism is connected to the controller 120 to control the activation and deactivation of the lifting pin mechanism.

[0072] In one embodiment, when the unprocessed side of the wafer is received in the chamber, the gap between it and the electrodes (upper nozzle 104 or ShoPed 106) is strictly controlled to a minimum using a lifting pin mechanism. This minimum is necessary to suppress plasma (which would otherwise cause plasma damage). Similarly, in embodiments including spacers on a carrier ring extending to the receiving area of ​​the ShoPed to separate the ShoPed from the lower surface of the wafer 101, the height of the spacers is controlled to ensure that the surfaces of the unprocessed side of the wafer 101 and the electrodes are sufficiently large to suppress plasma formation on the unprocessed side.

[0073] In one example, the system allows a minimum gap from approximately 2 mm to approximately 0.5 mm, and in another embodiment, it allows a gap from approximately 1 mm to approximately 0.05 mm (limited by wafer bending), and this gap can be controlled by the dimensions of the lifting pin mechanism or spacer. In one embodiment, the gap depends on the process conditions.

[0074] In one embodiment, the airflow substrate (i.e., ShoPed) enables (but is not limited to) achieving: (a) thermal stabilization of the wafer to the processing temperature prior to processing; and (b) selectively designing the outlet pattern on the ShoPed to selectively deposit different films in different regions on the back side of the wafer (see reference). Figure 4K(detailed description); (c) a replaceable ring with a specific exit mode can be attached to the top surface of the ShoPed to achieve appropriate plasma confinement; and (see reference) Figure 5A describe Figure 1 (details of alternative implementation schemes) (d) A stable wafer support mechanism, such as a lifting pin mechanism, spacer, etc., defined in a chamber, for supporting the wafer 101 and dynamically controlling the gap between the wafer and the surface of the nozzle 104 during deposition on the underside surface, and a wafer transfer mechanism for transferring an external wafer to another station or chamber or box—such as a spider fork, paddle, lifting pin, RF coupling feature, etc.; (e) Implementing gas mixing features, such as partitions with multiple internal chambers, baffles, etc.; enabling selective gas to flow to different areas defined on the back side of the wafer, and controlling the flow rate via a flow controller.

[0075] The wafer support mechanism enables: (a) controlling the distance from the deposition or reactant flow electrode to the position midway between the wafer side to be deposited or the gap between the upper nozzle and the ShoPed, allowing deposition to be performed on both sides; and (b) dynamically controlling the side to be deposited, the deposition profile, and the characteristics of the deposited film during the process (before plasma, during plasma, and after plasma). In another embodiment, for deposition modes used on the back side of the wafer, edge exclusion control is highly desirable to avoid lithography-related overlay problems. Edge exclusion control is accomplished via a carrier ring 134, which has design features to shield deposits on the edges, including the size and shape of the carrier ring and the size and shape of features formed on the underside of the carrier ring.

[0076] Figure 4A A perspective view of a ShoPed used in a processing chamber for depositing different films on the lower surface of wafer 101 is shown in one embodiment. ShoPed 106 shows different partitions defined using lower and upper separator fins. Figure 4A The perspective view shows only the upper separator fins 156. A pair of upper separator fins 156 are radially disposed on the top surface of the ShoPed, dividing the surface of the ShoPed into four distinct sectors, denoted by the reference letters “a”, “b”, “c”, and “d”. The two sectors “a” and “c” opposite each other define partition 1 (152), while the remaining two sectors “b” and “d” define partition 2 (154). Although this embodiment identifies two partitions, the distinct sectors defined by the current configuration of the upper separator fins 156 and the lower separator fins can be well used to identify four partitions, each associated with a different partition. Figure 4AThe configuration of the separator fins (upper and lower separator fins) shown is merely an example, and fewer or additional partitions can be defined using different orientations and / or different numbers of separator fins. Each partition is connected to a corresponding internal chamber that receives process gas from a corresponding process gas source and includes an outlet group for supplying the process gas to the area above the substrate surface corresponding to the respective partition.

[0077] The upper separator fin 156 defines a plasma generation region that, when received in the chamber, is confined within the gap between the upper surface of the ShoPed and the lower surface of the wafer 101. The depth of the plasma generation region can be defined as greater than a depth that would otherwise suppress plasma generation.

[0078] In one embodiment, the carrier ring 134 with the wafer can be received on top of the upper separator fin 156. Figure 4A One such embodiment is shown. In this embodiment, the carrier ring 134 can be supported on the edge region of the upper separator fin 156. To receive the carrier ring and provide reliable support, the profile of the top surface of the edge region of the upper separator fin 156 may include a step-down feature on which the carrier ring 134 is received. The height of the step-down feature of the upper separator fin 156 can be defined as shorter than the thickness of the carrier ring, so that when the carrier ring is received on top of the upper separator fin 156, the wafer 101 received on the carrier ring is shown as spaced apart from the top of the upper separator fin 156, and the separation height can be small to ensure that process gas in the first partition does not flow into the area covered by the second partition, and vice versa. Outlets are defined in each partition to allow the supply of process gas for deposition of the corresponding film. The size and distribution of the outlets in each partition can be similar or can be different. Figure 4A In the implementation shown, the size and distribution of the outlets in each partition are the same.

[0079] Figure 4B It shows Figure 4A The cross-sectional view of section AA of ShoPed 106, as indicated in the image, shows the orientation of the upper separator fin 156 as it extends from the center of ShoPed 106 to its outer periphery. Furthermore, Figure 4BA side extension 134b defined on the lower surface of the carrier ring 134 is shown for coupling with a corresponding recess 106a defined along the outer edge of the ShoPed 106. The thickness of the side extension 134b may be greater than the height of the upper separator fin 156, such that the side extension 134b of the carrier ring 134 can be received in the recess 106a defined in the outer edge region of the ShoPed 106. As shown, a plurality of side extensions 134b are distributed circumferentially along the ShoPed 106, and the number of recesses 106a defined in the ShoPed 106 may match the number of side extensions 134b defined in the carrier ring 134.

[0080] Figure 4C Showing from Figure 4A A cross-sectional view of the ShoPed 106 is shown in section BB. This cross-sectional view shows the upper separator fin 156 disposed at the center of the ShoPed, and the edges of the ShoPed 106 include spacers 130 for receiving a carrier ring 134 with a wafer 101. In this embodiment, the height of the spacers 130 is shown to be less than the height of the portion of the upper separator fin 156 extending from the surface of the ShoPed 106. The upper separator fin 156 may be fixed to the top surface of the ShoPed 106, or a portion of the upper separator fin 156 may be embedded within the ShoPed 106.

[0081] Figure 4D One embodiment is shown in which a portion of the upper separator fin 156 is embedded within the ShoPed 106. The upper separator fin 156 can have any design and can be oriented differently to define different partitions. Different shapes can be envisioned when designing the upper separator fin 156. In one embodiment, the upper separator fin 156 can be designed to have a specific geometry to reduce the size (i.e., thickness) of the boundary between the first and second films deposited on the lower surface of the wafer. For example, in Figure 4D In the illustrated embodiment, the upper separator fin 156 includes a top tapered portion 156a, a flat bottom portion 156b, and a body extending between the top tapered portion 156a and the flat bottom portion 156b. A portion of the flat bottom portion 156b is embedded in the Shoped 106. The height of the upper separator fin 156 is defined such that the top tapered portions 156a are spaced apart but positioned close to the lower surface of the wafer 101 received on the carrier ring 134. The separation distance between the top tapered portions 156a and the lower surface of the wafer 101 may be equal to the thickness of the bottom extension 134a of the carrier ring 134.

[0082] Figure 4EA side cross-sectional view of a ShoPed for depositing a film on the underside surface of a wafer in a processing chamber is shown in one embodiment. Figure 4E The cross-sectional view depicted is along the region defining the upper and lower separator fins within the ShoPed 106. The lower separator fin 158 is disposed within the ShoPed to define different zones. Each zone can be used to deposit membranes with different properties (e.g., composition, thickness, tensile or compressive properties, etc.). Each zone defined by the internal separator fin 158 includes a corresponding internal chamber (206a, 206b) to receive a volume of process gas from a process gas source (e.g., 112, 114) via a corresponding gas supply (e.g., 112a, 114a) for membrane deposition. The gas supplies (112a, 114a) for supplying process gas to the different zones are housed within a central column 160 supporting the ShoPed 106.

[0083] The upper separator fin 156 is disposed along the outer top surface of the ShoPed and aligned with the inner separator fin 158. Similar to the inner separator fin 158 defining different zones within the ShoPed 106, the upper separator fin 156 defines boundaries to confine process gases supplied from corresponding internal chambers to respective regions defined between the lower surface of the wafer 101 and the top surface of the ShoPed 106, thereby allowing the deposition of different films in each region. Figure 4E In the illustrated embodiment, partition separation line 162 is defined at the intersection of upper separator fins 156 used to define different partitions. A carrier ring 134 with wafer 101 is received on top of spacer 130 defined along the outer circumferential region on the top surface of the ShoPed.

[0084] Figure 4F An internal view of a ShoPed 106 in one embodiment is shown. The interior of the ShoPed includes a first internal chamber 206a and a second internal chamber 206b defined by a lower separator fin 158. A carrier ring 134 may be received on top of a spacer 130 or on an upper separator fin 156, or on both spacer 130 and upper separator fin 156. The spacer 130 and / or upper separator fin 156 ensure that the lower surface of the wafer 101 is spaced apart from the top surface of the ShoPed by a distance that allows plasma to be generated in the gap defined between the lower surface of the wafer and the ShoPed. The upper and lower separator fins 156, 158 define boundaries for containing plasmas of different gases, allowing different films to be formed in different regions defined on the lower surface of the substrate.

[0085] Figures 4G-1 to 4G-4The volume of different process gases in different internal chambers defined by partitions of a ShoPed is shown in one embodiment. For example... Figure 4G-1 As shown, internal chambers 206a and 206b are formed in partitions 1 and 2 (152, 154), respectively, and are separated by fin boundaries 158a defined by internal separator fins 158. The central column 160 includes a gas supply to provide process gases to provide the corresponding gas volumes in the respective internal chambers.

[0086] Figure 4G-2 A view is shown of gas supplies connected to corresponding internal chambers to provide process gases from corresponding process gas sources. For example, a first gas supply 112a is used to supply a first process gas from a first process gas source 112 to a first internal chamber 206a, and a second gas supply 114a is used to supply a second process gas from a second process gas source 114 to a second internal chamber 206b. As shown, the internal chambers contain a volume of the corresponding process gas, thereby providing process gases to produce a film for deposition. Figure 4G-3 A first gas supply 112a is shown that provides a certain volume of first process gas to the first internal chamber 206a, and Figure 4G-4 A second gas supply 114a is shown that provides a certain volume of second process gas to the second internal chamber 206b.

[0087] Figures 4H to 4J This illustration shows an alternative electrode face shape of the ShoPed 306, in one embodiment, which can be used to deposit different films in different regions on the lower surface of wafer 101. The electrode face can be as follows: Figure 4H As shown in the C-section and also in Figure 4I The concave shape depicted in the text, or as... Figure 4H As shown in the DD section and also Figure 4J The convex shape depicted in the image. Figure 4H In the illustrated embodiment, the face of ShoPed 306 is a combination of concave in one direction and convex in different directions. The face profile of ShoPed 306 can be predetermined to adjust or define the gap between the face of ShoPed and the underside surface of the wafer, adjust the process formulation for depositing different films, and regulate the plasma density of different zones. In one embodiment, the height variation of the face profile from the backside surface of wafer 101 can be between approximately 1 mm at the highest point and approximately 15 mm at the lowest point of the face of ShoPed 306. In an alternative embodiment, the variation range can be between approximately 2 mm and approximately 10 mm. In another embodiment, the variation range can be between approximately 3 mm and approximately 7 mm. Figure 4H or Figure 1The partitioned ShoPed implementation shown can be used to determine flow regulation in different partitions. Furthermore, ShoPed enables uniformity in film depth deposited in different partitions using the same or different process gases.

[0088] It should be noted that the selective deposition of films on the back side of the wafer to counteract the effects of wafer warping caused by films formed on the front side can be extended to front-side deposition. For example, a film deposited as a hard mask layer in certain portions of the top side of the wafer can be a sacrificial film. This hard mask layer can be formed on top of other films. Underlying films may settle differently in different directions, resulting in inhomogeneity of the hard mask layer. When other thin films are deposited on top of the hard mask layer, the effects of these other underlying layers' differential settling may have to be taken into account. The hard mask layer is given only as an example, and the deposition of other films to counteract the differential settling of underlying layers can be extended to any film deposited on the wafer surface (front or back side). As a result, the feature that allows selective deposition of films in different portions defined within the ShoPed 106 can be extended to the top electrode, thereby enabling deposition uniformity on the top surface. Figure 4H-4J The surface shape profile of the ShoPed shown can also be considered for the upper electrode. In this case, the selective deposition of different films can take into account the surface profile and define the difference characteristics of the film relative to other films to offset the deposition effect of the lower film.

[0089] Figure 4K The density, distribution, and size of outlets (i.e., orifices) 206c defined on the top surface of a ShoPed 106 in one embodiment are shown. The outlet configuration 206c is provided as an example and should not be considered limiting. The example ShoPed includes a first group of outlets 206c-1 defined in partition 1 for depositing a film 1 and a second group of outlets 206c-2 defined in partition 2 for depositing a film 2. The outlets in the first group 206c-1 are larger in size and confined to region 208, while the outlets in the second group 206c-2 are smaller in size and confined to region 210. The size and density of the outlets are designed to improve plasma density in certain portions rather than others. Larger outlet sizes promote more hollow cathode discharge (HCD), resulting in denser plasma, film depth ratio, etc. In one embodiment, the location and distribution of the first and second outlet groups may be based on the process formulation used for depositing the film, which is determined according to a mathematical model.

[0090] Gas sources 112 and 114 are configured to supply one or more different types of gases to the ShoPed 106. For example, the gas may be a reactive gas used for deposition on the back side of the substrate 101, such as when the carrier ring 134 is supported by a support 130 defined on the ShoPed 106. In one embodiment, the ShoPed 106 can be used to deposit a back-side material layer by flowing a process gas (e.g., silane (SiH4) + ammonia (NH3)). In this embodiment, the upper nozzle 104 may not be configured to deliver any reactive gas. Instead, the upper nozzle 104 may be configured to deliver an inert gas, such as nitrogen (N2), to act as a purge gas. The chemistry, location, and film thickness of the back-side deposition process are carefully selected to strategically counteract the stress caused by front-side deposition and to reduce or avoid wafer / substrate distortion.

[0091] When top-side deposition occurs in the processing chamber, the ShoPed 106 operates as a standard support chuck or base, and gas does not flow out of outlets 206c-1 or 206c-2. Alternatively, the carrier ring with the wafer can be lowered to the top surface of the ShoPed 106 by retracting the lifting pin, for example, where the spacer is used to support the wafer, or in an alternative embodiment using lifting pins to support the carrier ring with the wafer during back-side deposition. In this configuration, different types of process gases, depending on the selected formulation, can be introduced into the nozzle 104 and used for deposition on the top surface of the wafer 101. When under-side deposition occurs, the ShoPed 106 is used as a nozzle. During back-side or under-side deposition, the carrier ring with the wafer is lifted and supported on the spacer, or supported by lifting pins, or by other means used in the ShoPed (e.g., a spiderweb, etc.), and process gases are introduced through the ShoPed 106. At this stage, the ShoPed 106 is used as a nozzle. Backside deposition can compensate for the stress caused by the film defined in topside deposition and helps reduce wafer bending. Therefore, it should be understood that ShoPed 106 can operate in multiple modes depending on the surface on which the deposition is performed, such as the top or back surface of substrate 128.

[0092] In one embodiment, the ShoPed 106 may include a heater integrated therein to provide heating functionality during top-side deposition. The heater elements may be distributed to provide uniform heat distribution while still providing an outlet assembly for gas delivery during back-side deposition.

[0093] Figure 5A An alternative embodiment is shown in which ShoPed is used to deposit different films on the underside surface of the wafer. The ShoPed 106' in this embodiment is compared with the reference... Figures 1 to 4KThe difference in the described ShoPed is that the ShoPed 106' in this embodiment does not include upper separator fins. ShoPed 106' may include lower separator fins to define an internal chamber. Alternatively, ShoPed 106' may include an internal chamber 206' defined for receiving process gas from either of process gas sources 112, 114. Internal chamber 206' extends the width of the ShoPed and defines a volume for the process gas. Furthermore, internal chamber 206' is connected to an outlet assembly defined on the top surface of ShoPed 106'. This outlet assembly is used to provide process gas from one of the process gas sources (112, 114) for film deposition. In one embodiment, the internal chamber 206' may receive a first process gas from a first process gas source 112 to deposit a first film on a portion of the lower surface of the wafer 101, and after the first film deposition, the first process gas may be purged from the internal chamber 206', and a second process gas from a second process gas source 114 may be received into the internal chamber 206' for depositing a second film. The second film may be deposited on the first film or may be deposited in a different region.

[0094] Instead of using to limit Figure 1 The upper and lower separator fins in different areas of the ShoPed 106 are shown. Figure 5A The illustrated ShoPed 106' includes a mask 136. The mask 136 includes a first region 136a having an opening allowing process gases to flow through; and a second region 136b, which is shielded to prevent any process gas flow. The mask 136 is received or integrated onto the top surface of the ShoPed 106'. When the mask is received on the top surface of the ShoPed 106', the design of the mask 136 allows a first gap between the bottom surface of the mask 136 and the top surface of the ShoPed 106'. In addition to the first gap, when the wafer 101 is received on the carrier ring 134, the design of the mask 136 allows a second gap between the top surface of the mask 136 and the lower surface of the wafer 101. The size of the second gap is defined to allow the wafer to be spaced apart from the mask 136 but close enough to allow plasma generated from the process gases to be confined to the region defined on the lower surface of the wafer for receiving deposition. The size of the first gap is sufficient to generate plasma from the process gas supplied by the internal chamber 206'.

[0095] A mask 136 is received on the top surface of the ShoPed 106' such that the orientation of the mask 136 ensures that the first region 136a is aligned with the region on the lower surface of the wafer 101 used for receiving film deposition. Therefore, during film deposition on the lower surface of the wafer 101, process gas from the process gas source 1 is received and equalized, for example, in the internal chamber 206', and then supplied to the first gap through an outlet. The first gap extends over the entire width of the ShoPed 106'. Plasma is generated within the gap using the process gas received therein. Figure 5A As shown, the generated plasma is guided through an opening provided in the first region 136a of the masking plate 136 onto a first region on the underside surface of the wafer 101, thereby depositing a first film in the first region. A second region 136b is masked to prevent plasma from being applied to a second region on the underside surface of the wafer 101. The size of the second gap ensures that only the first region is exposed to the plasma. The first film can be deposited on the first region on the backside of the wafer 101 at a first station in a multi-station chamber or in a first processing chamber, and after the first film deposition, the wafer with a carrier ring can be transferred to a second station within the same chamber or to a second chamber, in which a second film can be deposited on the second region on the backside of the wafer 101. The second station or second chamber can be configured similarly to the first station or first chamber, except that the masking plate 136 in the second station or second chamber is oriented such that the first region 136a of the masking plate 136 is masked and the second region 136b of the masking plate 136 has an opening to expose the second region on the backside of the wafer 101 to the plasma for the deposition of the second film. The orientation of the masking plate 136 in the second chamber (where the first region is masked and the second region has an opening) is defined based on the orientation of the wafer 101 as it is moved out of the first station or first chamber and into the second station or second chamber. If the wafer moves into the second chamber with a different orientation, the orientation of the masking plate 136 in the second chamber is adjusted accordingly so that the second region on the back side of the wafer 101 receives the deposition of the second film.

[0096] Figure 5B-1 and 5B-2 An example orientation of the shielding plates in stations 1 and 2 is shown in one embodiment. For example, Figure 5B-1 The image shows a shielding plate 136 received above a ShoPed 106' in station 1 of a processing chamber. Station 1 may be part of a multi-station processing chamber or a single-station processing chamber. The shielding plate 136 includes an edge 136' along its outer circumference, a first region 136a including an opening, and a shielded second region 136b. Figure 5B-2The image shows a mask 136 received above ShoPed 106' at station 2. It can be seen that the first region 136a is masked or blocked, and the second region 136b includes an opening. The configuration of the mask plates at these two stations can be used to define different films in different regions on the back side of wafer 101. To illustrate the relative positions of the masked regions relative to the unmasked regions on the mask plates at different stations, Figure 5B-1 and 5B-2 A simple example of masking plates 136 with the same orientation is shown, although this may not be the case in reality. The locations of the masked and unmasked areas of the masking plates in each station can be defined based on the orientation of the wafers introduced into different stations.

[0097] Return to reference Figure 5A In one embodiment using a spacer as the support surface for the carrier ring 134, a mask is received on the top surface of the ShoPed 106' such that the top surface of the mask 136 is aligned with or below the top surface of the spacer 130. This is to allow the back side of the wafer 101 to be spaced apart from the mask 136 when the carrier ring 134 with the wafer 101 is received over the spacer 130. The edge 136' of the mask 136 is defined with a profile to allow sufficient space for the carrier ring 134 to be received over the ShoPed 106'. The carrier ring 134 can be received on the spacer 130, and the edge profile of the mask 136 ensures that no portion of the mask 136 obstructs the carrier ring received on the spacer 130. The profile of the edge 136' of the mask 136 may, for example, include a step-down region. The height of the step can be defined to ensure sufficient clearance between the inner edge of the carrier ring 134 and the top surface of the masking plate 136. The width of the stepping region can be equal to or greater than the bottom extension of the carrier ring 134. In one embodiment, the size of the opening in the masking plate is designed to ensure a membrane of a specific thickness.

[0098] Figure 5CAn enlarged view of the edge of a ShoPed 106' is shown in one embodiment, on which a carrier ring 134 and a masking plate 136 are received. The ShoPed 106' includes spacers 130 defined on its edge. These spacers 130 are distributed circumferentially along the edge of the ShoPed 106'. Each spacer 130 includes a recess 130a to receive an annular extension 134a of the carrier ring 134, thereby providing reliable support for the carrier ring and ensuring that the carrier ring does not shift when received on the spacer. The edge region 136' of the masking plate 136, defined on the top surface of the ShoPed, has a top profile that includes a step-down feature to allow the carrier ring 134 to be received on the spacer 130. The top profile of the edge region of the masking plate is shown to be complementary to the profile of the lower surface of the carrier ring 134, thus not interfering with the support of the carrier ring on the spacer 130. The top profile of the edge region of the masking plate 136 is given as an example, and other types of profiles can be envisioned for the edge region of the masking plate 136.

[0099] In another embodiment, the ShoPed may include partitions defined within the ShoPed 106 using lower separator fins. These partitions identify different internal chambers for receiving volumes of different process gases. Different sets of outlets, defined to interface with the internal chambers, supply corresponding process gases to different regions on the underside surface of the wafer to deposit different films. In this embodiment, the ShoPed does not include upper separator fins. Instead, the ShoPed may include a mask plate integrated on the top surface of the ShoPed. Different regions are defined on the mask plate, a first region being masked and a second region having openings to allow process gases supplied from the internal chambers to pass through. The process gases are used to deposit films. The mask plate is integrated into the top surface of the ShoPed such that each partition is aligned with a corresponding region on the mask plate. For example, a first partition of the ShoPed 106 may be aligned with a first region defined on the mask plate. Furthermore, regions in the mask plate are aligned such that masked regions are aligned with regions that do not require deposition, and regions with openings are aligned with regions on the underside surface of the wafer where deposition is taking place. Each partition is connected to a corresponding process gas source via a gas supply to receive a certain volume of process gas into its corresponding internal chamber. When a specific area on the underside of the wafer is to undergo deposition, process gas from the corresponding process gas source is supplied to that area through an opening in the mask, while other areas above the mask area of ​​the mask do not receive any process gas. In this embodiment, ShoPed allows selective operation of different internal chambers by opening the gas supply to the internal chamber corresponding to the first region, so that process gas is supplied when the gas supply to the remaining internal chambers is closed. Furthermore, the masked area in the mask further ensures that areas that should not be deposited are protected from exposure to process gas. This embodiment allows for selective deposition of films in different areas on the backside of the wafer while conserving process gas resources, because process gas is only supplied to the area above the opening in the mask area, and not to the entire area below the mask.

[0100] Various implementations allow for deposition in specific predefined regions on the back side of a wafer using ShoPed to compensate for stress caused by films deposited on the top side of the wafer, thereby preventing or substantially minimizing bends that could affect wafer yield. Masking or stencil features defined in ShoPed allow for the application of selective process gases to the back side of the wafer for selective deposition in certain areas. Masking allows for sequential deposition and the use of different stations to deposit on different regions, while partitioned ShoPed allows for sequential or simultaneous deposition within a defined pattern. The geometry of the masking allows for the adjustment of plasma impedance and flow during active deposition. Furthermore, when defining regions or partitions on the masking, the geometry of the masking can take into account the shape profile of the ShoPed's surfaces (convex, concave, convex / concave). The outlet distribution on the top surface of the ShoPed, as well as the density and size of the outlets (e.g., Figure 4K (As shown) allows for the adjustment of plasma density by enabling the adjustment (increasing or decreasing) of hollow cathode discharge (HCD). The pattern shape can be determined by a mathematical model using the shape of one or more deformed wafers as input, or by a device capable of in-situ metrology, and the pattern shape is used to define partitions. Various combinations of films and partitions modulate the stress on the back side of the wafer to compensate for wafer deformation caused by film deposition on the front side of the wafer. These and other advantages of various embodiments will readily be apparent to those skilled in the art.

[0101] In various embodiments, the materials deposited on the back side of the wafer may include dielectric materials. In some embodiments, the material deposited on the back side may be selected based on the tensile or compressive properties of the material, and this material selection may counteract the bending caused by the film deposited on the front side, thereby improving device quality and yield results. In some cases, oxides and / or nitrides (e.g., silicon oxide / silicon nitride) may be used. Examples of silicon-containing reactants that may be used include, but are not limited to, silanes, halosilanes, and aminosilanes. Silanes contain hydrogen and / or carbon groups but do not contain halogens. Examples of silanes are silanes (SiH4), disilanes (Si2H6), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane, di-tert-butylsilane, allylsilane, sec-butylsilane, tert-hexylsilane, isopentylsilane, tert-butyldisilane, di-tert-butyldisilane, etc. Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. Although halosilanes, especially fluorosilanes, can form reactive halide substances that can be etched onto silicon materials, in some embodiments described herein, no silicon-containing reactants are present when the plasma is excited. Specific chlorosilanes are tetrachlorosilane (SiCl4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), monochlorosilane (ClSiH3), allylchlorosilane, chloromethylsilane, dichlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorosec-butylsilane, tert-butyldimethylchlorosilane, dimethylchlorosilane, etc. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are monoaminosilanes, diaminosilanes, triaminosilanes, and tetraaminosilanes (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted monoaminosilanes, diaminosilanes, triaminosilanes, and tetraaminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilaneamine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3)2(BTBAS), tert-butyl silylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, etc. Another example of an aminosilane is trimethylsilylamine (N(SiH3)).Other potential silicon-containing reactants include tetraethyl orthosilicate (TEOS), and cyclic and acyclic TEOS variants such as tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethylcyclotetrasiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisilazane (HMDS), hexamethyldisilazane (HMDSO), hexamethylcyclotrisiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisilazane (TMDSO), divinyltetramethyldisilazane (VSI2), and methyltriethoxysilane. Silane (MTEOS), dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisiloxane (HMODS), bis(triethoxysilyl)ethane (BTEOSE), bis(trimethoxysilyl)ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetra(trimethylsiloxy)silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS), or tetrapropoxysilane (TPOS).

[0102] Exemplary nitrogen-containing reactants include, but are not limited to, ammonia, hydrazine, amines (e.g., amines containing carbon), such as methylamine, dimethylamine, ethylamine, isopropylamine, tert-butylamine, di-tert-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isopentylamine, 2-methylbut-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, di-tert-butylhydrazine, and aromatic amines, such as aniline, pyridine, and benzylamine. The amine can be a primary amine, secondary amine, tertiary amine, or quaternary amine (e.g., tetraalkylammonium compounds). Nitrogen-containing reactants may contain heteroatoms other than nitrogen; for example, hydroxylamine, tert-butyloxycarbonylamine, and N-tert-butylhydroxylamine are nitrogen-containing reactants.

[0103] Examples of oxygen-containing co-reactants include oxygen, ozone, nitrous oxide, carbon monoxide, nitric oxide, nitrogen dioxide, sulfur oxides, sulfur dioxide, oxygen-containing hydrocarbons (CxHyOz), water, and mixtures thereof.

[0104] The flow rates of these reactants will depend largely on the type of reaction used in the backside layer deposition. When using CVD / PECVD to deposit the backside layer, the flow rate of silicon-containing reactants can be between approximately 0.5–10 mL / min (before atomization), for example, between approximately 0.5–5 mL / min. The flow rates of nitrogen-containing reactants, oxygen-containing reactants, or other co-reactants can be between approximately 3–25 SLM, for example, between approximately 3–10 SLM.

[0105] Unless otherwise stated, the flow rates and power levels provided herein are illustrative and applicable to processing on 300mm wafers. Those skilled in the art will understand that these flow rates and power levels can be adjusted as needed for wafers of other sizes. The following detailed description assumes that the invention is implemented on a wafer. However, the invention is not limited thereto. Workpieces can have various shapes, sizes, and materials. Besides semiconductor wafers, other workpieces that can utilize the invention include various articles of manufacture, such as printed circuit boards, etc.

[0106] Figure 6 A control module 120 for controlling the aforementioned system is shown. For example, control module 120 may include a processor, memory, and one or more interfaces. Control module 120 can be used to control devices in the system in part based on sensed values. By way of example only, control module 120 may control one or more of valve 602, filter heater 604, pump 606, and other devices 608 based on sensed values ​​and other control parameters. Control module 120 receives sensed values ​​from (by way of example only) pressure gauge 610, flow meter 612, temperature sensor 614, and / or other sensors 616. Control module 120 can also be used to control process conditions during precursor delivery and film deposition. Control module 120 will typically include one or more memory devices and one or more processors.

[0107] Control module 120 can control the activities of the precursor delivery system and deposition apparatus. Control module 120 executes a computer program including a set of instructions for controlling process timing, delivery system temperature, differential pressure on filters, valve positions, gas mixing, chamber pressure, chamber temperature, wafer temperature, RF power levels, wafer chuck or pedestal positions, and other parameters specific to the process. Control module 120 can also monitor differential pressure and automatically switch the vapor precursor delivery from one or more paths to one or more other paths. In some embodiments, additional computer programs stored on a memory device associated with control module 800 may be used.

[0108] Typically, there is a user interface associated with the control module 120. The user interface may include a display 618 (e.g., a display screen for apparatus and / or process conditions and / or a graphical software display), and a user input device 620, such as a clicking device, a keyboard, a touch screen, a microphone, etc.

[0109] Computer programs used to control precursor delivery, deposition, and other processes in a process sequence can be written in any conventional computer-readable programming language (e.g., assembly language, C, C++, Pascal, Fortran, or other languages). The compiled object code or script is executed by a processor to perform the tasks identified in the program.

[0110] The control module parameters involve process conditions such as filter differential pressure, process gas composition and flow rate, temperature, pressure, plasma conditions such as RF power level and low-frequency RF frequency, cooling gas pressure, and chamber wall temperature.

[0111] System software can be designed or configured in many different ways. For example, various chamber assembly subroutines or control objects can be written to control the operation of the chamber assemblies required to perform the deposition process of the present invention. Examples of programs or program portions used for this purpose include substrate positioning code, process gas control code, pressure control code, heater control code, and plasma control code.

[0112] The substrate positioning procedure may include program code for controlling chamber assemblies used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber (e.g., gas inlets and / or targets). The process gas control procedure may include code for controlling gas composition and flow rate, and optionally for allowing gas to flow into the chamber prior to deposition to stabilize pressure within the chamber. The filter monitoring procedure includes code for comparing measured differences with predetermined values ​​and / or for switching paths. The pressure control procedure may include code for controlling pressure within the chamber by adjusting, for example, a throttle valve in the chamber's exhaust system. The heater control procedure may include code for controlling the current to a heating element for heating components, the substrate, and / or other parts of the system in the precursor delivery system. Alternatively, the heater control procedure may control the delivery of a heat transfer gas (e.g., helium) to the wafer chuck.

[0113] Examples of sensors that can be monitored during deposition include, but are not limited to, mass flow control modules, pressure sensors (e.g., pressure gauge 810), and thermocouples (e.g., temperature sensor 814) located in the delivery system, base, or chuck. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain the desired process conditions. The embodiments of the invention have been described above in single-chamber or multi-chamber semiconductor processing tools.

[0114] It is important to note that any component in the ShoPed described in the various embodiments is a consumable and replaceable component. Therefore, components such as the ShoPed, upper separator fins, lower separator fins, shielding plate, carrier ring, etc., may be damaged due to continuous exposure to plasma. Consequently, these components can be manufactured and replaced individually, or they can be replaced as a single unit based on the amount of damage suffered. For example, if necessary, the upper and lower separator fins can be replaced individually within the ShoPed, or alternatively, the entire ShoPed or portions of the ShoPed including the upper and lower separator fins can be replaced to maintain the quality of deposition performed in the chamber.

[0115] For illustrative and descriptive purposes, the foregoing description of embodiments has been provided. It is not intended to be exhaustive or limiting of the invention. Even without specific showing or description, individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and can be used in selected embodiments. The same can also be varied in many ways. Such variations should not be considered as departing from the invention, and all such modifications are intended to be included within the scope of the invention.

[0116] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be made within the scope of the appended claims. Therefore, these embodiments are to be considered illustrative rather than restrictive, and are not limited to the details given herein, but can be modified within their scope and equivalents of the claims.

Claims

1. An apparatus for processing a wafer, comprising: Nozzle base; The first chamber is located within the nozzle base; The second chamber is located within the nozzle base; One or more first gas supplies are fluidly connected to the first chamber within the nozzle base; One or more second gas supplies are fluidly connected to the second chamber within the nozzle base; The first outlet group is distributed on one or more first sections on the top surface of the nozzle base and is in fluid communication with the first chamber within the nozzle base; The second outlet group is distributed on one or more second sections on the top surface of the nozzle base and is in fluid communication with the second chamber within the nozzle base; as well as A wafer support mechanism configured to support a wafer above the nozzle base such that the wafer is lifted above the top surface of the nozzle base, wherein the first chamber and the second chamber are distributed to compensate for deformation of the wafer due to film deposition on the front side of the wafer.

2. The apparatus according to claim 1, wherein, The one or more first gas supplies are configured to supply a first set of one or more gases to the first chamber, and the one or more second gas supplies are configured to supply a second set of one or more gases to the second chamber.

3. The apparatus according to claim 2, wherein the first group of one or more gases is the same as the second group of one or more gases.

4. The apparatus according to claim 2, wherein the first group of one or more gases is different from the second group of one or more gases.

5. The apparatus of claim 3, wherein the nozzle base is configured to deliver, for the one or more first zones and the one or more second zones, processing gases of different flow rates from the first group of one or more gases and the second group of one or more gases.

6. The apparatus of claim 1, wherein the nozzle base is configured to deliver different flow rates of treatment gas to the one or more first zones and the one or more second zones.

7. The apparatus according to claim 1, wherein, The wafer support mechanism includes a plurality of spacers that extend upward from the top surface of the nozzle base.

8. The apparatus according to claim 7, wherein, The top surface of the nozzle base includes a carrier ring support region on the outer edge of the top surface of the nozzle base, and the spacer is located within the carrier ring support region.

9. The apparatus according to claim 7 or 8, wherein, The spacer is configured as a support carrier ring, which is configured to support the wafer above the top surface of the nozzle base.

10. The apparatus of claim 9, wherein each of the spacers has a recess located in the top surface of the spacer and configured to receive a corresponding ring extension on the lower surface of the carrier ring.

11. The apparatus according to claim 1, wherein, The first partition and the second partition are each fan-shaped, with each first partition located between two second partitions, and each second partition located between two first partitions.

12. The apparatus of claim 11, wherein the first partition and the second partition are identical in size and shape.

13. The apparatus of claim 12, wherein two first partitions and two second partitions are provided, and each of the first partitions and the second partitions defines a different quadrant of the top surface of the nozzle base.

14. The apparatus of claim 1, wherein the one or more first partitions comprises two first partitions, and the one or more second partitions extend between the two first partitions such that at least a portion of the one or more second partitions is located between the two first partitions.

15. The apparatus according to claim 14, wherein, The size of the outlets in the first outlet group is different from the size of the outlets in the second outlet group.

16. The apparatus according to claim 15, wherein, The exports in the first export group are greater than the exports in the second export group.

17. The apparatus of claim 1, further comprising at least one lower separator fin located within the nozzle base, the at least one lower separator fin defining a boundary between the first chamber and the second chamber.

18. The apparatus of claim 17, further comprising at least one upper separator fin extending above the top surface of the nozzle base and aligned with the at least one lower separator fin.

19. The apparatus of claim 1, further comprising a heater configured to heat the nozzle base.

20. The apparatus according to any one of claims 1 to 8 or 11 to 19, further comprising: Processing room; and The nozzle, including: The nozzle base is located within the processing chamber and below the nozzle. The nozzle includes a third outlet group distributed on the bottom surface of the nozzle and in fluid communication with a third chamber within the nozzle.

Images