Optical proximity effect correction method
By finding and moving abnormal edges in optical proximity correction, the problem of incomplete hole coverage at corners or line ends during photolithography is solved, improving product stability and electrical properties, reducing the running time and secondary processing of optical proximity correction, and increasing wafer fabrication efficiency.
Patent Information
- Application Number
- CN202511686076.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-17
- Publication Date
- 2026-02-10
AI Technical Summary
During the photolithography process, the diffraction and proximity effects of light can cause pattern distortion. In particular, when the aperture is at a corner or the end of a line, it can easily cause incomplete aperture coverage, affecting resistance and signal delay.
By finding abnormal edges in the target graphic layer and moving a first predetermined distance along the abnormal edges in a direction perpendicular to the target graphic layer, and then moving a second predetermined distance along each edge in a direction perpendicular to the target graphic layer, the OPC-corrected target graphic layer is obtained. This process is iterated to compensate for abnormal edges and reduce edge-mounted holes.
It reduces the problem of incomplete enclosure, improves product stability and electrical properties, reduces the optical proximity effect correction runtime, and improves fabrication efficiency and pattern quality.
Smart Images
Figure CN121500680A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a method for correcting the optical proximity effect. Background Technology
[0002] With the development of chip technology, linewidths are getting smaller and smaller, and pattern designs are becoming more and more complex. In the photolithography process, due to the limitations of the resolution of the photolithography machine, when the linewidth on the wafer is smaller than the exposure wavelength, the pattern distortion problem becomes increasingly serious due to the diffraction effect and proximity effect of light. For example, the designed pattern will produce rounded corners due to light interference during exposure, and there are problems such as critical dimension variation (CDV). Therefore, it is necessary to correct the mask pattern to achieve the consistency between the final pattern on the wafer and the designed pattern. This correction process is called optical proximity correction (OPC).
[0003] In OPC correction rules, when the actual pattern on the wafer is larger than the design pattern, the mask layout needs to be negatively shifted (biased) to ensure that the actual value on the wafer matches the design value. However, in this case, for vias that are close to the edge of the original design, near the edge of the target pattern, or slightly overlapping the edge of the target pattern, incomplete via coverage will occur. This is especially true when the via is placed at the corner of the target pattern, where the corner rounding effect further worsens the coverage, potentially leading to open circuits, increased resistance, signal delays, and other issues. Summary of the Invention
[0004] The purpose of this invention is to provide an optical proximity effect correction method that reduces the number of edge holes, avoids incomplete hole coverage caused by holes at corners or line ends, improves the development progress of the optical proximity effect correction program, and reduces the optical proximity effect correction operation time.
[0005] To address the aforementioned technical problems, this invention provides a method for correcting the optical proximity effect, comprising the following steps:
[0006] Select the original image layer containing the target graphic layer and the hole layer, and find the abnormal edges in the target graphic layer according to the positional relationship between the target graphic layer and the hole layer;
[0007] Move the abnormal edge along a direction perpendicular to the abnormal edge and away from the target graphics layer by a first predetermined distance;
[0008] Each edge in the target graphic layer is moved a second predetermined distance along a direction perpendicular to that edge and close to the target graphic layer to obtain an OPC-corrected target graphic layer; and
[0009] Iterate over the target graphics layer for OPC correction.
[0010] Optionally, the method for finding abnormal edges in the target graphic layer based on the positional relationship between the target graphic layer and the hole layer includes: determining whether the distance between one edge of the target graphic layer and the corresponding other edge in the hole layer is less than the process deviation; if it is less than the process deviation, then the edge of the target graphic layer is an abnormal edge.
[0011] Optionally, the first set distance Y is:
[0012]
[0013] Where X is the distance between the abnormal edge in the target graphic layer and the corresponding edge in the hole layer, K is the process deviation value, and Node is the value of different process nodes.
[0014] Optionally, the second set distance is the absolute value of the process deviation value.
[0015] Optionally, after obtaining the OPC-corrected target graphics layer, the process before iteration also includes:
[0016] The idealized pattern layer of the wafer is obtained by modifying the target pattern layer according to the OPC;
[0017] The OPC correction target graphics layer is segmented to form multiple movable line segments;
[0018] Tangents are added to the OPC correction target patterning layer to obtain the deviation between the OPC correction target patterning layer and the wafer idealized patterning layer.
[0019] Optionally, the edge of the OPC-corrected target graphic layer is cut into segments of equal length at fixed intervals to obtain line segments of equal length.
[0020] Optionally, the different side lengths of the OPC-corrected target graphic layer are calculated, and the OPC-corrected target graphic layer is segmented according to the set parameters to obtain multiple line segments of equal or unequal length.
[0021] Optionally, the OPC correction target pattern layer is iterated multiple times; after each iteration, the deviation between the simulation pattern obtained by the iteration and the idealized pattern layer of the wafer is calculated, and the deviation is multiplied by a set value as the movement amount for the next iteration, and the movement amount does not exceed the set maximum single movement amount.
[0022] Optionally, the setting value is a feedback ratio value set by the program.
[0023] In summary, the optical proximity effect correction method provided by this invention first selects an original pattern layer containing a target pattern layer and a hole layer, and then finds abnormal edges in the target pattern layer based on the positional relationship between the target pattern layer and the hole layer. Next, the abnormal edges are moved a first predetermined distance along a direction perpendicular to the abnormal edges and away from the target pattern layer. Then, each edge in the target pattern layer is moved a second predetermined distance along a direction perpendicular to each edge and closer to the target pattern layer, resulting in an OPC-corrected target pattern layer. The OPC-corrected target pattern layer is then iterated. Before moving each edge in the target pattern layer, this invention first finds and moves abnormal edges, i.e., it compensates for abnormal edges before globally moving the target pattern layer. This reduces the number of edge-mounted holes, solves the problem of incomplete hole coverage caused by global movement of the target pattern layer due to process deviations, and also solves the problem of incomplete hole coverage caused by holes at corners or line ends, thereby improving the stability and electrical characteristics of the product. Meanwhile, it reduces errors after the optical proximity effect correction program completes its automatic calculations, thereby avoiding secondary special processing corrections, accelerating the fabrication efficiency, improving pattern quality, and speeding up the development of the optical proximity effect correction program while reducing its runtime. Attached Figure Description
[0024] Figure 1 This is a flowchart of an optical proximity effect correction method provided in an embodiment of the present invention.
[0025] Figure 2 This is a schematic diagram of abnormal edges in the original image layer provided in an embodiment of the present invention.
[0026] Figure 3 This is a schematic diagram of the original image layer provided in an embodiment of the present invention.
[0027] Figure 4 This is a graphical schematic diagram of an abnormal edge moving a first predetermined distance, according to an embodiment of the present invention.
[0028] Figure 5 This is a schematic diagram of the shape after each edge has been moved a second predetermined distance, according to an embodiment of the present invention.
[0029] Figure 6 This is a schematic diagram of the wafer after obtaining the idealized pattern layer, provided by an embodiment of the present invention.
[0030] Figure 7 This is a schematic diagram of the OPC correction target graphic layer after segmentation, provided by an embodiment of the present invention.
[0031] Figure 8 This is a schematic diagram of the initial iteration provided in an embodiment of the present invention.
[0032] Figure 9 This is a schematic diagram of the completed iteration provided in an embodiment of the present invention.
[0033] Figure 10 This is a schematic diagram of the optical proximity effect correction provided in an embodiment of the present invention. Detailed Implementation
[0034] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0035] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include the meaning of “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include the meaning of “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include the meaning of “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.
[0036] Figure 1 This is a flowchart of an optical proximity effect correction method provided in an embodiment of the present invention. Please refer to it. Figure 1 As shown, the optical proximity effect correction method provided in this embodiment of the invention includes the following steps:
[0037] S1: Select the original image layer containing the target graphic layer and the hole layer, and find the abnormal edge in the target graphic layer according to the positional relationship between the target graphic layer and the hole layer;
[0038] S2: Move the abnormal edge along a direction perpendicular to the abnormal edge and away from the target graphics layer by a first predetermined distance;
[0039] S3: Move each edge of the target graphic layer by a second predetermined distance along a direction perpendicular to each edge and close to the target graphic layer to obtain the OPC-corrected target graphic layer; and
[0040] S4: Iterate over the target graphics layer of the OPC correction.
[0041] In step S1, the original layout layer includes a target graphic layer and a hole layer. The hole layer is located above or below the target graphic layer, and the target graphic layer and the hole layer have an overlapping area in the direction perpendicular to the target graphic layer. When the hole layer is relatively close to the edge of the target graphic layer, subsequent operations (such as moving all edges of the target graphic layer) will result in incomplete hole enclosure (i.e., the target graphic layer cannot completely surround the hole layer). In this embodiment, the edges on the target graphic layer that may have incomplete hole enclosure, i.e., abnormal edges, are first identified, and these abnormal edges are moved to prevent subsequent incomplete hole enclosure.
[0042] The method for identifying abnormal edges in the target graphic layer based on the positional relationship between the target graphic layer and the hole layer includes: determining whether the distance between one edge of the target graphic layer and the corresponding edge of the hole layer is less than a process deviation; if it is less than the process deviation, then that edge of the target graphic layer is an abnormal edge. Of course, if the distance is greater than or equal to the process deviation, then there is no abnormal edge.
[0043] Figure 2 This is a schematic diagram of abnormal edges in the original image layer provided in an embodiment of the present invention. Please refer to it. Figure 2 As shown, the original layout layer includes a target graphic layer 10 and multiple hole layers 20 located above or below the target graphic layer 10. It is determined whether the distance between each edge of the target graphic layer 10 and its corresponding edge in the hole layer 20 is less than the process deviation. If it is less than the process deviation, then that edge of the target graphic layer 10 is an abnormal edge. For example, it is determined whether the distance between edge 11 of the target graphic layer 10 and edge 21 of the hole layer 20 (edge 11 and edge 21 correspond) is less than the process deviation. If it is less than the process deviation, then edge 11 is an abnormal edge. Figure 2 Edges 11, 12, 13, 14, 15, and 16 of the target graphics layer 10 are all abnormal edges.
[0044] In this embodiment, abnormal edges in the target graphic layer are obtained by performing Boolean operations on the original image layer.
[0045] In step S2, the abnormal edge is moved a first predetermined distance in a direction perpendicular to the abnormal edge and away from the target graphic layer. Moving the abnormal edge away from the target graphic layer by the first predetermined distance increases the spacing between the edge of the target graphic layer and the edge of the hole layer, preventing incomplete hole enclosure when all edges of the target graphic layer are subsequently moved.
[0046] In one embodiment of the present invention, the first predetermined distance Y is:
[0047]
[0048] Where X is the distance between the abnormal edge in the target graphic layer and the corresponding edge in the hole layer, K is the process deviation value, which is the difference in size between the designed graphic and the actual graphic, and Node is the value of different process nodes. The first set distance Y varies with the distance between the two edges. For example, when X=0, that is, when the target graphic layer and the hole layer share an edge, the first set distance by which the edge of the target graphic layer moves outward is... .
[0049] For example, when K=6nm and X=2nm, K>X>0, then Y= When K = -6nm and X = -2nm, K < X < 0, then Y = .
[0050] In this embodiment, by moving the abnormal edges, the target pattern layer is compensated, thereby increasing the aperture ratio of the final actual pattern formed on the wafer.
[0051] In step S3, each edge in the target graphics layer is moved a second predetermined distance along a direction perpendicular to the edge and either away from or close to the target graphics layer, i.e., the target graphics layer is globally shifted (global bias) to obtain the OPC corrected target graphics layer (OPC Target).
[0052] Each edge in the target graphic layer moves along a direction perpendicular to that edge and moves closer to the target graphic layer, and each moves a second predetermined distance.
[0053] In one embodiment of the present invention, the second set distance is the absolute value of the process deviation, i.e., |K|. When the process deviation is positive, i.e., the actual image is larger than the layout graphic, each edge in the target graphic layer is moved along a direction perpendicular to that edge and close to the target graphic layer. In this embodiment, positive process deviations are compensated for by applying a global bias to the overall graphic.
[0054] For example, if K=6nm, then each edge in the target pattern layer is moved 6nm inward along a direction perpendicular to that edge.
[0055] In step S4, the OPC correction target graphics layer is iterated.
[0056] In one embodiment of the present invention, after obtaining the OPC-corrected target graphics layer, the method further includes, before performing OPC iteration:
[0057] First, the idealized wafer patterning layer (FlexTarget) is obtained based on the OPC-corrected target patterning layer (OPC Target). In this embodiment, the idealized wafer patterning layer can be obtained based on the OPC-corrected target patterning layer and empirical data.
[0058] Then, the OPC correction target graphic layer is segmented to form multiple movable line segments. In this embodiment, the length of the line segments can be manually determined according to factors such as process and layout accuracy. The length of each line segment can be equal or unequal. For example, uniform segmentation can be used, cutting the edge of the OPC correction target graphic layer at fixed intervals to obtain multiple line segments of equal length. Another example is calculating the lengths of different side lengths of the OPC correction target graphic layer and segmenting the OPC correction target graphic layer according to set parameters (e.g., uniformly segmenting each side) to obtain multiple line segments of equal or unequal length; that is, some line segments have unequal lengths, while others have equal lengths. Alternatively, a segmentation strategy can be predefined according to design rules; this invention does not limit this approach.
[0059] Next, a cutline is added to the OPC correction target patterning layer to obtain the deviation between the OPC correction target patterning layer and the wafer idealized patterning layer, that is, to obtain the deviation between the OPC correction target patterning layer and the wafer idealized patterning layer in the tangent direction.
[0060] Next, the OPC correction target pattern layer is iterated. Multiple OPC iterations can be performed to generate a simulated pattern (contour). For example, the number of iterations is 8. After each iteration, the deviation between the simulated pattern obtained in the iteration and the idealized pattern layer on the wafer is calculated. This deviation is multiplied by a set value as the movement amount for the next iteration, and this movement amount does not exceed the set maximum single movement amount. That is, if the calculated movement amount is greater than the set maximum single movement amount, the movement is done by the set maximum single movement amount. The set value is a feedback ratio value set by the program. The feedback ratio value can be determined manually based on experience, for example, the feedback ratio value is 0.2. For example, if the calculated deviation is 6nm and the feedback ratio value is 0.2, then 0.2 * 6nm is used as the movement amount for the next iteration. If the set maximum single movement amount is 1nm, and 0.2 * 6nm > 1nm, then 1nm is used as the movement amount for the next iteration. After multiple iterations, an optical proximity effect corrected pattern (POST_OPC) or an optical proximity effect corrected pattern mask (POST_OPC MASK) is obtained.
[0061] In this embodiment, before moving each edge of the target graphic layer, abnormal edges are first identified and moved. This means that abnormal edges are compensated before the global movement of the target graphic layer. This reduces the number of edge-fitting holes, resolving the issue of incomplete hole coverage caused by global movement of the target graphic layer due to process deviations. It also solves the problem of incomplete hole coverage caused by holes at corners or line ends, thereby improving product stability and electrical characteristics. Simultaneously, it reduces errors after the automatic calculation of the optical proximity effect correction program, avoiding secondary special processing corrections, accelerating fabrication efficiency, improving pattern quality, and speeding up the development of the optical proximity effect correction program while reducing its runtime.
[0062] The optical proximity effect correction method of the present invention is described below with specific schematic diagrams. Figure 3 This is a schematic diagram of the original plate layer provided in an embodiment of the present invention. Figure 4 This is a graphical schematic diagram of an abnormal edge after it has moved a first predetermined distance, according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a figure after each edge has been moved a second predetermined distance, according to an embodiment of the present invention. Figure 6 This is a schematic diagram of a wafer after obtaining an idealized pattern layer, according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the OPC correction target graphic layer after segmentation, according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the graphic representation after the first iteration according to an embodiment of the present invention. Figure 9This is a schematic diagram of the completed iteration provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of the optical proximity effect correction provided in an embodiment of the present invention.
[0063] For example, in step S1, please refer to Figure 3 As shown, the original image layer containing the target graphic layer 10 and the hole layer 20 is selected. Based on the positional relationship between the target graphic layer 10 and the hole layer 20, abnormal edges (e.g., edge 11) in the target graphic layer are found. In step S2, refer to... Figure 4 As shown, the abnormal edge is moved a first predetermined distance along a direction perpendicular to the abnormal edge and away from the target graphics layer 10. In step S3, refer to Figure 5 As shown, each edge in the target graphics layer 10 is moved a second predetermined distance along a direction perpendicular to the edge and close to the target graphics layer 10 to obtain the OPC-corrected target graphics layer 30.
[0064] Please refer to the following: Figure 6 As shown, the idealized wafer patterning layer 40 is obtained by correcting the target patterning layer 30 according to the OPC. Please refer to [the following text] next. Figure 7 As shown, the OPC correction target patterning layer 30 is segmented to form multiple movable line segments. Then, tangent lines are added to the OPC correction target patterning layer to obtain the deviation EPE between the OPC correction target patterning layer and the wafer idealized patterning layer.
[0065] In step S4, the OPC correction target graphics layer is iterated. Please refer to [link / reference]. Figure 8 As shown, after iteration, a simulation pattern 50 is formed. After each iteration, the deviation between the simulation pattern 50 obtained in the iteration and the idealized pattern layer 40 on the wafer (e.g., the deviation at the tangent 60) is calculated, and this deviation is multiplied by a set value as the shift amount for the next iteration. The iteration continues thereafter. Please refer to [reference needed]. Figure 9 As shown, at tangent 60, the simulated pattern 50 overlaps with the idealized wafer pattern layer 40, meaning the simulated pattern 50 and the idealized wafer pattern layer 40 are extremely close. Please refer to... Figure 10 As shown, after the iteration ends, the optical proximity effect corrected graph 70 is obtained.
[0066] In summary, the optical proximity effect correction method provided by this invention first selects an original pattern layer containing a target pattern layer and a hole layer, and then finds abnormal edges in the target pattern layer based on the positional relationship between the target pattern layer and the hole layer. Next, the abnormal edges are moved a first predetermined distance along a direction perpendicular to the abnormal edges and away from the target pattern layer. Then, each edge in the target pattern layer is moved a second predetermined distance along a direction perpendicular to each edge and closer to the target pattern layer, resulting in an OPC-corrected target pattern layer. Finally, OPC iteration is performed. Before moving each edge in the target pattern layer, this invention first finds and moves abnormal edges, i.e., it compensates for abnormal edges before globally moving the target pattern layer. This reduces the number of edge-mounted holes, solves the problem of incomplete hole enclosure caused by global movement of the target pattern layer due to process deviations, and also solves the problem of incomplete hole enclosure caused by holes at corners or line ends, thereby improving the stability and electrical characteristics of the product. Meanwhile, it reduces errors after the optical proximity effect correction program completes its automatic calculations, thereby avoiding secondary special processing corrections, accelerating the fabrication efficiency, improving pattern quality, and speeding up the development of the optical proximity effect correction program while reducing its runtime.
[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for correcting the optical proximity effect, characterized in that, Includes the following steps: Select the original image layer containing the target graphic layer and the hole layer, and find the abnormal edges in the target graphic layer according to the positional relationship between the target graphic layer and the hole layer; Move the abnormal edge along a direction perpendicular to the abnormal edge and away from the target graphics layer by a first predetermined distance; Each edge in the target graphic layer is moved a second predetermined distance along a direction perpendicular to the edge and close to the target graphic layer to obtain the OPC corrected target graphic layer; as well as Iterate over the target graphics layer for OPC correction.
2. The optical proximity effect correction method according to claim 1, characterized in that, The method for finding abnormal edges in the target graphic layer based on the positional relationship between the target graphic layer and the hole layer includes: determining whether the distance between one edge of the target graphic layer and the corresponding other edge in the hole layer is less than the process deviation; if it is less than the process deviation, then the edge of the target graphic layer is an abnormal edge.
3. The optical proximity effect correction method according to claim 1, characterized in that, The first set distance Y is: Where X is the distance between the abnormal edge in the target graphic layer and the corresponding edge in the hole layer, K is the process deviation value, and Node is the value of different process nodes.
4. The optical proximity effect correction method according to claim 1, characterized in that, The second set distance is the absolute value of the process deviation.
5. The optical proximity effect correction method according to claim 1, characterized in that, After obtaining the OPC-corrected target graphics layer, the process before iteration includes: The idealized pattern layer of the wafer is obtained by modifying the target pattern layer according to the OPC; The OPC correction target graphics layer is segmented to form multiple movable line segments; Tangents are added to the OPC correction target patterning layer to obtain the deviation between the OPC correction target patterning layer and the wafer idealized patterning layer.
6. The optical proximity effect correction method according to claim 5, characterized in that, The edge of the OPC-corrected target graphic layer is cut into segments of equal length at fixed intervals to obtain line segments of equal length.
7. The optical proximity effect correction method according to claim 5, characterized in that, Calculate the different side lengths of the OPC-corrected target graphic layer, and cut the OPC-corrected target graphic layer into segments according to the set parameters to obtain multiple line segments of equal or unequal length.
8. The optical proximity effect correction method according to claim 5, characterized in that, The OPC correction target pattern layer is iterated multiple times; after each iteration, the deviation between the simulation pattern obtained by the iteration and the idealized pattern layer of the wafer is calculated, and the deviation is multiplied by a set value as the movement amount for the next iteration, and the movement amount does not exceed the set maximum single movement amount.
9. The optical proximity effect correction method according to claim 8, characterized in that, The set value is the feedback ratio value set by the program.