Display device and communication method of display device

Abstract

The invention provides a display device and a communication method of the display device, and belongs to the technical field of display driving. The display device comprises a time schedule controller and a power management module; the time schedule controller and the power management module are connected with the same communication interface through a communication bus, and the communication interface is used for carrying out data interaction with a mainboard end; the power management module is configured to receive a first target address byte on the communication bus, and if the first target address byte is matched with a built-in address byte of the power management module, a target verification byte on the communication bus is received; and if the target verification byte is matched with the built-in verification byte of the power management module, receiving power driving data on the communication bus so as to execute corresponding read-write operation according to the power driving data. Therefore, on the premise that hardware is not newly added, the power management module cannot be read and written mistakenly even if mistaken addressing occurs, and therefore normal work of the display device can be guaranteed.

Description

Technical Field

[0001] This application relates to the field of display driver technology, and in particular to a display device and a communication method for the display device. Background Technology

[0002] When a display device displays an image, it needs to establish a connection with the motherboard to transmit image data and control signals. This allows the display device to control the display state of each pixel according to preset refresh rate and other display parameters, thus completing the image display. During this process, frequent data transmission is required between the motherboard and the display device, especially in high refresh rate displays (such as 120Hz and above). To ensure data transmission efficiency, an integrated circuit (IIC) is typically used to achieve data transmission between the motherboard and the display device.

[0003] Currently, because multiple slave devices in a display device, such as the timing controller and power management unit, need to communicate with the motherboard, the motherboard uses a bus protocol addressing method to send address bytes to all connected slave devices when it needs to communicate with a specific slave device. A connection is then established based on the slave device's response. However, in display devices, communication between the motherboard and the timing controller is more frequent, requiring the motherboard to send address bytes to all slave devices more frequently. This frequent addressing increases the risk of misaddressing. If misaddressing occurs, the corresponding slave device may be misread or written, causing malfunctions in the display device. Summary of the Invention

[0004] This application provides a display device to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a display device is provided, including a timing controller and a power management module; The timing controller and the power management module are connected to the same communication interface via a communication bus, and the communication interface is used to interact with the motherboard. The power management module is configured as follows: Receive a first target address byte on the communication bus; if the first target address byte matches the built-in address byte of the power management module, then receive a target verification byte on the communication bus. If the target verification byte matches the built-in verification byte of the power management module, then power drive data on the communication bus is received to perform corresponding read / write operations based on the power drive data.

[0006] Optionally, the power drive data includes first drive data; the timing controller and the power management module are connected via the communication bus; the timing controller is configured to: When it is necessary to establish communication with the power management module, the first target address byte of the power management module is determined from the preset address table, and the first target address byte is transmitted to the communication bus; In response to a first acknowledgment signal from the power management module and transmitted on the communication bus, the target verification byte of the power management module is determined from a preset key table, and the target verification byte is transmitted to the communication bus; In response to a second acknowledgment signal from the power management module and transmitted on the communication bus, the first drive data is transmitted to the communication bus.

[0007] Optionally, the power drive data includes second drive data; the motherboard is configured as follows: When it is necessary to establish communication with the power management module, the first target address byte of the power management module is determined from the preset address table, and the first target address byte is transmitted to the communication bus through the communication interface; In response to a first acknowledgment signal transmitted from the power management module on the communication bus, the target verification byte of the power management module is determined from a preset key table, and the target verification byte is transmitted to the communication bus through the communication interface; In response to a second acknowledgment signal from the power management module and transmitted on the communication bus, the second drive data is transmitted on the communication bus.

[0008] Optionally, the power management module is further configured to: After the first target address byte matches the built-in address byte of the power management module, the first response signal is output to the communication bus; After the target verification byte matches the built-in verification byte of the power management module, the second response signal is output to the communication bus.

[0009] Optionally, the timing controller is further configured to: The system receives a second target address byte on the communication bus. If the second target address byte matches the built-in address byte of the timing controller, it outputs a third response signal to the communication bus and transmits the third response signal to the motherboard through the communication interface, so that the motherboard can transmit display driver data to the communication bus through the communication interface. Receive display driver data from the communication bus to perform corresponding read / write operations based on the display driver data.

[0010] Optionally, the power management module includes a power management chip and a backlight power driver chip; The built-in address byte of the power management chip is different from the built-in address byte of the backlight power driver chip; The built-in verification byte of the power management chip is different from the built-in verification byte of the backlight power driver chip.

[0011] Optionally, the communication bus includes a data line and a clock line; the communication interface includes a first interface and a second interface; One end of the data cable is connected to the first interface, and the other end is connected to the timing controller and the power management module respectively. One end of the clock line is connected to the second interface, and the other end is connected to the timing controller and the power management module, respectively.

[0012] Optionally, the communication bus includes a pull-up module for providing a high-level state for the data line and the clock line; The pull-up module includes a first resistor and a second resistor; The first resistor includes a first terminal connected to a voltage source and a second terminal connected to the clock line; The second resistor includes a first end connected to the voltage source and a second end connected to the data line.

[0013] According to a second aspect of this application, a communication method for a display device is provided, based on the aforementioned display device and applied to the power management module, the method comprising: Receive a first target address byte on the communication bus; if the first target address byte matches the built-in address byte of the power management module, then receive a target verification byte on the communication bus. If the target verification byte matches the built-in verification byte of the power management module, then power drive data on the communication bus is received to perform corresponding read / write operations based on the power drive data.

[0014] According to a third aspect of this application, a communication method for a display device is provided, based on the aforementioned display device and applied to a timing controller, wherein the timing controller is connected to a power management module via the communication bus, the method comprising: When it is necessary to establish communication with the power management module, the first target address byte of the power management module is determined from the preset address table, and the first target address byte is transmitted to the communication bus; In response to a first acknowledgment signal from the power management module and transmitted on the communication bus, the target verification byte of the power management module is determined from a preset key table, and the target verification byte is transmitted to the communication bus; In response to a second acknowledgment signal from the power management module and transmitted on the communication bus, the first drive data is transmitted to the communication bus.

[0015] In summary, this application firstly identifies a unique power management module on the communication bus by matching the first target address byte, thus establishing a communication connection and receiving the target verification byte. Secondly, matching the target verification byte allows for secondary confirmation of the addressing process and separates addressing from read / write permissions. Read / write permissions are not directly granted after the communication connection is established by matching the first target address byte; power drive data on the communication bus is only received after the target verification byte is matched, and corresponding read / write operations are performed based on this data. Therefore, without adding new hardware, even in the event of misaddressing, the power management module will not be misread or written to, ensuring the normal operation of the display device.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a schematic diagram of the communication architecture between the display device and the motherboard in the related technologies provided in the exemplary embodiments of this application; Figure 2 This is a schematic diagram of a display device provided in an exemplary embodiment of this application; Figure 3 This is a schematic diagram of the communication architecture between the display device and the motherboard provided in an exemplary embodiment of this application; Figure 4 This is a flowchart of a communication method for a display device provided in an exemplary embodiment of this application; Figure 5 This is a flowchart of the communication method of the timing controller provided in an exemplary embodiment of this application; Figure 6 This is a flowchart of a communication method on the motherboard side provided in an exemplary embodiment of this application.

[0019] Explanation of reference numerals in the attached figures: 10, timing controller; 20, power management module; 21, power management chip; 22, backlight power driver chip; 30, communication bus; 31, pull-up module; R1, first resistor; R2, second resistor; SCL, clock line; SDA, data line. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] First, based on the aforementioned background information, the background of this application will be further explained. (Refer to...) Figure 1 , Figure 1 This diagram illustrates the connection between the display device and the motherboard. To address the issue of misaddressing and communication failures during frequent addressing by slave devices on the motherboard, related technologies utilize independent communication buses to connect the motherboard to the timing controller and the power management unit (PMU). For example, the motherboard connects to the timing controller via communication buses SCL and SDA1, and to the PMU via communication buses SCL and SDA0. A switching device MOS is positioned between communication buses SDA0 and SDA1, and a pull-up resistor R0 is placed on communication bus SDA0. When the motherboard needs to communicate with the timing controller, the MOS is deactivated, disconnecting the connection between the motherboard and the PMU, allowing only the timing controller to receive address bytes from the motherboard. When the motherboard needs to communicate with the PMU, the MOS is activated, enabling both the timing controller and the PMU to receive address bytes from the motherboard, thus establishing a communication connection between them. Since the communication requirements between the motherboard and the power management unit are less than those between the motherboard and the timing controller, the timing controller can still receive the addressing bytes during the process of the motherboard addressing the power management unit, but the probability of the timing controller misaddressing is greatly reduced.

[0022] However, while the above method can reduce the possibility of misaddressing, it requires the addition of a switching device MOS, a pull-up resistor R0, and a separate communication bus SDA0. It also occupies at least three communication interfaces PIN1, PIN39, and PIN40 in the display device, increasing hardware costs and hindering the reduction in display device size. Therefore, how to reduce the risk of misaddressing without increasing hardware is a problem that those skilled in the art are dedicated to solving. Based on this, embodiments of this application are proposed.

[0023] According to the first aspect of this application, referring to Figure 2 , Figure 3 and Figure 4 This application provides a display device, including a timing controller 10 and a power management module 20. The timing controller 10 and the power management module 20 are connected to the same communication interface via a communication bus 30, and the communication interface is used for data interaction with the motherboard.

[0024] Reference Figure 2 To further illustrate the architecture of the display device in this application, the display device also includes a gate driving circuit 40 and a source driving circuit 50. The display device has a display area 60, which may include multiple scan lines G1 to Gn, multiple data lines SDAD1 to Dm intersecting the scan lines G1 to Gn, and multiple pixel units respectively disposed in multiple regions defined by the intersections of the scan lines G1 to Gn and the data lines SDAD1 to Dm. For example, a pixel unit may include a thin-film transistor, which includes a gate and a source respectively connected to its corresponding scan line and data line SDA.

[0025] The power management module 20 provides analog voltage as a power supply for the timing controller 10, the source drive circuit 50, the gate drive circuit 40, and each pixel unit. Simultaneously, the power management module 20 can communicate with the external motherboard and the timing controller 10 to adjust the analog voltage according to their requirements. The timing controller 10 receives data from the motherboard and generates clock signals, image data, and control signals based on this data. It then performs preprocessing on the image data, such as format conversion and data sorting, to obtain data signals. These data signals and control signals are then sent to the source drive circuit 50 and the gate drive circuit 40, respectively. The gate drive circuit 40 receives the control signal and clock signal from the timing controller 10 to generate progressive scan gate drive signals. These gate drive signals sequentially turn the thin-film transistor switches in the display area 60 on or off, controlling the selection of scan lines. After receiving the data signal and control signal from the timing controller 10, the source drive circuit 50 stores the data signal in the internal register and outputs it synchronously to the pixel unit according to the scan signal of the gate drive circuit 40. When a scan line is selected from multiple scan lines G1 to Gn, the thin film transistor of the pixel unit connected to the selected scan line is turned on. Then the source drive circuit 50 can apply data signals to multiple data lines SDAD1 to Dm, thereby completing the display of the image.

[0026] Reference Figure 4 The power management module 20 is configured to execute steps S101 and S102, which will be described in detail below.

[0027] Step S101: Receive the first target address byte on the communication bus 30. If the first target address byte matches the built-in address byte of the power management module 20, then receive the target verification byte on the communication bus 30.

[0028] The first target address byte is an addressing byte used to establish a communication connection with the power management module 20. It can be sent to the communication bus 30 by the motherboard or the timing controller 10 as the master device, and the power management module 20 as the slave device receives the first target address byte. The power management module 20 internally stores a built-in address byte, which serves as its identifier. The received first target address byte is compared with the built-in address byte. Only when the first target address byte and the built-in address byte match is the addressing successful, allowing continued reception of data from the communication bus 30. For example, if the first target address byte does not match the built-in address byte of the power management module 20, the power management module 20 stops receiving data from the communication bus 30.

[0029] Step S102: If the target verification byte matches the built-in verification byte of the power management module 20, then power drive data on the communication bus 30 is received to perform corresponding read and write operations based on the power drive data.

[0030] The target verification byte verifies the read / write permissions of the power management module 20. After the first target address byte matches, although the power management module 20 establishes a communication connection with the host device (motherboard or timing controller 10), the host device cannot read or write data to the power management module 20 at this time. Only when the target verification byte matches the built-in verification byte of the power management module 20 is the read / write permission of the power management module 20 enabled, allowing the power management module 20 to perform corresponding read / write operations based on the power drive data.

[0031] As an example, if the target verification byte does not match the built-in verification byte of the power management module 20, the communication connection with the master device is disconnected.

[0032] In the above implementation, firstly, by matching the first target address byte, the uniquely identified power management module 20 on the communication bus 30 can be preliminarily addressed to establish a communication connection and receive the target verification byte. Next, by matching the target verification byte, the addressing process can be reconfirmed, and addressing and read / write permissions can be separated. After establishing a communication connection by matching the first target address byte, read / write permissions are not directly granted; only after matching the target verification byte will the power drive data on the communication bus 30 be received, and corresponding read / write operations be performed based on the power drive data. Thus, without adding any hardware, even in the event of misaddressing, the power management module 20 will not be misread or written, thereby ensuring the normal operation of the display device.

[0033] Reference Figure 5 In some embodiments, the power drive data includes first drive data. The timing controller 10 and the power management module 20 are connected via a communication bus 30. The timing controller 10 is configured to execute steps S201-S203, which will be described in detail below.

[0034] Step S201: When it is necessary to establish communication with the power management module 20, determine the first target address byte of the power management module 20 from the preset address table, and transmit the first target address byte to the communication bus 30.

[0035] The preset address table is a table pre-stored in the timing controller 10. The preset address table stores the first target address byte of at least one power management module 20. When the timing controller 10 needs to establish communication with the corresponding power management module 20, it retrieves the first target address byte of the power management module 20 from the preset address table in order to communicate with the corresponding power management module 20.

[0036] Step S202: In response to the first acknowledgment signal transmitted from the power management module 20 on the communication bus 30, the target verification byte of the power management module 20 is determined from the preset key table, and the target verification byte is transmitted to the communication bus 30.

[0037] The first response signal indicates that the communication connection between the timing controller 10 and the power management module 20 has been successfully established. The preset key table is a table pre-stored in the timing controller 10. The preset key table stores at least one target verification byte of the power management module 20. When the timing controller 10 needs to establish communication with the power management module 20, it queries the preset key table to retrieve the target verification byte of the power management module 20 to verify the read and write permissions of the power management module 20.

[0038] Step S203: In response to the second acknowledgment signal from the power management module 20 and transmitted on the communication bus 30, transmit the first drive data to the communication bus 30.

[0039] The second response signal is used to indicate that the timing controller 10 and the power management module 20 have read and write permissions. At this time, the first drive data is transmitted to the communication bus 30 to avoid the timing controller 10 transmitting the first drive data to the wrong power management module 20.

[0040] In the above implementation, firstly, a first target address byte is determined through a preset address table and transmitted to the communication bus 30, enabling the timing controller 10 to quickly establish a communication connection with the corresponding power management module 20. Next, upon receiving a first response signal from the power management module 20, a target verification byte is determined from a preset key table and transmitted. Verification using the target verification byte avoids erroneous readings and writes to the power management module 20. Finally, upon receiving a second response signal, first drive data is transmitted, indicating that the timing controller 10 and the power management module 20 have read / write permissions. At this point, the timing controller 10 then transmits the first drive data to the power management module 20, thereby preventing erroneous readings and writes between the timing controller 10 and the power management module 20.

[0041] Reference Figure 6 In some implementations, the power drive data includes second drive data. The motherboard is configured to execute steps S301-S303, which will be described in detail below.

[0042] Step S301: When it is necessary to establish communication with the power management module 20, the first target address byte of the power management module 20 is determined from the preset address table, and the first target address byte is transmitted to the communication bus 30 through the communication interface.

[0043] Step S302: In response to the first response signal transmitted from the power management module 20 and on the communication bus 30, determine the target verification byte of the power management module 20 from the preset key table, and transmit the target verification byte to the communication bus 30 through the communication interface.

[0044] Step S303: In response to the second acknowledgment signal from the power management module 20 and transmitted on the communication bus 30, transmit the second drive data to the communication bus 30.

[0045] As an example, the difference between the communication process between the motherboard and the power management module 20 and the communication process between the timing controller 10 and the power management module 20 is that the motherboard needs to transmit data to the communication bus 30 through the communication interface. The rest of the communication process is the same, and the first target address byte and the target verification byte need to be queried through the preset address table and the preset key table for verification, so as to avoid erroneous read and write between the motherboard and the power management module 20.

[0046] In some implementations, the power management module 20 is also configured to execute steps S104-S105, which will be described in detail below.

[0047] Step S104: After the first target address byte matches the built-in address byte of the power management module 20, output the first response signal to the communication bus 30.

[0048] Step S105: After the target verification byte matches the built-in verification byte of the power management module 20, output a second response signal to the communication bus 30.

[0049] Specifically, the first response signal reports successful addressing to the timing controller 10 or the motherboard, enabling the timing controller 10 or the motherboard to continue outputting the target verification byte to the communication bus 30. The second response signal reports successful read / write permission verification to the timing controller 10 or the motherboard, enabling the timing controller 10 or the motherboard to output first drive data or second drive data to the communication bus 30.

[0050] In some embodiments, the timing controller 10 is also configured to execute steps S204-S205, which will be described in detail below.

[0051] Step S204: Receive the second target address byte on the communication bus 30. If the second target address byte matches the built-in address byte of the timing controller 10, output a third response signal to the communication bus 30 and transmit the third response signal to the motherboard through the communication interface so that the motherboard can transmit display driver data to the communication bus 30 through the communication interface.

[0052] Step S205: Receive display driver data on communication bus 30, and perform corresponding read / write operations based on the display driver data.

[0053] In the above embodiments, since the communication between the timing controller 10 and the motherboard is more frequent and the misaddressing situation is less likely to occur, and the communication efficiency requirements between the timing controller 10 and the motherboard are higher, the timing controller 10 can directly receive the display driver data on the communication bus 30 and perform read and write operations after verifying that the second target address byte is successfully addressed, so as to improve the communication efficiency.

[0054] Reference Figure 2 In some embodiments, the power management module 20 includes a power management chip 21 and a backlight power driver chip 22. The built-in address bytes of the power management chip 21 and the backlight power driver chip 22 are different. The built-in verification bytes of the power management chip 21 and the backlight power driver chip 22 are also different.

[0055] The power management chip 21 (Power Management Integrated Circuit, PMIC) has its input connected to an external power supply, and its output is converted from a single voltage to multiple output voltages via a voltage converter within the display panel. These output voltages are then distributed to the source driver circuit 40, the gate driver circuit 50, and the timing control chip to achieve power distribution within the display device. The backlight power driver chip 22 (Light-Emitting Diode Driver, LED Driver) can be connected to either an external power supply or the power management chip 21. It uses either the external power supply or the power management chip 21 as a power input to provide a constant current output to the pixel units. Simultaneously, it can adjust the current duty cycle through pulse width modulation to control the backlight brightness of the pixel units.

[0056] In the above embodiments, the power management chip 21 and the backlight power driver chip 22 have different built-in address bytes and built-in verification bytes, so that the timing controller 10 and the motherboard can communicate with the power management chip 21 and the backlight power driver chip 22 respectively.

[0057] Reference Figure 3In some embodiments, the communication bus 30 includes a data line SDA and a clock line SCL. The communication interface includes a first interface and a second interface. One end of the data line SDA is connected to the first interface, and the other end is connected to the timing controller 10 and the power management module 20, respectively. One end of the clock line SCL is connected to the second interface, and the other end is connected to the timing controller 10 and the power management module 20, respectively.

[0058] Reference Figure 3 In some embodiments, the communication bus 30 includes a pull-up module 31 for providing a high-level state for the data line SDA and the clock line SCL. The pull-up module 31 includes a first resistor R1 and a second resistor R2. The first resistor R1 includes a first terminal connected to a voltage source and a second terminal connected to the clock line SCL. The second resistor R2 includes a first terminal connected to a voltage source and a second terminal connected to the data line SDA.

[0059] In the above embodiment, since the power management module 20 requires verification of both the first target address byte and the target verification byte before read / write operations are allowed, the power management module 20 and the timing controller 10 can share a single communication bus 30. Accordingly, only the first interface and the second interface need to be connected to the motherboard. Furthermore, only one pull-up module 31 needs to be configured on the communication bus 30, using the first resistor R1 and the second resistor R2 to pull up the data line SDA and the clock line SCL, respectively. This eliminates the need for additional circuit components, reducing hardware costs and the space occupied by the circuitry.

[0060] According to a second aspect of this application, a communication method for a display device is provided, based on the above-described display device and applied to a power management module 20, the method comprising steps S101-S102.

[0061] Step S101: Receive the first target address byte on the communication bus 30. If the first target address byte matches the built-in address byte of the power management module 20, then receive the target verification byte on the communication bus 30.

[0062] Step S102: If the target verification byte matches the built-in verification byte of the power management module 20, then power drive data on the communication bus 30 is received to perform corresponding read and write operations based on the power drive data.

[0063] According to a third aspect of this application, a communication method for a display device is provided. Based on the above-described display device, it is applied to a timing controller 10. The timing controller 10 is connected to a power management module 20 via a communication bus 30. The method includes steps S201-S203, which will be described in detail below.

[0064] Step S201: When it is necessary to establish communication with the power management module 20, determine the first target address byte of the power management module 20 from the preset address table, and transmit the first target address byte to the communication bus 30.

[0065] Step S202: In response to the first acknowledgment signal transmitted from the power management module 20 on the communication bus 30, the target verification byte of the power management module 20 is determined from the preset key table, and the target verification byte is transmitted to the communication bus 30.

[0066] Step S203: In response to the second acknowledgment signal from the power management module 20 and transmitted on the communication bus 30, transmit the first drive data to the communication bus 30.

[0067] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0069] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0070] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display device, characterized in that, Includes a timing controller and a power management module; The timing controller and the power management module are connected to the same communication interface via a communication bus, and the communication interface is used to interact with the motherboard. The power management module is configured as follows: Receive a first target address byte on the communication bus; if the first target address byte matches the built-in address byte of the power management module, then receive a target verification byte on the communication bus. If the target verification byte matches the built-in verification byte of the power management module, then power drive data on the communication bus is received to perform corresponding read / write operations based on the power drive data.

2. The display device according to claim 1, characterized in that, The power drive data includes first drive data; the timing controller and the power management module are connected via the communication bus; the timing controller is configured to: When it is necessary to establish communication with the power management module, the first target address byte of the power management module is determined from the preset address table, and the first target address byte is transmitted to the communication bus; In response to a first acknowledgment signal from the power management module and transmitted on the communication bus, the target verification byte of the power management module is determined from a preset key table, and the target verification byte is transmitted to the communication bus; In response to a second acknowledgment signal from the power management module and transmitted on the communication bus, the first drive data is transmitted to the communication bus.

3. The display device according to claim 1, characterized in that, The power drive data includes second drive data; the motherboard is configured as follows: When it is necessary to establish communication with the power management module, the first target address byte of the power management module is determined from the preset address table, and the first target address byte is transmitted to the communication bus through the communication interface; In response to a first acknowledgment signal transmitted from the power management module on the communication bus, the target verification byte of the power management module is determined from a preset key table, and the target verification byte is transmitted to the communication bus through the communication interface; In response to a second acknowledgment signal from the power management module and transmitted on the communication bus, the second drive data is transmitted on the communication bus.

4. The display device according to claim 2 or 3, characterized in that, The power management module is also configured to: After the first target address byte matches the built-in address byte of the power management module, the first response signal is output to the communication bus; After the target verification byte matches the built-in verification byte of the power management module, the second response signal is output to the communication bus.

5. The display device according to claim 1, characterized in that, The timing controller is also configured to: The system receives a second target address byte on the communication bus. If the second target address byte matches the built-in address byte of the timing controller, it outputs a third response signal to the communication bus and transmits the third response signal to the motherboard through the communication interface, so that the motherboard can transmit display driver data to the communication bus through the communication interface. Receive display driver data from the communication bus to perform corresponding read / write operations based on the display driver data.

6. The display device according to any one of claims 1 to 5, characterized in that, The power management module includes a power management chip and a backlight power driver chip. The built-in address byte of the power management chip is different from the built-in address byte of the backlight power driver chip; The built-in verification byte of the power management chip is different from the built-in verification byte of the backlight power driver chip.

7. The display device according to any one of claims 1 to 5, characterized in that, The communication bus includes a data line and a clock line; the communication interface includes a first interface and a second interface. One end of the data cable is connected to the first interface, and the other end is connected to the timing controller and the power management module respectively. One end of the clock line is connected to the second interface, and the other end is connected to the timing controller and the power management module, respectively.

8. The display device according to claim 7, characterized in that, The communication bus includes a pull-up module for providing a high-level state for the data line and the clock line; The pull-up module includes a first resistor and a second resistor; The first resistor includes a first terminal connected to a voltage source and a second terminal connected to the clock line; The second resistor includes a first end connected to the voltage source and a second end connected to the data line.

9. A communication method for a display device, based on the display device according to any one of claims 1 to 8, applied to the power management module, characterized in that, The method includes: Receive a first target address byte on the communication bus; if the first target address byte matches the built-in address byte of the power management module, then receive a target verification byte on the communication bus. If the target verification byte matches the built-in verification byte of the power management module, then power drive data on the communication bus is received to perform corresponding read / write operations based on the power drive data.

10. A communication method for a display device, based on the display device according to any one of claims 1 to 8, applied to the timing controller, wherein the timing controller is connected to a power management module via the communication bus, characterized in that, The method includes: When it is necessary to establish communication with the power management module, the first target address byte of the power management module is determined from the preset address table, and the first target address byte is transmitted to the communication bus; In response to a first acknowledgment signal from the power management module and transmitted on the communication bus, the target verification byte of the power management module is determined from a preset key table, and the target verification byte is transmitted to the communication bus; In response to a second acknowledgment signal from the power management module and transmitted on the communication bus, first drive data is transmitted to the communication bus.

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