Key soft-off method and device for LRM server

Abstract

The invention discloses a key soft shutdown method and device of an LRM server. A second programmable logic device monitors serial port information output by a processor through a local bus in the starting process and sets a starting state flag bit of the processor according to the serial port information; the first programmable logic device receives a power-off level signal generated by the power-on and power-off key; in response to a shutdown level signal, the first programmable logic device obtains a starting state flag bit from the second programmable logic device; if the starting state flag bit indicates that the processor enters the starting state, the first programmable logic device informs the second programmable logic device of sending a hardware interrupt signal to the processor; and the processor responds to the hardware interrupt signal and triggers a corresponding operating system to execute a soft shutdown process. The soft shutdown of the operating system is triggered through the physical key in a peripheral-free environment, the problems of data loss and system damage caused by hard shutdown are avoided, and the reliability of the LRM server is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of server power control, and in particular to a key soft shutdown method and device for LRM server. BACKGROUND

[0002] In modern military information warfare system, mobile combat platforms such as vehicle-mounted, ship-mounted and aircraft-mounted platforms have high requirements for high reliability, rapid maintenance and environmental adaptability of computing servers. LRM (Locally Replaceable Module) server has become the core information processing hub in such environment due to its characteristics of modularity, high reliability, resistance to harsh environment and support for hot plug. However, in these strong vibration and extremely limited space application scenarios, the server usually cannot be equipped with regular display, keyboard and mouse peripherals, which brings great challenges to the shutdown operation that needs to be performed frequently or urgently.

[0003] At present, the power switch key of most LRM servers is directly connected to the FPGA chip pin responsible for power management. When the user presses the shutdown key, the signal directly triggers the power module to perform a "hard shutdown" action, that is, to immediately cut off the power supply to all hardware including the CPU. This rough power-off method causes the operating system and all background service processes to be terminated abnormally, without any chance to perform any preset orderly shutdown process. The direct consequence is that the key task data (such as real-time intelligence and combat orders) being processed will be instantly lost due to memory power-off. At the same time, the file system is forcibly interrupted in the writing process, which is extremely easy to cause damage to its metadata or key configuration files, which not only causes the failure of the task at this time, but also significantly increases the risk of the system failing to start normally next time. SUMMARY

[0004] The present application provides a key soft shutdown method and device for LRM server to solve the problem of data loss and system stability reduction caused by direct hard shutdown when shutting down through physical keys in a non-peripheral environment.

[0005] In a first aspect, the present application provides a key soft shutdown method for LRM server, comprising: The second programmable logic device monitors the serial port information output by the local bus during the startup process, and sets the startup state flag bit of the processor according to the serial port information; The first programmable logic device receives the shutdown level signal generated by the shutdown key; In response to the shutdown level signal, the first programmable logic device obtains the startup state flag bit from the second programmable logic device; If the startup state flag bit indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor; The processor responds to a hardware interrupt signal, triggering the corresponding operating system to execute a soft shutdown process; After the soft shutdown process is completed, the second programmable logic device controls the CPU module to power down.

[0006] Secondly, this application provides a button-based soft shutdown device for an LRM server, comprising: The startup status flag setting module is configured as a second programmable logic device to monitor the serial port information output by the processor through the local bus during the startup process, and to set the processor's startup status flag based on the serial port information. The power-off level signal receiving module is configured as the first programmable logic device to receive the power-off level signal generated by the power-on / off button; The startup status flag acquisition module is configured to, in response to a power-off level signal, acquire the startup status flag from the second programmable logic device using the first programmable logic device. The hardware interrupt signal sending module is configured such that if the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor. The soft shutdown process execution module is configured so that the processor responds to a hardware interrupt signal and triggers the corresponding operating system to execute the soft shutdown process; The CPU module power-off module is configured to power off the CPU module after the soft shutdown process is completed, controlled by the second programmable logic device.

[0007] Thirdly, this application provides a readable medium including executable instructions, which, when executed by a processor of an electronic device, cause the electronic device to perform any of the methods described in the first aspect.

[0008] Fourthly, this application provides an electronic device including a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor performs the method as described in any of the first aspects.

[0009] This application provides a method and apparatus for soft shutdown of an LRM server via a physical button. A second programmable logic device (PLD) monitors the serial port information output by the processor through the local bus during startup and sets the processor's startup status flag based on the serial port information. A first PLD receives a shutdown level signal generated by the power button. In response to the shutdown level signal, the first PLD obtains the startup status flag from the second PLD. If the startup status flag indicates that the processor has entered the startup state, the first PLD notifies the second PLD to send a hardware interrupt signal to the processor. The processor responds to the hardware interrupt signal, triggering the corresponding operating system to execute a soft shutdown process. After the soft shutdown process is completed, the second PLD controls the CPU module to power down. This method achieves a safe soft shutdown at the operating system level via a physical button in an environment without peripherals, effectively avoiding data loss and system damage caused by traditional hard shutdown methods, and significantly improving the reliability and data integrity of the LRM server in military mobile platforms.

[0010] The further effects of the aforementioned non-conventional preferred method will be explained below in conjunction with specific embodiments. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application or the existing technical solutions, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating a button-based soft shutdown method for an LRM server provided in an embodiment of this application; Figure 2 A flowchart illustrating another method for soft shutdown of an LRM server via a button, provided in an embodiment of this application; Figure 3 A flowchart illustrating another method for soft shutdown of an LRM server via a button, provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a button-based soft shutdown device for an LRM server provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] In modern military information warfare systems, mobile combat platforms such as vehicle-mounted, shipborne, and airborne platforms place stringent demands on the high reliability, rapid maintainability, and environmental adaptability of computing servers. LRM (Field Replaceable Module) servers, with their modularity, high reliability, resilience to harsh environments, and hot-swappability, have become the core information processing hub in such environments. However, in these application scenarios characterized by strong vibrations and extremely limited space, servers typically cannot be equipped with conventional peripherals such as monitors, keyboards, and mice, posing a significant challenge to the frequent or urgent shutdown operations required.

[0015] Currently, the power switch on most LRM servers is directly connected to the pins of the FPGA chip responsible for power management. When the user presses the power button, this signal directly triggers the power module to perform a "hard shutdown," immediately cutting off power to all hardware, including the CPU. This abrupt power outage causes the operating system and all background service processes to terminate abnormally, without any time to execute any pre-set orderly shutdown procedures. The direct consequence is that critical mission data being processed (such as real-time intelligence and combat instructions) is instantly lost due to the memory power failure. Simultaneously, the file system is forcibly interrupted during the write process, easily leading to corruption of its metadata or critical configuration files. This not only causes the current task to fail but also significantly increases the risk of the system failing to boot normally on subsequent occasions.

[0016] To address this issue, this application proposes a button-based soft shutdown method for an LRM server, aiming to resolve the data loss and reduced system stability caused by direct hard shutdown via a physical button in an environment without peripherals. In this embodiment, the button-based soft shutdown method for an LRM server is applied to an LRM server; the LRM server includes a front panel, a carrier board, and a CPU module; the front panel is equipped with a power button; the carrier board is equipped with a first programmable logic device and a power module; the CPU module is equipped with a second programmable logic device and a processor, including: Step 101: The second programmable logic device monitors the serial port information output by the processor through the local bus during the startup process, and sets the processor's startup status flag bit according to the serial port information.

[0017] During the LRM server startup process, the second programmable logic device (PLD) continuously monitors the processor's operating status in real time. When the processor starts up, it outputs a series of serial port messages via the local bus. These messages record the complete process from hardware self-test, firmware loading, kernel initialization to operating system startup. As a hardware-level monitoring module, the second PLD has the capability to capture and parse this serial port information in real time.

[0018] The serial port information is parsed to see if it contains predefined specific information, such as kernel boot completion messages or login prompts corresponding to the operating system. If specific information is detected, it is determined that the processor has entered the operating system, and the boot status flag is set to indicate that it has entered the boot state.

[0019] After receiving serial port information, the second programmable logic device analyzes its contents line by line to find predefined specific information identifiers. These specific information mainly include two types of key markers: one is the kernel startup completion message, indicating that the operating system kernel has been successfully loaded and started running; the other is the login prompt corresponding to the operating system, indicating that the operating system has fully entered an interactive working state.

[0020] When the second programmable logic device detects any specific information, it can determine that the processor has successfully entered the operating system environment. At this time, the boot status flag is set to "booted," usually represented by a logic value of 1. Conversely, when the processor is in the pre-boot stage, such as BIOS self-test, firmware loading, or kernel initialization, the boot status flag remains at 0, indicating "not booted." The accurate setting of this flag provides a crucial basis for subsequent determination of which shutdown method to use.

[0021] Step 102: The first programmable logic device receives the power-off level signal generated by the power-on / off button.

[0022] The first programmable logic device establishes a physical connection with the power button on the front panel via the GPIO general-purpose input / output interface. When the operator presses the power button to shut down the server, the mechanical action of the button triggers a change in the voltage level. Specifically, when the button is pressed from the released state, a voltage level transition occurs, and this voltage level change signal is transmitted to the GPIO pin of the first programmable logic device through the connection line.

[0023] The first programmable logic device (PLD) internally implements a signal debouncing mechanism to filter out glitches caused by button mechanical bounce, ensuring that only genuine and valid button presses are detected. According to the system design, when the power button is released and pulled low, the PLD identifies this signal as a power-off signal. Successful reception of this signal signifies that the user has issued a power-off request, and the system needs to initiate the corresponding power-off process.

[0024] Step 103: In response to the power-off level signal, the first programmable logic device obtains the startup status flag bit from the second programmable logic device.

[0025] When the first programmable logic device confirms receipt of a valid power-off level signal, it does not immediately perform a power-off operation. Instead, it first needs to determine the current operating state of the processor to decide on the power-off method. Since the startup status flag is stored in the second programmable logic device, the first programmable logic device needs to obtain the startup status flag through the inter-device communication interface.

[0026] A data transmission channel is established between the two programmable logic devices (PLDs) via a serial communication interface. The first PLD sends a query request to the second PLD. Upon receiving the request, the second PLD reads the current startup status flag value from its internal register and sends this flag information back to the first PLD via the serial interface. This process enables cross-module status information sharing, allowing the first PLD, located on the carrier board, to accurately grasp the real-time operating status of the processor on the CPU module. After obtaining the startup status flag, the first PLD can select the subsequent shutdown processing strategy based on the value of the startup status flag.

[0027] Step 104: If the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor.

[0028] The first programmable logic device sends a trigger instruction to the second programmable logic device through a serial communication interface; in response to the trigger instruction, the second programmable logic device sends a hardware interrupt signal to the processor through a local bus connected to the processor; the hardware interrupt signal includes a system management interrupt signal or a platform management interrupt signal.

[0029] The first programmable logic device (PLD) performs a determination after acquiring the startup status flag. When the startup status flag is 1, indicating "entered startup state," it means the processor is currently running in an operating system environment. At this time, the operating system may be performing various tasks, including critical military tasks such as intelligence processing, communication relay, and data storage. The system memory contains a large amount of important data that has not yet been persisted, and the file system may also be performing write operations. In this situation, directly cutting off the power for a hard shutdown will forcibly interrupt all ongoing work, causing data loss and system damage.

[0030] Therefore, the first programmable logic device (PLD) will choose to safely shut down the system via a soft shutdown. Specifically, the first PLD sends a trigger command to the second PLD via a serial communication interface, carrying the semantic information of "requesting a soft shutdown." Upon receiving the trigger command, the second PLD sends a hardware interrupt signal to the processor via its local bus connected to the processor.

[0031] Hardware interrupt signals can be system management interrupt signals or platform management interrupt signals. These interrupts have high priority and can interrupt the processor's current execution flow, causing the processor to respond immediately. After receiving an interrupt signal, the processor will suspend the execution of the current task and start processing the shutdown interrupt request, thereby triggering the operating system-level soft shutdown process. This mechanism of triggering soft shutdown through hardware interrupts ensures that even when there are no peripherals and operation is not possible through the software interface, the normal shutdown procedure of the operating system can be safely initiated via physical buttons.

[0032] Step 105: The processor responds to the hardware interrupt signal and triggers the corresponding operating system to execute the soft shutdown process.

[0033] Upon receiving a hardware interrupt signal, the processor transmits the interrupt event to the operating system via the ACPI advanced configuration and power management interface. Once the operating system recognizes this as a shutdown request, it immediately initiates a pre-defined soft shutdown procedure. This procedure is a carefully designed orderly shutdown process by the operating system to ensure data integrity and system consistency.

[0034] Close background service processes running on the operating system; save the system status information and current running data corresponding to the operating system; synchronize the cache data corresponding to the operating system; release the resources occupied by the operating system; shut down the operating system and send a shutdown ready signal to the second programmable logic device.

[0035] The soft shutdown process first shuts down all background service processes running on the operating system. These processes may include database services, network communication services, logging services, etc. Each process performs necessary cleanup tasks before shutdown, such as releasing occupied network ports, closing open file handles, and disconnecting database connections. Next, the operating system saves the current system state information and running data, including information on tasks being processed, system configuration parameters, user session states, and other critical data, ensuring that this data is correctly written to non-volatile storage media.

[0036] Simultaneously, the operating system synchronizes all cached data. During normal operation, to improve performance, the operating system temporarily stores some data in a memory cache, delaying its write to disk. The synchronization operation forces all this cached data to be flushed to disk, ensuring that all modifications are persistently stored and preventing data loss due to power outages. Afterward, the operating system releases all occupied resources, including memory space, device handles, file locks, etc., ensuring that resources are properly released and preventing resource leaks.

[0037] Finally, once all cleanup is complete, the operating system will officially shut down and send a shutdown ready signal to the second programmable logic device. This signal notifies the hardware level that the software shutdown process is complete and the system is in a safe power-off state. The entire soft shutdown process ensures the complete preservation of data, the consistency of the file system, and the correct storage of system configuration, avoiding the various risks that may arise from a hard shutdown.

[0038] Step 106: After the soft shutdown process is completed, the second programmable logic device controls the CPU module to power down.

[0039] After receiving the shutdown readiness signal from the operating system, the second programmable logic device confirms that the software-level shutdown process has been successfully completed. At this point, it can safely disconnect the power supply to the CPU module. The second programmable logic device controls the power management circuitry inside the CPU module to gradually shut down the power supply to the CPU and its peripheral components. This power-down process is orderly and follows a predetermined power-down sequence, first shutting down secondary power rails and finally core power, ensuring that the power-down process does not cause electrical shock to the hardware.

[0040] Once the CPU module is fully powered down, the second programmable logic device updates its internal power status flag to 0, indicating that the CPU module is powered down. This flag update provides a basis for subsequent power-down operations on the carrier board. Compared to hard shutdown, this soft shutdown method ensures that all data is safely saved, all system resources are correctly released, and the file system has completed synchronization before power loss. This completely avoids data loss and file system corruption caused by sudden power outages, significantly improving system reliability and data integrity.

[0041] If the startup status flag indicates that the CPU module has not entered the startup state, the first programmable logic device controls the second programmable logic device to perform a hard power-down operation on the CPU module.

[0042] If the boot status flag indicates "not in boot state", that is, when the flag is 0, it means that the processor is currently in the stage of BIOS self-test, firmware loading or operating system startup. At this time, there is no complete operating system running, nor is there any task data or file system state that needs to be protected.

[0043] In this scenario, the first programmable logic device directly controls the second programmable logic device to perform a hard power-down operation on the CPU module, immediately cutting off the power supply and quickly completing the shutdown. This design, which intelligently selects the shutdown method based on the processor's startup state, ensures data security in the operating system environment while avoiding unnecessary soft shutdown procedures in non-operating system environments, thus improving shutdown efficiency.

[0044] As can be seen from the above technical solutions, the beneficial effects of this embodiment are: This application provides a method for soft shutdown of an LRM server via a physical button. A second programmable logic device (PLD) monitors the serial port information output by the processor through the local bus during startup and sets the processor's startup status flag based on the serial port information. A first PLD receives a shutdown level signal generated by the power button. In response to the shutdown level signal, the first PLD obtains the startup status flag from the second PLD. If the startup status flag indicates that the processor has entered the startup state, the first PLD notifies the second PLD to send a hardware interrupt signal to the processor. The processor responds to the hardware interrupt signal, triggering the corresponding operating system to execute a soft shutdown process. After the soft shutdown process is completed, the second PLD controls the CPU module to power down. This method achieves a safe soft shutdown at the operating system level via a physical button in an environment without peripherals, effectively avoiding data loss and system damage caused by traditional hard shutdown methods, and significantly improving the reliability and data integrity of the LRM server in military mobile platforms.

[0045] Figure 1 The above is only a basic embodiment of a button-based soft shutdown method for an LRM server according to this application. With certain optimizations and extensions, other preferred embodiments of the button-based soft shutdown method for an LRM server can be obtained.

[0046] like Figure 2 The image shows another specific embodiment of a button-based soft shutdown method for an LRM server according to this application.

[0047] In this embodiment, a method for soft shutdown of an LRM server via a button includes the following steps: Step 201: The second programmable logic device monitors the serial port information output by the processor through the local bus during the startup process, and sets the startup status flag bit of the processor according to the serial port information.

[0048] Step 202: The first programmable logic device receives the power-off level signal generated by the power-on / off button.

[0049] Step 203: In response to the power-off level signal, the first programmable logic device obtains the startup status flag bit from the second programmable logic device.

[0050] Step 204: If the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor.

[0051] Step 205: The processor responds to the hardware interrupt signal and triggers the corresponding operating system to execute the soft shutdown process.

[0052] Step 206: After the soft shutdown process is completed, the second programmable logic device controls the CPU module to power down.

[0053] Step 207: After the second programmable logic device detects that the CPU module has been powered down, it sets the power status flag bit.

[0054] After performing a power-down operation on the CPU module, the second programmable logic device (PLD) needs to continuously monitor the completion status of the power-down process. The power-down process involves shutting down multiple power supply rails and discharging capacitors, requiring a certain amount of time to ensure all power supplies are completely disconnected and the voltage drops to a safe level. The PLD determines whether the power-down operation has been fully completed by monitoring the power supply voltage and power enable signal inside the CPU module.

[0055] When it is detected that the voltage of all power rails of the CPU module has dropped below the threshold and all power enable signals are in the off state, the second programmable logic device confirms that the CPU module has completed power-down. At this time, the second programmable logic device updates the power status flag in its internal register, setting the power status flag to 0, indicating that the CPU module has completed power-down.

[0056] The power status flag is a state transition point in the shutdown process, providing a reliable basis for the first programmable logic device to determine whether the carrier board can be powered down. Real-time monitoring of the power status and accurate setting of the flag at the hardware level ensure that each step of the shutdown process is executed in the correct order, preventing electrical abnormalities or hardware damage that could occur if the carrier board is powered down before the CPU module is fully powered down.

[0057] Step 208: The first programmable logic device obtains the power status flag bit from the second programmable logic device.

[0058] After the first programmable logic device notifies the second programmable logic device to power down the CPU module, it needs to confirm whether the CPU module has safely completed the power-down process before proceeding to the next step of powering down the carrier board. To do this, the first programmable logic device sends a query request to the second programmable logic device again via the serial communication interface to obtain the current power status flag.

[0059] After receiving the query request, the second programmable logic device reads the current value of the power status flag from its internal register and sends this information back to the first programmable logic device via the serial interface. Upon receiving the power status flag, the first programmable logic device checks its value. If the power status flag is 0, it indicates that the CPU module has been completely powered down; if the power status flag is 1, it indicates that the CPU module's power-down process is not yet complete and may still be undergoing capacitor discharge or a power-off sequence.

[0060] If the CPU module is not fully powered down, the first programmable logic device will not immediately perform the power-down operation on the carrier board. Instead, it will wait for a period of time, such as 100 milliseconds, and then query the power status flag bit of the second programmable logic device again. This polling process is repeated until the CPU module is confirmed to be powered down. This synchronization mechanism based on status flag bits ensures the orderly execution of each power-down step in the shutdown process, avoids electrical anomalies caused by timing disorder, and improves the reliability and safety of the shutdown process.

[0061] Step 209: If the power status flag indicates that the CPU module has been powered down, the first programmable logic device controls the power module to power down the carrier board.

[0062] Once the first programmable logic device confirms that the power status flag indicates the CPU module has been powered down, it can safely perform the power-down operation on the carrier board. At this point, the CPU module is completely powered off and no longer consumes power from the carrier board. All other components on the carrier board, except for the first programmable logic device and the power module, are also in a state where they can be powered off.

[0063] The first programmable logic device sends a shutdown command to the power module, controlling the power module to stop supplying power to the carrier board. Upon receiving the command, the power module will gradually shut down the power supply rails to various parts of the carrier board according to a predetermined power shutdown sequence, ultimately cutting off all power output. Once the carrier board is completely powered down, the entire shutdown process of the LRM server is complete, and the server enters a completely power-off shutdown state, no longer consuming any power.

[0064] As can be seen from the above technical solution, the beneficial effects of this embodiment are as follows: By using a second programmable logic device to monitor the CPU module's power-down completion status in real time and set a power status flag, combined with the mechanism of the first programmable logic device using this flag to determine the power-down of the carrier board, a hierarchical and orderly power-down between the CPU module and the carrier board is achieved. This design ensures that the carrier board power-down operation is performed only after the CPU module is completely powered off, avoiding electrical abnormalities or hardware damage caused by disordered power-down timing, and improving the reliability and safety of the shutdown process.

[0065] like Figure 3 The image shows another specific embodiment of a button-based soft shutdown method for an LRM server according to this application. This embodiment is further described based on the foregoing embodiments.

[0066] In this embodiment, a method for soft shutdown of an LRM server via a button includes the following steps: Step 301: The second programmable logic device monitors the serial port information output by the processor through the local bus during the startup process, and sets the processor's startup status flag bit according to the serial port information.

[0067] Step 302: The first programmable logic device receives the power-off level signal generated by the power-on / off button.

[0068] Step 303: In response to the power-off level signal, the first programmable logic device obtains the startup status flag bit from the second programmable logic device.

[0069] Step 304: If the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor.

[0070] Step 305: The processor responds to the hardware interrupt signal and triggers the corresponding operating system to execute the soft shutdown process.

[0071] Step 306: After the soft shutdown process is completed, the second programmable logic device controls the CPU module to power down.

[0072] Step 307: In response to the power-on level signal, the first programmable logic device controls the power module to power on the carrier board and sends a CPU power enable signal to the second programmable logic device.

[0073] When an operator needs to start the LRM server, they press the power button on the front panel. Pressing the button triggers a voltage level transition. When the power button is pressed high, this voltage level change signal is transmitted to the first programmable logic device (PLD) via the GPIO interface. The signal processing circuitry inside the PLD performs debouncing and status recognition on the received voltage level signal. When a rising edge signal from low to high is detected, it is identified as a power-on signal, indicating that the user has requested to start the server.

[0074] Upon receiving a valid power-on signal, the first programmable logic device (PLD) immediately executes the power-on process. First, the PLD sends a power-on control command to the power module, instructing it to begin supplying power to the carrier board. Upon receiving the command, the power module activates its internal power conversion circuit, converting the input raw power into the various operating voltages required by the carrier board. Following a predetermined power-on sequence, it sequentially activates each power supply rail, providing a stable operating voltage to the electronic components on the carrier board.

[0075] Simultaneously, the first programmable logic device also sends a CPU power enable signal to the second programmable logic device located on the CPU module via a serial communication interface. This enable signal is a control signal used to notify the second programmable logic device that the carrier board has started powering on, the system is booting up, and requests the second programmable logic device to prepare to power on the CPU module. Electrically, the first programmable logic device pulls a dedicated CPU power enable signal line high, changing its level from low to high. This level change is detected by the input interface of the second programmable logic device.

[0076] Step 308: The second programmable logic device responds to the CPU power enable signal and controls the CPU module to power on.

[0077] The second programmable logic device (PLD), acting as the power management control unit on the CPU module, continuously monitors the CPU power enable signal from the first PLD. When the input interface of the second PLD detects that the CPU power enable signal changes from low to high, it recognizes that this is a power-on request for the CPU module issued by the first PLD. At this point, the carrier board has completed or is in the process of completing the power-on process, and the system's basic power supply and communication environment are ready.

[0078] Upon receiving the CPU power enable signal, the second programmable logic device immediately initiates the power-on control process of the CPU module. The CPU module contains the CPU processor and several peripheral components, such as the memory controller, cache, and voltage regulator. These components require power-on according to a specific timing sequence to ensure stable system startup. The second programmable logic device controls the power management circuitry within the CPU module, sequentially activating each power supply rail according to a preset power-on sequence.

[0079] Once all power rails have successfully powered on and reached a stable operating state, the second programmable logic device (PLD) releases the CPU's reset signal, causing the CPU to exit the reset state and begin executing its internal initialization code. The CPU then enters the BIOS self-test phase, begins detecting and initializing hardware resources, loads the firmware program, and finally boots the operating system. The entire power-on process is controlled and monitored by the second PLD to ensure the CPU module can start safely and orderly.

[0080] As can be seen from the above technical solution, the beneficial effects of this embodiment are as follows: A hierarchical startup mechanism is implemented, where the first programmable logic device responds to the power-on level signal to control the power supply module to power on the carrier board, and the CPU power enable signal triggers the second programmable logic device to control the power-on of the CPU module. This achieves an orderly power-on process between the carrier board and the CPU module. This design ensures that power is supplied to the carrier board and the CPU module sequentially according to the correct timing, avoiding instantaneous high-current surges and voltage instability caused by simultaneous power-on, thus protecting the safety of the power supply module and hardware circuitry.

[0081] like Figure 4 The image shown is a specific embodiment of a button-based soft shutdown device for an LRM server according to this application. This embodiment provides a button-based soft shutdown device for an LRM server, specifically used for executing... Figures 1-3 A physical device for a button-based soft shutdown method for an LRM server is provided. Its technical solution is essentially the same as the above embodiments, and the corresponding descriptions in the above embodiments are also applicable to this embodiment. This embodiment of a button-based soft shutdown device for an LRM server includes: The startup status flag setting module 401 is configured as a second programmable logic device to monitor the serial port information output by the processor through the local bus during the startup process, and to set the startup status flag of the processor according to the serial port information. The power-off level signal receiving module 402 is configured as a first programmable logic device to receive the power-off level signal generated by the power-on / off button; The startup status flag acquisition module 403 is configured to, in response to a power-off level signal, acquire the startup status flag from the second programmable logic device; The hardware interrupt signal sending module 404 is configured such that if the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor. The soft shutdown process execution module 405 is configured so that the processor responds to a hardware interrupt signal and triggers the corresponding operating system to execute the soft shutdown process. The CPU module power-off module 406 is configured such that after the soft shutdown process is completed, the second programmable logic device controls the CPU module to power off.

[0082] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and a memory. The memory may include RAM, such as high-speed random-access memory (RAM), or non-volatile memory, such as at least one disk storage device. Of course, the electronic device may also include other hardware required for other services.

[0083] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0084] Memory is used to store instructions for execution. Specifically, instructions for execution are computer programs that can be executed. Memory can include main memory and non-volatile memory, and it provides the processor with execution instructions and data.

[0085] In one possible implementation, the processor reads the corresponding execution instructions from non-volatile memory into main memory and then executes them. Alternatively, it may obtain the corresponding execution instructions from other devices to logically form a button-based soft shutdown device for an LRM server. The processor executes the execution instructions stored in the memory to implement a button-based soft shutdown method for an LRM server provided in any embodiment of this application.

[0086] The above is as stated in this application. Figure 4 The method for executing a button-based soft shutdown device of an LRM server provided in the illustrated embodiment can be applied to a processor, or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor.

[0087] The steps of the method disclosed in the embodiments of this application can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0088] This application also proposes a readable medium storing execution instructions. When these instructions are executed by the processor of an electronic device, the electronic device can perform a button-based soft shutdown method for an LRM server provided in any embodiment of this application, specifically for executing, for example... Figure 1 or Figure 2 or Figure 3 The method shown.

[0089] The electronic devices in the foregoing embodiments may be computers.

[0090] Those skilled in the art will understand that the embodiments of this application can be provided as methods or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or a combination of software and hardware.

[0091] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0092] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0093] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for soft shutdown of an LRM server via a button, characterized in that, The method is applied to an LRM server; the LRM server includes a front panel, a carrier board, and a CPU module; the front panel is provided with a power button; the carrier board is provided with a first programmable logic device and a power module; The CPU module is equipped with a second programmable logic device and a processor, and the method includes: The second programmable logic device monitors the serial port information output by the processor through the local bus during the startup process, and sets the startup status flag bit of the processor according to the serial port information; The first programmable logic device receives the power-off level signal generated by the power-on / off button; In response to the power-off level signal, the first programmable logic device obtains the startup status flag bit from the second programmable logic device; If the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor. The processor responds to the hardware interrupt signal and triggers the corresponding operating system to execute a soft shutdown process. After the soft shutdown process is completed, the second programmable logic device controls the CPU module to power down.

2. The method according to claim 1, characterized in that, Setting the processor's startup status flag based on the serial port information includes: The serial port information is analyzed to determine whether it contains predefined specific information, including kernel startup completion messages or login prompts corresponding to the operating system. If the specific information is detected, it is determined that the processor has entered the operating system, and the boot status flag is set to indicate that the processor has entered the boot state.

3. The method according to claim 1, characterized in that, The first programmable logic device instructs the second programmable logic device to send a hardware interrupt signal to the processor, including: The first programmable logic device sends a trigger command to the second programmable logic device through a serial communication interface; In response to the trigger instruction, the second programmable logic device sends the hardware interrupt signal to the processor via a local bus connected to the processor; the hardware interrupt signal includes a system management interrupt signal or a platform management interrupt signal.

4. The method according to claim 1, characterized in that, The operating system's soft shutdown process includes: Shut down the background service processes running on the operating system; Save the system status information and current running data corresponding to the operating system; Synchronize the cached data corresponding to the operating system; Release the resources occupied by the operating system; The operating system is shut down, and a power-off ready signal is sent to the second programmable logic device.

5. The method according to claim 1, characterized in that, After the second programmable logic device controls the CPU module to power down, it further includes: After detecting that the CPU module has been powered down, the second programmable logic device sets the power status flag bit; The first programmable logic device obtains the power status flag bit from the second programmable logic device; If the power status flag indicates that the CPU module has been powered down, the first programmable logic device controls the power module to power down the carrier board.

6. The method according to claim 1, characterized in that, Also includes: If the startup status flag indicates that the startup state has not been entered, the first programmable logic device controls the second programmable logic device to perform a hard power-down operation on the CPU module.

7. The method according to claim 1, characterized in that, If the first programmable logic device receives the power-on level signal generated by the power-on button, it further includes: In response to the power-on level signal, the first programmable logic device controls the power module to power on the carrier board and sends a CPU power enable signal to the second programmable logic device; The second programmable logic device responds to the CPU power enable signal and controls the CPU module to power on.

8. A button-based soft shutdown device for an LRM server, characterized in that, include: The startup status flag setting module is configured to monitor the serial port information output by the processor through the local bus during the startup process of the second programmable logic device, and set the startup status flag of the processor according to the serial port information. The power-off level signal receiving module is configured as the first programmable logic device to receive the power-off level signal generated by the power-on / off button; The startup status flag acquisition module is configured to, in response to the power-off level signal, have the first programmable logic device acquire the startup status flag from the second programmable logic device; The hardware interrupt signal sending module is configured such that if the startup status flag indicates that the startup state has been entered, the first programmable logic device notifies the second programmable logic device to send a hardware interrupt signal to the processor. The soft shutdown process execution module is configured so that the processor responds to the hardware interrupt signal and triggers the corresponding operating system to execute the soft shutdown process; The CPU module power-off module is configured such that after the soft shutdown process is completed, the second programmable logic device controls the CPU module to power off.

9. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to execute a button-based soft shutdown method for an LRM server as described in any one of claims 1-7.

10. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the button-based soft shutdown method for an LRM server as described in any one of claims 1-7.

Images