Chip reset method and device, chip, equipment, network interface card, storage medium and program product

Abstract

The application relates to a chip reset method and device, a chip, an equipment, a network interface card, a storage medium and a program product. The method comprises the following steps: if first interrupt information is generated by a monitoring unit corresponding to a first processor, and at least one trigger condition of a hot reset is detected, performing a hot reset on the chip; wherein the first processor is in a hanging state before and after the first interrupt information is generated by the monitoring unit corresponding to the first processor, and the first interrupt information is used for indicating the hot reset on the chip. The method can improve the flexibility of the chip reset.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip reset method, apparatus, chip, device, network interface card, storage medium, and program product. Background Technology

[0002] With the widespread adoption of information technology, chips are widely used in various electronic products. To prevent chips from getting stuck in an infinite loop, a reset function is usually provided.

[0003] In related technologies, watchdog signals can be monitored through multiple channels to achieve chip reset. Specifically, other controllers on the board where the chip is located can be used to form master and slave controllers, and Universal Asynchronous Receiver (UART) and Controller Area Network (CAN) buses can be used to form internal and external monitoring channels. Thus, the input signals of a single watchdog can be monitored through multiple monitoring channels, and a board-level reset operation is performed after the watchdog input signal is detected.

[0004] However, due to potential watchdog timeouts or abnormal triggering of resets, the chip reset implemented by monitoring the watchdog signal through multiple channels in related technologies cannot flexibly adapt to different system abnormal scenarios, thus resulting in low flexibility of chip reset. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip reset method, apparatus, chip, device, network interface card, storage medium, and program product that can improve the flexibility of chip reset in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a chip reset method, the method comprising:

[0007] If the monitoring unit corresponding to the first processor generates a first interrupt message, then the chip is thermally reset if at least one thermal reset trigger condition is detected.

[0008] The first processor is in a suspended state before and after its corresponding monitoring unit generates the first interrupt information, and the first interrupt information is used to indicate a hot reset of the chip.

[0009] In one embodiment, after the monitoring unit corresponding to the first processor generates a first interrupt message, the method further includes:

[0010] In response to the first interrupt information, the target timer is triggered to start counting;

[0011] Once the count value of the target timer exceeds the set value, it is determined that the trigger condition for the hot reset is met.

[0012] In one embodiment, after the monitoring unit corresponding to the first processor generates a first interrupt message, the method further includes:

[0013] If the monitoring unit corresponding to the second processor synchronously generates the second interrupt information, then it is determined that the triggering condition for the hot reset is met.

[0014] The second processor is in a suspended state before and after its corresponding monitoring unit generates a second interrupt message, and the second interrupt message is used to indicate a hot reset of the chip.

[0015] In one embodiment, after the monitoring unit corresponding to the first processor generates a first interrupt message, the method further includes:

[0016] If the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before the hot reset and sets the reset register corresponding to the second processor to the target value, then the triggering condition for the hot reset is determined to be met.

[0017] In one embodiment, the thermal reset of the chip includes:

[0018] A reset instruction message is sent to the clock reset generator of the chip, the reset instruction message being used to indicate the initiation of a hot reset of the chip.

[0019] In one embodiment, the method further includes:

[0020] Receive control information regarding the trigger conditions for the thermal reset;

[0021] Based on the control information of the thermal reset trigger conditions, the value of the flag bit in the trigger condition register is modified. The flag bit in the trigger condition register is used to enable or disable different thermal reset trigger conditions.

[0022] In one embodiment, the method further includes, prior to thermally resetting the chip:

[0023] Based on the abnormal information in the chip, determine the type of abnormal state of the chip;

[0024] Write the abnormal state type of the chip into the abnormal state register.

[0025] In one embodiment, the method further includes:

[0026] If the monitoring unit corresponding to the first processor generates a third interrupt message and sends it to the first processor, the first processor responds to the third interrupt message and performs a reset preprocessing operation to perform a hot reset on the chip.

[0027] The first processor was not in a suspended state before and after its corresponding monitoring unit generated the third interrupt information, and the third interrupt information was used to indicate a hot reset of the chip.

[0028] The reset preprocessing operation includes at least one of the following: recording the program execution location information of the first processor performing the chip reset, saving the register data and cache data of the first processor, and locking the state of the first processor.

[0029] Secondly, this application provides a chip reset device applied to a first processor in a chip, the device comprising:

[0030] The monitoring module is configured to monitor the first interrupt information generated by the monitoring unit corresponding to the first processor, wherein the first processor is in a suspended state before and after the first interrupt information is generated by its corresponding monitoring unit, and the first interrupt information is used to indicate a hot reset of the chip.

[0031] The reset module is configured to perform a thermal reset on the chip if at least one of the thermal reset trigger conditions is detected.

[0032] In one embodiment, the reset module is further configured to trigger a target timer to start timing in response to the first interrupt information; and to determine that the hot reset trigger condition is met after the count value of the target timer exceeds a set value.

[0033] In one embodiment, the reset module is further configured to determine that the triggering condition for hot reset is met if the monitoring unit corresponding to the second processor synchronously generates second interrupt information.

[0034] The second processor is in a suspended state before and after its corresponding monitoring unit generates a second interrupt message, and the second interrupt message is used to indicate a hot reset of the chip.

[0035] In one embodiment, the reset module is further configured to determine that the triggering condition for the hot reset is met if the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before the hot reset and sets the reset register corresponding to the second processor to the target value.

[0036] In one embodiment, the reset module is further configured to send reset indication information to the clock reset generator of the chip, the reset indication information being used to indicate the initiation of a hot reset of the chip.

[0037] In one embodiment, the reset module is further configured to receive control information for the triggering conditions of the hot reset; and to modify the value of the flag bit in the triggering condition register according to the control information for the triggering conditions of the hot reset, wherein the flag bit in the triggering condition register is used to enable or disable different hot reset triggering conditions.

[0038] In one embodiment, the reset module is further configured to determine the abnormal state type of the chip based on the abnormal information in the chip; and write the abnormal state type of the chip into an abnormal state register.

[0039] In one embodiment, the reset module is further configured to perform a reset preprocessing operation to perform a hot reset of the chip in response to the third interrupt information if the monitoring unit corresponding to the first processor generates a third interrupt information and sends it to the first processor.

[0040] The first processor was not in a suspended state before and after its corresponding monitoring unit generated the third interrupt information, and the third interrupt information was used to indicate a hot reset of the chip.

[0041] The reset preprocessing operation includes at least one of the following: recording the program execution location information of the first processor performing the chip reset, saving the register data and cache data of the first processor, and locking the state of the first processor.

[0042] Thirdly, this application also provides a chip, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the chip reset method of the first aspect described above.

[0043] Fourthly, this application also provides a computer device, including a processor and the chip described in the third aspect above, wherein the chip is used to schedule messages to the processor or to process them on its own, and the processor is used to process messages scheduled by the chip.

[0044] Fifthly, this application also provides a network interface card, including the chip and interface as described in the third aspect above, wherein the chip communicates externally through the interface.

[0045] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the chip reset method of the first aspect described above.

[0046] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the chip reset method of the first aspect described above.

[0047] In the aforementioned chip reset method, apparatus, chip, device, network interface card, storage medium, and program product, if the monitoring unit corresponding to the first processor generates a first interrupt message, the chip is hot-reset if at least one hot-reset trigger condition is detected. The first processor is in a suspended state before and after the first interrupt message is generated by its corresponding monitoring unit, and the first interrupt message indicates that the chip should be hot-reset. Because the first processor is in a suspended state, the detection of the hot-reset trigger condition can be triggered by the first interrupt message from the monitoring unit corresponding to the first processor, thereby hot-resetting the chip, when the first processor is in a suspended state, thus improving the flexibility of the reset process. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 A schematic flowchart illustrating a chip reset method provided in an embodiment of this application;

[0050] Figure 2 A schematic diagram of a multiprocessor collaborative watchdog provided in an embodiment of this application;

[0051] Figure 3 A schematic flowchart illustrating another chip reset method provided in an embodiment of this application;

[0052] Figure 4 This is a structural block diagram of a chip reset method provided in an embodiment of this application;

[0053] Figure 5 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0055] The relevant technologies will be explained below.

[0056] In related technologies, watchdog signals can be monitored through multiple channels to achieve chip reset. Specifically, other controllers on the board where the chip is located can be used to form master and slave controllers, and Universal Asynchronous Receiver (UART) and Controller Area Network (CAN) buses can be used to form internal and external monitoring channels. Thus, the input signals of a single watchdog can be monitored through multiple monitoring channels, and a board-level reset operation is performed after the watchdog input signal is detected.

[0057] However, chip reset in related technologies has the following drawbacks. First, the chip reset process requires the use of monitoring channels on the chip's periphery to achieve multi-core collaborative capabilities. Second, chip reset achieved by monitoring watchdog signals through multiple channels has limited service conditions and cannot flexibly adapt to different system anomaly scenarios, resulting in low flexibility in chip reset. Finally, the failure to record the state information before reset at the hardware level makes it difficult to quickly locate problems in system anomaly situations.

[0058] To address the aforementioned issues, this application provides a chip reset method, apparatus, chip, device, network interface card, storage medium, and program product. Since the first processor is in a suspended state, the detection of the hot reset trigger condition can be triggered by the first interrupt information of the hot reset trigger condition of the monitoring unit corresponding to the first processor, thereby performing a hot reset on the chip, thus improving the flexibility of the reset process.

[0059] It should be understood that the chip reset method provided in the embodiments of this application can be applied to chips of multi-core processors, which can be used in any electronic device, including terminals or network devices.

[0060] The multi-core processor chip may include multiple processors, including a System Control Processor (SCP) and a Manageability Control Processor (MCP).

[0061] The terminals can be, but are not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle systems, and projection devices. Portable wearable devices can include smartwatches, smart bracelets, and head-mounted displays. Head-mounted displays can include virtual reality (VR) devices, augmented reality (AR) devices, and smart glasses.

[0062] The aforementioned network devices may include, but are not limited to, data processing units, network interface cards, servers, network adapters, switches, or routers.

[0063] In one exemplary embodiment, such as Figure 1 As shown, a chip reset method is provided, and the method is applied to the above-mentioned chip for illustration, including S201-S202:

[0064] S201. Monitor the first interrupt information generated by the monitoring unit corresponding to the first processor.

[0065] The first processor is in a suspended state before and after its corresponding monitoring unit generates the first interrupt information. The first interrupt information is used to indicate that the chip should be hot-reset.

[0066] In some embodiments, the chip may include multiple types of processors, such as a System Control Processor (SCP), a Manageability Control Processor (MCP), an Integrated Micro-Processor Unit (IMU), or a second-generation N-series Arm processor (arm Neoverse 2, N2). The first processor and the second processor can be any two different processors in the chip. For example, the first processor can be an SCP, and the second processor can be an MCP.

[0067] For example, the first processor mentioned above may include SCP, MCP, IMU0, IMU1, N2, etc., and correspondingly, the target monitoring unit corresponding to the first interrupt information may include the monitoring unit corresponding to SCP (SCP_WDG), the monitoring unit corresponding to MCP (MCP_WDG), the monitoring unit corresponding to IMU0 (IMU0_WDG), the monitoring unit corresponding to IMU1 (IMU1_WDG), the monitoring unit corresponding to N2 (N2_WDG), etc.

[0068] In some embodiments, each processor may be provided with a corresponding monitoring unit. Each monitoring unit may route generated interrupt information to its corresponding processor, or it may route generated interrupt information to other processors not corresponding to that monitoring unit. For example, the monitoring unit corresponding to the SCP may send the first interrupt information to the SCP or MCP.

[0069] Among them, the monitoring unit can be a watchdog unit, which is a timer unit used to monitor the chip's operating status and prevent system failures (such as crashes or programs deviating from the normal code path), whether it is a hardware or software unit.

[0070] In some embodiments, the monitoring unit corresponding to the first processor may first send a third interrupt message (WS0) to the first processor to instruct the first processor to perform a chip reset. If the first processor is not in a suspended state before and after the third interrupt message is generated by its corresponding monitoring unit, but is in a normal working state, the first processor performs a reset preprocessing operation to perform a hot reset of the chip. If the first processor is in a suspended state before and after the third interrupt message is generated by its corresponding monitoring unit, the chip reset of the first processor fails. In this case, the monitoring unit corresponding to the first processor may send a first interrupt message to other processors. For example, the monitoring unit corresponding to the first processor may route the first interrupt message to a second processor, which will then perform the chip reset.

[0071] The first processor is not in a suspended state before and after the third interrupt information is generated by its corresponding monitoring unit. The third interrupt information is used to indicate that the chip should be hot-reset.

[0072] The reset preprocessing operation includes at least one of the following: recording the program execution location information of the first processor performing the chip reset, saving the register data and cache data of the first processor, and locking the state of the first processor.

[0073] For example, the above-mentioned program execution location information can be the code location currently being run by the program being executed by the target processor. For example, the above-mentioned locking of the target processor's state can be achieved by calling the debugger of the Baseboard Management Controller (BMC). By locking the target processor's state, the initial context that caused the chip reset problem can be preserved for problem localization.

[0074] For example, the above-mentioned reset preprocessing operation may also include saving the running state of the program on the chip, the running state of the memory, the configuration information of the peripherals, etc., so as to restore the program running after the chip is reset.

[0075] It should be understood that the above method can achieve two-level interrupt reset of the first processor and the second processor, thereby improving the chip reset success rate.

[0076] It should be understood that interrupt information from the monitoring units corresponding to each processor in the chip can be routed to different processors, and this application embodiment does not limit this. For example, Figure 2 A schematic diagram illustrating the framework of a multiprocessor collaborative watchdog protection mechanism provided in this application embodiment is shown below. Figure 2 As shown, taking SCP and MCP as examples, the WS0 route of the monitoring unit (SCPWDG) corresponding to SCP is routed to SCP. Accordingly, after receiving WS0, if SCP is in normal working condition, SCP directly resets the chip. If SCP is in a suspended state, the WS1 route of SCP WDG is routed to MCP, and MCP resets the chip.

[0077] For example, the WS0 of the MCP's monitoring unit is routed to the MCP. Accordingly, upon receiving WS0, if the MCP is in normal working condition, it directly resets the chip. If the MCP is in a suspended state, the WS1 of the MCP WDG is routed to the SCP, which then resets the chip. Furthermore, the WS1 of the monitoring units of IMU1 and IMU0 is routed to the SCP. The WS1 of the monitoring unit of IMU1 is routed to IMU1, and the WS1 of the monitoring unit of IMU0 is routed to IMU0.

[0078] In this application, since the interrupt information of each monitoring unit can be routed to the corresponding processor or to other processors, the processors can cooperate with each other to form a mesh protection mechanism, thereby improving the stability of the chip system and enhancing the collaborative capability of the heterogeneous multi-core system.

[0079] S202. If the monitoring unit corresponding to the first processor generates a first interrupt information, then the chip is thermally reset if at least one thermal reset trigger condition is detected.

[0080] The triggering conditions for hot reset involved in the embodiments of this application will be described below.

[0081] The first type of hot reset trigger condition can be the timeout of the target customizer corresponding to the first interrupt information.

[0082] In some embodiments, if the monitoring unit corresponding to the first processor generates a first interrupt message, the chip can trigger the target timer to start timing in response to the first interrupt message. Subsequently, after the count value of the target timer exceeds a set value, it is determined that the trigger condition for a hot reset is met.

[0083] For example, if the first processor is an SCP and the second processor is an MCU, then when the SCP hangs, the SCP's monitoring unit sends a first interrupt message (WS1) to the MCU. After receiving the first interrupt message (WS1) sent by the SCP's monitoring unit, the target timer (WS1_SCP_TIMER) can be triggered to start timing, and after the target timer's count value exceeds the set value, it is determined that the trigger condition for a hot reset is met.

[0084] The target counter mentioned above can be a hot-reset counter in the chip. The timeout setting of the target counter can be set according to the actual situation and can be any value. For example, the setting value of the target counter can be 5, 8, 10, etc.

[0085] The second type of hot reset trigger condition can be that the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before the hot reset, and sets the reset register corresponding to the second processor to the target value.

[0086] In some embodiments, if the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before hot reset and sets the reset register corresponding to the second processor to the target value, then it is determined that the triggering condition for hot reset is met.

[0087] The target data mentioned above can be hardware operating status data (last words data) when the first interrupt information is triggered, and may include snapshots of the fault scene, etc. Processing of the target data may include data acquisition, data recording, and other processing operations.

[0088] For example, the target value of the reset register can be 1. When the reset register is set to 1, the chip is reset. When the reset register is set to 0, the chip is not reset.

[0089] For example, the first interrupt information (WS1) of the monitoring unit corresponding to the SCP is routed to the MCP. At this time, after receiving the first interrupt information (WS1), the MCP performs target data processing before hot reset and sets the target value of the reset register to 1. After completing the target data processing and setting the target value of the reset register, the conditions for hot reset are met, and a subsequent hot reset can be performed.

[0090] The third type of hot reset trigger condition can be the synchronous receipt of a first interrupt information generated by the monitoring unit corresponding to the first processor and a second interrupt information generated by the monitoring unit corresponding to the second processor.

[0091] In some embodiments, if the monitoring unit corresponding to the second processor synchronously generates the second interrupt information, it is determined that the triggering condition for hot reset is met.

[0092] The second processor is in a suspended state before and after its corresponding monitoring unit generates the second interrupt information. The second interrupt information is used to indicate a hot reset of the chip.

[0093] For example, the first processor is SCP, and the second processor is MCP, both of which are in a suspended state. When MCP receives the first interrupt message (WS1) sent by the monitoring unit of SCP when SCP is suspended, it also simultaneously receives the second interrupt message sent by the monitoring unit of MCP when MCP is suspended. At this point, it can be determined that the triggering conditions for hot reset are met, and hot reset of the chip begins.

[0094] It should be understood that the embodiments of this application do not limit how the thermal reset trigger conditions are set. In some embodiments, the chip can receive control information for the thermal reset trigger conditions. Subsequently, the chip modifies the value of the flag bit in the trigger condition register according to the control information for the thermal reset trigger conditions. The flag bit in the condition register is used to enable or disable different thermal reset trigger conditions.

[0095] For example, the validity of each warm reset trigger condition can be indicated by the value of the flag bit (scp warm reset enable[2:0]) in the trigger condition register. By inputting the control information of the warm reset trigger condition, the user can instruct the user to modify the value of the flag bit in the trigger condition register, thereby enabling (effective) one or more warm reset trigger conditions, or disabling (invalidating) one or more warm reset trigger conditions.

[0096] In some embodiments, a thermal reset of the chip can also be manually triggered. For example, a thermal reset of the entire chip can be manually triggered through a specific trigger register, and the thermal reset function of the trigger register can be enabled and disabled.

[0097] This application provides multiple hot reset trigger conditions, allowing for flexible responses to various abnormal scenarios. By combining multiple hot reset trigger conditions, timely reset can be ensured under different abnormal conditions, enhancing the system's stability and fault tolerance.

[0098] In some embodiments, when the chip detects that at least one thermal reset trigger condition is met, a reset instruction message can be sent to the chip's clock and reset generator (CRG). The reset instruction message is used to indicate the initiation of a thermal reset of the chip.

[0099] For example, when the chip is powered on, the CRG can generate a specific reset signal to initiate a hot reset of the chip. The core logic module is reset by the specific reset signal, while retaining key configurations such as the power domain and clock source, thereby achieving rapid system recovery.

[0100] In some embodiments, before performing a thermal reset on the chip, the type of abnormal state of the chip can be determined based on the abnormal information stored in the chip. Subsequently, the reset can write the type of abnormal state of the chip into the abnormal state register.

[0101] The aforementioned abnormal information can be information automatically recorded by various hardware components within the chip.

[0102] For example, the chip can determine the exception state type of different exception information based on the exception information automatically recorded by various hardware components within the chip. This exception state type can be used to reflect the triggering conditions of the corresponding exception information. Subsequently, a reset can write the exception state type of the chip into the Exception Status Register, which can then be used for subsequent exception analysis and debugging.

[0103] Among them, anomalous status types can include the SCP's watchdog being killed, or the SCP and MCP both exhibiting anomalous behavior simultaneously.

[0104] In this application, the abnormal state type of the chip is recorded by an abnormal state register, so that after the chip is reset, the cause of the problem can be accurately traced based on the abnormal state type, thereby greatly improving debugging efficiency.

[0105] The chip reset method provided in this application embodiment, if the monitoring unit corresponding to the first processor generates a first interrupt information, then performs a hot reset on the chip if at least one hot reset trigger condition is detected. The first processor is in a suspended state before and after the first interrupt information is generated by its corresponding monitoring unit, and the first interrupt information is used to indicate that the chip should be hot reset. Since the first processor is in a suspended state, the detection of the hot reset trigger condition can be triggered by the first interrupt information of the hot reset trigger condition from the monitoring unit corresponding to the first processor, thereby performing a hot reset on the chip, when the first processor is in a suspended state, thus improving the flexibility of the reset process.

[0106] Figure 3 A flowchart illustrating another chip reset method provided in this application embodiment is shown below. Figure 3 As shown, this chip reset method is applied to the first processor in the chip, including S301-S305:

[0107] S301: Receive control information for the trigger conditions of thermal reset.

[0108] S302. Modify the value of the flag bit in the trigger condition register according to the control information of the thermal reset trigger condition.

[0109] The flag bits in the trigger condition register are used to enable or disable different thermal reset trigger conditions.

[0110] S303. If the monitoring unit corresponding to the first processor generates a first interrupt information, then the chip is thermally reset if at least one thermal reset trigger condition is detected.

[0111] The second processor is the processor in the chip that is in a suspended state, and the first interrupt information is used to indicate that the chip should be hot-reset.

[0112] In some embodiments, after the monitoring unit corresponding to the first processor generates a first interrupt message, the target timer can be triggered to start timing in response to the first interrupt message; after the count value of the target timer exceeds a set value, it is determined that the triggering condition for hot reset is met.

[0113] In some embodiments, if the monitoring unit corresponding to the first processor generates a first interrupt information and the monitoring unit corresponding to the second processor synchronously generates a second interrupt information, then it is determined that the triggering condition for hot reset is met.

[0114] The second processor is in a suspended state before and after its corresponding monitoring unit generates the second interrupt information. The second interrupt information is used to indicate a hot reset of the chip.

[0115] In some embodiments, if the monitoring unit corresponding to the first processor generates a first interrupt information, and if the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before hot reset and sets the reset register corresponding to the second processor to the target value, then it is determined that the triggering condition for hot reset is met.

[0116] S304. Determine the type of abnormal state of the chip based on the abnormal information in the chip.

[0117] S305. Write the chip's abnormal state type into the abnormal state register.

[0118] In this application, chip reset can be completed by hardware, thereby avoiding the intervention and delay caused by software reset, ensuring the rapid recovery of the system on the chip, especially in critical tasks, and avoiding long-term downtime caused by system deadlock or abnormality on the chip.

[0119] The chip reset method provided in this application embodiment, if the monitoring unit corresponding to the first processor generates a first interrupt information, then performs a hot reset on the chip if at least one hot reset trigger condition is detected. The first processor is in a suspended state before and after the first interrupt information is generated by its corresponding monitoring unit, and the first interrupt information is used to indicate that the chip should be hot reset. Since the first processor is in a suspended state, the detection of the hot reset trigger condition can be triggered by the first interrupt information of the hot reset trigger condition from the monitoring unit corresponding to the first processor, thereby performing a hot reset on the chip, when the first processor is in a suspended state, thus improving the flexibility of the reset process.

[0120] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0121] Based on the same inventive concept, this application also provides a chip reset device for implementing the chip reset method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more chip reset device embodiments provided below can be found in the limitations of the chip reset method described above, and will not be repeated here.

[0122] In one exemplary embodiment, such as Figure 4 As shown, a chip reset device 400 is provided, applied to a first processor in a chip. The chip reset device 400 includes: a monitoring module 401 and a reset module 402, wherein:

[0123] Monitoring module 401 is configured to monitor the first interrupt information generated by the monitoring unit corresponding to the first processor, wherein the first processor is in a suspended state before and after the first interrupt information is generated by its corresponding monitoring unit, and the first interrupt information is used to indicate a hot reset of the chip.

[0124] The reset module 402 is configured to perform a thermal reset on the chip when at least one thermal reset trigger condition is detected.

[0125] In one embodiment, the reset module 402 is further configured to trigger a target timer to start timing in response to a first interrupt message; and to determine that the triggering condition for a hot reset is met after the count value of the target timer exceeds a set value.

[0126] In one embodiment, the reset module 402 is further configured to determine that the triggering condition for hot reset is met if the monitoring unit corresponding to the second processor synchronously generates the second interrupt information.

[0127] The second processor is in a suspended state before and after its corresponding monitoring unit generates the second interrupt information. The second interrupt information is used to indicate a hot reset of the chip.

[0128] In one embodiment, the reset module 402 is further configured to determine that the hot reset triggering condition is met if the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before hot reset and sets the reset register corresponding to the second processor to the target value.

[0129] In one embodiment, the reset module 402 is further configured to send reset indication information to the chip's clock reset generator, the reset indication information being used to indicate the initiation of a hot reset of the chip.

[0130] In one embodiment, the reset module 402 is further configured to receive control information for the triggering conditions of a thermal reset; and to modify the value of the flag bit in the triggering condition register according to the control information for the triggering conditions of a thermal reset, wherein the flag bit in the triggering condition register is used to enable or disable different triggering conditions for a thermal reset.

[0131] In one embodiment, the reset module 402 is further configured to determine the abnormal state type of the chip based on the abnormal information in the chip; and write the abnormal state type of the chip into the abnormal state register.

[0132] In one embodiment, the reset module 402 is further configured to perform a reset preprocessing operation to perform a hot reset of the chip in response to the third interrupt information if the monitoring unit corresponding to the first processor generates a third interrupt information and sends it to the first processor.

[0133] The first processor was not in a suspended state before and after its corresponding monitoring unit generated the third interrupt information. The third interrupt information was used to indicate a hot reset of the chip.

[0134] The reset preprocessing operation includes at least one of the following: recording the program execution location information of the first processor performing the chip reset, saving the register data and cache data of the first processor, and locking the state of the first processor.

[0135] Each module in the aforementioned chip reset device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0136] In one embodiment, a computer device is provided, which has a network interface card (NIC) with a chip on it, and the computer device can implement the chip reset method described above. The internal structure diagram of the computer device can be shown as follows. Figure 5As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface (e.g., a network interface card) is connected to the system bus via the I / O interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a chip reset method.

[0137] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0138] In one exemplary embodiment, a chip is provided. The chip includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the chip reset method described above. The chip may be a data processing unit (DPU) chip used in a data center, or other data processing chip.

[0139] In one exemplary embodiment, a Network Interface Card (NIC) is provided. The NIC includes a chip as described in the foregoing embodiments and multiple interfaces (e.g., PCI / PCIE interfaces, USB interfaces, etc.), through which the chip communicates with the outside world.

[0140] In one exemplary embodiment, a computer device is provided. The computer device includes a central processing unit (CPU) and a chip or network interface card as described in the foregoing embodiments. The chip is used to schedule packets to the CPU or to process them itself, and the CPU is used to process the packets scheduled by the chip.

[0141] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the chip reset method described above.

[0142] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the chip reset method described above.

[0143] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0145] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip reset method, characterized in that, The method includes: If the monitoring unit corresponding to the first processor generates a first interrupt message, then the chip is thermally reset if at least one thermal reset trigger condition is detected. If the monitoring unit corresponding to the second processor synchronously generates the second interrupt information, then it is determined that the triggering condition for the hot reset is met. The first processor is in a suspended state before and after its corresponding monitoring unit generates a first interrupt message, which is used to indicate a hot reset of the chip. The second processor is in a suspended state before and after its corresponding monitoring unit generates a second interrupt message, which is used to indicate a hot reset of the chip.

2. The method according to claim 1, characterized in that, After the monitoring unit corresponding to the first processor generates the first interrupt information, the method further includes: In response to the first interrupt information, the target timer is triggered to start counting; Once the count value of the target timer exceeds the set value, it is determined that the trigger condition for the hot reset is met.

3. The method according to claim 1, characterized in that, After the monitoring unit corresponding to the first processor generates the first interrupt information, the method further includes: If the monitoring unit corresponding to the first processor sends the generated first interrupt information to the second processor, and the second processor completes the processing of the target data before the hot reset and sets the reset register corresponding to the second processor to the target value, then the triggering condition for the hot reset is determined to be met.

4. The method according to any one of claims 1-3, characterized in that, The hot reset of the chip includes: A reset instruction message is sent to the clock reset generator of the chip, the reset instruction message being used to indicate the initiation of a hot reset of the chip.

5. The method according to claim 1, characterized in that, The method further includes: Receive control information regarding the trigger conditions for the thermal reset; Based on the control information of the thermal reset trigger conditions, the value of the flag bit in the trigger condition register is modified. The flag bit in the trigger condition register is used to enable or disable different thermal reset trigger conditions.

6. The method according to claim 1, characterized in that, Before performing a thermal reset on the chip, the method further includes: Based on the abnormal information in the chip, determine the type of abnormal state of the chip; Write the abnormal state type of the chip into the abnormal state register.

7. The method according to claim 1, characterized in that, The method further includes: If the monitoring unit corresponding to the first processor generates a third interrupt message and sends it to the first processor, the first processor responds to the third interrupt message and performs a reset preprocessing operation to perform a hot reset on the chip. The first processor was not in a suspended state before and after its corresponding monitoring unit generated the third interrupt information, and the third interrupt information was used to indicate a hot reset of the chip. The reset preprocessing operation includes at least one of the following: recording the program execution location information of the first processor performing the chip reset, saving the register data and cache data of the first processor, and locking the state of the first processor.

8. A chip reset device, characterized in that, The device includes: The monitoring module is configured to monitor the first interrupt information generated by the monitoring unit corresponding to the first processor, wherein the first processor is in a suspended state before and after the first interrupt information is generated by its corresponding monitoring unit, and the first interrupt information is used to indicate a hot reset of the chip. The reset module is configured to perform a thermal reset on the chip when at least one of the thermal reset trigger conditions is detected; if the monitoring unit corresponding to the second processor synchronously generates a second interrupt information, it is determined that the thermal reset trigger condition is met; wherein the second processor is in a suspended state before and after its corresponding monitoring unit generates the second interrupt information, and the second interrupt information is used to indicate that the chip should be thermally reset.

9. A chip comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer device, characterized in that, The device includes a processor and the chip of claim 9, wherein the chip is used to schedule messages to the processor or to process them on its own, and the processor is used to process messages scheduled by the chip.

11. A network interface card, characterized in that, It includes the chip and interface as described in claim 9, wherein the chip communicates externally through the interface.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

Images