Hardware access control device used in multi-core system

Abstract

The invention provides a hardware access control device used in a multi-core system. The device comprises a plurality of main cores and a hardware lock module, the hardware lock module comprises a hardware lock register module and a hardware lock arbitration response module; the bit width of a register in the hardware lock register module is consistent with the number of the main cores, each bit corresponds to an access permission mark of one main core, only one bit is allowed to be set at the same moment, if one main core has set a lock bit, other main cores cannot set the lock bit, and the lock bit can be set after being unlocked; the hardware lock arbitration response module comprises a peripheral hardware lock arbitration module and a memory hardware lock arbitration module, and the peripheral hardware lock arbitration module and the memory hardware lock arbitration module correspond to APB and AHB bus access paths respectively. According to the hardware access control device used in the multi-core system provided by the invention, the hardware lock module is introduced into the multi-core system, so that hardware-level atom mutual exclusion access of resource access is realized, and the conflict that multiple cores access peripheral or memory resources at the same time is prevented.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a hardware access control device for multi-core systems. Background Technology

[0002] In a multi-core system, different master cores access peripherals and memory through a shared bus (such as AHB, Advanced High-performance Bus). When multiple master cores access the same peripheral or the same memory simultaneously, without an effective mutual exclusion mechanism, it can lead to data errors, state races, or even system crashes.

[0003] Currently, the most commonly used solutions in applications are software semaphores or mutexes. A semaphore uses an integer value to represent the number of available resources. When a master core wants to access a shared resource, it performs a P operation to acquire the resource and decrements the semaphore by 1. After accessing the resource, it performs a V operation to release the resource and increments the semaphore by 1. When the semaphore is 0, it means that no resource is currently available and access is not possible; access can only be granted after another master core releases the resource. A mutex, on the other hand, is a special case where the integer value of the semaphore is 1.

[0004] However, relying on software has the following drawbacks: 1. Access synchronization relies on software interruption or polling mechanisms, resulting in significant response delays; 2. Software semaphores cannot guarantee the atomicity of operations during bus arbitration, meaning that they may be interrupted or preempted between semaphore checks and updates, causing resource contention. 3. The synchronization complexity of different master cores is high, making debugging difficult.

[0005] Therefore, it is necessary to provide a hardware access control device for multi-core systems to effectively solve the above problems. Summary of the Invention

[0006] This invention addresses the problems and shortcomings of existing technologies by providing a hardware access control device for multi-core systems. By introducing a hardware lock module into the multi-core system, hardware-level atomic mutual exclusion access to resources is achieved, preventing conflicts caused by multiple cores simultaneously accessing peripheral or memory resources.

[0007] This invention provides a hardware access control device for a multi-core system, the device including multiple main cores and a hardware lock module; the hardware lock module includes a hardware lock register module and a hardware lock arbitration response module; The bit width of the registers in the hardware lock register module is the same as the number of master cores. Each bit corresponds to the access permission flag of a master core. Only one bit is allowed to be set at the same time. If a master core has set its lock bit, other master cores cannot set it. The lock bit can only be set after it is unlocked. The hardware lock arbitration response module includes a peripheral hardware lock arbitration module and a memory hardware lock arbitration module. The peripheral hardware lock arbitration module corresponds to the APB bus access path, and the memory hardware lock arbitration module corresponds to the AHB bus access path.

[0008] Preferably, the reading and writing of the hardware lock register module are both completed by the APB interface, and its operation is atomic.

[0009] Preferably, the hardware register module is used to generate the hardware lock register address and read / write the hardware lock register; The hardware lock register address is the base address plus the number of peripherals. ; The hardware lock register is written according to the requirements of the APB protocol. It can only be written when the value of the hardware lock register is all 0. If it is not 0, it means that the current resource has been locked and can only be written after it is unlocked. A bit is written to 1 according to the pmaster signal.

[0010] Preferably, the hardware lock register module includes a peripheral hardware lock register and a memory hardware lock register; The number of memory hardware lock registers is automatically calculated based on parameters; The peripheral hardware lock register includes the following parameters: number of accessible hosts, number of peripherals, and starting address of the peripheral hardware lock register; The memory hardware lock register includes the following parameters: number of accessible hosts, memory space size, size of the locked space, memory hardware lock start address, and number of lockable spaces.

[0011] Preferably, the peripheral hardware lock arbitration response module is located before the peripheral APB interface. If the accessed master core meets the requirements of the peripheral hardware register, the access is allowed to proceed normally; otherwise, the current access is intercepted and a response is generated.

[0012] Preferably, the interception of the current access and the generation of a response includes configuring the response as an interrupt or bus error response; The interrupt is reported to the main core's interrupt interface in a level manner, and the interrupt is cleared through register configuration; The bus error response will raise pslverr high, and pslverr will be lowered after the APB access ends.

[0013] Preferably, the memory hardware lock arbitration response module establishes arbitration logic with a preset address space size as the granularity to ensure that only one main core can access the current address space; the memory hardware lock arbitration response module is set before the memory interface. If the main core accessing the current address space meets the requirements of the memory hardware register, the access is allowed to proceed normally; otherwise, the current access is intercepted and a response is generated.

[0014] Preferably, the peripheral hardware lock arbitration response module includes the following parameters: the number of accessible hosts; The memory hardware lock arbitration response module includes the following parameters: number of accessible hosts, memory space size, size of locked space, memory starting address, and number of lockable spaces.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: This invention provides a hardware access control device for a multi-core system. The device includes multiple master cores and a hardware lock module. The hardware lock module includes a hardware lock register module and a hardware lock arbitration response module. The bit width of the registers in the hardware lock register module is consistent with the number of master cores. Each bit corresponds to an access permission flag of a master core. Only one bit is allowed to be set at a time. If a master core has set its lock bit, other master cores cannot set it until the lock bit is unlocked. The hardware lock arbitration response module includes a peripheral hardware lock arbitration module and a memory hardware lock arbitration module. The peripheral hardware lock arbitration module corresponds to the APB bus access path, and the memory hardware lock arbitration module corresponds to the AHB bus access path. By introducing a hardware lock module into the multi-core system, hardware-level atomic mutual exclusion access to resources is achieved, preventing conflicts caused by multiple cores simultaneously accessing peripheral or memory resources. Furthermore, by introducing hardware lock registers and arbitration judgment logic at the hardware level, real-time comparison of host IDs can be achieved in the peripheral and memory access paths, ensuring that only one master core can access the protected resources at any given time. Unlike traditional software semaphores or mutexes, this solution completes all operations within a bus cycle, achieving atomicity of access and avoiding asynchronous read / write operations and timing races in arbitration. Furthermore, the hardware lock arbitration logic is directly integrated into the APB / AHB interface, which can complete access comparison and response decision during the bus transmission stage without interrupting the arbitrator or software intervention, reducing system waiting time and improving real-time response in multi-core access scenarios. Furthermore, for unauthorized host access operations, a bus error response or interrupt signal can be automatically generated according to the configuration to protect access to critical resources, prevent abnormal system data or data corruption caused by unauthorized access, and enhance system operational stability. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a multi-core system for a hardware access control device in a multi-core system, according to a preferred embodiment of the present invention. Figure 2 This is a schematic diagram of the interface of a hardware latch register module for a hardware access control device in a multi-core system according to a preferred embodiment of the present invention. Figure 3 This is a schematic diagram of the connection of the peripheral hardware lock arbitration logic of the hardware access control device in a multi-core system according to a preferred embodiment of the present invention. Figure 4 This is a schematic diagram showing the connection of the memory hardware lock arbitration logic of the hardware access control device in a multi-core system according to a preferred embodiment of the present invention. Figure 5 This is a preferred embodiment of the peripheral hardware lock arbitration process for a hardware access control device in a multi-core system according to the present invention. Figure 6 The memory hardware lock arbitration process for a hardware access control device in a multi-core system is a preferred embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0020] This invention addresses the problems and shortcomings of existing technologies by providing a hardware access control device for multi-core systems. By introducing a hardware lock module into the multi-core system, hardware-level atomic mutual exclusion access to resources is achieved, preventing conflicts caused by multiple cores simultaneously accessing peripheral or memory resources.

[0021] Figure 1 This is a schematic diagram of the structure of a multi-core system for a hardware access control device in a multi-core system, according to a preferred embodiment of the present invention. Figure 2 This is a schematic diagram of the interface of a hardware latch register module for a hardware access control device in a multi-core system according to a preferred embodiment of the present invention. Figure 3 This is a schematic diagram of the connection of the peripheral hardware lock arbitration logic of the hardware access control device in a multi-core system according to a preferred embodiment of the present invention. Figure 4 This is a schematic diagram showing the connection of the memory hardware lock arbitration logic of the hardware access control device in a multi-core system according to a preferred embodiment of the present invention. Figure 5 This is a preferred embodiment of the peripheral hardware lock arbitration process for a hardware access control device in a multi-core system according to the present invention. Figure 6 This is a memory hardware lock arbitration process for a hardware access control device in a multi-core system, as described in a preferred embodiment of the present invention. Now see... Figures 1 to 6 The present invention provides a hardware access control device for a multi-core system, the device comprising multiple master cores and a hardware lock module; the hardware lock module comprising a hardware lock register module and a hardware lock arbitration response module; The bit width of the registers in the hardware lock register module is the same as the number of master cores. Each bit corresponds to the access permission flag of a master core. Only one bit is allowed to be set at the same time. If a master core has set its lock bit, other master cores cannot set it. The lock bit can only be set after it is unlocked. The hardware lock arbitration response module includes a peripheral hardware lock arbitration module and a memory hardware lock arbitration module. The peripheral hardware lock arbitration module corresponds to the APB bus access path, and the memory hardware lock arbitration module corresponds to the AHB bus access path.

[0022] Specifically, the main core includes Core0, Core1, Core2...CoreN. The AHB bus bridge is used for access between the main core and peripherals, memory, and user-defined IP modules. ROM stores the bootloader. SRAM is system memory. FLASH is external storage. AHB2APB is the AHB bus to APB bus bridge. UART is a serial port peripheral. TIMER is a timer peripheral. LOCK_REG is a hardware latch module. Peripheral refers to other peripherals. USERE IP is a user-defined AHB module. LOCK_REG is integrated into the peripheral bus as part of the hardware latch module. The input signals of LOCK_REG include: psel, paddr, pwdata, and pmaster; the output signals of LOCK_REG include: preply and prdata.

[0023] APB (Advanced Peripheral Bus) is a low-speed peripheral bus in the ARM AMBA architecture, emphasizing simplicity and low power consumption, and is specifically designed for connecting low-speed peripherals such as UART, I2C, and GPIO. AHB (Advanced High-performance Bus) is a high-performance core bus in the ARM AMBA bus architecture, primarily used for high-bandwidth, low-latency interconnection of internal on-chip devices.

[0024] In practice, the reading and writing of the hardware lock register module are both completed by the APB interface, and its operation is atomic.

[0025] In specific implementation, the hardware register module is used to generate the hardware lock register address and read / write the hardware lock register; The hardware lock register address is the base address plus the number of peripherals. ; The hardware lock register is written according to the requirements of the APB protocol. It can only be written when the value of the hardware lock register is all 0. If it is not 0, it means that the current resource has been locked and can only be written after it is unlocked. A bit is written to 1 according to the pmaster signal.

[0026] Specifically, the hardware lock register (i) address = base address + i (0 <= i < number of peripherals or number of locked memory locations). For example, if four peripherals need to have hardware locks defined, and the hardware lock base address is 0x42000000, then the corresponding addresses of the four peripheral hardware lock registers are 0x42000000, 0x42000004, 0x42000008, and 0x4200000c, respectively. The generation of memory hardware lock addresses is similar.

[0027] The pmaster signal refers to the control and data signal sent by the master device in the APB protocol. This type of signal is used to control the data transmission between the master device and the slave device and is the core control signal for low-speed peripheral communication.

[0028] In specific implementation, the hardware lock register module includes peripheral hardware lock registers and memory hardware lock registers; The number of memory hardware lock registers is automatically calculated based on parameters; The peripheral hardware lock register includes the following parameters: number of accessible hosts (Core_Num), number of peripherals (Peripheral_Num), and starting address of the peripheral hardware lock register (Peripheral_addr). The memory hardware lock register includes the following parameters: number of accessible hosts (Core_Num), memory space size (Memory_Size), lock space size (Block_Size), memory hardware lock start address (Memory_reg_addr), and number of lockable spaces (Memory_Lock_Num).

[0029] In specific implementation, the peripheral hardware lock arbitration response module is set before the peripheral APB interface. If the accessed master core meets the requirements of the peripheral hardware register, the access is passed normally; otherwise, the current access is intercepted and a response is generated.

[0030] In specific implementation, intercepting the current access and generating a response includes configuring the response as an interrupt or bus error response; The interrupt is reported to the main core's interrupt interface in a level manner, and the interrupt is cleared through register configuration; The bus error response will raise pslverr high, and pslverr will be lowered after the APB access ends.

[0031] Specifically, PSLVERR (APB Slave Error) is an error feedback signal for the APB bus slave device. It is specifically used to report abnormal situations during the transmission process from the slave device to the master device and is one of the key signals for the APB bus to achieve basic reliability assurance.

[0032] In specific implementation, the memory hardware lock arbitration response module establishes arbitration logic with a preset address space as the granularity to ensure that only one main core can access the current address space; the memory hardware lock arbitration response module is set before the memory interface. If the main core accessing the current address space meets the requirements of the memory hardware register, the access is passed normally; otherwise, the current access is intercepted and a response is generated.

[0033] In specific implementation, the peripheral hardware lock arbitration response module includes the following parameters: the number of accessible hosts (Core_Num). The memory hardware lock arbitration response module includes the following parameters: number of accessible hosts (Core_Num), memory space size (Memory_Size), lock space size (Block_Size), memory starting address (Memory_base_addr), and number of lockable spaces (Lock_Num).

[0034] In summary, the present invention provides a hardware access control device for a multi-core system. The device includes multiple master cores and a hardware lock module. The hardware lock module includes a hardware lock register module and a hardware lock arbitration response module. The bit width of the registers in the hardware lock register module is consistent with the number of master cores. Each bit corresponds to an access permission flag of a master core. Only one bit is allowed to be set at a time. If a master core has set its lock bit, other master cores cannot set it until the lock bit is unlocked. The hardware lock arbitration response module includes a peripheral hardware lock arbitration module and a memory hardware lock arbitration module. The peripheral hardware lock arbitration module corresponds to the APB bus access path, and the memory hardware lock arbitration module corresponds to the AHB bus access path. By introducing a hardware lock module into the multi-core system, hardware-level atomic mutual exclusion access to resources is achieved, preventing conflicts caused by multiple cores simultaneously accessing peripheral or memory resources. Furthermore, by introducing hardware lock registers and arbitration judgment logic at the hardware level, real-time comparison of host IDs can be achieved in the peripheral and memory access paths, ensuring that only one master core can access the protected resources at any given time. Unlike traditional software semaphores or mutexes, this solution completes all operations within a bus cycle, achieving atomicity of access and avoiding asynchronous read / write operations and timing races in arbitration. Furthermore, the hardware lock arbitration logic is directly integrated into the APB / AHB interface, which can complete access comparison and response decision during the bus transmission stage without interrupting the arbitrator or software intervention, reducing system waiting time and improving real-time response in multi-core access scenarios. Furthermore, for unauthorized host access operations, a bus error response or interrupt signal can be automatically generated according to the configuration to protect access to critical resources, prevent abnormal system data or data corruption caused by unauthorized access, and enhance system operational stability.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hardware access control device for a multi-core system, characterized in that, The device includes multiple main cores and a hardware lock module; the hardware lock module includes a hardware lock register module and a hardware lock arbitration response module. The bit width of the registers in the hardware lock register module is the same as the number of master cores. Each bit corresponds to the access permission flag of a master core. Only one bit is allowed to be set at the same time. If a master core has set its lock bit, other master cores cannot set it. The lock bit can only be set after it is unlocked. The hardware lock arbitration response module includes a peripheral hardware lock arbitration module and a memory hardware lock arbitration module. The peripheral hardware lock arbitration module corresponds to the APB bus access path, and the memory hardware lock arbitration module corresponds to the AHB bus access path.

2. The hardware access control device for a multi-core system as described in claim 1, characterized in that, The reading and writing of the hardware lock register module are both completed through the APB interface, and its operation is atomic.

3. The hardware access control device for a multi-core system as described in claim 1, characterized in that, The hardware register module is used to generate the hardware lock register address and read / write the hardware lock register; The hardware lock register address is the base address plus the number of peripherals. ; The hardware lock register is written according to the requirements of the APB protocol. It can only be written when the value of the hardware lock register is all 0. If it is not 0, it means that the current resource has been locked and can only be written after it is unlocked. A bit is written to 1 according to the pmaster signal.

4. The hardware access control device for a multi-core system as described in claim 1, characterized in that, The hardware lock register module includes peripheral hardware lock registers and memory hardware lock registers; The number of memory hardware lock registers is automatically calculated based on parameters; The peripheral hardware lock register includes the following parameters: number of accessible hosts, number of peripherals, and starting address of the peripheral hardware lock register; The memory hardware lock register includes the following parameters: number of accessible hosts, memory space size, size of the locked space, memory hardware lock start address, and number of lockable spaces.

5. The hardware access control device for a multi-core system as described in claim 1, characterized in that, The peripheral hardware lock arbitration response module is set before the peripheral APB interface. If the accessed master core meets the requirements of the peripheral hardware register, the access will pass normally; otherwise, the current access will be intercepted and a response will be generated.

6. The hardware access control device for a multi-core system as described in claim 5, characterized in that, The interception of the current access and generation of a response includes the response being configured as an interrupt or bus error response; The interrupt is reported to the main core's interrupt interface in a level manner, and the interrupt is cleared through register configuration; The bus error response will raise pslverr high, and pslverr will be lowered after the APB access ends.

7. The hardware access control device for a multi-core system as described in claim 1, characterized in that, The memory hardware lock arbitration response module establishes arbitration logic with a preset address space size as the granularity to ensure that only one main core can access the current address space. The memory hardware lock arbitration response module is set before the memory interface. If the main core accessing the current address space meets the requirements of the memory hardware register, the access is passed normally; otherwise, the current access is intercepted and a response is generated.

8. The hardware access control device for a multi-core system as described in claim 1, characterized in that, The peripheral hardware lock arbitration response module includes the following parameters: the number of accessible hosts; The memory hardware lock arbitration response module includes the following parameters: number of accessible hosts, memory space size, size of locked space, memory starting address, and number of lockable spaces.

Images