Rapid information processing system and method

Abstract

The invention provides a rapid information processing system and method. The system comprises a substrate, and a master DSP processor, a slave DSP processor, a master FPGA device and a slave FPGA device which are integrated on the substrate. The master DSP is in data connection with the slave DSP, the master FPGA device and the slave FPGA device through preset high-speed interfaces, and the slave DSP is in data connection with the master FPGA device and the slave FPGA device; the master DSP processor and the slave DSP processor are each provided with a first memory used for storing starting software of the DSP processor, a second memory used for storing pre-stored data information and a third memory used for storing the pre-stored data information and temporary data. The master FPGA device and the slave FPGA device are each provided with a fourth memory used for storing a starting program of the FPGA device and a fifth memory used for storing pre-stored data information and temporary data. The system provided by the invention is high in integration level and high in stability.

Description

Technical Field

[0001] This disclosure generally relates to the field of data transmission technology, and specifically to a rapid information processing system and method. Background Technology

[0002] Faced with increasingly complex and massive amounts of information and the rapid development of artificial intelligence, the computational demand for deep learning is becoming more and more urgent. Traditional digital signal processors (DSPs), as the core of information processing systems, utilize specialized algorithms for high-speed computation, playing a crucial role in real-time processing fields such as speech recognition and image enhancement. With the development and application of embedded systems, FPGAs (Field-Programmable Gate Arrays) are gradually entering design and application. As a programmable logic device, it boasts abundant internal programmable resources, including DSPs, block RAMs, programmable logic units (PLMs), clock management modules (CMTs), PCIe 3.0 protocol modules, and transceivers. It allows users to reconfigure its internal logic structure at the hardware level according to application requirements. Combined with the parallel processing capabilities of FPGAs, it is highly suitable for image data processing and computational applications.

[0003] In complex real-world applications, facing the multi-task requirements of interface control and image recognition, previous designs were relatively independent, typically employing separate designs for the control board and computing board, with data exchange between the two boards via a backplane. This approach involves connections between multiple boards, failing to meet the miniaturization and integration requirements of applications, and also increasing design and development costs. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a fast information processing system and method to solve the above problems.

[0005] The first aspect of this application provides a fast information processing system, including a substrate, and a main DSP processor, a slave DSP processor, a main FPGA device, and a slave FPGA device integrated on the substrate; The main DSP processor is connected to the slave DSP processor, the main FPGA device, and the slave FPGA device via a preset high-speed interface, and the slave DSP processor is connected to the main FPGA device and the slave FPGA device via a data connection. Both the master DSP processor and the slave DSP processor are equipped with a first memory, a second memory, and a third memory. The first memory is used to store the startup software of the DSP processor, the second memory is used to store pre-stored data information, and the third memory is used to store pre-stored data information and temporary data. Both the master FPGA device and the slave FPGA device are equipped with a fourth memory and a fifth memory. The fourth memory is used to store the FPGA device's startup program, and the fifth memory is used to store pre-stored data information and temporary data. The main DSP processor, slave DSP processor, main FPGA device, and slave FPGA device are all configured with communication interfaces for internal data interaction, and the main FPGA device is additionally configured with a communication interface for interaction with external devices.

[0006] According to the technical solution provided in the embodiments of this application, the preset high-speed interface includes a PCIe interface; The main DSP processor and the main FPGA device, as well as the slave DSP processor and the slave FPGA device, are connected via a PCIe interface. The PCIe interface adopts a 4X working mode, and the hardware circuit can be configured as 1 lane / 2 lane / 4 lane mode, with a maximum transmission rate of 5GBaud per lane.

[0007] According to the technical solution provided in the embodiments of this application, the preset high-speed interface further includes an SRIO interface; The main DSP processor and the slave DSP processor, as well as the main DSP processor and the slave FPGA device, are connected via an SRIO interface. The SRIO interface adopts a 4X working mode, and a single DSP processor is configured with two SRIO interfaces to meet the multi-path connection requirements.

[0008] According to the technical solution provided in the embodiments of this application, the first memory is a NOR FLASH memory, the second memory is a NAND FLASH memory, the third memory is a DDR3 SDRAM memory, the fourth memory is a NOR FLASH memory, and the fifth memory is a DDR3 SDRAM memory.

[0009] According to the technical solution provided in the embodiments of this application, the communication interface for realizing internal data interaction includes an EMIF interface. The EMIF interface configured in the main DSP processor, slave DSP processor, main FPGA device and slave FPGA device is used to assist in realizing low-speed data interaction or control signal transmission between processors.

[0010] According to the technical solution provided in the embodiments of this application, the communication interfaces configured for interaction with external devices by the main FPGA device include a 1M 1553B interface, a 4M 1553B interface, an LVDS interface, an Ethernet interface, and a synchronous / asynchronous RS40022 interface, so as to realize bidirectional information interaction with external devices.

[0011] According to the technical solution provided in the embodiments of this application, the debugging interface configured for each of the DSP processor, slave DSP processor, master FPGA device and slave FPGA device is a JTAG interface. The JTAG interface is connected to an external debugging device through hardware lines, which supports program burning, running status reading and fault diagnosis of each device.

[0012] According to the technical solution provided in the embodiments of this application, the system further includes a power module, which is connected to an external power supply device.

[0013] A second aspect of this application provides a rapid information processing method, based on the rapid information processing system described above, comprising: S100: System power-on initialization, the main DSP processor and the slave DSP processor load the startup software through their respective first memory, the main FPGA device and the slave FPGA device load the startup program through their respective fourth memory, and all devices enter the standby state. S200: The main DSP processor sends data processing instructions to the slave DSP processor, the main FPGA device, and the slave FPGA device through the internal communication interface. The instructions include the storage address of the data to be processed, the target processing device identifier, and the result return path. The target processing device includes the slave DSP processor, the main FPGA device, or the slave FPGA device. S300: The device that receives the instruction reads the data to be processed from its own configured corresponding memory according to the instruction, and transmits it to the corresponding memory unit configured by the target processing device through a preset high-speed interface; S400: The target processing device performs calculations or information processing on the received data, and after processing, temporarily stores the result data in the corresponding storage unit configured by itself. S500: The result data is returned to the corresponding storage unit configured on the transmitting device through the original preset high-speed interface, or sent to the external device by the main FPGA device through its configured external communication interface according to the instructions of the main DSP processor.

[0014] Further, in step S300, the corresponding memory for the device receiving the instruction to read the data to be processed is: the second or third memory corresponding to the main DSP processor and the slave DSP processor, and the fifth memory corresponding to the main FPGA device and the slave FPGA device; the corresponding storage unit configured for the target processing device is: the third memory corresponding to the main DSP processor and the slave DSP processor, and the fifth memory corresponding to the main FPGA device and the slave FPGA device.

[0015] Compared with existing technologies, the advantages of this application are as follows: by integrating master-slave DSP processors and master-slave FPGA devices on a single board, and adopting a multi-device collaborative architecture to replace the traditional multi-board design, the system integration is greatly improved, and the device size and space occupation are effectively reduced; each core device stores the boot program, pre-stored data and temporary data in a classified manner through a dedicated memory, and achieves efficient data interaction in conjunction with the internal communication interface; the main FPGA is additionally configured with an external communication interface to ensure stable connection with external devices; the overall structural optimization significantly enhances the system's operational stability, while reducing the failure risk caused by multi-board connections, and better adapts to the needs of complex multi-task information processing scenarios. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the structure of the rapid information processing system provided in Example 1; Figure 2 This is a schematic diagram of the data flow of the rapid information processing system in Example 1; Figure 3 This is a schematic diagram of the structure of the fast information processing method provided in Example 2.

[0017] Reference numerals: 1. Main DSP processor; 2. Slave DSP processor; 3. Main FPGA device; 4. Slave FPGA device; 5. First memory; 6. Second memory; 7. Third memory; 8. Fourth memory; 9. Fifth memory; 10. Power module. Detailed Implementation

[0018] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0020] Example 1 Please refer to Figure 1 and Figure 2 This embodiment provides a fast information processing system, including a substrate, and a main DSP processor 1, a slave DSP processor 2, a main FPGA device 3 and a slave FPGA device 4 integrated on the substrate; The main DSP processor 1 is connected to the slave DSP processor 2, the main FPGA device 3, and the slave FPGA device 4 via a preset high-speed interface, and the slave DSP processor 2 is connected to the main FPGA device 3 and the slave FPGA device 4 via a data connection. Both the main DSP processor 1 and the slave DSP processor 2 are equipped with a first memory 5, a second memory 6 and a third memory 7. The first memory 5 is used to store the startup software of the DSP processor, the second memory 6 is used to store pre-stored data information, and the third memory 7 is used to store pre-stored data information and temporary data. Both the master FPGA device 3 and the slave FPGA device 4 are equipped with a fourth memory 8 and a fifth memory 9. The fourth memory 8 is used to store the startup program of the FPGA device, and the fifth memory 9 is used to store pre-stored data information and temporary data. The main DSP processor 1, the slave DSP processor 2, the main FPGA device 3, and the slave FPGA device 4 are all configured with communication interfaces for internal data interaction, and the main FPGA device 3 is additionally configured with a communication interface for interaction with external devices.

[0021] Specifically, such as Figure 1 As shown, the system uses a highly integrated substrate as a carrier, integrating the main DSP processor 1, slave DSP processor 2, main FPGA device 3 and slave FPGA device 4 on the device pads preset on the surface of the substrate. Each device is connected to the circuit through the metal wiring inside the substrate, replacing the traditional multi-board split design, greatly reducing the overall size of the system and reducing the risk of inter-board connection failure.

[0022] The main DSP processor 1, as the core control unit of the system, establishes bidirectional data transmission channels with the slave DSP processor 2, the main FPGA device 3, and the slave FPGA device 4 through preset high-speed interfaces. It can issue control commands and transmit data to be processed to each slave device. The slave DSP processor 2 is connected to the main FPGA device 3 and the slave FPGA device 4 through the same type of preset high-speed interface to realize data interaction and collaborative processing between slave devices.

[0023] In terms of storage configuration, both the main DSP processor 1 and the slave DSP processor 2 are connected to the first memory 5, the second memory 6, and the third memory 7 via a data bus. The first memory 5 is directly connected to the boot control pin of the DSP processor and is used only to store the boot software of the DSP processor, ensuring that the boot program can be loaded quickly when the system is powered on. The second memory 6 is connected to the storage control pin of the DSP processor through an independent data channel and is specifically used to store pre-stored data information for the DSP processor to call when processing tasks. The third memory 7 is connected to the arithmetic unit pin of the DSP processor and is used to store pre-stored data information and temporary data generated during processing, taking into account both data storage and temporary caching functions.

[0024] Both the master FPGA device 3 and the slave FPGA device 4 are connected to the fourth memory 8 and the fifth memory 9 via a configuration bus: the fourth memory 8 is connected to the configuration pins of the FPGA device and is used only to store the startup program of the FPGA device to ensure that the logic configuration is completed quickly after the FPGA is powered on; the fifth memory 9 is connected to the logic operation module pins of the FPGA device and is used to store pre-stored data information and temporary data during processing to meet the data storage requirements of FPGA parallel processing.

[0025] In addition, the control pins of the main DSP processor 1, slave DSP processor 2, main FPGA device 3, and slave FPGA device 4 are all connected to the internal communication interface through substrate wiring. This interface is used for internal data interaction between the devices. The main FPGA device 3 additionally leads out an external communication interface through the interface terminal on the edge of the substrate. This interface is connected to the input and output pins of the main FPGA device 3 to realize the interaction between the system and external devices.

[0026] Furthermore, the preset high-speed interface includes a PCIe interface; The main DSP processor 1 and the main FPGA device 3, and the slave DSP processor 2 and the slave FPGA device 4 are connected via a PCIe interface. The PCIe interface adopts a 4X working mode, and the hardware circuit can be configured as 1 lane / 2 lane / 4 lane mode, with a maximum transmission rate of 5GBaud per lane.

[0027] Specifically, in the system, the data connections between the main DSP processor 1 and the main FPGA device 3, and between the slave DSP processor 2 and the slave FPGA device 4, are all implemented through PCIe interfaces constructed using internal wiring on the substrate. The hardware circuit of this PCIe interface adopts a standardized PCI Express architecture design, with a core operating mode configured as 4X mode, that is, data is transmitted in parallel through 4 independent data channels to ensure high-speed data interaction requirements.

[0028] Meanwhile, to adapt to the bandwidth adjustment requirements of different scenarios, the hardware circuit of this PCIe interface supports flexible configuration in 1-lane, 2-lane, or 4-lane modes: when the system is processing lightweight data tasks and has low requirements for transmission rate, the interface can be configured in 1-lane or 2-lane mode to reduce unnecessary resource consumption; when processing massive data and requiring high bandwidth support, it can be switched to 4-lane mode. In 4-lane mode, the maximum transmission rate of each lane can reach 5GBaud, which can meet the high real-time data transmission requirements between the main DSP processor 1 and the main FPGA device 3, and between the slave DSP processor 2 and the slave FPGA device 4, providing interface-level support for the system to efficiently process complex information.

[0029] Furthermore, the preset high-speed interface also includes an SRIO interface; The main DSP processor 1 and the slave DSP processor 2, and the main DSP processor 1 and the slave FPGA device 4 are connected via an SRIO interface. The SRIO interface adopts a 4X working mode, and a single DSP processor is configured with two SRIO interfaces to meet the multi-path connection requirements.

[0030] Specifically, in the system, the data connections between the main DSP processor 1 and the slave DSP processor 2, and between the main DSP processor 1 and the slave FPGA device 4, are all implemented through SRIO interfaces constructed using internal wiring on the substrate. This SRIO interface adopts a SerialRapidIO architecture design, with a core operating mode configured as 4X mode. It transmits data through four parallel serial data channels, adapting to high-throughput, low-latency data interaction scenarios between multiple devices, and meeting the real-time data scheduling requirements between processors and between processors and FPGA devices within the system.

[0031] Meanwhile, to ensure the stability and flexibility of multi-path connections, each DSP processor (including the main DSP processor 1 and the slave DSP processor 2) is configured with two independent SRIO interfaces through substrate wiring: one is used to realize direct data interaction between the main DSP processor 1 and the slave DSP processor 2, ensuring efficient transmission of instructions and data between the master and slave processors; the other is used to connect the main DSP processor 1 and the slave FPGA device 4, ensuring that the main DSP issues task instructions to the slave FPGA device 4 and processes and returns the data. The dual-interface design avoids the bottleneck of single-interface transmission and further improves the reliability of high-speed data interaction within the system.

[0032] Furthermore, the first memory 5 is a NOR FLASH memory, the second memory 6 is a NAND FLASH memory, the third memory 7 is a DDR3 SDRAM memory, the fourth memory 8 is a NOR FLASH memory, and the fifth memory 9 is a DDR3 SDRAM memory.

[0033] Specifically, the first memory 5 configured for the main DSP processor 1 and the slave DSP processor 2 uses NOR FLASH memory. This memory is directly connected to the boot control pin of the DSP processor through substrate wiring. Utilizing the fast read speed and random access characteristics of NOR FLASH memory, it ensures that the DSP processor can quickly load the boot software after power-on, shortening the system initialization time. The second memory 6 uses NAND FLASH memory, which is connected to the storage control module of the DSP processor through a data bus. Relying on the advantages of large capacity and low cost of NAND FLASH memory, it is used to store the pre-stored data information required for system operation for a long time, meeting the needs of massive static data storage. The third memory 7 uses DDR3 SDRAM memory, which is connected to the arithmetic unit pin of the DSP processor through a high-speed memory bus. Utilizing the high bandwidth and fast read / write speed of DDR3 SDRAM memory, it can both temporarily store pre-stored data information and cache temporary data generated during DSP processor processing in real time, adapting to the high-frequency data interaction needs during operation.

[0034] The fourth memory 8 configured on both the main FPGA device 3 and the slave FPGA device 4 uses NOR FLASH memory. It is connected to the configuration pins of the FPGA device through the configuration bus. Utilizing the fast read characteristics of NOR FLASH memory, it ensures that the FPGA device can quickly load the startup program after power-on, complete the logic configuration, and enter the standby state. The fifth memory 9 uses DDR3 SDRAM memory, which is connected to the logic operation module pins of the FPGA device through a high-speed data interface. Combined with the high throughput of DDR3 SDRAM memory, it meets the dual requirements of pre-stored data retrieval and temporary data caching during the parallel processing of the FPGA device, providing storage support for the FPGA to efficiently complete data processing tasks.

[0035] Furthermore, the communication interface for realizing internal data interaction includes an EMIF interface. The EMIF interfaces configured on the main DSP processor 1, the slave DSP processor 2, the main FPGA device 3, and the slave FPGA device 4 are used to assist in realizing low-speed data interaction or control signal transmission between the processors.

[0036] The main DSP processor 1, slave DSP processor 2, main FPGA device 3, and slave FPGA device 4 are all equipped with industry-standard EMIF interfaces. The hardware circuit of this EMIF interface is directly connected to the control pins and low-speed data pins of each device. Its core function is to assist in realizing low-speed data interaction and control signal transmission between the processors and devices, making up for the resource waste problem of the preset high-speed interface in low-speed and low-bandwidth scenarios.

[0037] In actual operation, when the system does not require high real-time and high-throughput data transmission, each device can complete data interaction through the EMIF interface: for example, the main DSP processor 1 sends a low-rate operating mode configuration signal to the slave FPGA device 4 through the EMIF interface, or the slave DSP processor 2 sends back device operating status data to the main FPGA device 3 through the EMIF interface. This not only ensures the comprehensiveness of internal data interaction, but also avoids the ineffective occupation of high-speed interface resources, and further optimizes the efficiency of system resource allocation.

[0038] Furthermore, the main FPGA device 3 is configured with communication interfaces for interacting with external devices, including a 1M1553B interface, a 4M 1553B interface, an LVDS interface, an Ethernet interface, and a synchronous / asynchronous RS40022 interface, to achieve bidirectional information interaction with external devices.

[0039] Specifically, the main FPGA device 3 integrates a 1M1553B interface, a 4M 1553B interface, an LVDS interface, an Ethernet interface, and a synchronous / asynchronous RS40022 interface through pre-set interface terminals on the edge of the substrate and internal dedicated wiring. Each interface is directly connected to the input / output logic module pins of the main FPGA device 3, forming a multi-type, all-scenario external interaction channel to meet the connection and data transmission needs of different external devices.

[0040] Furthermore, the debugging interface configured for each of the DSP processor, slave DSP processor 2, master FPGA device 3, and slave FPGA device 4 is a JTAG interface. The JTAG interface is connected to an external debugging device through hardware lines, supporting program burning, running status reading, and fault diagnosis for each device.

[0041] Specifically, the main DSP processor 1, slave DSP processor 2, main FPGA device 3, and slave FPGA device 4 are all configured with JTAG interfaces conforming to the IEEE 1149.1 standard through dedicated debugging circuitry inside the substrate. The JTAG pins of each device converge to a pre-set JTAG debugging interface terminal at the edge of the substrate via substrate wiring. This terminal can be directly connected to external debugging equipment via a dedicated data line, forming a unified debugging path.

[0042] In practical applications, control commands can be sent to the JTAG interface via external debugging equipment to program various devices—writing the compiled DSP boot software and FPGA boot program into the corresponding memory through the JTAG interface; at the same time, the operating status data of each device can be read in real time, such as the register values ​​of the DSP processor and the working status of the FPGA logic units; when the system malfunctions, fault logs and data snapshots can also be obtained through the JTAG interface to quickly locate the fault node, providing convenient and efficient hardware support for system debugging, maintenance and functional upgrades.

[0043] Furthermore, the system also includes a power module 10, which is connected to an external power supply device.

[0044] Specifically, the power module 10 in the system is integrated on the substrate through the power mounting area preset on the substrate. Its input terminal is directly connected to the external power supply equipment through the external power line to receive external power input. The output terminal of the power module 10 is connected to the power pins of the main DSP processor 1, the slave DSP processor 2, the main FPGA device 3, the slave FPGA device 4 and each memory through multiple sets of independent power wiring inside the substrate.

[0045] In this high-speed information processing system, the main DSP processor 1 acts as the system's overall scheduler, controlling the execution of all tasks and data interaction. The slave DSP processor 2, main FPGA device 3, and slave FPGA device 4 all complete their respective computational or information processing tasks under the commands of the main DSP processor 1. The high-speed information processing system has four main data flows, such as... Figure 2 Data streams A, B, C, and D are shown in the diagram.

[0046] Data Flow A: This data flow mainly realizes the information interaction between the main DSP processor 1 and the main FPGA device 3. The main DSP processor 1 reads data from its own third memory 7 and transmits it to the storage space of the fifth memory 9 of the main FPGA device 2 via the PCIe interface; after the main FPGA device 3 finishes processing the data, it transmits the processed data back to the third memory 7 of the main DSP processor 1 via the PCIe interface for storage.

[0047] Data Flow B: This data flow mainly realizes the information interaction between the main FPGA processor 1 and the slave DSP processor 2. The slave DSP processor 2 reads data from its own third memory 7 and transmits it to the storage space of the fifth memory 9 of the main FPGA device 3 via the SRIO interface; after the main FPGA device 3 finishes processing the data, it transmits the processed data back to the third memory 7 of the slave DSP processor 2 via the SRIO interface for storage.

[0048] Data Flow C: This data flow mainly realizes the information exchange between the DSP processor 2 and the FPGA device 4. The DSP processor 2 reads data from its own third memory 7 and transmits it to the storage space of the fifth memory 9 of the main FPGA device 3 via the PCIe interface; after the main FPGA device 3 processes the data, it transmits the processed data back to the third memory 7 of the DSP processor 2 via the PCIe interface for storage.

[0049] Data Flow D: This data flow mainly realizes the information interaction between the main DSP processor 1 and the slave DSP processor 2. The main DSP processor 1 reads data from its own third memory 7 and transmits it to the storage space of the slave DSP processor 2's third memory 7 via the SRIO interface; after the slave DSP processor 2 finishes processing the data, it transmits the processed data back to the main DSP processor 1's memory 7 via the SRIO interface for storage.

[0050] In addition to the four main data paths mentioned above, for external devices, when the main FPGA device 3 receives the read command from the main DSP processor 1, it receives the data into the internal fifth memory 9 or transmits it to the third memory 7 of the main DSP processor 1 through the various interfaces of the main FPGA device 3; when the main FPGA device 3 receives the write command from the main DSP processor 1, it sends the data in the point memory 7 and the fifth memory 9 out through the various interfaces of the main FPGA device 3.

[0051] Example 2 refer to Figure 3 Based on Embodiment 1 above, this embodiment provides a rapid information processing method, which, based on the rapid information processing system described in Embodiment 1, includes: S100: System power-on initialization. The main DSP processor 1 and the slave DSP processor 2 load the startup software through their respective first memory 5. The main FPGA device 3 and the slave FPGA device 4 load the startup program through their respective fourth memory 8. All devices enter the standby state.

[0052] Specifically, in step S100, after the system is connected to an external power supply, the power module 10 supplies power to the main DSP processor 1, the slave DSP processor 2, the main FPGA device 3, the slave FPGA device 4, and each memory. The startup control pins of the main DSP processor 1 and the slave DSP processor 2 read the startup software stored in their respective first memories 5 through dedicated lines to complete the processor core initialization and peripheral configuration; the configuration pins of the main FPGA device 3 and the slave FPGA device 4 read the startup program stored in their respective fourth memories 8 to complete the configuration of internal logic units and interface modules. After all devices have completed initialization, they all enter a standby state, waiting for the main DSP processor 1 to issue processing instructions.

[0053] S200: The main DSP processor 1 sends data processing instructions to the slave DSP processor 2, the main FPGA device 3, and the slave FPGA device 4 through the internal communication interface. The instructions include the storage address of the data to be processed, the target processing device identifier, and the result return path. The target processing device includes the slave DSP processor 2, the main FPGA device 3, or the slave FPGA device 4.

[0054] Specifically, in step S200, the main DSP processor 1 generates data processing instructions based on the system's preset task requirements. These instructions include the storage address of the data to be processed in the corresponding memory (e.g., the address of the second memory 6 of the DSP device, or the address of the fifth memory 9 of the FPGA device), the target processing device identifier (specifying whether it is the DSP processor 2, the main FPGA device 3, or the slave FPGA device 4), and the result return path (returning to the main DSP processor 1 or sending to an external device). The main DSP processor 1 converts the instructions into control signals through its internal communication interface and transmits them to the control pins of the slave DSP processor 2, the main FPGA device 3, and the slave FPGA device 4, respectively, achieving precise task allocation.

[0055] S300: The device that receives the instruction reads the data to be processed from its own configured corresponding memory according to the instruction, and transmits it to the corresponding memory unit configured by the target processing device through a preset high-speed interface.

[0056] Specifically, in step S300, the device receiving the instruction first parses the storage address in the instruction: if it is a slave DSP processor 2, it reads the data to be processed from its own second memory 6 or third memory 7; if it is a master FPGA device 3 or a slave FPGA device 4, it reads the data to be processed from its own fifth memory 9. Subsequently, the device transmits the data to be processed to the corresponding storage unit of the target device specified in the instruction through a preset high-speed interface (the master DSP processor 1 and the master FPGA device 3, and the slave DSP processor 2 and the slave FPGA device 4 use a PCIE interface, and the master DSP processor 1 and the slave DSP processor 2, and the master DSP processor 1 and the slave FPGA device 4 use an SRIO interface). When the target is a DSP processor, the data is transmitted to the third memory 7; when the target is an FPGA device, the data is transmitted to the fifth memory 9.

[0057] S400: The target processing device performs calculations or information processing on the received data, and after processing, temporarily stores the result data in the corresponding storage unit configured in itself.

[0058] Specifically, after receiving the data to be processed, the target device activates the corresponding processing module according to the instruction type: the main DSP processor 1 and the slave DSP processor 2 call their internal arithmetic units to perform serial processing on the data in the third memory 7 based on a preset algorithm; the main FPGA device 3 and the slave FPGA device 4 activate their internal parallel logic units to perform parallel processing on the data in the fifth memory 9 using programmable resources. Temporary data generated during processing is temporarily stored in its corresponding storage unit. After processing is completed, the final result data is still temporarily stored in the same storage unit, awaiting the next instruction.

[0059] S500: The result data is returned to the corresponding storage unit configured on the transmitting device through the original preset high-speed interface, or sent to the external device by the main FPGA device 3 through its configured external communication interface according to the instructions of the main DSP processor 1.

[0060] Specifically, if the instruction specifies that the result should be sent back to the sending device, the target device will transmit the result data from its own storage unit to the corresponding storage unit of the sending device through the original preset high-speed interface; if the instruction specifies that the result should be output to an external device, the main DSP processor 1 will send an output instruction to the main FPGA device 3, and the main FPGA device 3 will read the result data from its own fifth memory 9, convert the data into a signal format suitable for the external device through its configured external communication interface, and transmit it to the external device to complete the entire information processing flow.

[0061] Further, in step S300, the corresponding memory for the device receiving the instruction to read the data to be processed is: the second memory 6 or the third memory 7 corresponding to the main DSP processor 1 and the slave DSP processor 2, and the fifth memory 9 corresponding to the main FPGA device 3 and the slave FPGA device; the corresponding storage unit configured for the target processing device is: the third memory 7 corresponding to the main DSP processor 1 and the slave DSP processor 2, and the fifth memory 9 corresponding to the main FPGA device 3 and the slave FPGA device 4.

[0062] Specifically, when the system executes step S300, the device that receives the instruction from the main DSP processor 1 needs to read the data to be processed from the corresponding preset memory according to its own device type (DSP processor or FPGA device): If the device receiving the instruction is the master DSP processor 1 or the slave DSP processor 2, then the memory is selected according to the attributes of the data to be processed in the instruction: if the data is static basic data pre-stored by the system, it is read from its own second memory 6; if the data is temporary data generated during the early processing or pre-stored data that needs to be quickly called, it is read from its own third memory 7. By classifying and reading, the storage characteristics of different data are adapted to ensure data reading efficiency. If the device receiving the instruction is either the master FPGA device 3 or the slave FPGA device 4, it will uniformly read the data to be processed from its own fifth memory 9. Since FPGA devices mainly use parallel processing, the high read and write speed of the fifth memory 9 can match its data processing rhythm and avoid the storage bottleneck affecting the processing efficiency.

[0063] Simultaneously, after the data to be processed is transmitted to the target processor, it needs to be stored in the corresponding memory unit preset by the target device: If the target processing device is the master DSP processor 1 or the slave DSP processor 2, the data is directly stored in its third memory 7. This memory serves as a high-speed cache unit for the DSP device, which can quickly provide data support for the DSP's computing unit and adapt to the real-time data requirements of DSP serial computing. If the target processing device is the master FPGA device 3 or the slave FPGA device 4, the data is directly stored in its fifth memory 9. This memory is directly connected to the parallel logic operation module of the FPGA, which can realize parallel data access, match the parallel processing capability of the FPGA, and ensure the smoothness of the data processing flow.

[0064] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A rapid information processing system, characterized in that, It includes a substrate, and a main DSP processor (1), a slave DSP processor (2), a main FPGA device (3), and a slave FPGA device (4) integrated on the substrate. The main DSP processor (1) is connected to the slave DSP processor (2), the main FPGA device (3) and the slave FPGA device (4) via a preset high-speed interface, and the slave DSP processor (2) is connected to the main FPGA device (3) and the slave FPGA device (4) via a data connection. The main DSP processor (1) and the slave DSP processor (2) are each equipped with a first memory (5), a second memory (6) and a third memory (7). The first memory (5) is used to store the startup software of the DSP processor, the second memory (6) is used to store pre-stored data information, and the third memory (7) is used to store pre-stored data information and temporary data. Both the master FPGA device (3) and the slave FPGA device (4) are equipped with a fourth memory (8) and a fifth memory (9). The fourth memory (8) is used to store the startup program of the FPGA device, and the fifth memory (9) is used to store pre-stored data information and temporary data. The main DSP processor (1), the slave DSP processor (2), the main FPGA device (3), and the slave FPGA device (4) are all equipped with communication interfaces for internal data interaction, and the main FPGA device (3) is additionally equipped with a communication interface for interaction with external devices.

2. The rapid information processing system according to claim 1, characterized in that, The preset high-speed interface includes a PCIe interface; The main DSP processor (1) and the main FPGA device (3), and the slave DSP processor (2) and the slave FPGA device (4) are connected via a PCIE interface. The PCIE interface adopts a 4X working mode, and the hardware circuit can be configured as 1 lane / 2 lane / 4 lane mode, with a maximum transmission rate of 5GBaud per lane.

3. The rapid information processing system according to claim 2, characterized in that, The preset high-speed interface also includes an SRIO interface; The main DSP processor (1) and the slave DSP processor (2), and the main DSP processor (1) and the slave FPGA device (4) are connected via an SRIO interface. The SRIO interface adopts a 4X working mode, and a single DSP processor is configured with two SRIO interfaces to meet the multi-path connection requirements.

4. The rapid information processing system according to claim 3, characterized in that, The first memory (5) is a NOR FLASH memory, the second memory (6) is a NAND FLASH memory, the third memory (7) is a DDR3 SDRAM memory, the fourth memory (8) is a NOR FLASH memory, and the fifth memory (9) is a DDR3 SDRAM memory.

5. The rapid information processing system according to claim 4, characterized in that, The communication interface for realizing internal data interaction includes an EMIF interface. The EMIF interface configured in the main DSP processor (1), slave DSP processor (2), main FPGA device (3) and slave FPGA device (4) is used to assist in realizing low-speed data interaction or control signal transmission between the processors.

6. The rapid information processing system according to claim 5, characterized in that, The main FPGA device (3) is configured with communication interfaces for interacting with external devices, including a 1M 1553B interface, a 4M 1553B interface, an LVDS interface, an Ethernet interface, and a synchronous / asynchronous RS40022 interface, so as to realize bidirectional information interaction with external devices.

7. The rapid information processing system according to claim 6, characterized in that, The debugging interface configured for each of the DSP processor, the slave DSP processor (2), the master FPGA device (3), and the slave FPGA device (4) is a JTAG interface. The JTAG interface is connected to an external debugging device through a hardware line, which supports the programming, reading of the running status, and troubleshooting of each device.

8. The rapid information processing system according to claim 7, characterized in that, The system also includes a power module (10), which is connected to an external power supply device.

9. A rapid information processing method, based on the rapid information processing system as described in any one of claims 1-8, characterized in that, include: S100: The system is powered on and initialized. The main DSP processor (1) and the slave DSP processor (2) load the startup software through their respective first memory (5). The main FPGA device (3) and the slave FPGA device (4) load the startup program through their respective fourth memory (8). All devices enter the standby state. S200: The main DSP processor (1) sends data processing instructions to the slave DSP processor (2), the main FPGA device (3) and the slave FPGA device (4) through the internal communication interface. The instructions include the storage address of the data to be processed, the target processing device identifier and the result return path. The target processing device includes the slave DSP processor (2), the main FPGA device (3) or the slave FPGA device (4). S300: The device that receives the instruction reads the data to be processed from its own configured corresponding memory according to the instruction, and transmits it to the corresponding memory unit configured by the target processing device through a preset high-speed interface; S400: The target processing device performs calculations or information processing on the received data, and after processing, temporarily stores the result data in the corresponding storage unit configured by itself. S500: The result data is returned to the corresponding storage unit configured by the transmitting device through the original preset high-speed interface, or sent to the external device by the main FPGA device (3) through its configured external communication interface according to the instructions of the main DSP processor (1).

10. The rapid information processing method according to claim 9, characterized in that, In step S300, the corresponding memory for the device receiving the instruction to read the data to be processed is: the second memory (6) or third memory (7) corresponding to the main DSP processor (1) and the slave DSP processor (2), and the fifth memory (9) corresponding to the main FPGA device (3) and the slave FPGA device; the corresponding memory unit configured for the target processing device is: the third memory (7) corresponding to the main DSP processor (1) and the slave DSP processor (2), and the fifth memory (9) corresponding to the main FPGA device (3) and the slave FPGA device (4).

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