Vector processor dynamic compression method and system oriented to sparse calculation

Abstract

The invention discloses a sparse computation-oriented vector processor dynamic compression method and system, and belongs to the technical field of data processing and vector processors, and the method is implemented by the following steps of: adding a metadata register for each vector register in a vector register file, the vector register block is used for describing the distribution condition of effective non-zero elements in the vector register to form a metadata register block; a sparse data encoder is additionally arranged on a write-in path of a vector register file and is responsible for compressing data and generating metadata; a sparse data decoder is additionally arranged on a memory writing path of a vector register file and is responsible for restoring compressed data into a standard dense format. According to the method, under the condition that any software code is not modified, the access bandwidth and power consumption of the VRF are greatly reduced, and the sparse data processing efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of data processing and vector processor technology, specifically a dynamic compression method and system for vector processors oriented towards sparse computing. Background Technology

[0002] In key areas such as high-performance computing, artificial intelligence, and scientific computing, sparse matrix operations have become a critical computational load supporting core applications. In such matrices, the vast majority of elements are zero, with only a few being non-zero. Using traditional dense matrix operations methods would waste significant computational resources and storage bandwidth on zero-value operations, severely limiting system efficiency. While existing software-level optimization schemes can store only non-zero values ​​and their positions using formats such as Compressed Sparse Rows (CSR) and Compressed Sparse Columns (CSC), these schemes require specific modifications to the algorithm and program code, increasing programming complexity and resulting in significantly lower compression efficiency compared to hardware-level optimization schemes.

[0003] While dedicated sparse computing accelerators have emerged at the hardware level, these devices often rely on specific instruction set extensions or dedicated programming models, limiting their versatility and hindering seamless compatibility with existing software ecosystems optimized for dense computing. Vector processors, widely used for their powerful data-level parallel processing capabilities, rely heavily on their core component, the Vector Register File (VRF), as a crucial link between the computing unit and the memory system. Its access bandwidth and power consumption characteristics directly determine the processor's overall performance and energy efficiency. However, traditional VRFs still require storing complete vectors (containing a large number of zeros) when processing sparse data, resulting in a significant waste of valuable on-chip storage resources and read / write bandwidth. Therefore, there is an urgent need in this field for an innovative solution: to achieve efficient processing of sparse data at the hardware level without altering existing software programming models. Summary of the Invention

[0004] The technical objective of this invention is to address the above-mentioned shortcomings by providing a dynamic compression method and system for vector processors in sparse computing, which can significantly reduce the access bandwidth and power consumption of VRF without modifying any software code, thereby improving the efficiency of processing sparse data.

[0005] The technical solution adopted by this invention to solve its technical problem is:

[0006] A dynamic compression method for vector processors aimed at sparse computation, the implementation of which includes:

[0007] Add a metadata register to each vector register in the vector register file VRF to describe the distribution of valid non-zero elements in that vector register, forming a metadata register group;

[0008] Add a sparse data encoder to the write path of the vector register file (VRF) to compress data and generate metadata;

[0009] A sparse data decoder is added to the memory write path of the Vector Register File (VRF) to restore the compressed data to the standard dense format.

[0010] This method introduces a hardware mechanism within the vector processor to dynamically compress the data stored in the VRF, storing only non-zero valid data and automatically decompressing it when the data is read out. This significantly reduces the access bandwidth and power consumption of the VRF without modifying any software code, thereby improving the efficiency of processing sparse data.

[0011] Furthermore, the metadata register group is associated with each vector register in the vector register file VRF and is used to store compressed format metadata of the corresponding vector data;

[0012] The metadata is in bitmap format, where each bit indicates whether the element at the corresponding position in the original vector is zero.

[0013] Furthermore, the sparse data encoder receives the raw vector data to be written to the vector register file VRF; the encoder analyzes the input vector, identifies all non-zero elements and their positions, generates metadata based on the position information and stores it in the corresponding metadata register, and compresses the raw vector into a compact format containing only non-zero data, and then writes it to the physical storage unit of the vector register file VRF.

[0014] Furthermore, when data needs to be sent to main memory, the sparse data decoder mixes the compact format data stored in the vector register file (VRF) with zero values ​​according to the information in the metadata register, and restores it to the standard dense vector format in real time, ensuring that the data format received by the memory subsystem is completely consistent with that when it is uncompressed, thereby achieving software transparency.

[0015] Furthermore, the method is implemented as follows:

[0016] After the data read from memory enters the computation channel of the vector processor through the loading unit, the sparse coding unit located in the write path of the vector register file (VRF) analyzes the original vector to be written. On the one hand, it generates bitmap-format metadata and stores it in the metadata register group that is associated with the vector registers of the vector register file (VRF). On the other hand, it compresses the original vector into a compact format that contains only non-zero data and writes it into the vector register file (VRF).

[0017] When data needs to be written back to memory from the Vector Register File (VRF), the sparse decoding unit located on the memory write path mixes the compact format data and zero values ​​in the VRF with the original positions according to the metadata stored in the metadata register group, and restores it to the standard dense vector format in real time. Then, it is written back to memory through the storage unit. The entire "compression-restore" process is completely transparent to the software, which not only effectively reduces storage bandwidth consumption, but also achieves efficient storage and transmission of sparse data through the collaboration of the metadata register group, sparse encoding unit, sparse decoding unit and the original modules of the processor.

[0018] Furthermore, when the vector processor performs vector computation (such as "vector A × vector B"), it synchronously retrieves the metadata and vector data of the corresponding vector registers from the metadata register set and the vector register file (VRF). If the metadata indicates that vector A or vector B involved in the computation has a zero element, the computation type can be further identified (for example, in multiplication, if the corresponding element of A or B is zero, the operation can be skipped and a zero result can be output). With this design, when dealing with sparse matrices, a large number of invalid computations such as "multiplications with zero participants" and "additions of zero and zero" can be omitted; at the same time, since zero elements do not need to be stored, a lot of storage time can be saved, significantly shortening the overall processing cycle of sparse matrices.

[0019] Furthermore, the compressed storage logic of sparse vectors in the metadata register set and the vector register file VRF is as follows:

[0020] The metadata register group is responsible for recording the non-zero distribution characteristics of the vector, marking each position of the original vector as non-zero, defining the start and end positions of the continuous distribution of non-zero elements in the original vector, and counting the total number of non-zero elements.

[0021] The vector register file (VRF) only compresses and stores the values ​​of non-zero elements, while retaining the original values ​​in subsequent positions to maintain the length of the vector structure.

[0022] This design, through the combination of "metadata register group marking non-zero distribution + vector register file compressed storage of non-zero values", not only omits the storage time of a large number of zero elements in the original vector, but also provides a foundation for subsequent sparse data processing (such as skipping invalid calculations of zero elements and reducing data transmission bandwidth).

[0023] Furthermore, the workflow of the sparse coding unit is as follows:

[0024] The original vector first passes through zero detection logic to identify non-zero elements. The zero detection logic needs to focus on whether the highest bit is the sign bit. Then, it is processed by compression logic. On the one hand, metadata is generated and written to the metadata register group, including bitmap, start and end positions of non-zero elements, and total number of non-zero elements. On the other hand, the values ​​of non-zero elements are compressed and written to the vector register file VRF, omitting zero elements to reduce storage overhead.

[0025] The workflow of the sparse decoding unit is as follows:

[0026] When data needs to be written back to memory from the Vector Register File (VRF), the metadata (bitmap, position, total) stored in the metadata register group and the non-zero values ​​compressed and stored in the VRF are input together into the data population logic. This logic restores the non-zero values ​​to the corresponding positions in the original vector based on the non-zero positions recorded in the metadata, and fills the remaining positions with zeros, finally restoring the complete original vector. This ensures that the memory receives the standard dense vector format, achieving sparse data restoration that is transparent to the software.

[0027] This invention also claims a vector processor dynamic compression device for sparse computing, comprising:

[0028] Metadata Register File (MRF): Associated with each vector register in the Vector Register File (VRF), it stores compressed metadata of the corresponding vector data; this metadata can be in bitmap format, where each bit indicates whether the element at the corresponding position in the original vector is zero;

[0029] Sparse Encode Unit (SEU): Located on the write path of the Vector Register File (VRF), it receives the raw vector data to be written to the VRF. The encoder analyzes the input vector, identifies all non-zero elements and their positions, generates metadata based on the position information and stores it in the corresponding metadata register, and compresses the raw vector into a compact format containing only non-zero data, and then writes it to the physical storage unit of the VRF.

[0030] Sparse Decode Unit (SDU): Located on the write path to memory of the Vector Register File (VRF), when data needs to be sent to main memory, this decoder mixes the compact format data stored in the VRF with zero values ​​according to the information in the metadata register, and restores it in real time to the standard dense vector format, ensuring that the data format received by the memory subsystem is completely consistent with the uncompressed data, thereby achieving software transparency.

[0031] This device can implement the above-described method.

[0032] The present invention also claims a computer-readable medium storing computer instructions that, when executed by a processor, implement the above-described method.

[0033] Compared with existing technologies, the vector processor dynamic compression method and system of the present invention for sparse computing has the following advantages:

[0034] First, it significantly reduces the amount of data actually read and written by the VRF, thereby reducing the port bandwidth pressure and dynamic power consumption of the VRF.

[0035] Secondly, this method is completely transparent to software, and existing compilers and applications can automatically benefit without any modification.

[0036] Finally, this invention improves the overall energy efficiency and performance of vector processors when processing highly sparse data. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the overall architecture of a vector processor dynamic compression method for sparse computing provided in one embodiment of the present invention;

[0038] Figure 2 This is a diagram illustrating the metadata register format provided in one embodiment of the present invention;

[0039] Figure 3 This is a flowchart illustrating the SEU encoding process according to an embodiment of the present invention;

[0040] Figure 4 This is a flowchart illustrating the SDU decoding process provided in one embodiment of the present invention. Detailed Implementation

[0041] The present invention will be further described below with reference to specific embodiments.

[0042] This invention provides a dynamic compression method for vector processors in sparse computing. It offers a hardware mechanism for dynamic data compression and decompression within a Vector Register File (VRF), enabling efficient processing of sparse data (such as sparse matrices) and significantly reducing register file access bandwidth and power consumption, while maintaining complete transparency to upper-layer software applications. The implementation of this method includes:

[0043] Add a metadata register to each vector register in the vector register file VRF to describe the distribution of valid non-zero elements in that vector register, forming a metadata register group;

[0044] Add a sparse data encoder to the write path of the vector register file (VRF) to compress data and generate metadata;

[0045] A sparse data decoder is added to the memory write path of the Vector Register File (VRF) to restore the compressed data to the standard dense format.

[0046] The Metadata Register File (MRF), associated with each vector register in the Vector Register File (VRF), stores compressed metadata of the corresponding vector data. This metadata can be in bitmap format, where each bit indicates whether the element at the corresponding position in the original vector is zero.

[0047] The Sparse Encode Unit (SEU), located on the write path of the VRF, receives the raw vector data to be written to the VRF. The encoder analyzes the input vector, identifies all non-zero elements and their positions, generates metadata based on the position information and stores it in the corresponding metadata register, and simultaneously compresses the raw vector into a compact format containing only non-zero data before writing it to the physical storage unit of the VRF.

[0048] The Sparse Decode Unit (SDU) is located on the VRF's write path to memory. When data needs to be sent to main memory, the decoder mixes the compact format data stored in the vector register file VRF with zero values ​​according to the information in the metadata register, and restores it in real time to the standard dense vector format. This ensures that the data format received by the memory subsystem is completely consistent with the uncompressed format, thereby achieving software transparency.

[0049] like Figure 1 The diagram illustrates a vector processor data path architecture that supports transparent compression of sparse data, and its implementation process is as follows:

[0050] After the data read from memory enters the computation channel of the vector processor via the load unit, the sparse coding unit (SEU) located in the write path of the vector register file (VRF) analyzes the original vector to be written. On the one hand, it generates bitmap format metadata and stores it in the metadata register group (MRF) that is associated one-to-one with the vector registers of the vector register file (VRF). On the other hand, it compresses the original vector into a "compact format containing only non-zero data" and writes it to the vector register file (VRF).

[0051] When data needs to be written back to memory from the Vector Register File (VRF), the Sparse Decoding Unit (SDU) located on the memory write path mixes the compact format data and zero values ​​in the VRF with the original positions according to the metadata stored in the Metadata Register Set (MRF), restores it to the standard dense vector format in real time, and then writes it back to memory via the Store Unit. The entire "compression-restore" process is completely transparent to the software, which not only effectively reduces storage bandwidth consumption, but also achieves efficient storage and transmission of sparse data through the collaboration of MRF, SEU, SDU and the original modules of the processor.

[0052] Furthermore, when the vector processor performs vector computations (such as "vector A × vector B"), it synchronously retrieves the metadata and vector data of the corresponding vector registers from the metadata register set MRF and the vector register file VRF. If the metadata indicates that vector A or vector B involved in the computation has a zero element, the computation type can be further identified (for example, in multiplication, if the corresponding element of A or B is zero, the operation can be skipped and the result of zero can be output). With this design, when dealing with sparse matrices, a large number of invalid computations such as "multiplications with zero participation" and "additions of zero and zero" can be omitted; at the same time, since zero elements do not need to be stored, a lot of storage time can be saved, significantly shortening the overall processing cycle of sparse matrices.

[0053] like Figure 2 The diagram illustrates the compressed storage logic of sparse vectors in the Metadata Register Set (MRF) and Vector Register File (VRF):

[0054] Taking the original vector [0,0,9,0,1,0,3,0] as an example, the metadata register group MRF is responsible for recording the non-zero distribution characteristics of the vector. The bitmap (8'b00101010) marks each position of the original vector as non-zero ("1" represents non-zero, "0" represents zero). The start bit (2) and end bit (6) define the start and end positions of the continuous distribution of non-zero elements in the original vector. The total number (3) counts the total number of non-zero elements.

[0055] The vector register file (VRF) only compresses and stores the values ​​of non-zero elements (9, 1, 3), while keeping the original values ​​in subsequent positions to maintain the length of the vector structure.

[0056] This design, through the combination of "MRF marking non-zero distribution + VRF compression storage of non-zero values", not only omits the storage time of a large number of zero elements in the original vector, but also provides a foundation for subsequent sparse data processing (such as skipping invalid calculations of zero elements and reducing data transmission bandwidth).

[0057] like Figure 3The diagram illustrates the workflow of a Sparse Coding Unit (SEU):

[0058] The original vector [0,5,0,0,0,7,0,0] first passes through zero-detection logic to identify non-zero elements (values ​​5 and 7, located in the 1st and 5th bits respectively). The zero-detection logic focuses on whether the highest bit is the sign bit. Then, it is processed by compression logic. On the one hand, metadata is generated and written to the metadata register group (MRF) – 0x22 is a bitmap (marking the “non-zero / zero” state of each element), 1 and 5 record the start and end positions of non-zero elements, and 2 indicates the total number of non-zero elements. On the other hand, the values ​​of non-zero elements 5 and 7 are compressed and written to the vector register file (VRF), omitting zero elements to reduce storage overhead.

[0059] like Figure 4 The diagram illustrates the workflow of the Sparse Decoding Unit (SDU):

[0060] When data needs to be written back to memory from the vector register file (VRF), the metadata (bitmap, position, total) stored in the metadata register group (MRF) and the non-zero values ​​5 and 7 stored in the compressed vector register file (VRF) are input together into the data population logic. This logic restores the non-zero values ​​5 and 7 to their corresponding positions (1st and 5th bits) in the original vector based on the non-zero positions recorded in the metadata, and fills the remaining positions with zeros, finally restoring the complete original vector [0,5,0,0,0,7,0,0], ensuring that the memory receives the standard dense vector format, and realizing sparse data restoration that is transparent to the software.

[0061] This method adds a Metadata Register Set (MRF), a Sparse Coding Unit (SEU), and a Sparse Decoding Unit (SDU). During data loading, the SEU analyzes the original vector, generates metadata which is stored in the MRF, and simultaneously compresses the vector into a format containing only non-zero data, writing it to the Vector Register File (VRF). When writing back to memory, the SDU restores the vector to a standard dense vector based on the MRF metadata, all transparent to the software. During computation, the metadata can also be used to skip invalid operations involving zero elements. This design reduces storage bandwidth, saves storage space, eliminates invalid calculations involving zero elements, and requires no software modification, significantly shortening the sparse matrix processing time.

[0062] This method introduces a hardware mechanism within the vector processor to dynamically compress the data stored in the VRF, storing only non-zero valid data and automatically decompressing it when the data is read out. This significantly reduces the access bandwidth and power consumption of the VRF without modifying any software code, thereby improving the efficiency of processing sparse data.

[0063] This invention also claims a vector processor dynamic compression device for sparse computing, comprising:

[0064] Metadata Register File (MRF): Associated with each vector register in the Vector Register File (VRF), it stores compressed metadata of the corresponding vector data. This metadata can be in bitmap format, where each bit indicates whether the element at the corresponding position in the original vector is zero.

[0065] The Sparse Encode Unit (SEU) is located on the write path of the Vector Register File (VRF) and receives the raw vector data to be written to the VRF. This encoder analyzes the input vector, identifies all non-zero elements and their positions, generates metadata based on the position information and stores it in the corresponding metadata register, and simultaneously compresses the raw vector into a compact format containing only non-zero data before writing it to the physical storage unit of the VRF.

[0066] Sparse Decode Unit (SDU): Located on the write path to memory of the Vector Register File (VRF), when data needs to be sent to main memory, the decoder mixes the compact format data stored in the VRF with zero values ​​according to the information in the metadata register, and restores it in real time to the standard dense vector format, ensuring that the data format received by the memory subsystem is completely consistent with that of the uncompressed data, thereby achieving software transparency.

[0067] This device can implement the vector processor dynamic compression method for sparse computing described in the above embodiments. Its architecture is implemented as follows:

[0068] Data read from memory enters the vector processor's computation lane via the load unit. The sparse encoding unit (SEU), located on the Vector Register File (VRF) write path, analyzes the original vector to be written. On one hand, it generates bitmap-format metadata and stores it in the metadata register set (MRF) associated with each VRF vector register. On the other hand, it compresses the original vector into a "compact format containing only non-zero data" and writes it to the VRF. When data needs to be written back to memory from the VRF, the sparse decoding unit (SDU), located on the memory write path, mixes the compact format data in the VRF with zero values ​​according to their original positions based on the metadata stored in the MRF, restoring it in real time to the standard dense vector format. Then, it is written back to memory via the store unit. The entire "compression-restoration" process is completely transparent to the software, effectively reducing storage bandwidth consumption and achieving efficient storage and transmission of sparse data through the collaboration of the MRF, SEU, SDU, and the processor's original modules. Furthermore, when the vector processor performs vector computations (such as "vector A × vector B"), it synchronously retrieves the metadata and vector data of the corresponding vector registers from the MRF and VRF. If the metadata indicates that vector A or vector B involved in the computation has a zero element, the computation type can be further identified (for example, in multiplication, if the corresponding element of A or B is zero, the operation can be skipped and a zero result can be output). With this design, when dealing with sparse matrices, a large number of invalid computations such as "multiplications involving zero" and "additions of zero" can be omitted; at the same time, since zero elements do not need to be stored, a lot of storage time can be saved, significantly shortening the overall processing cycle of sparse matrices.

[0069] The compressed storage logic of sparse vectors in the Metadata Register Set (MRF) and Vector Register File (VRF) is as follows: Figure 2 As shown, taking the original vector [0,0,9,0,1,0,3,0] as an example, the MRF is responsible for recording the non-zero distribution characteristics of the vector. The bitmap (8'b00101010) marks each position of the original vector as non-zero ("1" represents non-zero, "0" represents zero). The start bit (2) and end bit (6) define the start and end positions of the continuous distribution of non-zero elements in the original vector. The total number (3) counts the total number of non-zero elements. The VRF only compresses and stores the values ​​of non-zero elements (9, 1, 3), and keeps the original values ​​of subsequent positions to maintain the length of the vector structure. This design, through the combination of "MRF marking non-zero distribution + VRF compressing and storing non-zero values", not only saves the storage time of a large number of zero elements in the original vector, but also provides a basis for subsequent sparse data processing (such as skipping invalid calculations of zero elements and reducing data transmission bandwidth).

[0070] The workflow of a Sparse Coding Unit (SEU) is as follows: Figure 3 As shown: The original vector [0,5,0,0,0,7,0,0] first passes through zero-detection logic to identify non-zero elements (values ​​5 and 7, located in the 1st and 5th bits respectively). The zero-detection logic focuses on whether the highest bit is the sign bit. Then, it is processed by compression logic. On one hand, metadata is generated and written to the metadata register group (MRF) – 0x22 is a bitmap (marking the "non-zero / zero" state of each element), 1 and 5 record the start and end positions of non-zero elements, and 2 indicates the total number of non-zero elements. On the other hand, the values ​​5 and 7 of the non-zero elements are compressed and written to the vector register file (VRF), omitting zero elements to reduce storage overhead. The workflow of the Sparse Decoding Unit (SDU) is as follows: Figure 4 As shown: When data needs to be written back to memory from VRF, the metadata (bitmap, position, total number) stored in MRF and the non-zero values ​​5 and 7 stored in compressed VRF are input together into the data population logic. This logic restores 5 and 7 to their corresponding positions in the original vector (1st and 5th positions) based on the non-zero positions recorded in the metadata, and fills the remaining positions with zeros, finally restoring the complete original vector [0,5,0,0,0,7,0,0], ensuring that the memory receives the standard dense vector format, and realizing sparse data restoration that is transparent to the software.

[0071] This device implements a hardware mechanism for dynamic data compression and decompression within the vector processor, enabling efficient processing of sparse data (such as sparse matrices) and significantly reducing register file access bandwidth and power consumption, while maintaining complete transparency to upper-layer software applications.

[0072] This invention also provides a computer-readable medium storing computer instructions. When executed by a processor, the computer instructions cause the processor to perform the vector processor dynamic compression method for sparse computing described in the above embodiments. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0073] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of the present invention.

[0074] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0075] Furthermore, it should be clear that not only can the program code read by the computer be executed, but also the operating system or other components operating on the computer can be instructed based on the program code to perform some or all of the actual operations, thereby realizing the function of any of the embodiments described above.

[0076] Furthermore, it is understood that the program code read from the storage medium is written to the memory set in the expansion board inserted into the computer or to the memory set in the expansion unit connected to the computer. Then, based on the instructions of the program code, the CPU or other components installed on the expansion board or expansion unit execute some and all of the actual operations, thereby realizing the function of any of the embodiments described above.

[0077] The present invention has been shown and described in detail above with reference to the accompanying drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments. Based on the above embodiments, those skilled in the art will know that more embodiments of the present invention can be obtained by combining the code review methods in the different embodiments. These embodiments are also within the protection scope of the present invention.

Claims

1. A dynamic compression method for vector processors oriented towards sparse computing, characterized in that, The implementation of this method includes: Add a metadata register to each vector register in the vector register file to describe the distribution of valid non-zero elements in that vector register, forming a metadata register group; Add a sparse data encoder to the write path of the vector register file to compress the data and generate metadata; A sparse data decoder is added to the memory write path of the vector register file to restore the compressed data to the standard dense format.

2. The vector processor dynamic compression method for sparse computing according to claim 1, characterized in that, The metadata register group is associated with each vector register in the vector register file and stores the compressed format metadata of the corresponding vector data. The metadata is in bitmap format, where each bit indicates whether the element at the corresponding position in the original vector is zero.

3. The vector processor dynamic compression method for sparse computing according to claim 1, characterized in that, The sparse data encoder receives the raw vector data to be written to the vector register file. The encoder analyzes the input vector, identifies all non-zero elements and their positions, generates metadata based on the position information and stores it in the corresponding metadata register, and compresses the raw vector into a compact format containing only non-zero data, and then writes it to the physical storage unit of the vector register file.

4. The vector processor dynamic compression method for sparse computing according to claim 1, characterized in that, When data needs to be sent to main memory, the sparse data decoder mixes the compact format data stored in the vector register file with zero values ​​according to the information in the metadata register, and restores it into a standard dense vector format in real time, ensuring that the data format received by the memory subsystem is completely consistent with that of the uncompressed data.

5. The vector processor dynamic compression method for sparse computing according to claim 1, characterized in that, The method is implemented as follows: After the data read from memory enters the computation channel of the vector processor through the loading unit, the sparse coding unit located in the vector register file write path will analyze the original vector to be written. On the one hand, it will generate bitmap format metadata and store it in the metadata register group that is associated one-to-one with the vector registers of the vector register file. On the other hand, it will compress the original vector into a compact format containing only non-zero data and write it to the vector register file. When data needs to be written back to memory from the vector register file, the sparse decoding unit located on the memory write path will mix the compact format data and zero values ​​in the vector register file according to their original positions based on the metadata stored in the metadata register group, restore it to the standard dense vector format in real time, and then write it back to memory through the storage unit.

6. The vector processor dynamic compression method for sparse computing according to claim 5, characterized in that, When the vector processor performs vector computation, it synchronously retrieves the metadata and vector data of the corresponding vector register from the metadata register set and the vector register file. If the metadata indicates that the vectors involved in the computation contain zero elements, the computation type can be further identified.

7. The vector processor dynamic compression method for sparse computing according to claim 5, characterized in that, The compressed storage logic for sparse vectors in the metadata register set and vector register file is as follows: The metadata register group is responsible for recording the non-zero distribution characteristics of the vector, marking each position of the original vector as non-zero, defining the start and end positions of the continuous distribution of non-zero elements in the original vector, and counting the total number of non-zero elements. The vector register file only compresses and stores the values ​​of non-zero elements, and retains the original values ​​in subsequent positions to maintain the length of the vector structure.

8. A vector processor dynamic compression method for sparse computing according to claim 5, characterized in that, The workflow of a sparse coding unit is as follows: The original vector first passes through zero detection logic to identify non-zero elements. The zero detection logic needs to pay attention to whether the highest bit is the sign bit. Then, it is processed by compression logic. On the one hand, metadata is generated and written to the metadata register group. The metadata includes a bitmap, the start and end positions of non-zero elements, and the total number of non-zero elements. On the other hand, the values ​​of non-zero elements are compressed and written to the vector register file, omitting zero elements to reduce storage overhead. The workflow of the sparse decoding unit is as follows: When data needs to be written back to memory from the vector register file, the metadata stored in the metadata register group and the non-zero values ​​compressed and stored in the vector register file are input together into the data filling logic. This logic restores the non-zero values ​​to the corresponding positions in the original vector based on the non-zero positions recorded in the metadata, and fills the remaining positions with zeros, finally restoring the complete original vector.

9. A vector processor dynamic compression device for sparse computing, characterized in that, include: Metadata register group: Associated with each vector register in the vector register file, used to store compressed format metadata of the corresponding vector data; Sparse data encoder: Located on the write path of the vector register file, it receives the raw vector data to be written to the vector register file; the encoder analyzes the input vector, identifies all non-zero elements and their positions, generates metadata based on the position information and stores it in the corresponding metadata register, and compresses the raw vector into a compact format containing only non-zero data, and then writes it to the physical storage unit of the vector register file. Sparse data decoder: Located on the path of the vector register file to write to memory, when data needs to be sent to main memory, the decoder mixes the compact format data stored in the vector register file with zero values ​​according to the information in the metadata register, and restores it in real time into the standard dense vector format, ensuring that the data format received by the memory subsystem is completely consistent with that of the uncompressed data. The device is capable of implementing the method described in any one of claims 1 to 8.

10. A computer-readable medium, characterized in that, The computer-readable medium stores computer instructions that, when executed by a processor, implement the method described in any one of claims 1 to 8.

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