Method for operating security device comprising physically unclonable functional unit

Abstract

Disclosed is an operation method of a security device including first to Nth physical unclonable function (PUF) cells, the method including: applying a first voltage to a first word line connected to the first to Nth PUF cells; obtaining first information from the first PUF unit, and obtaining second information from the second PUF unit to the Nth PUF unit; determining a first bit of the first PUF unit from the obtained first information and the obtained second information; applying a first voltage to a first word line connected to the first to Nth PUF cells; obtaining third information from the second PUF unit, and obtaining fourth information from the first PUF unit, the third PUF unit to the Nth PUF unit; determining a second bit of the second PUF unit based on the obtained third information and fourth information; and generating a security key for responding to the authentication request based on the first bit and the second bit, where N is a positive integer.

Description

[0001] This application is a divisional application of the following application: Application No.: 202011174686.8; Application Date: October 28, 2020; Invention Title: "Safety Device Including Physically Unclonable Functional Units and PUF Unit Device Operation Method". Technical Field

[0002] The embodiments of the inventive concept disclosed herein relate to security devices, and more specifically, to methods of operating security devices including physically unclonable function (PUF) units. Background Technology

[0003] Technologies associated with security and encryption are crucial for communication and mobile devices. In cryptography, a key is a piece of information that determines the functional output of a cryptographic algorithm. When keys are generated using software on a system connected to a network, unauthorized users can obtain them by intruding into the system. Therefore, hardware-based security technologies are being developed.

[0004] Security devices based on Physically Unclonable Function (PUF) randomly generate unique keys based on the device's process, voltage, and temperature (PVT). However, errors may occur in the keys due to various environmental factors. This error reduces the reliability of the PUF device. Summary of the Invention

[0005] At least one exemplary embodiment of the present invention provides a security device including a physically unclonable function (PUF) unit with improved reliability and reduced circuit complexity, a method of operating the security device, and a method of operating the physically unclonable function unit device.

[0006] According to an exemplary embodiment, a security device includes: a Physically Unclonable Function (PUF) cell array including a plurality of first PUF cells connected to a first word line; a controller that selects a target PUF cell among the plurality of first PUF cells and outputs a control signal indicating the selected target PUF cell; a decoder that applies a first voltage to the first word line in response to the control signal; a bit line selection circuit connected to a plurality of first bit lines and outputting a first target current and a first sum current, the first target current passing through a bit line among the plurality of first bit lines connected to the target PUF cell, and the first sum current corresponding to the sum of currents passing through the remaining bit lines connected to other PUF cells among the plurality of first PUF cells; and a bit determiner that outputs a target bit of the target PUF cell based on the first target current and the first sum current, and the security device generates a security key based on the target bit for responding to an authentication request.

[0007] According to an exemplary embodiment, an operation method of a Physically Unclonable Function (PUF) Unit Device including a plurality of Physically Unclonable Function (PUF) Units includes: selecting a target PUF Unit among the plurality of PUF Units; applying a first voltage to a first word line connected to the target PUF Unit; generating a target value based on a target current corresponding to the target PUF Unit, and generating a center value based on a sum current corresponding to the sum of currents output from other PUF Units connected to the first word line; determining a target bit of the target PUF Unit based on the target value and the center value; and generating a security key based on the target bit for responding to an authentication request.

[0008] According to an exemplary embodiment, a method of operating a security device including first to Nth Physically Unclonable Function (PUF) units includes: applying a first voltage to a first word line connected to the first to Nth PUF units; obtaining first information from the first PUF unit and second information from the second to Nth PUF units; determining a first bit of the first PUF unit from the obtained first information and the obtained second information; applying the first voltage to the first word line connected to the first to Nth PUF units; obtaining third information from the second PUF unit and fourth information from the first PUF unit and the third to Nth PUF units; determining a second bit of the second PUF unit based on the obtained third information and fourth information; and generating a security key based on the first bit and the second bit for responding to an authentication request, wherein N is a positive integer. Attached Figure Description

[0009] The inventive concept will become apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a security device according to an exemplary embodiment of the present invention.

[0011] Figure 2 This is a diagram illustrating the method used to determine the target bit of a PUF cell.

[0012] Figure 3 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 1 Block diagram of the PUF unit device.

[0013] Figure 4 It is shown Figure 3 A diagram illustrating an exemplary structure of multiple PUF units.

[0014] Figure 5 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 3 A diagram illustrating the configuration of the PUF unit device.

[0015] Figure 6 It is shown Figure 3 and Figure 5 The flowchart shows the operation of the PUF unit device.

[0016] Figure 7 It is used to describe Figure 3 A diagram illustrating the operation of the PUF unit device.

[0017] Figure 8 This is for describing an exemplary embodiment of the concept according to the present invention. Figure 3 A diagram illustrating the method for determining the target bits of a PUF unit device.

[0018] Figure 9 This is a diagram illustrating an exemplary embodiment of a PUF cell array according to a concept of the present invention.

[0019] Figure 10A It is shown Figure 9 A diagram illustrating an exemplary PUF cell device in which a PUF cell array is applied.

[0020] Figures 10B to 10D This is for describing an exemplary embodiment of the concept according to the present invention. Figure 10A A diagram illustrating the operation of the PUF unit device.

[0021] Figure 11 This is a diagram used to describe ways to improve the reliability of PUF unit devices.

[0022] Figure 12A This is for describing an exemplary embodiment of the concept according to the present invention. Figure 1 The flowchart shows the operation of a stable or effective PUF unit in a PUF unit device.

[0023] Figure 12B It is used to describe Figure 1 A diagram illustrating the operation of a stable or effective PUF unit in a PUF unit device.

[0024] Figure 13A and Figure 13B It is used to describe according to Figure 12A The flowchart illustrates the operation.

[0025] Figure 14 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 1 Block diagram of the controller.

[0026] Figure 15 This is a diagram illustrating the operation of a PUF unit device according to an exemplary embodiment of the present invention.

[0027] Figure 16AThis is a block diagram used to describe the operation of a security device according to an exemplary embodiment of the present invention.

[0028] Figure 16B and Figure 16C This is a flowchart describing the operation of a security device according to an exemplary embodiment of the present invention.

[0029] Figure 17 This is a block diagram illustrating an exemplary embodiment of a security device applied to an electronic system according to a concept of the present invention.

[0030] Figure 18 This is a block diagram illustrating an exemplary embodiment of a security device applied to an electronic device according to a concept of the present invention. Detailed Implementation

[0031] The embodiments of the inventive concept will now be described in detail and clearly to the extent that those skilled in the art can implement the inventive concept.

[0032] The components described in the detailed description using terms such as "component," "unit," "module," and "layer," as well as the functional blocks shown in the accompanying drawings, can be implemented in software, hardware, or a combination thereof. For example, software can be machine code, firmware, embedded code, and application software. Hardware can include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

[0033] Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as understood by one of ordinary skill in the art to which the inventive concept pertains. Unless expressly defined in the specification, terms defined in common dictionaries shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an ideal or overly formal meaning.

[0034] To illustrate the inventive concept, several exemplary components or numerical values ​​are provided below, but the inventive concept is not limited thereto. For example, in the following figures, for the sake of simplicity, an example of eight PUF units connected to a word line is shown. However, the inventive concept is not limited thereto, as this example is only used to illustrate the inventive concept.

[0035] Figure 1 This is a block diagram illustrating a security device according to an exemplary embodiment of the present invention. Figure 2 This is a diagram illustrating the method used to determine the target bit of a PUF cell. Figure 2 The horizontal axis of the distribution indicates information obtained from the PUF cell (e.g., mismatch information or current quantity). (Refer to...) Figure 1 and Figure 2 The security device 10 includes an array-based Physically Unclonable Function (PUF) unit device 100 (e.g., a semiconductor device) and a controller 101 (e.g., a control circuit).

[0036] The array-based PUF unit device 100 may include multiple PUF units. These multiple PUF units may be arranged in an array. For ease of description, the array-based PUF unit device 100 will be referred to simply as "PUF unit device 100".

[0037] In one exemplary embodiment, each of the plurality of PUF units can be implemented using at least one of various types of PUFs, such as transistor-based threshold voltage PUF units, arbitrator-based PUF units (e.g., feedforward PUF units, XOR PUF units in which arbitrator PUF units are arranged in parallel, or lightweight PUF units), ring oscillator-based PUF units, memory-based PUF units (e.g., static random access memory (SRAM) PUF units, latch PUF units, flash memory PUF units, or memristor PUF units), and PUF units that can be reconfigured according to laser beam or thermal changes.

[0038] In the following description of the inventive concept, it is assumed that each of the plurality of PUF cells is a PUF cell based on the threshold voltage of a transistor. However, the inventive concept is not limited thereto. For example, each of the plurality of PUF cells can be implemented using various types of PUF cells.

[0039] PUF unit device 100 is configured to output target bit TB under the control of controller 101. Controller 101 controls PUF unit device 100. For example, controller 101 provides a control signal CTRL to PUF unit device 100. The control signal CTRL may include information or an address for selecting a target PUF unit among a plurality of PUF units included in PUF unit device 100. For example, the control signal may uniquely identify the target PUF unit.

[0040] The PUF unit device 100 can select a target PUF unit from a plurality of PUF units in response to the control signal CTRL received from the controller 101, and can output the target bit TB corresponding to the selected target PUF unit.

[0041] The controller 101 can receive target bits TB associated with all or some of the multiple PUF units included in the PUF unit device 100, and can generate and output a security key KEY based on the received target bits TB.

[0042] In one exemplary embodiment, multiple PUF cells can have different process, voltage, and temperature (PVT) variations. Even when the same bias (e.g., bias current, bias voltage, etc.) is provided to multiple PUF cells, each of the multiple PUF cells can output different information depending on the corresponding PVT variation. For example, even if multiple PUF cells are fabricated using the same semiconductor process or on the same wafer, the multiple PUF cells can have different PVT variations due to various factors (e.g., doping concentration, gate oxide layer thickness, and geometry).

[0043] That is, even if the first PUF unit and the second PUF unit are manufactured using the same semiconductor process or on the same wafer, the information output from the first PUF unit can be positive, while the information output from the second PUF unit can be negative. Alternatively, the magnitude or value of the information output from the first PUF unit and the magnitude or value of the information output from the second PUF unit can be different.

[0044] The target bit TB associated with each of the multiple PUF units can be determined based on the information of each PUF unit. For example, multiple pieces of information output from multiple PUF units included in the PUF unit device 100 can be formed Figure 2 The first distribution DB1 is shown. In an exemplary embodiment, the first distribution DB1 may be a Gaussian distribution or a normal distribution. The center value (e.g., peak value) of the first distribution DB1 may be used as a reference value REF0 for determining the polarity of each of the plurality of PUF cells. For example, a PUF cell with information less than the center value may be considered to have negative polarity, and a PUF cell with information greater than or equal to the center value may be considered to have positive polarity.

[0045] An exemplary PUF unit device determines the target bit of the target PUF unit by collecting analog information of the target PUF unit, converting the collected analog information into digital data via an analog-to-digital converter, and comparing the converted digital data with reference data (i.e., reference value REF0).

[0046] However, a PUF unit device 100 according to an exemplary embodiment of the present invention determines the target bit TB of a target PUF unit without using a separate analog-to-digital converter and separate reference data. For example, a PUF unit device 100 according to an exemplary embodiment of the present invention can determine the target bit TB by generating or calculating a center value based on other PUF units corresponding to the target PUF unit among a plurality of PUF units, and by comparing the target value corresponding to the target PUF unit with the center value. The structure and operation of a PUF unit device 100 according to an exemplary embodiment of the present invention will now be described with reference to the accompanying drawings.

[0047] Figure 3 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 1 A block diagram of a PUF cell device is provided. For the sake of simplicity, the example is shown as multiple PUF cell PCs arranged in an 8×8 matrix, but the inventive concept is not limited thereto. The PUF cell array 110 may further include additional PUF cells, thus increasing the number of word lines and bit lines. In an exemplary embodiment, the number of PUF cell PCs connected to a word line is at least “N”. In this case, “N” indicates the minimum number of PUF cells whose values ​​form a normal or Gaussian distribution. In an exemplary embodiment, “N” can be in the range of 4 to 256.

[0048] For ease of description, it is assumed that the information obtained from each of the plurality of PUF cells PC is a current generated based on the word line bias of each of the plurality of PUF cells PC. However, the inventive concept is not limited thereto. For example, the information obtained from the PUF cells can be varied or modified depending on the type of PUF cell.

[0049] Reference Figure 1 and Figure 3 The PUF unit device 100 includes a PUF unit array 110, a decoder 120 (e.g., decoder circuitry), a bit line selection circuit 130, a bit determiner 140 (e.g., circuitry), and a voltage regulator 150.

[0050] PUF cell array 110 includes multiple PUF cells PC. The multiple PUF cell PCs can be arranged in both row and column directions to form an array. The multiple PUF cell PCs can be connected to multiple word lines WL1 to WL8 and multiple bit lines BL1 to BL8. Each of the multiple PUF cell PCs can be configured to output current depending on the bias (e.g., bias current, bias voltage, etc.) of the corresponding word line among the multiple word lines WL1 to WL8. As described above, the current output from each of the multiple PUF cell PCs can have a value that varies depending on the physical characteristics or environmental conditions of each of the multiple PUF cell PCs.

[0051] Decoder 120 receives and decodes control signal CTRL from controller 101. For example, control signal CTRL may include address information corresponding to a target PUF cell among multiple PUF cells PC that will determine its target bit TB. Decoder 120 decodes the address information corresponding to the target PUF cell and controls multiple word lines WL1 to WL8 based on the decoding result. Decoder 120 provides bit line selection signal BS to bit line selection circuit 130 based on the decoding result. Bit line selection signal BS may be a signal used to select the bit line corresponding to the target PUF cell from multiple bit lines BL1 to BL8.

[0052] Bit line selection circuit 130 receives bit line selection signal BS from decoder 120 and controls multiple bit lines BL1 to BL8 based on the received bit line selection signal BS. For example, suppose the bit line selection signal BS corresponds to the third bit line BL3. In this case, bit line selection circuit 130 outputs the signal (e.g., current) received through the third bit line BL3 as the target current I_tg, and outputs the sum of the signals (e.g., current) received from the remaining bit lines BL1, BL2, and BL4 to BL8 as the sum current I_sum.

[0053] Bit determiner 140 receives a target current I_tg and a sum current I_sum. Bit determiner 140 determines the target bit TB of the target PUF cell based on the target current I_tg and the sum current I_sum. For example, bit determiner 140 may divide the sum current I_sum by a given value. In an exemplary embodiment, the given value is a value obtained by subtracting "1" from the number of PUF cell PCs connected to a word line (e.g., N-1). That is, as described above, in the case where the target current I_tg is provided from one of the PUF cell PCs connected to the third bit line BL3 and the sum current I_sum is provided from the PUF cell PCs connected to the first bit line BL1, the second bit line BL2, and the fourth bit line BL4 to the eighth bit line BL8 (i.e., 7 PUF cell PCs), the sum current I_sum is divided by "7". That is, bit determiner 140 calculates the average current per unit PUF cell based on the sum current I_sum.

[0054] Bit determiner 140 compares the calculated average current with the target current I_tg and determines the target bit TB of the target PUF cell based on the comparison result.

[0055] Voltage regulator 150 provides decoder 120 with voltages "V" to be applied to multiple word lines WL1 to WL8. In one exemplary embodiment, the bias voltages or active voltages (or bias currents) provided to the multiple word lines WL1 to WL8 respectively have the same level. Alternatively, the bias voltages or active voltages provided to the multiple word lines WL1 to WL8 may vary depending on the physical characteristics of the multiple PUF cell PCs. Alternatively, the bias voltages or active voltages provided to the multiple word lines WL1 to WL8 may have different levels, such that the information collected from the multiple PUF cell PCs forms a normal distribution or a Gaussian distribution.

[0056] Figure 4 It is shown Figure 3 A diagram illustrating an exemplary structure of multiple PUF units. (Refer to...) Figure 3 and Figure 4Any one of the multiple PUF cells PC, PCa, includes a first transistor TR1. The gate of the first transistor TR1 is connected to the word line WL, its drain is connected to the bit line BL, and its source is connected to receive a specific voltage level. The first transistor TR1 can control the magnitude of the current output to the bit line BL depending on the level of the word line WL. In this case, the magnitude of the current can vary depending on the physical characteristics of the first transistor TR1. That is, even if the multiple PUF cells PC are formed with the same structure as “PCa” and the same word line bias is applied to each of the multiple PUF cells PC, the current flowing through the bit line BL can vary depending on the physical characteristics of each PUF cell.

[0057] Alternatively, any one of the plurality of PUF cells PC includes a first transistor TR1 and a second transistor TR2. The first transistor TR1 and the second transistor TR2 are connected in series between a node providing a specific voltage level and the bit line BL, and can operate depending on the level of the word line WL. As described above, even if the plurality of PUF cells PC are formed with the same structure as “PCb” and the same word line bias is applied to each of the plurality of PUF cells PC, the current flowing through the bit line BL can vary depending on the physical characteristics of each PUF cell.

[0058] Reference Figure 4 The transistor-based PUF units PCa and PCb described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Multiple PUF units PC can be implemented in a variety of ways using the various structures described above.

[0059] Figure 5 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 3 A diagram illustrating the configuration of the PUF unit device. For the sake of simplicity, an example is shown where the PUF unit array 110 includes first PUF units PC1 to eighth PUF units PC8 connected to the first word line WL1, but the inventive concept is not limited thereto. For example, the PUF unit array 110 may further include additional PUF units connected to multiple word lines and multiple bit lines. For the sake of simplicity, some components (such as decoder 120 and voltage regulator 150) are omitted.

[0060] Reference Figure 3 and Figure 5The PUF unit device 100 includes a PUF unit array 110, a bit line selection circuit 130, and a bit determiner 140. The PUF unit array 110 may include first PUF units PC1 to eighth PUF units PC8. First PUF units PC1 to eighth PUF units PC8 are connected to a first word line WL1. First PUF units PC1 to eighth PUF units PC8 are respectively connected to first bit lines BL1 to eighth bit lines BL8. In response to a first voltage V1 provided to the first word line WL1, first PUF units PC1 to eighth PUF units PC8 output a first current I1 to an eighth current I8 through first bit lines BL1 to eighth bit lines BL8. The first voltage V1 may be provided by a voltage regulator 150.

[0061] Bit line selection circuit 130 includes first selectors SEL1 to eighth selectors SEL8. First selectors SEL1 to eighth selectors SEL8 are respectively connected to the first bit line BL1 to the eighth bit line BL8. First selectors SEL1 to eighth selectors SEL8 operate in response to bit line selection signals BS1 to BS8 and inverted phase line selection signals / BS1 to / BS8.

[0062] For example, the first selector SEL1 includes: a first transistor configured to provide a first current I1 output from the first bit line BL1 to a second converter 142 of the bit determiner 140 in response to a first bit line select signal BS1; and a second transistor configured to provide the first current I1 output from the first bit line BL1 to a first converter 141 of the bit determiner 140 in response to an inverse phase line select signal / BS1. Similar to the above description, the remaining selectors SEL2 to SEL8 can also operate in response to corresponding bit line select signals BS2 to BS8 and corresponding inverse phase line select signals / BS2 to / BS8; therefore, additional descriptions are omitted to avoid repetition.

[0063] In one exemplary embodiment, each of the bit line selection signals BS1 to BS8 is a signal for selecting the bit line corresponding to the target PUF unit, and each of the anti-phase line selection signals / BS1 to / BS8 is a signal for selecting the bit line corresponding to each of the remaining PUF units. For example, suppose the target PUF unit is the third PUF unit PC3. In this case, the third bit line selection signal BS3 is activated, and the first anti-phase line selection signal / BS1, the second anti-phase line selection signal / BS2, and the fourth anti-phase line selection signals / BS4 to the eighth anti-phase line selection signals / BS8 are activated. Thus, the third current I3 output through the third bit line BL3 is provided to the second converter 142, and the first current I1, the second current I2, and the fourth current I4 to the eighth current I8 output from the first bit line BL1, the second bit line BL2, and the fourth bit line BL4 to the eighth bit line BL8 are provided to the first converter 141 as the sum current I_sum.

[0064] Bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP (e.g., an operational amplifier or other comparator circuit). The first converter 141 can be connected to a transistor among the transistors included in the plurality of selectors SEL1 to SEL8 that operates in response to the inverted phase line select signals / BS1 to / BS8. The second converter 142 can be connected to a transistor among the transistors included in the plurality of selectors SEL1 to SEL8 that operates in response to the bit line select signals BS1 to BS8.

[0065] That is, as described above, the first converter 141 receives a sum current I_sum corresponding to the sum of the currents output from the remaining PUF units excluding the target PUF unit, and the second converter 142 receives a target current I_tg output from the target PUF unit. The first converter 141 converts the received sum current I_sum to output a center value CV, and the second converter 142 converts the target current I_tg to output a target value TV.

[0066] In one exemplary embodiment, the center value CV and the target value TV are voltage levels corresponding to the current I_sum and the target current I_tg, respectively. That is, the first converter 141 and the second converter 142 can be current-to-voltage converters. However, the inventive concept is not limited thereto. For example, each of the first converter 141 and the second converter 142 can be implemented using a current mirror configured to replicate the received current at a given ratio.

[0067] In an exemplary embodiment, the first converter 141 determines the center value CV by dividing the sum current I_sum by a given value. That is, the first converter 141 can provide the functionality of a divider DIV configured to divide the sum current I_sum by a given value. For example, the first converter 141 may include a divider or divider circuitry to divide the sum current I_sum by a given value. For example, as described above, when the target PUF cell is the third PUF cell PC3, the sum current I_sum may be the sum of currents (e.g., I1, I2, and I4 to I8) output from seven PUF cells (e.g., PC1, PC2, and PC4 to PC8). That is, the first converter 141 can calculate the current value corresponding to the center value CV by dividing the sum current I_sum by "7". In an exemplary embodiment, the center value CV indicates the center value of a normal or Gaussian distribution formed by information obtained from a plurality of PUF cells PC1 to PC8 (however, the number of PUF cells is greater than 8) connected to the first word line WL1. That is, when the number of multiple PUF units is a specific number or more (e.g., 4 to 256 or more), the remaining PUF units other than the target PUF unit can form a normal distribution or a Gaussian distribution. Therefore, the center value CV can be calculated by using the remaining PUF units.

[0068] In one exemplary embodiment, the division ratio of the first converter 141 is determined based on the number of PUF cells corresponding to the sum current I_sum. In one exemplary embodiment, the division ratio of the first converter 141 may be greater than or less than the number of PUF cells corresponding to the sum current I_sum by a given value.

[0069] In one exemplary embodiment, the second converter 142 determines the target value TV without performing a separate division operation on the target current I_tg. Alternatively, the second converter 142 determines the target value TV by dividing the target current I_tg based on a given ratio. In one exemplary embodiment, the second division ratio of the second converter 142 is based on the first division ratio of the first converter 141. In one exemplary embodiment, the second division ratio of the second converter 142 is less than the first division ratio of the first converter 141.

[0070] Comparator COMP receives the center value CV from the first converter 141 and the target value TV from the second converter 142. Comparator COMP compares the center value CV and the target value TV and outputs the target bit TB as the comparison result.

[0071] As described above, the PUF cell device 100 according to an exemplary embodiment of the present invention determines the target bit TB of the target PUF cell by using some of the calculated center values ​​CV in a plurality of PUF cells PCs without separate analog-to-digital converters and separate reference data, and by comparing the calculated center value CV with the target value TV of the target PUF cell. Therefore, the circuit complexity of the PUF device 100 is reduced, and a PUF cell device 100 with improved reliability can be implemented.

[0072] Figure 6 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 3 and Figure 5 The flowchart for the operation of the PUF unit device is shown below. (Refer to...) Figure 3 , Figure 5 and Figure 6 In operation S110, PUF unit device 100 selects a target PUF unit. For example, PUF unit device 100 can receive a control signal CTRL from controller 101 and can select a target PUF unit from multiple PUF unit PCs based on the received control signal CTRL.

[0073] In operation S120, the PUF cell device 100 provides a first voltage V1 to the word line corresponding to the selected target PUF cell. In an exemplary embodiment, the first voltage V1 may have a level for obtaining different magnitudes of current from a plurality of PUF cells connected to the first word line WL1.

[0074] In operation S130, PUF unit device 100 generates a center value CV. For example, as shown in reference... Figure 5 The PUF unit device 100 can obtain a sum current I_sum corresponding to the sum of currents of the remaining PUF units (excluding the target PUF unit) among the plurality of PUF units connected to the word line, and can generate a center value CV based on the obtained sum current I_sum.

[0075] In operation S140, the PUF unit device 100 compares the target value TV and the center value CV. For example, as shown in reference... Figure 5 The target value TV can be a value corresponding to the target current I_tg obtained from the target PUF cell, and the center value CV can be a value generated based on the sum of currents I_sum obtained from the other PUF cells. The PUF cell device 100 can determine whether the target value TV is greater than the center value CV.

[0076] When the target value TV is greater than the center value CV, in operation S151, the PUF unit device 100 sets the target bit TB to a first value (e.g., "bit 1"). When the target value TV is less than the center value CV, in operation S152, the PUF unit device 100 sets the target bit TB to a second value different from the first value (e.g., "bit 0"). In an exemplary embodiment, the target bit is set to the first value when the target value is greater than or equal to the center value CV. In an alternative embodiment, the target bit is set to the second value when the target value is less than or equal to the center value.

[0077] In operation S160, the PUF unit device 100 outputs the determined target bit TB.

[0078] Figure 7 It is used to describe Figure 3 A diagram illustrating the operation of the PUF unit device. Figure 7 The horizontal axis of the distribution indicates information obtained from the PUF cell (such as mismatch information or current quantity).

[0079] Reference Figure 3 and Figure 7 Information obtained from multiple PUF unit PCs included in the PUF unit device 100 can form a first distribution DB1. (Refer to...) Figure 2 The central value of the first distribution DB1, i.e. the reference value REF0, is described, so additional descriptions are omitted to avoid repetition.

[0080] In one exemplary embodiment, information obtained from a plurality of PUF unit PCs connected to a first word line WL1 forms a first sub-distribution sDB1, and information obtained from a plurality of PUF unit PCs connected to a second word line WL2 forms a second sub-distribution sDB2. Figure 7 As shown, each of the first sub-distribution sDB1 and the second sub-distribution sDB2 can have the shape of a normal distribution or a Gaussian distribution.

[0081] That is, when selecting a first target PUF unit from the plurality of PUF units PC connected to the first word line WL1, the average value of the information obtained from the remaining PUF units (excluding the target PUF unit) among the plurality of PUF units PC connected to the first word line WL1 has a first center value CVa. Thus, the first target PUF unit can be determined as either a positive PUF unit +PC with positive polarity or a negative PUF unit -PC with negative polarity by comparing the first target value based on the information obtained from the first target PUF unit with the first center value CVa.

[0082] Similarly, when selecting a second target PUF unit from among the multiple PUF units PC connected to the second word line WL2, the average value of the information obtained from the remaining PUF units (excluding the target PUF unit) among the multiple PUF units PC connected to the second word line WL2 has a second center value CVb. Thus, by comparing the second target value based on the information obtained from the second target PUF unit with the second center value CVb, it can be determined whether the second target PUF unit is a positive PUF unit +PC with positive polarity or a negative PUF unit -PC with negative polarity.

[0083] As described above, the plurality of PUF cells PCs included in the PUF cell device 100 of the present invention can form a normal distribution or a Gaussian distribution that varies depending on the word line offset. Therefore, the PUF cell device 100 of the present invention can calculate the center value by using PUF cells connected to the same word line as the target PUF cell, and can determine the target bit of the target PUF cell based on the calculated center value.

[0084] Figure 8 This is for describing an exemplary embodiment of the concept according to the present invention. Figure 3 A diagram illustrating the target bit determination method for the PUF unit device. (Refer to...) Figure 3 and Figure 8 The PUF unit device 100 includes a PUF unit array 110, a bit line selection circuit 130, and a bit determiner 140. The PUF unit array 110 includes multiple PUF units PC1 to PC8 connected to a first word line WL1 and multiple bit lines BL1 to BL8. The bit line selection circuit 130 includes multiple selectors SEL1 to SEL8. The bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP. The components have already been described above; therefore, additional descriptions are omitted to avoid repetition. Furthermore, it is assumed that a third PUF unit PC3 is the target PUF unit.

[0085] When the third PUF unit PC3 is selected as the target PUF unit, a first voltage V1 is provided to the first word line WL1 connected to the third PUF unit PC3. In response to the first voltage V1 of the first word line WL1, the multiple PUF units PC1 to PC8 respectively output multiple currents I1 to I8 through multiple bit lines BL1 to BL8.

[0086] Because the third PUF unit PC3 is the target PUF unit, the third bit line selection signal BS3, used to select the third bit line BL3 connected to the third PUF unit PC3, is activated, and the inverse phase line selection signals / BS1, / BS2, and / BS4 to / BS8, used for the remaining bit lines BL1, BL2, and BL4 to BL8, are activated. That is, in response to the third bit line selection signal BS3, the third selector SEL3 provides the third current I3 of the third bit line BL3 to the second converter 142 as the target current I_tg. In response to the first anti-phase line selection signal / BS1, the second anti-phase line selection signal / BS2, and the fourth to eighth anti-phase line selection signals / BS4 to / BS8, the first selector SEL1, the second selector SEL2, and the fourth to eighth selectors SEL4 provide the first current I1, the second current I2, and the fourth to eighth current I8 of the first bit line BL1, the second bit line BL2, the fourth bit line BL4, and the eighth bit line BL8 to the first converter 141 as the sum current I_sum.

[0087] The first converter 141 outputs a center value CV based on the sum of currents I_sum, and the second converter 142 outputs a target value TV based on the third current I3 (i.e., the target current). The comparator COMP compares the center value CV and the target value TV to generate the target bit TB, and outputs the target bit TB in the third PUF unit PC3.

[0088] Figure 9 This is a diagram illustrating a PUF cell array according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 9 The PUF cell array 110A includes multiple PUF cells PCs, and the multiple PUF cell PCs are connected to multiple word lines WL1 to WL6 and multiple bit lines BL11 to BL18 and BL21 to BL28. In an exemplary embodiment, the number of PUF cells, the number of word lines, or the number of bit lines in the PUF cell array 110A are not limited to... Figure 9 The configuration shown.

[0089] With reference Figure 2 The described PUF cell array 110 is different. Figure 9The PUF cell array 110A has multiple PUF cells PCs connected to bit lines BL11 to BL18 of the first group and bit lines BL21 to BL28 of the second group. For example, the PUF cell PCs connected to the first word line WL1, the third word line WL3, and the fifth word line WL5 are connected to the bit lines BL11 to BL18 of the first group, and the PUF cell PCs connected to the second word line WL2, the fourth word line WL4, and the sixth word line WL6 are connected to the bit lines BL21 to BL28 of the second group. That is, the PUF cell PCs connected to the first word line WL1, the third word line WL3, and the fifth word line WL5, as well as the PUF cell PCs connected to the second word line WL2, the fourth word line WL4, and the sixth word line WL6, are connected to bit lines of different groups and can operate independently of each other.

[0090] Figure 10A It is shown Figure 9 A diagram illustrating the application of a PUF cell array to its PUF cell device. Figures 10B to 10D It is used to describe Figure 10A A diagram illustrating the operation of the PUF unit device. For the sake of brevity, components identical to those described above are not depicted.

[0091] Reference Figures 10A to 10D The PUF unit device includes a PUF unit array 110A, a first bit line selection circuit 131, a second bit line selection circuit 132, and a bit determiner (e.g., a comparator COMP). The PUF unit array 110A includes multiple PUF units PC11 to PC18 and PC21 to PC28. The multiple PUF units PC11 to PC18 and PC21 to PC28 can be connected to a first word line WL1 and a second word line WL2. The PUF units PC11 to PC18 connected to the first word line WL1 are connected to the first group of bit lines BL11 to BL18, and the PUF units PC21 to PC28 connected to the second word line WL2 are connected to the second group of bit lines BL21 to BL28.

[0092] The first bit selection circuit 131 is connected to bit lines BL11 to BL18 of the first group. In an exemplary embodiment, the first bit selection circuit 131 includes a reference... Figure 5 and Figure 8 The selected circuit described herein includes a first bit line selection circuit 131, which is connected to bit lines BL11 to BL18 of a first group and operates in response to a corresponding bit line selection signal or a corresponding inverted phase line selection signal. A second bit line selection circuit 132 is connected to bit lines BL21 to BL28 of a second group. In an exemplary embodiment, the second bit line selection circuit 132 includes reference to... Figure 5 and Figure 8The selectors described herein are connected to the bit lines BL21 to BL28 of the second group, respectively, and operate in response to the corresponding bit line selection signal or the corresponding inverse phase line selection signal. For the sake of simplicity and ease of description, the detailed configuration and operation of the selectors have been described above, and therefore additional descriptions are omitted to avoid repetition.

[0093] The first converter 141 outputs a target value TV or a center value CV based on information (e.g., current) received from the second bit line selection circuit 132. The second converter 142 outputs a center value CV or a target value TV based on information (e.g., current) received from the first bit line selection circuit 131.

[0094] In one exemplary embodiment, the first bit selection circuit 131 provides the target current or sum current to the second converter 142, and the second bit selection circuit 132 provides the sum current or target current to the first converter 141.

[0095] For example, such as Figure 10B As shown, assume that PUF unit PC13 connected to the first word line WL1 is the target PUF unit. In this case, a first voltage V1 is applied to the first word line WL1 and the second word line WL2. In an exemplary embodiment, the voltage applied to the first word line WL1 and the second word line WL2 can be set differently depending on the physical characteristics of the plurality of PUF units PC11 to PC18 and PC21 to PC28 connected to the first word line WL1 and the second word line WL2. In response to the first voltage V1 applied to the first word line WL1 and the second word line WL2, each of the plurality of PUF units PC11 to PC18 and PC21 to PC28 outputs a corresponding current.

[0096] The first bit selection circuit 131, in response to the third bit selection signal BS3, provides the second converter 142 with a current I13 output from the PUF unit PC13, which is connected to the first word line WL1 and the third bit line BL13 of the first group. In this case, the current I13 is the target current I_tg. The second converter 142 outputs a target value TV based on the target current I_tg.

[0097] In response to the inverse phase line selection signals / BS1, / BS2, and / BS4 to / BS8, the second bit line selection circuit 132 provides the first converter 141 with a sum current I_sum2 corresponding to the sum of the currents provided through some bit lines BL21, BL22, and BL24 to BL28 of the second group. The first converter 141 outputs a center value CV based on the sum current I_sum2 provided from the second bit line selection circuit 132. The comparator COMP compares the center value CV with the target value TV to generate the target bit TB and outputs the target bit TB of the third PUF unit PC3 as the comparison result.

[0098] As described above, a PUF cell device according to an exemplary embodiment of the present invention calculates a center value CV based on current obtained from a number of PUF cells connected to a second word line different from the first word line corresponding to the target PUF cell. In this case, the "a few PUF cells" may refer to the PUF cells connected to the different word lines, excluding the bit line corresponding to the target PUF cell. That is, in Figure 10B In the embodiment, when the target PUF unit is connected to the third bit line BL13 of the first group, the PUF unit used to calculate the center value CV is PUF unit PC21, PC22 and PC24 to PC28 connected to the second word line WL2 and the first bit line BL21, the second bit line BL22 and the fourth bit line BL24 to the eighth bit line BL28 of the second group.

[0099] However, the inventive concept is not limited thereto. For example, such as Figure 10C As shown, when the target PUF unit (e.g., PC13) is connected to the first word line WL1, all PUF units PC21 to PC28 connected to the second word line WL2 can be used to calculate the center value CV. In this case, except that the second bit line selection circuit 132 receives the first anti-phase line selection signal / BS1 to the eighth anti-phase line selection signal / BS8 and all PUF units PC21 to PC28 connected to the second word line WL2 are used to calculate the center value CV, the target bit determination operation is similar to the operation described above, so additional description is omitted to avoid repetition.

[0100] However, the inventive concept is not limited thereto. For example, such as Figure 10DAs shown, when the target PUF unit (e.g., PC13) is connected to the first word line WL1, all remaining PUF units PC11 to PC18 and PC21 to PC28, excluding the target PUF unit PC13, among the plurality of PUF units PC11 to PC18 and PC21 to PC28 connected to the first word line WL1 to the second word line WL2, are used to calculate the center value CV. In this case, the second bit line selection circuit 132 provides a second sum current I_sum2 to the first converter 141, which corresponds to the sum of the currents from the PUF units PC21 to PC28 connected to the second word line WL2, and the first bit line selection circuit 131 provides a first sum current I_sum1 to the first converter 141, which corresponds to the sum of the currents from the remaining PUF units PC11, PC12 and PC14 to PC18, excluding the target PUF unit PC3, among the PUF units PC11 to PC18 connected to the first word line WL1. The first converter 141 outputs the center value CV based on both the first sum current I_sum1 and the second sum current I_sum2.

[0101] In one exemplary embodiment, the division ratio of the first converter 141 or the second converter 142 may vary depending on the number of PUF units to be used to calculate the center value CV.

[0102] The exemplary embodiments described above are provided to illustrate the inventive concept and are not intended to limit the inventive concept. For example, in a PUF cell device, the number of PUF cells, the number of word lines, or the number of bit lines can be varied or modified. Furthermore, the PUF cells used for calculating the center value CV can be constructed in various ways depending on the structure of the PUF cell array. For example, refer to… Figures 10A to 10D An embodiment for calculating the center value is described using PUF cells on word lines adjacent to the word line of the target PUF cell; however, PUF cells on word lines physically separated from the word line of the target PUF cell can also be used to calculate the center value. Alternatively, multiple PUF cells connected to multiple word lines can be used to calculate the center value.

[0103] Figure 11 This is a diagram illustrating methods for improving the reliability of PUF unit devices. (Refer to...) Figure 11As described above, the information obtained from multiple PUF cells in a PUF cell device can form a normal or Gaussian distribution, similar to the first distribution DB1, and the target bit TB or the polarity of the PUF cell can be determined based on the reference value REF0. The information output from the PUF cell can vary depending on various conditions (e.g., operating temperature and operating voltage). That is, in a PUF cell that outputs information close to the reference value REF0, the output information can vary depending on various factors; therefore, the polarity of the PUF cell or the determined bit can change. This leads to a decrease in the reliability of the PUF cell device.

[0104] In this way, the exemplary PUF unit device can collect information from each of the multiple PUF units included in the PUF unit device through individual test operations, convert the collected information into digital data through an analog-to-digital converter, and discard PUF units with information between the reference value REF0 and "-a" or "+a". For example, PUF units with information in the range of REF0-a to REF0+a can be discarded (ignored). Discarding a specific PUF unit means that the specific PUF unit is not selected as the target PUF unit in the next PUF unit operation. That is, the overall reliability of the PUF unit device can be improved by discarding (or ignoring) PUF units PC with relatively low reliability.

[0105] However, as mentioned above, in order to discard the relatively unreliable PUF unit PC, it is necessary to perform operations such as converting the information of all PUF units into digital data through an analog-to-digital converter and setting a separate reference value REF0.

[0106] According to an exemplary embodiment of the present invention, a PUF cell device 100 identifies and discards unstable PUF cells by adjusting the division ratio for the center value CV and determining the target bit based on the adjusted division ratio.

[0107] Figure 12A This is for describing an exemplary embodiment of the concept according to the present invention. Figure 1 The flowchart shows the operation of a stable or effective PUF unit in a PUF unit device. Figure 12B It is used to describe Figure 1 A diagram illustrating the operation of a stable or effective PUF unit in a PUF unit device. (Refer to...) Figure 1 , Figure 2 , Figure 12A and Figure 12B In operation S211, the PUF unit device 100 selects a target PUF unit. For example, the PUF unit device may select a target PUF unit based on a received control signal.

[0108] In operation S212, the PUF unit device 100 generates a target value TV and a first center value CV1 based on a first division ratio "Na". In an exemplary embodiment, "N" is a positive integer and "a" is a real number. For example, the PUF unit device 100 may be based on a reference... Figures 1 to 10D The described operation method generates a target value TV and a first center value CV1 corresponding to the target PUF unit. In this case, the division ratio for the first center value CV1 can be less than a given division ratio. For example, in the case of calculating the center value using "N" PUF units, in the above embodiment, the 0th center value CV0 is calculated based on the division ratio "N". However, in operation S212, in the case of calculating the center value using "N" PUF units, the center value is calculated based on the division ratio "Na" (i.e., less than the division ratio in the above embodiment). In this case, as... Figure 12B As shown, the first central value CV1 calculated based on the division ratio "Na" is greater than the 0th central value CV0 calculated based on the division ratio "N".

[0109] In operation S213, the PUF unit device 100 compares the target value TV with the first center value CV1. When the target value TV is not greater than the first center value CV1, the PUF unit device 100 proceeds to operation S215. When the target value TV is greater than the first center value CV1, in operation S214, the PUF unit device 100 determines the selected target PUF unit as a valid PUF unit. For example, as... Figure 12B As shown, a target value TV greater than the first center value CV1 can mean that the target value TV is separated from the 0th center value CV0 by a certain distance (e.g., logical distance). That is, even if the information output from the target PUF unit varies depending on various environmental conditions, the probability that the target value TV of the target PUF unit is lower than the 0th center value CV0 can be very low. In other words, a target PUF unit with a target value TV greater than the first center value CV1 is a stable (or effective) PUF unit.

[0110] When it is determined in operation S214 or in operation S213 that the target value TV is not greater than the first center value CV1, in operation S215, the PUF unit device 100 determines whether the above operations have been completely performed on all PUF units. If it is determined that the above operations have not been completely performed on all PUF units, in operation S216, the PUF unit device 100 selects the next target PUF unit. Thereafter, the PUF unit device 100 may repeat operations S212 to S216.

[0111] As described above, by performing operations S211 to S216, the PUF unit device 100 of the present invention calculates a first center value CV1 (i.e., greater than the 0th center value) by using a division ratio smaller than a given division ratio, and determines a PUF unit having a target value greater than the first center value CV1 as a valid PUF unit.

[0112] In operation S221, PUF unit device 100 selects a target PUF unit. In operation S222, PUF unit device 100 generates a target value TV and generates a second center value CV2 based on a second division ratio "N+a". For example, PUF unit device 100 based on a reference... Figures 1 to 10D The described operation method generates a target value TV and a second center value CV2 corresponding to the target PUF unit. In this case, as described above, when calculating the center value using "N" PUF units, the 0th center value CV0 is calculated based on a division ratio "N". In contrast, in operation S222, the second center value CV2 is calculated based on a division ratio "N+a" which is greater than the division ratio "N". In this case, the second center value CV2 is less than... Figure 12B The zeroth center value CV0 is shown.

[0113] In operation S223, PUF unit device 100 determines whether the target value TV is less than the second center value CV2.

[0114] When the target value TV is not less than the second center value CV2, the PUF unit device 100 proceeds to operation S225. When the target value TV is less than the second center value CV2, in operation S224, the PUF unit device 100 determines the selected target PUF unit as a valid PUF unit. For example, as... Figure 12B As shown, a target value TV less than the second center value CV2 means that the target value TV is separated from the 0th center value CV0 by a certain distance (e.g., logical distance). That is, even if the information output from the target PUF unit varies depending on various environmental conditions, the probability that the target value TV of the target PUF unit is higher than the 0th center value CV0 can be very low. In other words, a target PUF unit with a target value TV less than the second center value CV2 can be a stable (e.g., effective) PUF unit.

[0115] Subsequently, the PUF unit device 100 can perform operations S225 and S226. Operations S225 and S226 are similar to operations S215 and S216 described above, therefore, additional descriptions are omitted to avoid repetition.

[0116] As described above, by performing operations S221 to S226, the PUF unit device 100 of the present invention calculates the second center value CV2 (i.e. less than the 0th center value) by using a division ratio larger than a given division ratio, and can determine the PUF unit with a target value less than the second center value CV2 as a valid PUF unit.

[0117] Subsequently, in operation S230, the PUF unit device 100 stores information about valid PUF units. For example, the PUF unit device 100 may store address information about valid PUF units. In this case, because the stored information is only the address information of the valid PUF unit, and no other information about the polarity or target value of the valid PUF unit (i.e., information that can determine the bit value) is stored separately, it is impossible to recover the target value or security key even if the address information is leaked or illegally accessed.

[0118] For the sake of simplicity and ease of description, operation S230 is shown separately, but the inventive concept is not limited thereto. For example, operation S230 can be performed separately in operation S214 or operation S224. Alternatively, operation S230 can be performed by controller 101. For example, depending on the result of operation S213, a first value or a second value can be output as the target bit TB of the target PUF unit. Controller 101 can determine the target PUF unit as a valid PUF unit when it receives a first value indicating that the target value TV is greater than the first center value CV1, and does not perform a separate determination of the target PUF unit when it receives a second value indicating that the target value TV is less than the first center value CV1. In an exemplary embodiment, information about the target PUF unit (e.g., address information) used to determine the target PUF unit as a valid PUF unit is stored in a separate memory of controller 101.

[0119] In one exemplary embodiment, such as Figure 12B As shown, PUF units that are not determined to be valid PUF units among multiple PUF units can be managed as invalid PUF units. In an exemplary embodiment, an invalid PUF unit may refer to a PUF unit that is not selected as a target PUF unit in the target bit determination operation of the PUF unit device 100.

[0120] Figure 13A and 13B It is used to describe according to Figure 12A The flowchart illustrates the operation. (Refer to...) Figure 1 , Figure 2 , Figure 13A and Figure 13BThe PUF unit device 100 includes a PUF unit array 110, a bit line selector 130, and a bit determiner 140. The PUF unit array 110 includes multiple PUF units PC1 to PC8 connected to a first word line WL1 and multiple bit lines BL1 to BL8. The bit line selector 130 includes multiple selectors SEL1 to SEL8. The bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP. Each component has been described above, therefore additional descriptions are omitted to avoid repetition.

[0121] First, refer to Figure 13A describe Figure 12A Operations S211 to S214. For example... Figure 13A As shown, the third PUF element PC3 is selected as the target PUF element. In this case, as in the reference... Figure 8 In the above description, a first voltage V1 is provided to the first word line WL1, and the first selector SEL1, the second selector SEL2, and the fourth selector SEL4 through the eighth selector SEL8 provide the first converter 141 with a sum current I_sum corresponding to the sum of the currents I1, I2, and I4 through I8 of the corresponding bit lines BL1, BL2, and BL4 through BL8 in response to the corresponding inverse phase line selection signals / BS1, / BS2, and / BS4 through / BS8. In response to the third bit line selection signal BS3, the third selector SEL3 provides the third current I3 of the third bit line BL3 to the second converter 142 as the target current.

[0122] For reference Figure 12A As described in operation S212, the first converter 141 outputs a first center value CV1 based on a first division ratio (e.g., "Na"). The second converter 142 outputs a target value TV based on a third current I3. The comparator COMP compares the first center value CV1 and the target value TV to generate a first classification result CR1 and outputs the first classification result CR1.

[0123] When the value of the first classification result CRL is the first value (i.e., when the target value TV is greater than the first center value CV1), the third PUF unit PC3 is determined to be a valid PUF unit. In this case, Figure 12B In the distribution, the third PUF unit PC3 can be understood as having a value greater than the first center value CV1.

[0124] When the value of the first classification result CRl is the second value (i.e., when the target value TV is not greater than the first center value CVl), the third PUF unit PC3 can be determined as a valid PUF unit or an invalid / unstable PUF unit. For example, as from Figure 12BBased on the distribution, when the target value TV is not greater than the first center value CV1, the third PUF cell PC3 can be an invalid / unstable PUF cell or an effective / stable PUF cell. In this case, it is not determined whether the third PUF cell PC3 is an effective PUF cell.

[0125] References can be performed on each of the multiple PUF units PC1 to PC8. Figure 13A The described operation determines the effective PUF cell among multiple PUF cells PC1 to PC8 that has a target value greater than the first center value CV1.

[0126] Next, refer to Figure 13B describe Figure 12A Operations S221 to S224. For example... Figure 13B As shown, the fourth PUF unit PC4 can be selected as the target PUF unit. In this case, each of the multiple selectors SEL1 to SEL8 can operate in response to the corresponding bit line select signal or the corresponding inverse phase line select signal. The operation of the multiple selectors SEL1 to SEL8 is similar to that described above, so additional descriptions will be omitted to avoid repetition.

[0127] Through the operation of multiple selectors SEL1 to SEL8, a sum current I_sum corresponding to the sum of the currents I1 to I8, excluding the fourth current I4, is provided to the first converter 141, and the fourth current I4 is provided to the second converter 142. The second converter 142 outputs a target value TV based on the fourth current I4.

[0128] Regarding Figure 13A Unlike the above description, the first converter 141 outputs a second center value CV2 based on a second division ratio (e.g., "N+a"). The comparator COMP compares the second center value CV2 with the target value TV to generate a second classification result CR2 and outputs the second classification result CR2.

[0129] When the value of the second classification result CR2 is the second value (i.e., when the target value TV is less than the second center value CV2), the fourth PUF unit PC4 is determined to be a valid PUF unit. In this case, Figure 12B In the distribution, the fourth PUF unit PC4 can be understood as having a value less than the second center value CV2.

[0130] In one exemplary embodiment, reference can be performed on each of the plurality of PUF units PC1 to PC8. Figure 13B The described operation determines the effective PUF cell among multiple PUF cells PC1 to PC8 that has a target value less than the second center value CV2.

[0131] In one exemplary embodiment, the reference is first executed Figure 13A In the case of the described operation, it may depend on the reference. Figure 13A The described operation results in selective execution of the reference. Figure 13B The described operation. For example, it can be applied only to the reference. Figure 13A PUF units that are not determined to be valid PUF units in the described operation are executed by reference. Figure 13B The described operation. Alternatively, the reference is executed first. Figure 13B In the case of the described operation, it is possible to refer only to Figure 13B PUF units that are not determined to be valid PUF units in the described operation are executed by reference. Figure 13A The described operation.

[0132] Although the operations for determining a valid PUF cell with a target value greater than the first center value CV1 and the operations for determining a valid PUF cell with a target value less than the second center value CV2 are shown and described separately, the inventive concept is not limited thereto. For example, the first converter 141 can simultaneously calculate the first center value CV1 based on a first division ratio and the second center value CV2 based on a second division ratio through a conversion operation, and the comparator COMP can simultaneously compare the first center value CV1 and the second center value CV2 with the target value TV. In this case, whether the target PUF cell is a valid PUF cell can be determined through a sensing operation.

[0133] In one exemplary embodiment, whether a target PUF unit is a valid PUF unit can be determined by the controller 101. For example, the controller 101 can perform a reference operation on each of the plurality of PUF units in the PUF unit device 100. Figure 13A The described operation allows the controller 101 to receive a first comparison result (or a first target bit) for each of a plurality of PUF units. Subsequently, the controller 101 can perform a reference comparison on each of the plurality of PUF units of the PUF unit device 100. Figure 13B The described operation allows the controller 101 to receive a second comparison result (or a second target bit) for each of a plurality of PUF units. The controller 101 can determine the valid PUF unit by combining the first comparison result (or the first target bit) and the second comparison result (or the second target bit), and can store the address information of the determined valid PUF unit.

[0134] Figure 14 This illustrates an exemplary embodiment based on the concept of the present invention. Figure 1 The block diagram of the controller. (Refer to...) Figure 1 and Figure 14The controller 101 includes a target PUF unit selection circuit 101a, a memory 101b, a security key generator 101c (e.g., circuitry), and a control circuit 101d.

[0135] The target PUF unit selection circuit 101a selects a target PUF unit from among a plurality of PUF units included in the PUF unit device 100. The target PUF unit selection circuit 101a can output a control signal CTRL based on the selected target PUF unit. In an exemplary embodiment, the target PUF unit selection circuit 101a is configured to select a reference. Figures 12A to 13B The target PUF cell in the described effective PUF cell. For example, memory 101b may include information about the target PUF cell via a reference. Figures 12A to 13B The described operation generates information about valid PUF cells (e.g., address information). The target PUF cell selection circuit 101a can select a target PUF cell among valid PUF cells based on information stored in the memory 101b.

[0136] Security key generator 101c receives target bits TB from PUF unit device 100. In an exemplary embodiment, security key generator 101c generates a security key KEY by combining multiple target bits TB received from PUF unit device 100. The generated security key KEY can be provided to an external electronic device or integrated circuit. Control circuitry 101d can be configured to control the overall operation of controller 101. The security key KEY can be used to authenticate PUF unit device 100.

[0137] Figure 15 This is a diagram illustrating the operation of a PUF unit device according to an exemplary embodiment of the present invention. For ease of description, reference will be made to... Figure 3 PUF unit device 100 and Figure 14 The controller 101 is used to describe the controller based on Figure 15 The operation. Furthermore, assuming by reference... Figures 12A to 13B The described operation determines the third PUF cell PC3, the fifth PUF cell PC5, and the eighth PUF cell PC8 out of the multiple PUF cells PC1 to PC8 as valid PUF cells. That is, Figure 14 The controller 101 may include information about the active PUF units PC3, PC5 and PC8.

[0138] Reference Figure 1 , Figure 14 and Figure 15The PUF unit device 100 includes a PUF unit array 110, a bit line selection circuit 130, and a bit determiner 140. The PUF unit array 110 includes multiple PUF units PC1 to PC8 connected to a first word line WL1 and multiple bit lines BL1 to BL8. The bit line selection circuit 130 includes multiple selectors SEL1 to SEL8. The bit determiner 140 includes a first converter 141, a second converter 142, and a comparator COMP. These components have been described above, therefore additional descriptions are omitted to avoid repetition.

[0139] Unlike the embodiments described above, in Figure 15 In this embodiment, the center value CV is calculated using some of a plurality of PUF cells connected to the word line of the target PUF cell. For example, if the target PUF cell is the third PUF cell PC3, PUF cells that are not valid PUF cells (i.e., invalid / unstable PUF cells) among the plurality of PUF cells PC1 to PC8 connected to the first word line WL1 are used as PUF cells to calculate the center value CV. See reference Figure 12B The invalid PUF cell is the PUF cell adjacent to the 0th center value CV0. That is, by using invalid PUF cells to calculate the center value CV, a value closer to the 0th center value CV0 can be obtained. Furthermore, by reducing the number of PUF cells used to calculate the center value CV, the total power consumption of the PUF cell device 100 can be reduced. For example, in... Figure 15 In the diagram, PUF cells PC1, PC2, PC4, PC6, and PC7 are invalid PUF cells used to generate current I_sum.

[0140] Figure 16A This is a block diagram illustrating the operation of a security device according to an exemplary embodiment of the present invention. Figure 16B and Figure 16C This is a flowchart describing the operation of a security device according to an exemplary embodiment of the present invention. (Refer to...) Figure 16A and Figure 16B The security device 200 includes a PUF cell array 210, an analog-to-digital converter 220, and a memory 230. In an exemplary embodiment, the PUF cell array 210 is referenced to... Figures 1 to 15 Describe a PUF unit device or PUF unit array.

[0141] Reference Figure 16B describe Figure 16A The operation of safety equipment 200. In Figure 16B In operation S310, the security device 200 obtains the sensed value of each of the plurality of PUF cells included in the PUF cell array 210. The sensed value may be analog information obtained from each of the plurality of PUF cells.

[0142] In operation S320, the safety device 200 converts the sensed value SV into a digital value DV and stores the converted digital value DV in the memory 230.

[0143] In operation S330, the security device 200 determines the valid PUF unit based on the digital value DV stored in the memory 230. For example, as shown in reference... Figure 11 The security device 200 can determine the PUF cell corresponding to a digital value in the digital value DV that is larger or smaller than the reference value REF0 by a given amount as a valid PUF cell. In an exemplary embodiment, information about valid PUF cells can be stored in the memory 230.

[0144] In operation S340, the security device 200 performs a bit determination operation on each valid PUF cell by using the center value of the invalid PUF cell. For example, the security device 200 may perform a reference operation based on information about the invalid PUF cell. Figure 15 The described operation.

[0145] In one exemplary embodiment, the security device 200 performs reference using an analog-to-digital converter 220. Figures 1 to 5 The described target bit determination operation. For example, refer to... Figure 16A and Figure 16C In operation S410, the security device 200 obtains a sensed value from each PUF unit. In an exemplary embodiment, the security device 200 obtains sensed values ​​for all PUF units. Alternatively, the security device 200 can obtain sensed values ​​from a target PUF unit and PUF units associated with the target PUF unit (e.g., as referenced). Figures 1 to 15 The PUF unit used to calculate the center value obtains the sensed value.

[0146] In operation S420, the safety device 200 converts the acquired sensed values ​​into digital values.

[0147] In operation S430, the security device 200 can calculate the center value CV. For example, as described above, the security device 200 calculates the center value based on the digital values ​​corresponding to other PUF cells associated with the target PUF cell. That is, unlike the above embodiments, the security device 200 uses the analog-to-digital converter 220 to obtain the digital values ​​of other PUF cells associated with the target PUF cell and calculates the center value based on the obtained digital values.

[0148] Subsequently, the security device 200 performs operations S440 to S460. In an exemplary embodiment, apart from performing the operations of calculating the center value CV and determining the target bit after analog-to-digital conversion using the analog-to-digital converter 220, the basic operating principle can be similar to... Figure 6 The above embodiments. For example, operation S440 is executed after operation S430 and can be performed by... Figure 6 Operation S140 is implemented, and operation S451 is executed when operation S440 determines that the target value is greater than the center value CV, and can be performed by... Figure 6 Operation S151 is implemented, operation S452 is executed when operation S440 determines that the target value is not greater than the center value CV and can be implemented by operation S152, operation S460 can be executed after this and can be implemented by operation S160.

[0149] As described above, the security device 200 receives sensed values ​​SV from a plurality of PUF cells from the PUF cell array 210. The security device 200 can convert the sensed values ​​SV of the plurality of PUF cells into digital values ​​DV using an analog-to-digital converter 220. The digital values ​​DV can be stored in memory 230 or a separate storage circuit. The security device 200 can calculate a center value CV based on at least two or more corresponding digital values ​​in the digital values ​​DV that correspond to at least two of the remaining PUF cells other than the target PUF cell. In an exemplary embodiment, whenever the target bit is determined, the security device 200 can perform the following operations on the associated other PUF cells: obtaining sensed values ​​and converting the sensed values ​​into digital values. Alternatively, the digital values ​​of each of the plurality of PUF cells can be stored in memory 230, and the security device 200 can calculate the center value using the digital values ​​stored in memory 230.

[0150] Figure 17 This is a block diagram illustrating an electronic system in which a security device according to an embodiment of the present invention is applied. (Refer to...) Figure 17 The electronic system 1000 includes a host 1100 (e.g., a host device) and a security device 1200. The electronic system 1000 may be an electronic device such as a portable communication terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smartphone, a digital camera, or a wearable device.

[0151] Host 1100 can be configured to control security device 1200. Security device 1200 includes PUF unit array 1210 and can be configured to operate under the control of host 1100. In an exemplary embodiment, security device 1200 is a smart card such as an integrated circuit (IC) card or chip, or it may be a separate hardware component provided to generate security keys.

[0152] For example, host 1100 may receive a device identifier (ID) from security device 1200. Host 1100 may send a challenge to security device 1200 based on the received device identifier (ID). Security device 1200 may send a response to host 1100 in response to the challenge from host 1100. In an exemplary embodiment, the response includes references to... Figures 1 to 1 6 describes the security key KEY. That is, it depends on the reference... Figures 1 to 1 According to the operating method described in 6, the security device 1200 can obtain data based on a challenge from the host 1100 from multiple PUF units included in the PUF unit array 1210, generate a response (i.e., a security key) based on the obtained data, and send the response to the host 1100. The host 1100 can perform authentication operations on the security device 1200 or any other device based on the received response (e.g., based on the security key).

[0153] Figure 18 This is a block diagram illustrating an electronic device in which a security device according to an exemplary embodiment of the inventive concept is applied. (Refer to...) Figure 18 The electronic device 3000 includes a main processor 3100, a touch panel 3200, a touch driver integrated circuit 3202, a display panel 3300, a display driver integrated circuit 3302, a system memory 3400, a storage device 3500, an image processor 3800, a communication block 3700, an audio processor 3600, and a security chip 3900. In an exemplary embodiment, the electronic device 3000 may be one of various electronic devices such as portable communication terminals, personal digital assistants (PDAs), portable media players (PMPs), digital cameras, smartphones, tablet computers, laptop computers, and wearable devices.

[0154] The main processor 3100 can control the overall operation of the electronic device 3000. The main processor 3100 can control / manage the operation of the components of the electronic device 3000. The main processor 3100 can handle various operations for the purpose of operating the electronic device 3000.

[0155] Touch panel 3200 can be configured to sense touch input from a user under the control of touch driver integrated circuit 3202. Display panel 3300 can be configured to display image information under the control of display driver integrated circuit 3302.

[0156] System memory 3400 may store data for the operation of electronic device 3000. For example, system memory 3400 may include volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM) or synchronous DRAM (SDRAM) and / or non-volatile memory such as phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM) or ferroelectric RAM (FRAM).

[0157] Storage device 3500 can store data regardless of whether it is powered on. For example, storage device 3500 may include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, storage device 3500 may include embedded memory and / or removable memory of electronic device 3000.

[0158] The audio processor 3600 can process audio signals using the audio signal processor 3610. The audio processor 3600 can receive audio input via the microphone 3620 or provide audio output via the speaker 3630.

[0159] Communication block 3700 can exchange signals with external devices / systems via antenna 3710. The transceiver 3720 and modulator / demodulator (MODEM) 3730 of communication block 3700 can process signals exchanged with external devices / systems according to at least one of the following wireless communication protocols: Long Term Evolution (LTE), Global Microwave Access Interoperability (WiMax), Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wi-Fi, and Radio Frequency Identification (RFID).

[0160] The image processor 3800 can receive light through the lens 3810. The image device 3820 and image signal processor 3830 included in the image processor 3800 can generate image information about an external object based on the received light.

[0161] The security chip 3900 can be implemented to manage security operations or authentication operations associated with the electronic device 3000. In one exemplary embodiment, the security chip 3900 includes references to... Figures 1 to 1 6 describes the PUF unit device or safety device.

[0162] In one exemplary embodiment, Figure 18 A portion of the components can be implemented as a system-on-a-chip and can be provided as an application processor (AP) of the electronic device 3000.

[0163] According to at least one embodiment of the present invention, a center value is calculated using other PUF cells associated with the target PUF cell without separate reference data, and the target bit of the target PUF cell is determined based on the calculated center value. Therefore, a separate analog-to-digital converter or reference data is not required. This means that the circuit complexity of the security device is reduced. Furthermore, because an optimized center value is determined for each PUF cell, the reliability of the security device can be improved.

[0164] Therefore, a security device including a physically unclonable function (PUF) unit with improved reliability and reduced cost, a method of operating the security device, and a method of operating the physically unclonable function unit device are provided.

[0165] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept.

Claims

1. A method of operating a security device including a first Physically Unclonable Function (PUF) to an Nth PUF unit, the method comprising: Apply a first voltage to the first word line connected to the first PUF cell through the Nth PUF cell; First information is obtained from the first PUF unit, and second information is obtained from the second PUF unit to the Nth PUF unit; The first bit of the first PUF unit is determined from the first information and the second information obtained; Apply a first voltage to the first word line connected to the first PUF cell through the Nth PUF cell; The third information is obtained from the second PUF unit, and the fourth information is obtained from the first PUF unit, the third PUF unit, and the Nth PUF unit; The second bit of the second PUF unit is determined based on the obtained third and fourth information; and A security key is generated based on the first and second bits to respond to authentication requests. Where N is a positive integer.

2. The method according to claim 1, wherein, The first PUF unit to the Nth PUF unit are respectively connected to the first bit line to the Nth bit line, and Among them, the first PUF unit to the Nth PUF unit respond to the first voltage by outputting the first current to the Nth current through the first bit line to the Nth bit line respectively.

3. The method according to claim 2, wherein, The first information corresponds to the first current, and the second information corresponds to the value obtained by dividing the first sum current, which corresponds to the sum of the second to the Nth currents, by a given division ratio. The third information corresponds to the second current, and the fourth information corresponds to the value obtained by dividing the second current, which corresponds to the sum of the first current and the third to the Nth currents, by a given division ratio.

4. The method according to claim 3, wherein, The given division ratio corresponds to the value (N-1).

5. The method according to claim 2, wherein, The first piece of information is the first digital value corresponding to the first current. The second information consists of the first center value of the second to Nth digital values ​​corresponding to the second to Nth currents, respectively. The third piece of information is the second digital value corresponding to the second current, and The fourth information consists of the first digital value and the second center value corresponding to the first current and the third to Nth currents, respectively.

6. The method according to claim 1, wherein, Determining the first bit includes: Determine whether the first piece of information is greater than the second piece of information; and When the first piece of information is greater than the second piece of information, the first bit is set to the first value; when the first piece of information is not greater than the second piece of information, the first bit is set to the second value. The determination of the second bit includes: Determine whether the third piece of information is greater than the fourth piece of information; and When the third information is greater than the fourth information, the second bit is set to the first value, and when the third information is not greater than the fourth information, the second bit is set to the second value.

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