Electronic component heat distribution simulation method and system

Abstract

The invention provides an electronic component heat distribution simulation method and system. The method comprises the following steps: acquiring micro-gap height data and interlayer thermal resistance data; fitting a dynamic mapping relationship between the micro-gap and the interlayer thermal resistance according to the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data; performing thermal resistance dynamic assignment on different micro-gap height distribution areas in the three-dimensional twinning model to obtain a digital twinning dynamic model of the chip layer; dividing the chip layer according to the heat flux density gradients of different space units to obtain a plurality of local hot spot areas, and generating a grid refining scale in each local hot spot area during heat distribution simulation; and performing adaptive grid reconstruction on the digital twinning dynamic model based on the grid refining scale, and generating an interlayer heat distribution simulation report of the multi-chip stacked element according to a reconstruction result in combination with a preset heat distribution threshold value. By adopting the scheme of the invention, dynamic heat distribution simulation can be carried out on the multi-chip stacked element under the coupling action of interlayer heat resistance and working conditions.

Description

Technical Field

[0001] This application relates to the field of thermal distribution simulation technology, and more specifically, to a method and system for simulating thermal distribution of electronic components. Background Technology

[0002] Thermal distribution simulation is a technical application field that uses digital modeling systems and multiphysics numerical solution algorithms to visualize the heat transfer process of objects and systems under different environments, accurately calculate temperature field parameters, and derive thermal performance optimization schemes. It typically relies on core thermal simulation software (such as ANSYS Icepak, COMSOL Multiphysics, Fluent), 3D geometric modeling tools (such as SolidWorks, AutoCAD, Blender), and simulation result analysis platforms. It combines core technologies such as coupled heat conduction solution and basic thermophysical theoretical models to virtually reproduce the heat transfer process, quantitatively output temperature distribution data, and predict and generate optimization schemes for thermal performance problems.

[0003] Electronic component thermal distribution simulation utilizes professional-grade thermal simulation software and multiphysics numerical algorithms to accurately simulate the internal and surrounding heat transfer processes of various electronic components under different operating conditions and environmental factors. This allows for quantitative analysis of temperature field data, ultimately leading to thermal performance evaluation and the development of heat dissipation optimization strategies. Traditional thermal distribution simulation methods for multi-chip stacked components often rely on fixed thermal resistance parameters under a single operating state and a uniform mesh generation strategy across the entire area. This makes it difficult to address the coupling problem where different operating conditions (temperature and pressure) affect the height of tiny gaps between layers, thus altering heat transfer resistance. For example, in multi-chip stacked components... When stacked chip components are operating normally, the temperature of the core chip rises, causing the chip material to expand thermally, thus reducing the originally tiny gaps between the layers. Increased pressure increases the contact area between the layers. According to the inverse relationship between heat transfer resistance and contact area (the larger the contact area, the easier it is to transfer heat, and the smaller the resistance), the heat transfer resistance between the layers will decrease accordingly. However, traditional simulations completely fail to consider the coupling effect of different operating conditions and interlayer thermal resistance, directly using a fixed thermal resistance value under a single operating condition, which leads to errors in thermal resistance calculation. Therefore, how to perform dynamic thermal distribution simulation of multi-chip stacked components under the coupling effect of interlayer thermal resistance and operating conditions has become a challenge for the industry. Summary of the Invention

[0004] This application provides a method and system for simulating the thermal distribution of electronic components, which can perform dynamic thermal distribution simulation of multi-chip stacked components under the coupling effect of interlayer thermal resistance and operating conditions.

[0005] In a first aspect, this application provides a method for simulating the thermal distribution of electronic components, comprising the following steps: When multi-chip stacked devices are working, collect data on the micro-gap height and interlayer thermal resistance between chip layers under different operating conditions. Based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data, a dynamic mapping relationship between the micro-gap and the interlayer thermal resistance under different operating conditions is obtained by fitting. By combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of multi-chip stacked components, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model is dynamically assigned, resulting in a digital twin dynamic model of the interlayer thermal resistance of chip layers under different operating conditions. Based on the heat flux density gradient of different spatial units in the digital twin dynamic model, multiple local hot spot regions are divided in the chip layer. Then, based on the height distribution of the micro gaps between the chip layers, the mesh refinement scale of each local hot spot region is generated during the heat distribution simulation. Based on the mesh refinement scale, the digital twin dynamic model is adaptively reconstructed, and then an interlayer thermal distribution simulation report of multi-chip stacked components is generated based on the reconstruction results and a preset thermal distribution threshold.

[0006] In some embodiments, fitting the dynamic mapping relationship between the microgap and the interlayer thermal resistance under different operating conditions based on the numerical correlation characteristics of the microgap height data and the interlayer thermal resistance data specifically includes: Determine the numerical correlation characteristics between the micro-gap height data and the interlayer thermal resistance data; Obtain parameter information for multiple operating conditions of multi-chip stacked components during operation; Based on all parameter information and the numerical correlation characteristics, a mapping simulation is performed to obtain the dynamic mapping relationship between micro-gap and interlayer thermal resistance under different operating conditions.

[0007] In some embodiments, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model of the multi-chip stacked device is dynamically assigned to the three-dimensional twin model by combining the dynamic mapping relationship with the micro-gap height distribution between chip layers, thereby obtaining a digital twin dynamic model of the interlayer thermal resistance of the chip layers under different operating conditions. Specifically, this includes: Based on the height distribution of micro-gap between chip layers in the three-dimensional twin model of multi-chip stacked components, the chip layers in the three-dimensional twin model are divided into regions with different micro-gap height distributions; Based on the dynamic mapping relationship, multiple thermal resistance mapping values ​​of the three-dimensional twin model are determined; By dynamically assigning values ​​to the three-dimensional twin model using all thermal resistance mapping values, a digital twin dynamic model of the interlayer thermal resistance of the chip layer under different operating conditions is obtained.

[0008] In some embodiments, dividing the chip layer into multiple local hotspot regions based on the heat flux density gradient of different spatial units in the digital twin dynamic model specifically includes: Determine the heat flux density gradient of different spatial units in the digital twin dynamic model; Multiple local hotspot regions are obtained in the chip layer by combining all heat flux density gradients with a preset heat flux threshold.

[0009] In some embodiments, the mesh refinement scale in each local hot spot region during thermal distribution simulation, based on the height distribution of micro-gaps between chip layers, specifically includes: The micro-gap characteristic value of each local hot spot region is determined based on the height distribution of the micro-gap between chip layers; Preset the scale mapping rules between the mesh scale and the micro-gap between chip layers during thermal distribution simulation; The mesh refinement scale for each local hot spot region is determined based on the scale mapping rule and the micro-gap characteristic value of each local hot spot region during the thermal distribution simulation.

[0010] In some embodiments, adaptive mesh reconstruction of the digital twin dynamic model based on the mesh refinement scale specifically includes: Obtain the network topology of the digital twin dynamic model; Based on the aforementioned grid topology, the grid refinement scale of each local hotspot region is spatially matched with the aforementioned digital twin dynamic model; Based on the matching results, the mesh of each local hotspot area is adaptively refined to obtain multiple adaptive mesh elements; The digital twin dynamic model is reconstructed by topologically refactoring all adaptive mesh cells to obtain the reconstructed digital twin dynamic model.

[0011] In some embodiments, generating an interlayer thermal distribution simulation report for multi-chip stacked components based on the reconstruction results and a preset thermal distribution threshold specifically includes: Based on the reconstruction results, interlayer thermal analysis information between chip layers of multi-chip stacked components is generated; Based on a preset thermal distribution threshold, the interlayer thermal analysis information is thermally verified to obtain the thermal characteristic state information between chip layers. A simulation report on the interlayer thermal distribution of multi-chip stacked components is generated based on the thermal characteristic state information.

[0012] Secondly, this application provides an electronic component thermal distribution simulation system, comprising: The data acquisition module is used to collect micro-gap height data and interlayer thermal resistance data between chip layers under different operating conditions when multi-chip stacked components are working. The processing module is used to fit the dynamic mapping relationship between the micro-gap and the interlayer thermal resistance under different operating conditions based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data. The processing module is also used to dynamically assign thermal resistance values ​​to different micro-gap height distribution regions in the three-dimensional twin model by combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of multi-chip stacked components, so as to obtain a digital twin dynamic model of interlayer thermal resistance of chip layers under different operating conditions. The processing module is also used to divide multiple local hot spot regions in the chip layer according to the heat flux density gradient of different spatial units in the digital twin dynamic model, and then generate the mesh refinement scale of each local hot spot region during heat distribution simulation based on the height distribution of the micro gaps between chip layers. The execution module is used to perform adaptive mesh reconstruction on the digital twin dynamic model based on the mesh refinement scale, and then generate an interlayer thermal distribution simulation report of multi-chip stacked components based on the reconstruction results and a preset thermal distribution threshold. Thirdly, this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described intelligent performance detection method based on fiber sheathing.

[0013] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described intelligent performance detection method based on fiber sheathing.

[0014] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: The electronic component thermal distribution simulation method and system provided in this application collects micro-gap height data and interlayer thermal resistance data between chip layers under different operating conditions when a multi-chip stacked component is working. Based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data, a dynamic mapping relationship between the micro-gap and interlayer thermal resistance under different operating conditions is obtained. Using this dynamic mapping relationship and the micro-gap height distribution between chip layers in a three-dimensional twin model of the multi-chip stacked component, thermal resistance is dynamically assigned to different micro-gap height distribution regions in the three-dimensional twin model, resulting in a digital twin dynamic model of the interlayer thermal resistance of the chip layers under different operating conditions. Multiple local hotspot regions are divided in the chip layer according to the heat flux density gradient of different spatial units in the digital twin dynamic model. Then, based on the micro-gap height distribution between chip layers, a mesh refinement scale is generated for each local hotspot region during thermal distribution simulation. Based on the mesh refinement scale, the digital twin dynamic model undergoes adaptive mesh reconstruction. Finally, based on the reconstruction results and a preset thermal distribution threshold, an interlayer thermal distribution simulation report for the multi-chip stacked component is generated.

[0015] Therefore, this solution firstly collects micro-gap height data and interlayer thermal resistance data between chip layers under different operating conditions during the operation of multi-chip stacked components. Based on the numerical correlation characteristics of these two data, a dynamic mapping relationship between micro-gap and interlayer thermal resistance under different operating conditions is obtained. This dynamic mapping relationship can accurately quantify the interaction between operating conditions and interlayer thermal resistance. Whether it is the chip thermal expansion caused by temperature increase leading to a reduction in micro-gap, or the increase in pressure leading to an increase in contact area and a reduction in thermal resistance, or the linkage change between micro-gap and thermal resistance caused by operating condition switching, the dynamic mapping relationship can be analyzed layer by layer through the quantitative model of data fitting to analyze the nonlinear correlation law between micro-gap and thermal resistance under different operating conditions. This restores the true characteristics of interlayer thermal resistance dynamically changing with operating conditions, avoiding the calculation deviation caused by the use of fixed thermal resistance parameters in traditional methods. Compared with the traditional method that only relies on the measured thermal resistance under a single operating condition, this process, through the acquisition and correlation fitting of data under all operating conditions, frees thermal resistance calculation from the limitation of the assumption of constant operating conditions, providing a more accurate and accurate calculation method. The subsequent dynamic thermal resistance assignment of the digital twin model provides a precise quantitative basis. Then, after obtaining the dynamic digital twin model of the interlayer thermal resistance of the chip, multiple local hot spot regions are divided according to the heat flux density gradient of different spatial units in the model. Then, the mesh refinement scale of each local hot spot region is generated according to the height distribution of the micro gaps between the chip layers. The mesh refinement scale can realize mesh optimization with on-demand densification. This process locates the hot spot priority through the heat flux density gradient and determines the refinement degree in combination with the micro gap distribution. It can correct the defect that the coarse mesh in the whole area cannot capture the temperature change of the hot spot, and ensure that high-precision mesh resources are only invested in key hot areas. Compared with the traditional method that only relies on a uniform mesh scale, this process formulates a mesh strategy through the dual constraints of thermal characteristics and micro gap distribution, so that the mesh division is consistent with the actual heat transfer law and reduces the interference to the thermal distribution analysis. In summary, this scheme can perform dynamic thermal distribution simulation of multi-chip stacked components under the coupling effect of interlayer thermal resistance and operating conditions. Attached Figure Description

[0016] Figure 1 This is a flowchart illustrating a method for simulating the thermal distribution of electronic components according to some embodiments of this application; Figure 2 This is a flowchart illustrating the determination of dynamic mapping relationships according to some embodiments of this application; Figure 3 This is a schematic flowchart illustrating the implementation of thermal characteristic verification according to some embodiments of this application; Figure 4 This is a schematic diagram of the structure of an electronic component thermal distribution simulation system according to some embodiments of this application; Figure 5 This is an internal structural diagram of a computer device that implements a method for simulating the thermal distribution of electronic components according to some embodiments of this application. Detailed Implementation

[0017] To better understand the technical solutions in this embodiment, the technical solutions in this embodiment will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0018] refer to Figure 1 The figure is a flowchart illustrating a method for simulating the thermal distribution of electronic components according to some embodiments of this application. The method mainly includes the following steps: In step 101, when the multi-chip stacked device is working, data on the micro-gap height and interlayer thermal resistance between chip layers are collected under different operating conditions.

[0019] In practice, dynamic acquisition data of the target component can be obtained through a working condition simulation experiment system. The acquisition process needs to cover operating scenarios with different temperature conditions, different pressure conditions, and corresponding combinations of working condition parameters. Preferably, the micro-gap height values ​​of each acquisition point can be extracted from the detection records of the laser displacement sensor, the interlayer thermal resistance parameters can be derived from the synchronous measurement data of the thermocouple and heat flow meter, and the temperature and pressure parameter information of the corresponding acquisition period can be extracted from the log of the working condition control system as micro-gap height data and interlayer thermal resistance data between chip layers under different working conditions.

[0020] It should be noted that the micro-gap height data mentioned in this application refers to a set of parameters that reflect the physical gap characteristics between the chip layers of a multi-chip stacked element, and its physical meaning is the gap distance at each spatial position of the interlayer contact surface; the interlayer thermal resistance data refers to a set of parameters that characterize the ability of the chip layers of a multi-chip stacked element to impede heat flow transfer, and its physical meaning is the temperature difference passing through the interlayer under a unit heat flux density. In addition, the operating conditions include multiple operating condition parameters, such as temperature parameters and pressure parameters.

[0021] In step 102, the dynamic mapping relationship between the micro-gap and the interlayer thermal resistance under different operating conditions is obtained by fitting the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data.

[0022] In some embodiments, reference Figure 2 As shown in the figure, this is a flowchart illustrating the determination of dynamic mapping relationships in some embodiments of this application. The dynamic mapping relationship between the micro-gap and interlayer thermal resistance under different operating conditions can be obtained by fitting the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data using the following steps: First, in step 1021, the numerical correlation characteristics between the micro-gap height data and the interlayer thermal resistance data are determined; Then, in step 1022, parameter information of multiple operating condition parameters when the multi-chip stacked element is working is obtained; Finally, in step 1023, a mapping simulation is performed based on all parameter information and the numerical correlation characteristics to obtain the dynamic mapping relationship between micro-gap and interlayer thermal resistance under different operating conditions.

[0023] In specific implementation, determining the numerical correlation characteristics between the micro-gap height data and the interlayer thermal resistance data can be achieved through the following steps: First, determine the Pearson correlation coefficient between the micro-gap height data and the interlayer thermal resistance data. Preferably, this includes first calculating the mean values ​​of the micro-gap height data and the interlayer thermal resistance data respectively; then calculating the deviation of each data point from the mean and summing the corresponding products to obtain the covariance; next, calculating the product of the standard deviations of the micro-gap height data and the interlayer thermal resistance data; finally, dividing the covariance by the standard deviation product to obtain the Pearson correlation coefficient. In a preferred embodiment, the microgap height data and the interlayer thermal resistance data can be plotted as a scatter plot. By observing the distribution trend of the scatter plot, it can be determined whether there is a nonlinear relationship between the two, such as exponential decay or other curve forms. Then, based on the trend of the scatter plot, preliminary nonlinear characteristic parameters are extracted, including trend direction, curve steepness, or coefficient range of the fitted curve, to characterize the nonlinear relationship between the microgap height and the interlayer thermal resistance. Finally, the Pearson correlation coefficient and the nonlinear trend parameters are used as the numerical correlation features between the microgap height data and the interlayer thermal resistance data.

[0024] It should be noted that the numerical correlation features mentioned in this application refer to a set of parameters used to characterize the numerical relationship between microgap height data and interlayer thermal resistance data. The numerical correlation features include the linear relationship strength reflected by the Pearson correlation coefficient and nonlinear feature parameters extracted based on the scatter plot trend, which are used to characterize the comprehensive numerical correlation characteristics between microgap height and interlayer thermal resistance.

[0025] It should be noted that the operating parameters mentioned in this application refer to the operating status of the target multi-chip stacked component under different combinations of temperature and pressure. The temperature parameters can be recorded in real time by temperature sensors in the packaging test system or operating condition control system, and the pressure parameters can be obtained by force sensors or pressure monitoring modules in the packaging system. The acquisition frequency of the operating parameters can be set according to the dynamic change characteristics of the micro gaps between chip layers. For example, temperature and pressure data can be collected every one to ten seconds to cover the typical operating range of the target component. In a preferred embodiment, the operating condition control system log can be synchronously collected and recorded with the sensors to ensure the integrity and continuity of temperature and pressure parameters. In other embodiments, the operating parameters can also be dynamically labeled and classified by the temperature gradient change rate or pressure change rate characteristics, which is not limited in this application.

[0026] In specific implementation, the dynamic mapping relationship between micro-gap and interlayer thermal resistance under different operating conditions can be obtained by performing mapping simulation based on all parameter information and the numerical correlation features, as follows: First, the numerical correlation features of the micro-gap height data and interlayer thermal resistance data, along with the corresponding operating condition parameter information, are organized into a mapping training dataset, where each data entry includes the micro-gap height value, temperature parameter, pressure parameter, and corresponding interlayer thermal resistance value; then, the interlayer thermal resistance is used as the dependent variable, and the micro-gap height, temperature, and pressure are used as independent variables, assuming a nonlinear relationship between the interlayer thermal resistance and the independent variables; subsequently, the least squares method is used to fit the nonlinear function, and the function coefficients are iteratively adjusted to minimize the sum of squared residuals between the measured interlayer thermal resistance and the fitted value until convergence; in a preferred embodiment, an exponential, power-law, or polynomial form of nonlinear function can be used for fitting, and the fitting accuracy is judged by cross-validation; In another embodiment, existing neural network algorithms can also be used for mapping simulation, specifically including: First, constructing a feedforward neural network with an input layer, a hidden layer, and an output layer, wherein the neurons in the input layer correspond to the micro-gap height, temperature, and pressure parameters, and the neurons in the output layer correspond to the interlayer thermal resistance value; the hidden layer uses one to three layers, with several neurons in each layer, and setting an activation function to increase the nonlinear fitting ability; then, training the network using the micro-gap height data and the interlayer thermal resistance data, minimizing the mean square error between the network output interlayer thermal resistance value and the measured value through gradient descent or Adam optimizer, until the training error converges; finally, by inputting the micro-gap height, temperature, and pressure parameters under different operating conditions into the trained neural network model, the corresponding interlayer thermal resistance value can be calculated and output, thereby using the trained neural network model as a dynamic mapping relationship between the micro-gap and interlayer thermal resistance of multi-chip stacked components under different temperature and pressure combinations.

[0027] It should be noted that the dynamic mapping relationship described in this application refers to a parameterized mapping model used to characterize the numerical correspondence between the micro-gap height and interlayer thermal resistance of multi-chip stacked components under different operating conditions. This model is used to reflect the nonlinear correspondence and dynamic coupling characteristics between the micro-gap height and interlayer thermal resistance under various operating conditions.

[0028] In step 103, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model of the multi-chip stacked components is dynamically assigned by combining the dynamic mapping relationship with the micro-gap height distribution in the three-dimensional twin model, so as to obtain a digital twin dynamic model of the interlayer thermal resistance of the chip layers under different operating conditions.

[0029] It should be noted that the three-dimensional twin model of the multi-chip stacked device described in this application refers to a digital model constructed in virtual space based on the actual structural parameters, material properties, and operating condition data of the target multi-chip stacked device through three-dimensional modeling and numerical simulation technology. This model is used to dynamically map and simulate the geometric morphology, micro-gap distribution, and thermal resistance characteristics between chip layers. The three-dimensional twin model can be generated using finite element modeling tools, thermal analysis software, or a self-developed simulation platform. Its data sources include chip geometric dimensions, packaging hierarchy, material thermal conductivity, and measured operating condition parameters. Furthermore, the three-dimensional twin model includes multiple spatial units. Each spatial unit is the smallest geometric unit obtained by discretizing the chip layers and their inter-layer micro-gap regions according to a preset meshing method during the construction of the three-dimensional twin model. Each spatial unit corresponds to a unique geometric coordinate range and material properties, used to carry local temperature distribution values, micro-gap height values, and thermal resistance calculation results. The spatial units can adopt regular cubic, tetrahedral, or hexahedral mesh forms, and the meshing accuracy can be adjusted according to the complexity of the chip structure and the simulation accuracy requirements, such as micrometer-level or sub-micrometer-level meshing.

[0030] In some embodiments, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model of the multi-chip stacked device is dynamically assigned by combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model, thereby obtaining a digital twin dynamic model of the interlayer thermal resistance of the chip layers under different operating conditions. This can be achieved by the following steps: Based on the height distribution of micro-gap between chip layers in the three-dimensional twin model of multi-chip stacked components, the chip layers in the three-dimensional twin model are divided into regions with different micro-gap height distributions; Based on the dynamic mapping relationship, multiple thermal resistance mapping values ​​of the three-dimensional twin model are determined; By dynamically assigning values ​​to the three-dimensional twin model using all thermal resistance mapping values, a digital twin dynamic model of the interlayer thermal resistance of the chip layer under different operating conditions is obtained.

[0031] In specific implementation, dividing the chip layers in the 3D twin model into different micro-gap height distribution regions based on the micro-gap height distribution between chip layers in the 3D twin model of multi-chip stacked components can be achieved in the following way: First, obtain the micro-gap height data of each chip layer in the 3D twin model. The micro-gap height data can be obtained through simulation and represents the micro-gap height value at different spatial locations between chip layers. Then, statistically analyze the minimum, maximum, mean, and standard deviation of all micro-gap height data. Based on all statistical measures, divide the micro-gap height values ​​into several continuous intervals. For example, a low micro-gap region, a medium micro-gap region, and a high micro-gap region can be set, with each interval corresponding to a certain range. The micro-gap height value is then determined. Next, all spatial units in the 3D twin model are traversed, and each unit is assigned to a corresponding micro-gap height distribution region based on the interval to which its micro-gap height value belongs. This divides the chip layers in the 3D twin model into different micro-gap height distribution regions. As a preferred embodiment, the interval boundaries can be adaptively adjusted based on the statistical distribution of the micro-gap height to ensure a reasonable number of spatial units in each micro-gap height distribution region, fully reflecting the microscopic height differences between chip layers. In other embodiments, clustering algorithms can be used to automatically group the micro-gap height data, classifying spatial units with similar micro-gap heights into the same region. This application does not limit this approach.

[0032] It should be noted that the micro-gap height distribution region mentioned in this application refers to several spatial sub-regions formed by statistical partitioning or clustering based on the micro-gap height data of each spatial unit in the chip layer of the three-dimensional twin model.

[0033] In specific implementation, determining multiple thermal resistance mapping values ​​of the three-dimensional twin model based on the dynamic mapping relationship can be achieved in the following way: First, for each microgap height distribution region, obtain the microgap height values ​​of all spatial units within that region, and calculate their average or weighted average as the representative microgap height value for that region; then, obtain the temperature and pressure parameters under the current operating conditions, and perform unified normalization processing on the microgap height values, temperature, and pressure parameters, using the normalized values ​​as the input vector of the dynamic mapping model; next, input this input vector into the model corresponding to the dynamic mapping relationship. Preferably, this model can be a multivariate nonlinear regression function or a trained feedforward neural network, with the root inside the model... The thermal resistance value is calculated based on the input microgap height, temperature, and pressure parameters. The nonlinear regression function obtains the fitting coefficients through least-squares fitting, and the neural network calculates the output layer neuron values ​​through forward propagation, all representing the interlayer thermal resistance of the corresponding region. Then, the thermal resistance value output by the model is used as the thermal resistance mapping value for the microgap height distribution region. In a preferred embodiment, necessary feature transformations (such as exponential, logarithmic, or polynomial expansion) can be performed on the input vector before calculation to enhance the model's ability to fit nonlinear relationships. In other embodiments, the microgap height value and operating parameters can be input separately for each unit within the region to obtain a more accurate local thermal resistance mapping; this application does not limit this approach.

[0034] It should be noted that the thermal resistance mapping value mentioned in this application refers to the interlayer thermal resistance value calculated by the representative micro-gap height value, temperature parameter and pressure parameter of the micro-gap height distribution region under given operating conditions based on the dynamic mapping relationship model. It is used to characterize the interlayer thermal resistance characteristics of the micro-gap height distribution region under specific operating conditions.

[0035] In specific implementation, the digital twin dynamic model of interlayer thermal resistance under different operating conditions is obtained by dynamically assigning all thermal resistance mapping values ​​to the three-dimensional twin model. This can be achieved in the following way: First, obtain all spatial units of each chip layer in the three-dimensional twin model. Each spatial unit has a clear three-dimensional coordinate and a corresponding micro-gap height value. Then, traverse each micro-gap height distribution area and assign the thermal resistance mapping value of that area to all spatial units in the area to form a preliminary regional thermal resistance distribution. Next, for each spatial unit, record its three-dimensional coordinates in the three-dimensional twin model coordinate system and the assigned thermal resistance value to ensure that the thermal resistance value of each spatial unit corresponds one-to-one with its physical location. In a preferred embodiment, the thermal resistance of each adjacent chip layer can be... The thermal resistance values ​​of the spatial units are spatially smoothed by calculating a weighted average of the thermal resistance values ​​in the neighborhood of each spatial unit. The weights can be determined based on the inverse ratio of the distance between units, thereby ensuring the spatial continuity and gradient smoothness of the thermal resistance values. In other embodiments, the thermal resistance value of each spatial unit can be calculated individually based on its micro-gap height value and corresponding operating parameters input into a dynamic mapping relationship model, and then assigned to the spatial unit to obtain a more refined local thermal resistance distribution. Finally, after assigning thermal resistance values ​​to all spatial units in the three-dimensional twin model, a digital twin dynamic model of the interlayer thermal resistance of the chip layer under different operating conditions is formed. The thermal resistance value of each spatial unit is clearly recorded and can be used for thermal analysis, optimization design, and operational status evaluation. This application does not limit this aspect.

[0036] It should be noted that the digital twin dynamic model described in this application refers to a thermal resistance distribution model formed by dynamically assigning values ​​to each chip layer and its spatial units based on the spatial unit structure of a three-dimensional twin model and the thermal resistance mapping values ​​calculated under different operating conditions. The digital twin dynamic model can characterize the interlayer thermal resistance spatial distribution characteristics of the target multi-chip stacked components under varying operating conditions such as temperature and pressure. Its numerical updates are adjusted in real time according to the operating parameters, thereby reflecting the dynamic evolution process of interlayer thermal behavior.

[0037] In step 104, multiple local hotspot regions are divided in the chip layer according to the heat flux density gradient of different spatial units in the digital twin dynamic model, and then the mesh refinement scale of each local hotspot region is generated according to the height distribution of the micro gaps between the chip layers during heat distribution simulation.

[0038] In some embodiments, the division of multiple local hotspot regions in the chip layer based on the heat flux density gradient of different spatial units in the digital twin dynamic model can be achieved by the following steps: Determine the heat flux density gradient of different spatial units in the digital twin dynamic model; Multiple local hotspot regions are obtained in the chip layer by combining all heat flux density gradients with a preset heat flux threshold.

[0039] In specific implementation, the heat flux density gradient of different spatial units in the digital twin dynamic model can be determined in the following way: First, the interlayer temperature difference of the spatial unit is calculated by multiplying the interlayer thermal resistance value of each spatial unit with the power consumption value of the chip under the current operating condition, and the interlayer temperature difference values ​​of all spatial units are combined to construct the temperature difference distribution between chip layers; then, based on Fourier's law of thermal conductivity, the temperature change rate of each spatial unit is multiplied by the thermal conductivity of the material to calculate the heat flux density value of the spatial unit, and the heat flux density distribution within the chip layer is constructed from the heat flux density values ​​of all spatial units; next, for each spatial unit, the rate of change of heat flux density is calculated in the horizontal, vertical and thickness directions of the three-dimensional spatial coordinates, thereby obtaining the heat flux density gradient of the spatial unit in the three-dimensional coordinate system, which is used to characterize the change of heat flux in different directions; as a preferred embodiment, the finite difference method can be used to numerically approximate the derivative of the heat flux density difference between adjacent spatial units to obtain a more accurate heat flux density gradient; in other embodiments, the finite element method can also be combined to obtain a more accurate heat flux density gradient. The heat flux density gradient distribution can be directly obtained by solving the temperature field change rate in the local element matrix. This application does not limit this method. It should be noted that the power consumption value under the current operating condition mentioned in this application refers to the instantaneous power consumption of the target multi-chip stacked element under a specific temperature and pressure combination. The power consumption may include the total power consumption of each functional unit inside the chip layer. The power consumption value can be obtained in real time by the power monitoring module in the packaging and testing system or the power consumption acquisition unit built into the chip. The acquisition method can be a combination of current and voltage measurement and digital sampling to record the instantaneous power or average power data. The acquisition frequency of the power consumption value can be set according to the temperature change rate between chip layers and the dynamic change characteristics of micro gaps. For example, power consumption data can be collected once every one to ten seconds to cover the power fluctuation range of the target element under typical operating conditions. In a preferred embodiment, the power consumption data can be collected and recorded synchronously by the operating condition control system log and the power sensor to ensure the integrity and continuity of the power consumption data. In other embodiments, the chip power consumption can also be dynamically labeled and classified by the power change rate characteristics. This application does not limit this method.

[0040] It should be noted that the heat flux density gradient mentioned in this application refers to the rate of change of heat flux density in the three-dimensional spatial coordinate system along the horizontal, vertical and thickness directions, obtained by calculating the local temperature difference generated by the interlayer thermal resistance and power consumption of each spatial unit under the current operating conditions based on the digital twin dynamic model and combining it with the thermal conductivity of the material. This is used to characterize the trend and intensity of heat flux change in different directions of each spatial unit in the target multi-chip stacked element.

[0041] In specific implementation, the division of multiple local hotspot regions in the chip layer by combining all heat flux density gradients and a preset heat flux threshold can be achieved in the following way: First, for each spatial unit in the digital twin dynamic model, the rate of change of heat flux density in the horizontal, vertical, and thickness directions of the spatial unit is obtained, and the square root of the sum of the squares of the rates of change in the three directions is taken to obtain the heat flux density gradient magnitude of the spatial unit, which is used to characterize the overall heat flux change intensity of the spatial unit in the three-dimensional coordinate system; then, a preset heat flux threshold is obtained, which can be set according to industry thermal failure standards, experimental calibration values, or adaptive adjustment strategies; next, the heat flux density gradient magnitude of each spatial unit is compared with the heat flux threshold one by one. When the heat flux density gradient magnitude of a certain spatial unit is greater than or equal to the heat flux threshold, the hotspot is determined. When the heat flux density gradient magnitude of a spatial unit is less than the heat flux threshold, the spatial unit is marked as a non-hotspot unit, thus achieving preliminary classification of the spatial units. Then, all hotspot candidate units are traversed, and based on their adjacency relationship in three-dimensional spatial coordinates, the continuously distributed hotspot candidate units are aggregated to form several independent hotspot regions. As a preferred embodiment, a connected component segmentation method can be used to determine whether candidate units belong to the same hotspot region by judging whether they are in contact within a six-neighbor or twenty-six-neighbor range. In other embodiments, a clustering algorithm can also be used to spatially cluster hotspot candidate units, classifying spatially closely distributed units into the same hotspot region, thereby obtaining multiple local hotspot regions. This application does not limit this.

[0042] It should be noted that the local hot spot region mentioned in this application refers to a local spatial region in the target multi-chip stacked element where the heat flow distribution is concentrated and the heat flow changes significantly under specific operating conditions. It is used to characterize the location and spatial distribution characteristics of the chip layers where high thermal stress or thermal failure risk may occur.

[0043] In some embodiments, the mesh refinement scale for each local hot spot region during thermal distribution simulation, based on the height distribution of micro-gaps between chip layers, can be achieved using the following steps: The micro-gap characteristic value of each local hot spot region is determined based on the height distribution of the micro-gap between chip layers; Preset the scale mapping rules between the mesh scale and the micro-gap between chip layers during thermal distribution simulation; The mesh refinement scale for each local hot spot region is determined based on the scale mapping rule and the micro-gap characteristic value of each local hot spot region during the thermal distribution simulation.

[0044] In specific implementation, the micro-gap characteristic value of each local hot spot region can be determined based on the micro-gap height distribution between chip layers in the following manner: First, for each local hot spot region, the micro-gap height data of all spatial units within its coverage area is obtained. The micro-gap height data can be obtained through simulation and represents the chip layer gap value at different spatial locations within the region. Subsequently, all micro-gap height data within the local hot spot region are statistically processed, and the average micro-gap value of the corresponding local hot spot region is calculated as the micro-gap characteristic value of the local hot spot region. In other embodiments, other methods can also be used to obtain the micro-gap characteristic value, which is not limited here.

[0045] It should be noted that the micro-gap characteristic value mentioned in this application refers to a representative parameter value used to characterize the size of the inter-chip gap in each local hot spot region in a multi-chip stacked element, in order to reflect the concentration trend of the micro-height distribution and local structural characteristics of the hot spot region.

[0046] It should be noted that the scale mapping rule described in this application refers to a preset correspondence between the micro-gap characteristic values ​​between chip layers and the simulation mesh size during thermal distribution simulation. The mapping rule can be set according to the structure type, material properties, and simulation accuracy requirements of the target multi-chip stacked component. The mapping relationship can be expressed in the form of tables, functions, or empirical formulas. For example, the smaller the micro-gap height, the finer the corresponding simulation mesh size, so as to ensure the analytical accuracy of local heat flow changes. The determination of the mapping rule can refer to industry thermal simulation standards or obtain an optimal range through simulation accuracy verification. In a preferred embodiment, different scale mapping rules can be set for different types of chip layers to adapt to the needs of industrial-grade or high-precision packaging. In other embodiments, the mapping rule can also be dynamically adjusted, for example, the mesh size can be adaptively optimized according to the dispersion of the micro-gap distribution between chip layers or the hot spot density. This application does not limit this.

[0047] In specific implementation, the mesh refinement scale for each local hotspot region during thermal distribution simulation, based on the scale mapping rule and the micro-gap characteristic value of each local hotspot region, can be determined in the following way: First, for each local hotspot region, its micro-gap characteristic value is obtained. The micro-gap characteristic value is the average or weighted average of the micro-gap heights of all spatial units in the region. Then, the micro-gap characteristic value is substituted into a pre-set scale mapping rule. The mapping rule can be in the form of a table, function, or empirical formula. For example, different micro-gap height ranges can be mapped to different mesh sizes through a table, or a linear or non-linear relationship can be established between the micro-gap height and the mesh size through an empirical formula, such as the mesh size being equal to the micro-gap characteristic value multiplied by a preset coefficient. Next, the mapped mesh size value is used as the mesh refinement scale for the corresponding local hotspot region during thermal distribution simulation. In other embodiments, other methods can also be used to determine this, which are not limited here.

[0048] It should be noted that the mesh refinement scale mentioned in this application refers to the parameter value used to characterize the fineness of the finite element mesh in each local hot spot region during the simulation of interlayer thermal distribution of multi-chip stacked components, in order to reflect the spatial resolution and computational accuracy required for thermal analysis in that region.

[0049] In step 105, the digital twin dynamic model is adaptively reconstructed based on the mesh refinement scale, and then a simulation report of interlayer thermal distribution of multi-chip stacked components is generated based on the reconstruction results and a preset thermal distribution threshold.

[0050] In some embodiments, adaptive mesh reconstruction of the digital twin dynamic model based on the mesh refinement scale can be achieved using the following steps: Obtain the network topology of the digital twin dynamic model; Based on the aforementioned grid topology, the grid refinement scale of each local hotspot region is spatially matched with the aforementioned digital twin dynamic model; Based on the matching results, the mesh of each local hotspot area is adaptively refined to obtain multiple adaptive mesh elements; The digital twin dynamic model is reconstructed by topologically refactoring all adaptive mesh cells to obtain the reconstructed digital twin dynamic model.

[0051] It should be noted that the acquisition of the network topology of the digital twin dynamic model described in this application refers to acquiring all node and element information constituting the three-dimensional twin model during thermal distribution simulation or finite element modeling, including the spatial coordinates of each node, the node index of the element, and the adjacency relationship between elements. The node coordinates can be obtained through initial mesh generation software or simulation preprocessing module, representing the discrete spatial position of the chip layer and its gaps. The element can be a tetrahedron, hexahedron, or other polyhedron, used to discretely represent the volume of the chip layer and its gaps. The element node index and adjacency relationship can be obtained by exporting or programming the initial mesh file through finite element software to establish complete mesh topology information. The acquisition frequency of the topology can be set according to the simulation accuracy and the dynamic change characteristics of the micro gaps between chip layers. For example, node and element information can be extracted once for each thermal distribution update or each time step to ensure the accuracy of adaptive mesh reconstruction.

[0052] In specific implementation, spatial matching of the mesh refinement scale of each local hotspot region with the digital twin dynamic model based on the mesh topology can be achieved in the following way: First, for each local hotspot region, obtain the node coordinates and unit boundary information of all spatial units within its coverage area, and simultaneously obtain the corresponding mesh refinement scale of the region; then, compare the mesh refinement scale with the initial unit size of each unit within the coverage area to divide the units that need to be refined, that is, when the unit size is larger than the target mesh refinement scale, the unit is marked as a refined unit; then, for each refined unit, insert new nodes within the unit according to the target mesh refinement scale. The points are divided into several sub-units, and the size of each sub-unit is made close to the target mesh refinement scale, thereby achieving spatial distribution matching. That is, the new node coordinates and boundary information of each sub-unit after the division of each encrypted unit are used as the matching result. As a preferred embodiment, the encrypted sub-units can be evenly distributed in the hot spot area by geometric center positioning and volume equalization, covering the entire hot spot area, while retaining the original unit size in the non-hot spot area to reduce the amount of computation. In other embodiments, recursive partitioning or topology optimization algorithms can also be used to obtain the spatial coordinates and unit topology information of each sub-unit through node insertion and unit re-partitioning. This application does not limit this.

[0053] In specific implementation, the adaptive mesh refinement of each local hotspot region based on the matching results to obtain multiple adaptive mesh elements can be achieved in the following way: First, for the refinement element in each local hotspot region, obtain the spatial element coordinates and sub-element boundary information contained in its matching results; then, divide the spatial volume of the refinement element into several equally spaced segments along three orthogonal directions, with the division spacing based on the target mesh refinement scale, so that the spatial length corresponding to each segment is close to the preset mesh refinement scale; next, form a regular mesh lattice according to the spatial element coordinates in each direction after division, and combine adjacent spatial elements sequentially according to the standard connection rules of tetrahedral or hexahedral elements to generate each sub-element, while recording the node number, boundary information and adjacent element relationship of each sub-element, thereby forming an adaptive mesh element set for each local hotspot region, that is, obtaining multiple adaptive mesh elements corresponding to each local hotspot region. In other embodiments, recursive partitioning, topology optimization or finite element adaptive reconstruction algorithms can also be combined to generate adaptive mesh elements by iteratively adjusting the partitioning spacing and node position, which is not limited in this application.

[0054] It should be noted that the adaptive mesh element described in this application refers to the finite element element that is adaptively generated based on the thermal characteristics, micro-gap features and mesh refinement scale of each local hot spot region during the simulation of interlayer thermal distribution of multi-chip stacked components. Each element has clear node coordinates, spatial boundaries and relationships with adjacent elements, in order to reflect the details of local thermal distribution in the region and improve the spatial resolution and calculation accuracy of thermal analysis.

[0055] In specific implementation, the digital twin dynamic model is topologically reconstructed using all adaptive mesh elements. The reconstructed digital twin dynamic model can be achieved in the following way: First, obtain the node coordinates, element boundary information, and node numbers of the adaptive mesh elements in each local hotspot region and the original elements in the non-hotspot region. Then, perform coordinate alignment processing on the adaptive mesh elements and the original elements in the non-hotspot region in three-dimensional space, that is, map each element node to a unified three-dimensional coordinate system according to its actual position in space, and merge nodes whose distance is less than a preset tolerance to ensure the uniqueness and continuity of nodes. Next, according to the boundary definition order of each spatial element, combine the aligned node numbers to form the node connection sequence of the element. At the same time, determine the relationship between adjacent elements based on the node sharing situation, that is, if two elements share at least one face or edge, they are recorded as adjacent elements. On this basis, summarize the node connection sequence, boundary information, and adjacent element relationship of all elements to construct a complete node set and single The set of elements is used as the reconstructed digital twin dynamic model. In a preferred embodiment, the set of spatial elements and the topological relationships between elements are used as the reconstructed digital twin dynamic model. This can be achieved by traversing all elements and generating a data structure containing node coordinates, node connection sequences, and adjacent element relationships. This allows for seamless combination of adaptive mesh elements and original elements in non-hotspot regions. In other embodiments, topology optimization algorithms or topology reconstruction tools provided by finite element software can be used to automate node merging, element reconstruction, and adjacency relationship generation. This application does not limit this. The node merging preset tolerance refers to the spatial distance threshold used to determine whether adjacent nodes should be considered as the same node during the three-dimensional coordinate alignment process between the adaptive mesh elements and the original elements in non-hotspot regions. The preset tolerance can be set according to the size characteristics of the micro-gap between chip layers, the initial mesh size, and the simulation accuracy requirements. For example, it can be set to a range of 1% to 5% of the target mesh refinement scale to ensure the continuity between the densified mesh in hotspot regions and the original mesh nodes in non-hotspot regions.

[0056] In some embodiments, generating an interlayer thermal distribution simulation report for multi-chip stacked components based on the reconstruction results and a preset thermal distribution threshold can be achieved using the following steps: Based on the reconstruction results, interlayer thermal analysis information between chip layers of multi-chip stacked components is generated; Based on a preset thermal distribution threshold, the interlayer thermal analysis information is thermally verified to obtain the thermal characteristic state information between chip layers. A simulation report on the interlayer thermal distribution of multi-chip stacked components is generated based on the thermal characteristic state information.

[0057] As a preferred embodiment, generating interlayer thermal analysis information between chip layers of a multi-chip stacked element based on the reconstruction results can be achieved in the following manner: First, the reconstructed digital twin dynamic model is imported into the Steady-State Thermal solver in the ANSYS Workbench environment, and node and element information is loaded through command flow or the Workbench geometry import interface; then, material thermal properties parameters, including thermal conductivity, specific heat capacity, and density, are specified for each chip layer and its gaps. Preferably, this can be achieved through the APDL command material properties (Material... Properties (MP) are used to set thermal conductivity, specific heat capacity, and density. Next, boundary conditions are applied: chip layer power consumption is applied as a volumetric heat source, ambient temperature is applied as a node temperature constraint, and packaging pressure is applied as a contact pressure. Contact pairs are then established in the contact cells. Subsequently, a steady-state or transient finite element solver is selected, and the node temperature and element heat flux are iteratively solved using the SOLVE command. The solver internally constructs a thermal conductivity matrix and uses iterative or direct methods to obtain the temperature distribution of each spatial cell. After the solution is completed, the temperature of each spatial cell is obtained using the GET command, the element heat flux density is extracted using ETABLE, and the hotspot temperature peak, interlayer thermal resistance, and heat flux density distribution of each region are calculated based on the coordinates of the spatial cells. Finally, the temperature of each spatial cell, the element heat flux density, and the hotspot temperature peak are used as interlayer thermal analysis information between chip layers. In other embodiments, other methods can be used, which are not limited here.

[0058] It should be noted that the interlayer thermal analysis information between chip layers mentioned in this application refers to the set of parameters such as temperature distribution, unit heat flux density, hot spot temperature peak and interlayer thermal resistance of each chip layer and its micro-gap space unit obtained by finite element solution based on the reconstructed digital twin dynamic model. These parameters are used to characterize the interlayer thermal conduction characteristics and hot spot distribution of multi-chip stacked components under specific operating conditions.

[0059] It should be noted that the preset thermal distribution threshold mentioned in this application refers to a set of benchmark values ​​used to determine whether the temperature of each node, the heat flux density of each unit, and the peak temperature of hot spots between chip layers meet the design or operational requirements during the thermal characteristic verification process of interlayer thermal analysis information. The threshold set may include temperature thresholds, heat flux density thresholds, and hot spot temperature thresholds, used to characterize the allowable range and over-limits of chip layers under different thermal parameter dimensions. The temperature threshold can be determined by the thermal failure critical temperature of the chip material or the safe operating temperature range of the packaging process, reflecting the risk boundary of possible chip failure under overheating conditions. The heat flux density threshold can be determined based on the chip material's thermal failure critical temperature or the safe operating temperature range of the packaging process. The interlayer thermal conductivity and packaging interface heat dissipation efficiency are set to characterize whether the heat flow in different spatial units exceeds the tolerable conduction limit; the hot spot temperature threshold can be obtained through experimental calibration or design specifications to describe the highest allowable temperature level in a local area of ​​the chip under typical operating conditions; preferably, the preset heat distribution threshold can be dynamically updated according to the simulation accuracy and heat distribution update frequency during application, for example, it can be extracted and corrected once after each simulation time step, each temperature field reconstruction, or each thermal risk assessment to ensure that the thermal characteristic verification is consistent with the chip operating state. In other embodiments, other methods can be used to preset it, which are not limited here.

[0060] For specific implementation, refer to Figure 3 As shown in the figure, this is a schematic diagram of the process for implementing thermal characteristic verification according to some embodiments of this application. The thermal characteristic verification of the interlayer thermal analysis information based on a preset thermal distribution threshold to obtain the interlayer thermal characteristic state information of the chip can be achieved in the following manner: First, the temperature, heat flux density, and hot spot temperature peak of each spatial unit in the interlayer thermal analysis information are compiled into a verification dataset; then, the temperature, heat flux density, and hot spot temperature of each spatial unit in the verification dataset are compared one by one with the preset thermal distribution threshold. Specifically, this includes: when the temperature of the spatial unit is greater than or equal to the temperature threshold, it is considered that the temperature of the spatial unit exceeds the limit; when the heat flux density of the spatial unit is greater than or equal to the heat flux density threshold... The space unit is considered to exceed the limit when the heat flow exceeds the limit. When the peak temperature of the hotspot in the space unit is greater than or equal to the hotspot temperature threshold, the space unit is considered to exceed the limit. Furthermore, if any one of the three parameters of the space unit exceeds or equals the corresponding threshold, the entire space unit is marked as an out-of-limit space unit, and the corresponding value and three-dimensional spatial position are recorded. Only when all parameters are less than the corresponding threshold is the space unit or node marked as a compliant space unit. Then, the verification results of all space units are summarized to form the thermal characteristic status information between chip layers. In other embodiments, weighted scoring or statistical analysis methods can be combined to comprehensively evaluate the thermal characteristics of the hotspot region; this application does not limit this.

[0061] It should be noted that the thermal characteristic status information mentioned in this application refers to the interlayer thermal analysis information based on each chip layer and its gap in a multi-chip stacked element. After comparison and verification with a preset thermal distribution threshold, the temperature, heat flux density, and hot spot temperature peak of each spatial unit are marked with a status (such as compliant or exceeding the limit) and the corresponding three-dimensional spatial position is recorded to form a set of parameters to characterize the thermal characteristic compliance between chip layers.

[0062] In specific implementation, generating an interlayer thermal distribution simulation report for multi-chip stacked components based on the aforementioned thermal characteristic state information can be achieved in the following manner: First, extract key thermal parameters based on the interlayer thermal characteristic state information, including the temperature of each node, the heat flux density of the unit, and the peak temperature of the hot spot; for example, for a spatial unit of a chip layer, the temperature is 75°C, the heat flux density is 0.8 W / mm², and the peak temperature of the hot spot is 80°C; simultaneously, record the three-dimensional spatial coordinates and status identifier (compliant spatial unit or over-limit spatial unit) of each spatial unit; then, compare and analyze the thermal parameters of the spatial unit with a preset thermal distribution threshold, and calculate the average temperature, maximum temperature, number of local hot spots, and interlayer thermal resistance distribution of each chip layer; through statistical analysis, the hot spot concentration area and abnormal heat flux distribution pattern can be obtained, for example, when the graphics processing unit (Graphics Processing) In the GPU (Unit) layer, continuous over-limit nodes form thermal concentration bands. Next, based on the analysis results, an inter-layer thermal distribution pattern description is generated, which can preferably include hotspot concentration, uniform distribution, and local anomaly types. For example, when there are obvious hotspot concentration bands and abnormal heat flux density in the chip layer, it can be described as a local hotspot concentration type. Then, the extracted thermal parameters, statistical analysis results, and inter-layer thermal distribution pattern descriptions are integrated to form multi-dimensional analysis content, including text descriptions (e.g., average temperature, hotspot descriptions), tabular data (e.g., node temperature, heat flux density, status indicators, and three-dimensional coordinates), and visualization graphics (e.g., color isothermal surface plots, heat flux vector diagrams, and hotspot annotation diagrams). Finally, the integrated multi-dimensional analysis content is output as an electronic document or image file to generate an inter-layer thermal distribution simulation report for multi-chip stacked components.

[0063] It should be noted that the interlayer thermal distribution simulation report of multi-chip stacked components mentioned in this application refers to a comprehensive analysis document or image file generated after statistical and visualization processing of the temperature, heat flux density and hot spot distribution of each spatial unit based on the interlayer thermal characteristic state information of the chip and the adaptive mesh analysis results, in order to comprehensively characterize the interlayer thermal distribution of the chip.

[0064] In another aspect, in some embodiments, this application provides an electronic component thermal distribution simulation system, with reference to... Figure 4The figure is a schematic diagram of the structure of an electronic component thermal distribution simulation system according to some embodiments of this application. The electronic component thermal distribution simulation system 200 includes: a data acquisition module 201, a processing module 202, and an execution module 203, which are described below: The acquisition module 201 in this application is mainly used to acquire micro-gap height data and interlayer thermal resistance data between chip layers under different operating conditions when multi-chip stacked components are working. Processing module 202, in this application, is mainly used to fit the dynamic mapping relationship between micro gap and interlayer thermal resistance under different working conditions based on the numerical correlation characteristics of the micro gap height data and the interlayer thermal resistance data. In addition, the processing module 202 in this application is also used to dynamically assign thermal resistance values ​​to different micro-gap height distribution regions in the three-dimensional twin model by combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of multi-chip stacked components, so as to obtain a digital twin dynamic model of interlayer thermal resistance of chip layers under different operating conditions. In addition, the processing module 202 in this application is also used to divide multiple local hot spot regions in the chip layer according to the heat flux density gradient of different spatial units in the digital twin dynamic model, and then generate the mesh refinement scale in each local hot spot region during heat distribution simulation based on the height distribution of the micro gaps between chip layers. The execution module 203 in this application is mainly used to perform adaptive mesh reconstruction on the digital twin dynamic model based on the mesh refinement scale, and then generate an interlayer thermal distribution simulation report of multi-chip stacked components based on the reconstruction result and a preset thermal distribution threshold.

[0065] In addition, this application also provides a computer device, the computer device including a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the above-described electronic component thermal distribution simulation method.

[0066] In some embodiments, reference Figure 5 This figure is an internal structural diagram of a computer device implementing an electronic component thermal distribution simulation method according to some embodiments of this application. The electronic component thermal distribution simulation method in the above embodiments can be implemented through... Figure 5 The computer device shown is used to implement this, and the computer device 300 includes at least one processor 301, a communication bus 302, a memory 303, and at least one communication interface 304.

[0067] The processor 301 may be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more devices used to control the execution of the thermal distribution simulation method for electronic components in this application.

[0068] The communication bus 302 is used to transmit information between the aforementioned components.

[0069] Memory 303 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.), magnetic disks or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 303 may exist independently and be connected to processor 301 via communication bus 302. Memory 303 may also be integrated with processor 301.

[0070] The memory 303 stores program code for executing the scheme of this application, and its execution is controlled by the processor 301. The processor 301 executes the program code stored in the memory 303. The program code may include one or more software modules. In the above embodiments, the environmental quality monitoring method can be implemented by the processor 301 and one or more software modules in the program code in the memory 303.

[0071] Communication interface 304 uses any transceiver-like device to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0072] In a specific implementation, as one example, a computer device may include multiple processors, each of which may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0073] The aforementioned computer device can be a general-purpose computer device or a special-purpose computer device. In specific implementations, the computer device may be a desktop computer, a portable computer, a network server, a handheld digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. This application does not limit the type of computer device.

[0074] In addition, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for simulating the thermal distribution of electronic components.

[0075] In summary, the electronic component thermal distribution simulation method and system disclosed in this application collects micro-gap height data and interlayer thermal resistance data between chip layers under different operating conditions when a multi-chip stacked device is working; based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data, a dynamic mapping relationship between micro-gap and interlayer thermal resistance under different operating conditions is obtained; and by combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of the multi-chip stacked device, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model is dynamically assigned, thus obtaining the thermal resistance of the chip layers under different operating conditions. A digital twin dynamic model of interlayer thermal resistance is used; multiple local hotspot regions are divided in the chip layer according to the heat flux density gradient of different spatial units in the digital twin dynamic model; then, the mesh refinement scale of each local hotspot region is generated according to the height distribution of the micro gaps between chip layers for thermal distribution simulation; the digital twin dynamic model is adaptively reconstructed based on the mesh refinement scale; and then, the interlayer thermal distribution simulation report of multi-chip stacked components is generated according to the reconstruction result and a preset thermal distribution threshold; dynamic thermal distribution simulation of multi-chip stacked components can be performed under the coupling effect of interlayer thermal resistance and operating conditions.

[0076] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0077] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for simulating the thermal distribution of electronic components, characterized in that, Includes the following steps: When multi-chip stacked devices are working, collect data on the micro-gap height and interlayer thermal resistance between chip layers under different operating conditions. Based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data, a dynamic mapping relationship between the micro-gap and the interlayer thermal resistance under different operating conditions is obtained by fitting. By combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of multi-chip stacked components, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model is dynamically assigned, resulting in a digital twin dynamic model of the interlayer thermal resistance of chip layers under different operating conditions. Based on the heat flux density gradient of different spatial units in the digital twin dynamic model, multiple local hot spot regions are divided in the chip layer. Then, based on the height distribution of the micro gaps between the chip layers, the mesh refinement scale of each local hot spot region is generated during the heat distribution simulation. Based on the mesh refinement scale, the digital twin dynamic model is adaptively reconstructed, and then an interlayer thermal distribution simulation report of multi-chip stacked components is generated based on the reconstruction results and a preset thermal distribution threshold.

2. The method as described in claim 1, characterized in that, Based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data, the dynamic mapping relationship between the micro-gap and the interlayer thermal resistance under different operating conditions is obtained by fitting, specifically including: Determine the numerical correlation characteristics between the micro-gap height data and the interlayer thermal resistance data; Obtain parameter information for multiple operating conditions of multi-chip stacked components during operation; Based on all parameter information and the numerical correlation characteristics, a mapping simulation is performed to obtain the dynamic mapping relationship between micro-gap and interlayer thermal resistance under different operating conditions.

3. The method as described in claim 1, characterized in that, By combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of multi-chip stacked components, the thermal resistance of different micro-gap height distribution regions in the three-dimensional twin model is dynamically assigned, resulting in a digital twin dynamic model of the interlayer thermal resistance of chip layers under different operating conditions. Specifically, this includes: Based on the height distribution of micro-gap between chip layers in the three-dimensional twin model of multi-chip stacked components, the chip layers in the three-dimensional twin model are divided into regions with different micro-gap height distributions; Based on the dynamic mapping relationship, multiple thermal resistance mapping values ​​of the three-dimensional twin model are determined; By dynamically assigning values ​​to the three-dimensional twin model using all thermal resistance mapping values, a digital twin dynamic model of the interlayer thermal resistance of the chip layer under different operating conditions is obtained.

4. The method as described in claim 1, characterized in that, Based on the heat flux density gradient of different spatial units in the digital twin dynamic model, multiple local hotspot regions are obtained in the chip layer, specifically including: Determine the heat flux density gradient of different spatial units in the digital twin dynamic model; Multiple local hotspot regions are obtained in the chip layer by combining all heat flux density gradients with a preset heat flux threshold.

5. The method as described in claim 1, characterized in that, The mesh refinement scale for each local hot spot region during thermal distribution simulation, based on the height distribution of micro-gaps between chip layers, specifically includes: The micro-gap characteristic value of each local hot spot region is determined based on the height distribution of the micro-gap between chip layers; Preset the scale mapping rules between the mesh scale and the micro-gap between chip layers during thermal distribution simulation; The mesh refinement scale for each local hot spot region is determined based on the scale mapping rule and the micro-gap characteristic value of each local hot spot region during the thermal distribution simulation.

6. The method as described in claim 1, characterized in that, The adaptive mesh reconstruction of the digital twin dynamic model based on the mesh refinement scale specifically includes: Obtain the network topology of the digital twin dynamic model; Based on the aforementioned grid topology, the grid refinement scale of each local hotspot region is spatially matched with the aforementioned digital twin dynamic model; Based on the matching results, the mesh of each local hotspot area is adaptively refined to obtain multiple adaptive mesh elements; The digital twin dynamic model is reconstructed by topologically refactoring all adaptive mesh cells to obtain the reconstructed digital twin dynamic model.

7. The method as described in claim 1, characterized in that, Based on the reconstruction results and a preset thermal distribution threshold, a simulation report on the interlayer thermal distribution of multi-chip stacked components is generated, specifically including: Based on the reconstruction results, interlayer thermal analysis information between chip layers of multi-chip stacked components is generated; Based on a preset thermal distribution threshold, the interlayer thermal analysis information is thermally verified to obtain the thermal characteristic state information between chip layers. A simulation report on the interlayer thermal distribution of multi-chip stacked components is generated based on the thermal characteristic state information.

8. A simulation system for thermal distribution of electronic components, characterized in that, include: The data acquisition module is used to collect micro-gap height data and interlayer thermal resistance data between chip layers under different operating conditions when multi-chip stacked components are working. The processing module is used to fit the dynamic mapping relationship between the micro-gap and the interlayer thermal resistance under different operating conditions based on the numerical correlation characteristics of the micro-gap height data and the interlayer thermal resistance data. The processing module is also used to dynamically assign thermal resistance values ​​to different micro-gap height distribution regions in the three-dimensional twin model by combining the dynamic mapping relationship with the micro-gap height distribution between chip layers in the three-dimensional twin model of multi-chip stacked components, so as to obtain a digital twin dynamic model of interlayer thermal resistance of chip layers under different operating conditions. The processing module is also used to divide multiple local hot spot regions in the chip layer according to the heat flux density gradient of different spatial units in the digital twin dynamic model, and then generate the mesh refinement scale of each local hot spot region during heat distribution simulation based on the height distribution of the micro gaps between chip layers. The execution module is used to perform adaptive mesh reconstruction on the digital twin dynamic model based on the mesh refinement scale, and then generate an interlayer thermal distribution simulation report of multi-chip stacked components based on the reconstruction results and a preset thermal distribution threshold.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the electronic component thermal distribution simulation method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the electronic component thermal distribution simulation method as described in any one of claims 1 to 7.

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