Method and system for establishing crg-agent based on UVM
By using a UVM-based crg-agent construction method, the time-consuming and laborious problem of manually generating clock and reset signals in chip verification was solved, achieving efficient and reliable signal generation and monitoring, and improving the versatility and efficiency of the verification platform.
Patent Information
- Application Number
- CN202511532253.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-02-10
AI Technical Summary
In chip verification, engineers need to manually generate clock and reset signals, resulting in diverse, time-consuming, and labor-intensive implementation methods that lack versatility and efficiency.
A method for building a UVM-based crg-agent is provided. By configuring input parameters, a clock reset interface is generated, signals are dynamically configured and detected, a control reset sequence is generated, and coverage is collected to achieve dynamic transmission and monitoring.
It improves the efficiency and reliability of chip verification platform construction, provides stable clock and reset signals, and has high versatility.
Smart Images
Figure CN121503358A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the chip verification technical field, and in particular to a crg-agent building method and system based on UVM. BACKGROUND
[0002] In the field of chip verification, clock and reset cannot be avoided, and generally, engineers generate the required clock and reset in the verification environment, which results in different implementation methods of various engineers, and the method is repetitive and time-consuming and laborious. Therefore, using UVM to build a general CRG (Clock and Reset Generator) Agent is a significant thing in digital chip verification, which is responsible for providing stable and reliable clock and reset signals for the verification platform.
[0003] Due to the high universality, a comprehensive and powerful crg_agent is very necessary, and good design and packaging can greatly improve the building efficiency and reliability of the verification platform. However, how to have universality? It is necessary to consider whether the agent can meet the needs of most clocks and resets. SUMMARY
[0004] The present application aims at overcoming the deficiencies of the prior art, and provides a crg-agent building method and system based on UVM.
[0005] The purpose of the present application is achieved by the following technical solutions: In a first aspect, the present application discloses a crg-agent building method based on UVM, comprising the following steps: S1, configuring input parameters to generate a clock reset interface; S2, creating a configuration object; S3, dynamically configuring the input parameters to realize dynamic transmission; S4, generating clock and reset signals according to the configuration transmitted in step S3; S5, detecting the clock and reset signals generated in step S4; S6, generating a control reset sequence; S7, collecting coverage.
[0006] Based on the first aspect, the clock reset interface in step S1 comprises: defining clock and reset signals; defining a duty cycle and a maximum clock jitter control variable of the clock; defining a general clock jitter control variable of the clock, and the general clock jitter control variable is less than or equal to the maximum clock jitter control variable. Define a clock frequency switching unit task, which is used to control the clock output by passing frequency and delay parameters; Define a reset generation unit task, which is used to control the timing and width of the reset output by passing delay control parameters; Define a synthesis unit task to control the clock output, reset output timing and width via parameters; Define a clock enable control switch, which is controlled by a 1-bit variable; Set up a clock frequency detection mechanism to record the time at each rising edge of the clock in the always statement, thereby detecting the clock cycle; Set at least 8 clocks generated by dividing the main frequency clock; Set the frequency switching and reset completion flags to raise the corresponding flags after the frequency switching or reset operation is completed; A clock phase control method is configured, which is implemented by reversing the clock phase control method; A control variable that defines the delay size of the clock, used to implement the clock delay; Define a control variable to determine the reset delay, which is used to implement the reset delay. Define a control variable to control the reset time.
[0007] Based on the first aspect, the configuration object mentioned in step S2 specifically includes: creating an initial clock frequency, an initial clock value, an initial reset value, the order in which clock and reset are generated, the minimum and maximum clock frequencies, and whether to generate clock and reset requests by default.
[0008] Based on the first aspect, the dynamic configuration of the input parameters in step S3 includes: Set the control variable to generate a clock or a reset, or to generate both a clock and a reset; Randomly generated clock frequency; Randomly generated clock delay control variables; A randomly generated control variable with a reset delay; The control variable for the randomly generated reset time; The control variable for randomly generated clock phase settings; The control variables are randomly generated clocks and resets, and their order of occurrence is determined by the clock.
[0009] Based on the first aspect, step S4 includes: generating a clock and a reset randomly for the first time according to the content of the configuration object; then obtaining the configuration clock and reset information from the sequence module and generating a clock and a reset randomly.
[0010] Based on the first aspect, step S5 includes: detecting and collecting clock frequency, detecting whether the maximum clock jitter control variable and the general clock jitter control variable meet the settings, and detecting and collecting reset information.
[0011] Based on the first aspect, step S6 includes: Use frequency as a randomly constrained variable passed by the sequence module to change the clock sequence; Use the period as a randomly constrained variable passed by the sequence module to change the clock sequence; Use a random, constrained variable that controls the reset and reset delay to control the sequence that generates the reset; Provide a sequence that can generate both clock and reset functions, and reserve the aforementioned random control variables for user control. It provides the sequence for generating the clock and reset, and reserves variables for the user to control the delay phase.
[0012] Based on the first aspect, step S7 includes: reset coverage, clock coverage, clock and reset phase coverage, and clock and reset cross coverage.
[0013] Secondly, this application also discloses a UVM-based crg-agent building system, which applies the UVM-based crg-agent building method described above, including: a parameter configurator, an interface module, an item module, a driver module, a sequencer module, a sequence module, an agent module, and a function coverage module. The parameter configurator is used to configure input parameters; The Interface module is used to define the interface for clock and reset signals based on input parameters; The Item module is used to implement dynamic configuration and dynamic transmission; The driver module is used to generate clock and reset signals according to the configuration. The sequencer module is used to control the generation of the reset sequence; The sequence module is used to generate the operation sequence for clock reset; The agent module is used to connect to various UVM components and interfaces; The Function coverage module is used to collect coverage data.
[0014] Based on the second aspect, it also includes a Monitor module, which is used to monitor the status of the clock and reset signals.
[0015] The beneficial effects of this invention are: 1) This application provides a stable and reliable clock and reset signal for the verification platform. Due to the highly versatile crg_agent, it greatly improves the efficiency and reliability of the verification platform construction. Attached Figure Description
[0016] Figure 1 This is a schematic diagram illustrating the steps of the UVM-based crg-agent construction method according to an embodiment of the present invention. Detailed Implementation
[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] This application provides a UVM-based crg-agent construction method and system to solve the problem of engineers repeatedly generating their own clocks and resets in the prior art, which is time-consuming and laborious. Here, the specific terms used in this application are explained: UVM (Universal Verification Methodology) is a standardized verification methodology based on SystemVerilog, specifically designed for digital circuit verification. It provides a reusable and scalable verification framework to help engineers efficiently build verification environments for complex chips (such as SoCs, ASICs, and FPGAs). A UVM Agent is a modular, configurable, and reusable verification component unit that encapsulates driver, monitor, and sequencer functions, specifically responsible for interacting with a specific interface of the DUT. It is the foundation for building a modular, reusable UVM test platform, greatly improving verification efficiency and code reusability. By configuring its working mode (Active / Passive), the Agent can flexibly adapt to different verification needs (active stimulus generation or passive monitoring). CRG (Clock and Reset Generator) represents the clock and reset generator. `crg_agent` represents an agent implemented using UVM, whose function is to generate clocks and reset. `DUT` (Design Under Test) represents the design to be tested. `Component` in UVM refers to the base class that constitutes the hierarchical structure of the UVM test platform, inheriting from the `uvm_component` class. UVM components are the basic building blocks of the test platform, possessing lifecycle management (through a phase mechanism), hierarchical configuration, and reporting functions. Common components include agent, driver, and monitor. Components cannot dump waveforms. `Interface` is a native concept in the SystemVerilog language, used to encapsulate a collection of hardware signals (such as bus signals and control signals). It acts as a physical connection bridge between the DUT and the verification environment, serving as the medium for interaction between UVM components (such as Driver and Monitor) and hardware signals. Interfaces can dump waveforms. `Function coverage` represents the functional coverage rate. In this application, "Debug" refers to the process of debugging during simulation, analyzing the location of problems, and identifying the causes of problems. A schematic diagram of the steps of the method is shown below. Figure 1 As shown, the specific steps include: S1. Configure input parameters and generate clock reset interface; S2. Create a configuration object; S3. Dynamically configure input parameters to achieve dynamic transmission; S4. Generate a clock and reset signal according to the configuration transmitted in step S3; S5. Detect the clock and reset signals generated in step S4; S6. Generate a control reset sequence; S7, Collection Coverage.
[0019] Specifically, the clock reset interface mentioned in step S1 includes: Define the clock and reset signals; Define the clock duty cycle and the maximum clock jitter control variables; Define a general clock jitter control variable for the clock, wherein the general clock jitter control variable is less than or equal to the maximum clock jitter control variable; clock jitter refers to the time deviation between the actual edge (rising edge or falling edge) of the clock signal and the ideal clock edge. Define a clock frequency switching unit task, which is used to control the clock output by passing frequency and delay parameters; Define a reset generation unit task, which is used to control the timing and width of the reset output by passing delay control parameters; Define a synthesis unit task to control the clock output and the timing and width of the reset output through parameters; the synthesis unit task has the functions of a clock frequency switching unit task and a reset generation unit task. Define a clock enable control switch, which is controlled by a 1-bit variable; Set up a clock frequency detection mechanism to record the time at each rising edge of the clock in the always statement, thereby detecting the clock cycle; Set at least 8 clocks generated by dividing the main frequency clock; Set the frequency switching and reset completion flags to raise the corresponding flags after the frequency switching or reset operation is completed; A clock phase control method is configured, which is implemented by reversing the clock phase control method; A control variable that defines the delay size of the clock, used to implement the clock delay; Define a control variable to determine the reset delay, which is used to implement the reset delay. Define a control variable to control the reset time.
[0020] Specifically, the configuration object mentioned in step S2 includes: Creates the initial clock frequency, which users can use to control the initial clock frequency.
[0021] Create an initial value for the clock (which has random values such as 0, 1, z, x, etc.), and the user can control the initial value of the clock through the created initial value; Create a reset initial value (which has random values such as 0, 1, z, x, etc.), and the user can control the initial value of the reset through the created reset initial value; The order in which the clock and reset are generated can be controlled by the user to determine whether the clock or reset is generated first. Create the minimum and maximum frequencies of the clock, which users can use to control the range of frequencies randomly generated by the clock; Create a request to determine whether to generate a clock and reset by default. Users can use this to control whether a clock and reset are required by default.
[0022] Specifically, the dynamic configuration of the input parameters in step S3 includes: Set the control variable to generate a clock or a reset, or to generate both a clock and a reset; Randomly generated clock frequency; Randomly generated clock delay control variables; A randomly generated control variable with a reset delay; The control variable for the randomly generated reset time; The control variable for randomly generated clock phase settings; The control variables are randomly generated clocks and resets, and their order of occurrence is determined by the clock.
[0023] Specifically, step S4 includes: generating a clock and reset randomly for the first time based on the content of the configuration object; then obtaining the configuration clock and reset information from the sequence module and generating a clock and reset randomly.
[0024] Specifically, step S5 includes: detecting and collecting clock frequency, detecting whether the maximum clock jitter control variable and the general clock jitter control variable meet the settings, and detecting and collecting reset information.
[0025] Specifically, step S6 includes: Use frequency as a randomly constrained variable passed by the sequence module to change the clock sequence; Use the period as a randomly constrained variable passed by the sequence module to change the clock sequence; Use a random, constrained variable that controls the reset and reset delay to control the sequence that generates the reset; Provide a sequence that can generate both clock and reset functions, and reserve the aforementioned random control variables for user control. It provides the sequence for generating the clock and reset, and reserves variables for the user to control the delay phase.
[0026] Specifically, step S7 includes: reset coverage, clock coverage, clock and reset phase coverage, and clock and reset cross coverage.
[0027] Secondly, this application also discloses a UVM-based crg-agent building system, which applies the UVM-based crg-agent building method described above, including: a parameter configurator (Config Object), an Interface module, an Item module, a driver module, a sequencer module, a sequence module, an agent module, and a Functioncoverage module; The parameter configurator (Config Object) is used to configure input parameters; for example, clock frequency, reset duration, synchronous / asynchronous reset, etc. The Interface module is used to define the interface for clock and reset signals based on input parameters; The Item module is used to implement dynamic configuration and dynamic transmission; it is a data transmission object that carries the "commands" that the verification platform intends to configure the clock and reset generation modules of the DUT; it is the foundation for realizing dynamic, automatic, and comprehensive verification of the chip clock reset system, and by abstracting the configuration parameters, it greatly enhances the flexibility of testing and the reusability of the verification platform. The driver module is used to generate clock and reset signals according to the configuration. The sequencer module is used to control the generation of the reset sequence; The sequence module is used to generate the operation sequence for clock reset; The agent module is used to connect various UVM components and interfaces, etc. The Function coverage module is used to collect coverage parameters such as frequency, reset, and configuration.
[0028] It also includes a Monitor module, which monitors the status of the clock and reset signals. Because the CRGAgent function is relatively fixed, it is usually designed as a Passive Agent, meaning it only includes a Monitor and not a Driver or Sequencer, or its Driver function is highly standardized. However, the concept of its modes (Active / Passive) still applies. Active Mode: The Agent actively drives the clock and reset signals to the DUT. This is the most commonly used mode for CRG Agents. Passive Mode: The Agent only monitors the existing clock and reset signals, typically used in subsystems or for inspection.
[0029] The UVM-based crg-agent construction method and system disclosed in this application are characterized by flexibility in system configuration: the CRG configuration class is parameterized as much as possible, supporting multiple clock domains, variable phase relationships (such as 90-degree offset), randomized reset triggering, and waveform control (duty cycle). Frequency switching reset is also flexible: both the interface and sequence can set the clock and reset. It also uses uvm_config_db: this is the recommended method for setting virtual interfaces and configuration parameters. It is more flexible than the older set_config_int method and avoids deprecation warnings. Sequence control: for more complex scenarios, simple sequences can be written to dynamically control the assertion and release timing of the reset signal, rather than relying solely on a fixed loop in the driver. It has monitoring and checking functions: even in Active mode, the Monitor is useful. It can automatically check clock stability (such as jitter, whether the frequency is within the expected range), whether the pulse width of the reset signal conforms to specifications, etc. For agents like CRGs that typically only generate a simple transaction, their sequencer may not need a complex sequence mechanism; sometimes, signal generation can even be completed directly in the driver. However, if you want more flexible control over the reset sequence, using a Sequencer is a better choice.
[0030] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for building a crg-agent based on UVM, characterized in that, Includes the following steps: S1. Configure input parameters and generate clock reset interface; S2. Create a configuration object; S3. Dynamically configure input parameters to achieve dynamic transmission; S4. Generate a clock and reset signal according to the configuration transmitted in step S3; S5. Detect the clock and reset signals generated in step S4; S6. Generate a control reset sequence; S7, Collection Coverage.
2. The UVM-based crg-agent construction method according to claim 1, characterized in that, The clock reset interface mentioned in step S1 includes: Define the clock and reset signals; Define the clock duty cycle and maximum clock jitter control variables; Define a general clock jitter control variable for the clock, wherein the general clock jitter control variable is less than or equal to the maximum clock jitter control variable; Define a clock frequency switching unit task, which is used to control the clock output by passing frequency and delay parameters; Define a reset generation unit task, which is used to control the timing and width of the reset output by passing delay control parameters; Define a synthesis unit task to control the clock output, reset output timing and width via parameters; Define a clock enable control switch, which is controlled by a 1-bit variable; Set up a clock frequency detection mechanism to record the time at each rising edge of the clock in the always statement, thereby detecting the clock cycle; Set at least 8 clocks generated by dividing the main frequency clock; Set the frequency switching and reset completion flags to raise the corresponding flags after the frequency switching or reset operation is completed; A clock phase control method is configured, which is implemented by reversing the clock phase control method; A control variable that defines the delay size of the clock, used to implement the clock delay; Define a control variable to determine the reset delay, which is used to implement the reset delay. Define a control variable to control the reset time.
3. The UVM-based crg-agent construction method according to claim 2, characterized in that, The configuration objects mentioned in step S2 specifically include: initial clock frequency, initial clock value, initial reset value, order of clock and reset generation, minimum and maximum clock frequency, and whether to generate clock and reset requests by default.
4. The UVM-based crg-agent construction method according to claim 3, characterized in that, The dynamic configuration of input parameters in step S3 includes: Set the control variable to generate a clock or a reset, or to generate both a clock and a reset; Randomly generated clock frequency; Randomly generated clock delay control variables; A randomly generated control variable with a reset delay; The control variable for the randomly generated reset time; The control variable for randomly generated clock phase settings; The control variables are randomly generated clocks and resets, and their order of occurrence is determined by the clock.
5. The UVM-based crg-agent construction method according to claim 4, characterized in that, Step S4 includes: generating a clock and reset randomly for the first time based on the content of the configuration object; then obtaining the configuration clock and reset information from the sequence module and generating a clock and reset randomly.
6. The UVM-based crg-agent construction method according to claim 5, characterized in that, Step S5 includes: detecting and collecting clock frequency, detecting whether the maximum clock jitter control variable and the general clock jitter control variable meet the settings, and detecting and collecting reset information.
7. The UVM-based crg-agent construction method according to claim 6, characterized in that, Step S6 includes: Use frequency as a randomly constrained variable passed by the sequence module to change the clock sequence; Use the period as a randomly constrained variable passed by the sequence module to change the clock sequence; Use a random, constrained variable that controls the reset and reset delay to control the sequence that generates the reset; Provide a sequence that can generate both clock and reset functions, and reserve the aforementioned random control variables for user control. It provides the sequence for generating the clock and reset, and reserves variables for the user to control the delay phase.
8. The UVM-based crg-agent construction method according to claim 7, characterized in that: Step S7 includes: reset coverage, clock coverage, clock and reset phase coverage, and clock and reset cross coverage.
9. A UVM-based crg-agent construction system, employing the UVM-based crg-agent construction method according to any one of claims 1-8, characterized in that, include: The module includes a parameter configurator, an interface module, an item module, a driver module, a sequencer module, a sequence module, an agent module, and a function coverage module. The parameter configurator is used to configure input parameters; The Interface module is used to define the interface for clock and reset signals based on input parameters; The Item module is used to implement dynamic configuration and dynamic transmission; The driver module is used to generate clock and reset signals according to the configuration. The sequencer module is used to control the generation of the reset sequence; The sequence module is used to generate the operation sequence for clock reset; The agent module is used to connect to various UVM components and interfaces; The Function coverage module is used to collect coverage data.
10. The UVM-based crg-agent construction system according to claim 9, characterized in that: It also includes a Monitor module, which is used to monitor the status of the clock and reset signals.