Generation method and device of gating unit and medium

Abstract

The invention discloses a gate control unit generation method and device and a medium, and relates to the technical field of electronic design automation. A first connection relation of boundary ports of the first gate control unit under the general library logic unit structure, and a second connection relation of ports between a latch and an AND gate unit in the first gate control unit under the general library logic unit structure. A first mapping relation between pin signals of respective corresponding gating units under the standard library unit structure and the general library logic unit structure is established in advance. And creating a second gating unit of the standard library unit structure according to the first connection relationship, the second connection relationship and the first mapping relationship to complete the generation process of the gating unit. And replacement from a general library logic unit structure to a specific standard library unit structure is realized. Integration is achieved through the corresponding spliced gating units before optimization, the clock network power consumption is reduced, meanwhile, the burr phenomenon caused by timing sequence mismatch caused by spliced clock gating is avoided, and the design correctness is improved.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, and in particular to a method, apparatus and medium for generating gated units. Background Technology

[0002] In digital circuit design, integrated clock gating is used to control the clock's toggle frequency and reduce dynamic power consumption. It involves adding a control terminal to control the clock signal output; when the control terminal is 0, the clock signal remains stable and does not toggle, thus reducing dynamic power consumption. This can be implemented in code, which is an abstract description of digital logic functionality. If users simply use generic logic from standard libraries to cobble together clock gating units, it becomes difficult for the libraries to meet low-power design requirements, and timing mismatches can introduce glitches, posing potential functional risks and reducing the correctness of the design.

[0003] Therefore, how to integrate clock gating units to meet low-power design requirements and avoid risks while improving design accuracy is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a method, apparatus, and medium for generating gated units to solve the problem that clock gated units pieced together from general logic are difficult to meet low-power design requirements, and that timing mismatches cause glitches, which pose potential functional risks and reduce the correctness of the design.

[0005] To address the aforementioned technical problems, this application provides a method for generating a gating unit, comprising:

[0006] Receive the first instruction from the synthesis tool and parse it to obtain the first connection relationship of the boundary port of the first gate unit under the general library logic unit structure;

[0007] Receive the second instruction from the synthesis tool and parse it to obtain the second connection relationship between the latches in the first gate unit and the ports between the AND gate units under the general library logic unit structure;

[0008] A first mapping relationship is pre-established between the pin signals of the corresponding gate units under the standard library unit structure and the general library logic unit structure;

[0009] The second gating unit of the standard library unit structure is created based on the first connection relationship, the second connection relationship, and the first mapping relationship to complete the generation process of the gating unit.

[0010] On the one hand, the process of determining the first connection relationship includes:

[0011] The current operational hierarchy of the hierarchical structure is determined according to the first instruction;

[0012] In the current operation hierarchy, the first sub-operation instruction is received to obtain the port signal of the target first gate control unit;

[0013] The first connection relationship of the boundary port of the target first gating unit is obtained based on the port signal.

[0014] On the other hand, the second instruction includes a second sub-operation instruction, a third sub-operation instruction, and a fourth sub-operation instruction, and the process of determining the second connection relationship includes:

[0015] The first latch is obtained by parsing the second sub-operation instruction;

[0016] The first AND gate is obtained by parsing the third sub-operation instruction;

[0017] The second connection relationship between the first latch and the first AND gate is obtained by parsing the fourth sub-operation instruction.

[0018] On the other hand, a first mapping relationship is pre-established between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure, including:

[0019] Establish a mapping between the clock input pin signal of the gated unit under the standard library unit structure and the clock enable pin signal of the gated unit under the general library logic unit structure;

[0020] Establish a mapping between the gate enable pin signal of the gate unit under the standard library unit structure and the enable pin signal of the gate unit under the general library logic unit structure;

[0021] Establish a mapping between the test enable pin signal of the gated unit under the standard library unit structure and the scan enable pin signal of the gated unit under the general library logic unit structure;

[0022] The output pin signals of the gated unit under the standard library unit structure are mapped to the gated clock output pin signals of the gated unit under the general library logic unit structure to complete the establishment of the first mapping relationship.

[0023] On the other hand, the second gating unit that creates the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship includes:

[0024] The connection relationship corresponding to the data input pin signal of the first latch is obtained according to the second connection relationship;

[0025] Determine whether the connection relationship corresponding to the data input pin signal of the first latch is the same as the first connection relationship of the boundary port of the target first gate control unit;

[0026] If they are the same, it is determined that the general library logic unit structure does not have an OR gate unit; a preset gated unit under the standard library unit structure is obtained; the gate enable pin signal of the preset gated unit is connected to the enable pin signal of the first latch; the scan enable pin signal of the preset gated unit is in an unconnected state; and the scan enable pin signal of the preset gated unit is assigned a value of 0; the first connection relationship and the second connection relationship under the general library logic unit structure are disconnected; the preset gated unit after assignment is processed according to the first mapping relationship to generate the second gated unit;

[0027] If they are different, add the first OR gate unit under the general library logic unit structure; create the second OR gate unit of the standard library unit structure according to the connection relationship of the first OR gate unit, and use it in combination with the second gate unit to generate the final gate unit.

[0028] On the other hand, a second OR gate unit of the standard library unit structure is created based on the connection relationship of the first OR gate unit, including:

[0029] Receive the third instruction from the integrated tool;

[0030] The third connection relationship of the first OR gate unit under the general library logic unit structure is obtained by parsing the third instruction.

[0031] A second mapping relationship is pre-established between the pin signals of the corresponding OR gate units under the standard library unit structure and the general library logic unit structure;

[0032] The second OR gate unit of the standard library unit structure is created based on the second mapping relationship and the third connection relationship.

[0033] On the other hand, after generating the second gating unit, it also includes:

[0034] Receive the fourth instruction from the integrated tool;

[0035] The fourth connection relationship of the first NOT gate unit under the general library logic unit structure is obtained by parsing the fourth instruction.

[0036] A third mapping relationship is pre-established between the pin signals of the corresponding NOT gate units under the standard library unit structure and the general library logic unit structure;

[0037] Based on the third mapping relationship and the fourth connection relationship, a second NOT gate unit of the standard library unit structure is created and used in conjunction with the second gating unit to generate the final gating unit.

[0038] To address the aforementioned technical problems, this application also provides a gating unit generation apparatus, comprising:

[0039] The first parsing module is used to receive the first instruction from the synthesis tool and parse the first connection relationship of the boundary port of the first gate unit under the general library logic unit structure.

[0040] The second parsing module is used to receive the second instruction from the synthesis tool and parse the second connection relationship between the latches in the first gate unit and the ports between the AND gate units under the general library logic unit structure.

[0041] A module is established to pre-establish a first mapping relationship between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure.

[0042] A creation module is used to create a second gating unit of the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship, so as to complete the generation process of the gating unit.

[0043] To address the aforementioned technical problems, this application also provides a gating unit generation device, comprising:

[0044] Memory, used to store computer programs;

[0045] A processor, used to implement the steps of the gating unit generation method as described above when executing the computer program.

[0046] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the gating unit generation method described above.

[0047] The beneficial effect of this application lies in providing a method for generating gated units. First, it receives a first instruction from the synthesis tool and parses the first connection relationship of the boundary ports of the first gated unit under the general library logic unit structure. Then, it receives a second instruction from the synthesis tool and parses the second connection relationship between the latches and gate units within the first gated unit under the general library logic unit structure. This serves as a reference for subsequent replacement with standard library units, ensuring the correct connection relationship of the gated unit after synthesis optimization. Second, it pre-establishes a first mapping relationship between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure. This mapping relationship between the pins of the gated units before and after synthesis optimization serves as a bridge. Finally, it creates a second gated unit of the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship, thus completing the gated unit generation process. Following the boundary signal connection relationship of the general library logic unit structure (before synthesis optimization), it connects the corresponding ports of the standard library unit structure (after synthesis optimization) to the design, thereby enabling the replacement of the logic unit of the gated unit from the general library logic unit structure to the specific standard library unit structure. This application achieves integration by piecing together corresponding gated units before optimization. This reduces clock network power consumption and avoids glitches caused by timing mismatches due to piecing together clock gating, mitigating potential risks and improving design correctness. Furthermore, conventional solutions for updating and iterating general-purpose library logic unit structures primarily use device names for code setting and synthesis optimization. However, changes in manufacturer names for their process libraries lead to synchronized code changes and re-verification to ensure functionality remains unchanged, requiring repeated verification throughout the process. This application primarily refers to device types and performs synthesis optimization based on the boundary signal connection relationships of the general-purpose library logic unit structure (before synthesis optimization). This avoids redundant verification work through direct instantiation in the code, saving design costs and improving code reusability.

[0048] Secondly, by obtaining the hierarchical structure units, the first connection relationship of the boundary ports of the target first gate unit is determined. The graphical connection presentation can quickly identify problems such as incorrect or missing port connections, avoiding subsequent synthesis or simulation failures due to logic connection deviations, and significantly reducing design rework costs. It helps users clarify the signal flow and connection requirements between the trigger and surrounding devices, avoiding routing detours or conflicts due to unreasonable port placement planning during layout. The connection relationship between latches and AND gate units is obtained through various operation commands of the synthesis tool, facilitating verification of whether the physical implementation of the clock gating logic conforms to the design intent, and enabling rapid location of timing and power consumption issues. The first mapping relationship between the pin signals of the corresponding gate units under the standard library unit structure and the general library logic unit structure is established, breaking down interface barriers between different libraries and achieving cross-library compatibility, automated tool flow, and consistency between logic and physical implementation. Seamless migration and design reuse from general libraries to standard libraries are achieved. The automation level of the front-end to back-end process is greatly improved, reducing the error rate of manual intervention and shortening the design cycle. The creation process of the second gating unit is clearly defined, with each type corresponding to a unique logical function and physical implementation, avoiding functional ambiguity. Fixed boundary ports and connection relationships make signal transmission paths predictable, enabling rapid calculation of parameters such as delay and crosstalk during timing analysis, avoiding excessive complexity in timing verification due to uncertain ports or connections. In the physical verification stage, standardized connection relationships can quickly match design rules, such as port spacing and wiring width, reducing physical violations. In addition, in scenarios where OR gates are used, no additional latches or AND gate units are needed; multiple enabled OR logic control can be achieved through a single OR gate unit, simplifying the circuit structure while ensuring that all enable signals are latched without glitches.

[0049] In addition, this application also provides a gating unit generation apparatus, device and medium, which have the same beneficial effects as the gating unit generation method described above. Attached Figure Description

[0050] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A flowchart illustrating a method for generating a gating unit as provided in an embodiment of this application;

[0052] Figure 2 A port diagram of a gating unit under a general library logic unit structure provided in an embodiment of this application;

[0053] Figure 3 A port diagram of a gated unit under a standard library unit structure provided in this application embodiment;

[0054] Figure 4 A flowchart illustrating another method for generating a gating unit provided in an embodiment of this application;

[0055] Figure 5 A structural diagram of a gating unit generation device provided in an embodiment of this application;

[0056] Figure 6 This is a structural diagram of a gating unit generation device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0058] The core of this application is to provide a method, apparatus, and medium for generating gated units, in order to solve the problem that clock gated units pieced together from general logic are difficult to meet the requirements of low-power design, and that timing mismatches cause glitches, which pose potential functional risks and reduce the correctness of the design.

[0059] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] With the rapid development of modern integrated circuits, circuit designs are becoming increasingly large-scale, leading to a greater demand for Electronic Design Automation (EDA) tools. Logic synthesis, as a part of EDA technology, serves as a bridge between high-level abstract design and physical implementation, converting high-level hardware description languages ​​into gate-level netlists. It is an indispensable step in the digital circuit design process. Integrated circuit designers typically use Hardware Description Languages ​​(HDLs) to describe the high-level abstraction of circuits (usually data and behavior at the register transfer level of digital circuits) to represent the logical functions of digital circuits. This avoids studying extremely complex circuit layout and interconnection issues from the outset, allowing designers to focus more on functional design. After the design is completed, the circuit needs to be converted from a high-level abstract description to a logic gate-level circuit connection netlist. During this process, the logic function must be optimized to meet various constraints; this process is called logic synthesis.

[0061] Most current synthesis tools convert the design into a Boolean network format representing nodes with the same functionality before performing synthesis and optimization. Before synthesis, all logic units are represented as generic library logic units, i.e., a general, technology-independent logic unit or module. While this makes the algorithms used during synthesis more versatile, optimization of the network during synthesis can lead to structural deviations. For circuits with specific structures, optimization can disrupt the structure and fail to yield ideal results. Therefore, in design, it is often necessary to include specific logic units in the circuit and manually instantiate them as units from a standard technology library to meet functional requirements.

[0062] Integrated clock gating cells are used to control the clock's toggle frequency to reduce dynamic power consumption. An integrated clock gating cell controls the clock signal output by adding a control terminal (EN terminal). When the EN signal is 0, the clock signal remains stable and does not toggle, thus reducing dynamic power consumption. A clock gating cell can be implemented in code, typically described as a latch and an AND gate. Code describes functionality through logical operators and cannot express physical-level details. A key risk of clock gating is that changes in the gating signal can cause glitches in the clock output, especially when the timing of the latch and AND gate is mismatched. Integrated clock gating cells eliminate clock glitches, and the internal path delay is verified through process technology to ensure that glitches do not propagate to the output clock. Additionally, for high-load clock networks, it reduces clock network latency and power consumption. If there is currently no integrated clock gating unit, the use of general-purpose logic patchwork cannot meet the requirements of low-power design. It may even lead to timing mismatches and glitches due to process variations, temperature and voltage changes. Furthermore, the lack of verified integrated units introduces potential functional risks into designs based on this library, reducing design correctness. The gating unit generation method provided in this application can solve the above-mentioned technical problems.

[0063] Figure 1 A flowchart illustrating a method for generating a gating unit provided in this application embodiment is shown below. Figure 1 As shown, the method includes:

[0064] S11: Receive the first instruction from the synthesis tool and parse it to obtain the first connection relationship of the boundary port of the first gate unit under the general library logic unit structure;

[0065] S12: Receive the second instruction from the synthesis tool and parse it to obtain the second connection relationship between the latches in the first gate unit and the ports between the AND gate units under the general library logic unit structure;

[0066] S13: Pre-establish the first mapping relationship between the pin signals of the corresponding gate units under the standard library unit structure and the general library logic unit structure;

[0067] S14: Create a second gated unit of the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship to complete the generation process of the gated unit.

[0068] Specifically, based on the provided list of required logic units, these logic units may not be individual instances (cells), but rather small, instantiated concrete units (modules) with specific functions. These modules can be obtained using the `get_designs` command of the synthesis tool. Now, let's take one of these modules as an example. Let this module be A. During the mapping phase of logic synthesis, A will be transformed into a hierarchy cell composed of general library logic units.

[0069] Use `get_cells-hier-filter "ref_name=~*A*"` to retrieve the hierarchy cell. The graphical interface of the synthesis tool will display the circuit diagram and connections of this hierarchy cell. Since all generic library logic units within this hierarchy cell will be replaced with standard library units while their external connections remain unchanged, it's crucial to focus on the boundary port connections of this hierarchy cell. These ports need to be reconnected to the correct locations after the replacement. Iterate through all cells within this hierarchy to obtain their port connections, serving as a reference for connecting the replaced standard library units.

[0070] Upon receiving the first instruction from the synthesis tool, the system parses the first connection relationship corresponding to the boundary port of the first gated unit under the general library logic unit structure. Here, the boundary port refers to the actual signal of the port of a specific logic module (unit) extracted during EDA physical design (such as after placement and routing), clarifying the signal source, destination, and electrical characteristics to provide a basis for subsequent verification or optimization. The connection relationship refers to the specific connection information between which ports are involved between other devices in this trigger domain.

[0071] In step S12, the second instruction from the synthesis tool is received, and the second connection relationship between the latches and AND gates within the first gating unit of the general-purpose library logic unit structure is obtained through parsing. It should be noted that the core structure of the clock gating unit consists of latches and AND gates, determined by its core function of suppressing clock flips and the reliability requirement of avoiding glitches. When the enable signal is invalid, the clock (clk) output is cut off, stopping downstream register flips to reduce power consumption. The AND gate physically cuts off the clock, while the latch eliminates glitches and ensures timing safety. The second connection relationship corresponds to the port connections between the latches and AND gates.

[0072] In step S13, a first mapping relationship is pre-established between the pin signals of the corresponding gated units under the standard library cell structure and the general library logic cell structure. The standard library cell structure mostly corresponds to fixed standardized cells in semi-custom designs such as application-specific integrated circuits (ASICs), while the general library logic cell structure is commonly found in the flexible macrocell structure of programmable devices such as generic array logic (GAL). The pin signal mapping schemes for flip-flops differ significantly between the two, and they are adapted to different circuit design requirements. Here, a first mapping relationship is established between their pin signals to make subsequent adaptation flexible.

[0073] In step S14, a second gated unit of the standard library unit structure is created based on the first connection relationship, the second connection relationship, and the first mapping relationship. Here, the substitution between the standard library unit structure and the general library logic unit structure can be realized based on the different mapping relationships of the pin signals. The first connection relationship and the second connection relationship can ensure that the gated unit under the created standard library unit structure is fully matched with external devices, and the connection relationship between the latches and AND gate units inside the gated unit.

[0074] The beneficial effect of this application embodiment lies in providing a method for generating gated units. First, it receives a first instruction from a synthesis tool and parses the first connection relationship of the boundary ports of the first gated unit under the general library logic unit structure. Then, it receives a second instruction from the synthesis tool and parses the second connection relationship between the latches and gate units within the first gated unit under the general library logic unit structure, providing a reference for subsequent replacement with standard library units, ensuring the correct connection relationship of the gated unit after synthesis optimization. Second, it pre-establishes a first mapping relationship between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure, building a bridge between the pins of the gated units before and after synthesis optimization. Finally, it creates a second gated unit of the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship, thus completing the gated unit generation process. The ports corresponding to the standard library unit structure (after synthesis optimization) are connected to the design according to the boundary signal connection relationship of the general library logic unit structure (before synthesis optimization), thereby realizing the replacement of the logic unit of the gated unit from the general library logic unit structure to the specific standard library unit structure. This application achieves integration by piecing together corresponding gated units before optimization. This reduces clock network power consumption and avoids glitches caused by timing mismatches due to piecing together clock gating, mitigating potential risks and improving design correctness. Furthermore, conventional solutions for updating and iterating general-purpose library logic unit structures primarily use device names for code setting and synthesis optimization. However, changes in manufacturer names for their process libraries lead to synchronized code changes and re-verification to ensure functionality remains unchanged, requiring repeated verification throughout the process. This application primarily refers to device types and performs synthesis optimization based on the boundary signal connection relationships of the general-purpose library logic unit structure (before synthesis optimization). This avoids redundant verification work through direct instantiation in the code, saving design costs and improving code reusability.

[0075] In some embodiments, the process of determining the first connection relationship includes:

[0076] The current operational hierarchy of the hierarchical structure is determined based on the first instruction;

[0077] In the current operation hierarchy, the first sub-operation instruction is received to obtain the port signal of the target first gate control unit;

[0078] The first connection relationship of the boundary port of the first gating unit of the target is obtained based on the port signal.

[0079] Specifically, the current operational hierarchy of the hierarchical structure is determined based on the first instruction (current_design). Within this hierarchy, the first sub-operation instruction (get_ports) is received to acquire the port signals of the target first gating unit. Generally, the port signal and the connected connection information (net) have the same name. The acquired port signal name is also the name of the connected connection information. Therefore, the first connection relationship of the boundary ports of the target first gating unit is determined based on the port signal, providing an important reference for subsequent comprehensive optimization.

[0080] This embodiment provides a method to determine the first connection relationship of the boundary ports of the target first gate unit by obtaining the hierarchical structure unit. The graphical connection presentation can quickly identify problems such as incorrect or missing port connections, avoiding subsequent synthesis or simulation failures due to logic connection deviations, and significantly reducing design rework costs. It helps users clarify the signal flow and connection requirements between the trigger and surrounding devices, avoiding detours or conflicts in wiring due to unreasonable port location planning during layout.

[0081] In some embodiments, the second instruction includes a second sub-operation instruction, a third sub-operation instruction, and a fourth sub-operation instruction, and the process of determining the second connection relationship includes:

[0082] The first latch is obtained by parsing the second sub-operation instruction;

[0083] The first AND gate is obtained by parsing the third sub-operation instruction;

[0084] The second connection relationship between the first latch and the first AND gate is obtained by parsing the fourth sub-operation instruction.

[0085] Specifically, the first latch is obtained using the second sub-operation instruction of the synthesis tool (get_attribute[get_cells*]is_sequential). If the return value is true, it indicates that the cell is a latch. The first AND gate is obtained using the third sub-operation instruction of the synthesis tool (get_cells –filter “ref_name==GTECH_AND2”), and the return value is the corresponding AND gate cell. The second connection relationship between the first latch and the first AND gate is obtained according to the fourth sub-operation instruction, that is, the second connection relationship between the first latch and the first AND gate is obtained using the fourth sub-operation instruction (all_connected).

[0086] This embodiment provides the ability to obtain the connection relationship between latches and AND gate units through the operation instructions of the synthesis tool, so as to verify whether the connection of the physical implementation of the clock gating logic conforms to the design intent and can quickly locate timing and power consumption problems.

[0087] In some embodiments, a first mapping relationship is pre-established between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure, including:

[0088] Establish a mapping between the clock input pin signal of the gated unit under the standard library unit structure and the clock enable pin signal of the gated unit under the general library logic unit structure;

[0089] Establish a mapping between the gate enable pin signal of the gate unit under the standard library unit structure and the enable pin signal of the gate unit under the general library logic unit structure;

[0090] Establish a mapping between the test enable pin signal of the gated unit under the standard library unit structure and the scan enable pin signal of the gated unit under the general library logic unit structure;

[0091] The output pin signals of the gated unit under the standard library unit structure are mapped to the gated clock output pin signals of the gated unit under the general library logic unit structure to complete the establishment of the first mapping relationship.

[0092] Specifically, Figure 2 This application provides a schematic diagram of the port of a gating unit under a general library logic unit structure, as shown in the embodiments of this application. Figure 2 As shown, this includes the connection between the latch and the door. Figure 3 A port diagram of a gating unit under a standard library unit structure provided in this application embodiment is shown below. Figure 3 As shown, the established mapping relationships ensure the correct connection of the replaced standard library units. A mapping is established between the clock input pin (CP pin) of the gated unit under the standard library unit structure and the clock enable pin (clock) of the gated unit under the general library logic unit structure; a mapping is established between the gate enable pin (E pin) of the gated unit under the standard library unit structure and the enable pin (enable) of the gated unit under the general library logic unit structure; a mapping is established between the test enable pin (TE pin) of the gated unit under the standard library unit structure and the scan enable pin (scan_enable) of the gated unit under the general library logic unit structure; and a mapping is established between the output pin (Q pin) of the gated unit under the standard library unit structure and the gated clock output pin (Gated Clock) of the gated unit under the general library logic unit structure.

[0093] This embodiment establishes a first mapping relationship between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure, breaking down interface barriers between different libraries and achieving cross-library compatibility, automated tool flow, and consistency between logic and physical implementation. It enables seamless migration and design reuse from general libraries to standard libraries. The automation level of the front-end to back-end process is significantly improved, reducing the error rate of manual intervention and shortening the design cycle.

[0094] In some embodiments, a second gating unit for creating a standard library unit structure based on a first connection relationship, a second connection relationship, and a first mapping relationship includes:

[0095] The connection relationship corresponding to the data input pin signal of the first latch is obtained according to the second connection relationship;

[0096] Determine whether the connection relationship corresponding to the data input pin signal of the first latch is the same as the first connection relationship of the boundary port of the target first gate control unit;

[0097] If they are the same, determine that the general library logic unit structure does not have an OR gate unit; obtain the preset gate unit under the standard library unit structure; connect the gate enable pin signal of the preset gate unit to the enable pin signal of the first latch; set the scan enable pin signal of the preset gate unit to be in an unconnected state; and assign the scan enable pin signal of the preset gate unit to 0; disconnect the first connection relationship and the second connection relationship under the general library logic unit structure; process the assigned preset gate unit according to the first mapping relationship to generate the second gate unit;

[0098] If they are different, add the first OR gate unit under the general library logic unit structure; create the second OR gate unit of the standard library unit structure according to the connection relationship of the first OR gate unit, and use it in combination with the second gate unit to generate the final gate unit.

[0099] Specifically, the connection relationship corresponding to the data input pin signal of the first latch is obtained according to the second connection relationship. This connection relationship is then checked against the first connection relationship of the boundary port of the target first gating unit. If they are the same, it is determined that no OR gate unit exists, meaning there is no test scenario in the current scenario. The clock gating unit needs to support both normal operation mode and scan test mode simultaneously. The OR gate unit is used to superimpose the enable signals for both modes. In normal mode, the latch output is connected to one end of the OR gate. In test mode, the scan enable signal is connected to the other end of the OR gate, and the OR gate output is connected to the enable terminal of the AND gate.

[0100] If no OR gate unit exists in the general library logic unit structure, obtain the preset gated unit under the standard library unit structure, and connect the enable pin signal of the preset gated unit to the enable pin signal of the first latch. It should be noted that the data input terminal of the first latch is connected to the corresponding enable pin signal. Set the scan enable pin signal of the preset gated unit to an unconnected state, assign a value of 0 to the scan enable pin signal of the preset gated unit, and then disconnect the first and second connection relationships under the general library logic unit structure. Then, process the assigned preset gated unit according to the first mapping relationship to generate the second gated unit. Obtain the net connected to the latch's data_in pin; if it has the same name as the hierarchy port signal, it indicates this is the case. At this time, the E pin of the standard library unit is directly connected to the enable signal of the port, while the TE pin will be unconnected. A logic 0 cell needs to be created and connected to the TE pin.

[0101] If the connection relationship of the data input pin signal of the first latch is different from the first connection relationship of the boundary port of the target first gating unit, an OR gate unit needs to be added. That is, a second OR gate unit of standard library unit structure is created according to the connection relationship of the first OR gate unit, and used in conjunction with the second gating unit. The generation process of the second gating unit is the same as the creation process in the above embodiment, and is not limited here. The combined use here means connecting the connection relationship of the boundary port of the second OR gate unit with the port of the second gating unit, that is, connecting it to the enable terminal of the AND gate unit.

[0102] The creation process of the second gating unit provided in this embodiment is clearly defined, with each type corresponding to a unique logical function and physical implementation, avoiding functional ambiguity. Fixed boundary ports and connection relationships make the signal transmission path predictable, and timing analysis can quickly calculate parameters such as delay and crosstalk, avoiding excessive complexity in timing verification due to uncertain ports or connections. In the physical verification stage, standardized connection relationships can quickly match design rules, such as port spacing and wiring width, reducing physical violations. In addition, in scenarios where OR gates are used, there is no need to add additional latches or AND gate units; multiple enabled OR logic control can be achieved through a single OR gate unit, simplifying the circuit structure while ensuring that all enabled signals are latched without glitches.

[0103] In some embodiments, creating a second OR gate unit of the standard library unit structure based on the connection relationship of the first OR gate unit includes:

[0104] Receive the third instruction from the integrated tool;

[0105] The third connection relationship of the first OR gate unit under the general library logic unit structure is obtained by parsing the third instruction.

[0106] A second mapping relationship is pre-established between the pin signals of the corresponding OR gate units under the standard library unit structure and the general library logic unit structure;

[0107] Create the second OR gate unit of the standard library unit structure based on the second mapping relationship and the third connection relationship.

[0108] Specifically, the synthesis tool (get_cells –filter "ref_name==GTECH_OR2") retrieves the OR gate, and the return value is the corresponding OR gate cell. The third instruction (all_connected) from the synthesis tool is then parsed to obtain the third connection relationship of the first OR gate cell under the general library logic cell structure. This third connection relationship refers to the connection relationship between the boundary port of the first OR gate cell and other devices. A second mapping relationship is pre-established between the pin signals of the corresponding OR gate cells under the standard library cell structure and the general library logic cell structure. This second mapping relationship serves the same purpose as the first mapping relationship mentioned above and is not limited here. Based on the second mapping relationship and the third connection relationship, the second OR gate cell of the standard library cell structure can be created.

[0109] The creation process of the second OR gate unit in the standard library unit structure provided in this embodiment, through the characteristics of logical OR, allows the gate control unit to adapt to more design requirements without changing the latch anti-glitch and AND gate clock switch, thereby simplifying load operation. At the same time, the second OR gate unit is integrated separately into the standard library unit, improving the flexibility of adaptation.

[0110] In some embodiments, after generating the second gating unit, the method further includes:

[0111] Receive the fourth instruction from the integrated tool;

[0112] The fourth connection relationship of the first NOT gate unit under the general library logic unit structure is obtained by parsing the fourth instruction.

[0113] A third mapping relationship is pre-established between the pin signals of the corresponding NOT gate units under the standard library unit structure and the general library logic unit structure;

[0114] Based on the third mapping relationship and the fourth connection relationship, a second NOT gate unit of the standard library unit structure is created, and it is used in conjunction with the second gating unit to generate the final gating unit.

[0115] Specifically, in the basic structure, the latch output signal must be a high-level valid signal to enable the AND gate clock. If the original enable signal is low-level valid, a NOT gate needs to be added before the input in the latch. No modification to the basic structure is required; simply using NOT gates to adapt enable signals of different polarities avoids gating logic failure due to polarity mismatch.

[0116] The synthesis tool (get_cells –filter “ref_name==GTECH_NOT”) obtains the NOT gate, and the returned value is the corresponding NOT gate cell. The fourth instruction (all_connected) from the synthesis tool is parsed to obtain the fourth connection relationship of the first NOT gate cell. This fourth connection relationship refers to the connection relationship between the boundary port of the first NOT gate cell and other devices. A third mapping relationship is pre-established between the pin signals of the corresponding NOT gate cells under the standard library cell structure and the general library logic cell structure. This third mapping relationship serves the same purpose as the first mapping relationship mentioned above and is not limited here. Based on the third mapping relationship and the fourth connection relationship, a second NOT gate cell of the standard library cell structure is created and combined with a second gating cell to generate the final gating cell. This combination is the same as in the above embodiment, and its creation process is also the same as the creation of the gating cell in the above embodiment, so it will not be repeated here.

[0117] The creation process of the second OR gate unit of the standard library unit structure provided in this embodiment is designed to adapt to the polarity requirements of the enable signal or clock signal, while not compromising the core functions of the latch anti-glitch and AND gate clock switch. It achieves signal polarity reversal through logic NOT, thus solving the polarity mismatch problem that the basic structure cannot cover.

[0118] In some embodiments, after generating the second gating unit, the method further includes:

[0119] Receive the fifth instruction from the integrated tool;

[0120] The fifth connection relationship of the first XOR gate unit under the general library logic unit structure is obtained by parsing the fifth instruction.

[0121] A fourth mapping relationship is pre-established between the pin signals of the corresponding XOR gate units under the standard library unit structure and the general library logic unit structure;

[0122] Based on the fourth mapping relationship and the fifth connection relationship, a second XOR gate unit of the standard library unit structure is created, and it is used in conjunction with the second gating unit to generate the final gating unit.

[0123] Specifically, the AND gate in the basic structure can only transmit the original clock polarity (e.g., active high). If the gated unit needs to be adapted to downstream registers with two polarities (partially triggered by rising edges, partially triggered by falling edges), the XOR gate can achieve dynamic control of the clock polarity. After the clock signal is input to the XOR gate, the output of the XOR gate is then connected to the AND gate, with the polarity control signal serving as the other input of the XOR gate. The latch output is connected to the other end of the AND gate.

[0124] The synthesis tool (get_cells –filter "ref_name==GTECH_XOR") retrieves the NOT gate, and the returned value is the corresponding XOR gate cell. The fifth instruction (all_connected) from the synthesis tool is parsed to obtain the fifth connection relationship of the first XOR gate cell. This fifth connection relationship refers to the connection relationship between the boundary port of the first XOR gate cell and other devices. A fourth mapping relationship is pre-established between the pin signals of the corresponding XOR gate cells under the standard library cell structure and the general library logic cell structure. This fourth mapping relationship serves the same purpose as the first mapping relationship mentioned above and is not limited here. Based on the fourth mapping relationship and the fifth connection relationship, a second XOR gate cell of the standard library cell structure is created and combined with a second gating cell to generate the final gating cell. This combination is the same as in the above embodiment, and its creation process is also the same as the creation of the gating cell in the above embodiment, so it will not be repeated here.

[0125] The creation process of the second XOR gate unit of the standard library unit structure provided in this embodiment utilizes its logic characteristic of outputting 1 when the inputs are different and outputting 0 when the inputs are the same to realize dynamic switching of clock polarity or conditional flipping of enable signal, while retaining the core functions of latch anti-glitch and AND gate clock switch, thereby improving the flexibility of clock gating unit.

[0126] Figure 4 A flowchart of another method for generating a gating unit provided in an embodiment of this application is shown below. Figure 4 As shown, the method includes:

[0127] S21: Obtain the modules that need to be replaced from the designer;

[0128] S22: Obtain the first connection relationship corresponding to the boundary port of the gate unit under the general logic unit structure, and the second connection relationship between the latch and the AND gate unit in the gate unit;

[0129] S23: Determine whether the connection relationship of the data input terminal pin signal of the latch is the same as the connection relationship of the boundary port of the target first gate control unit; if they are the same, proceed to step S24; if they are different, proceed to step S25.

[0130] S24: Set the scan enable pin signal of the gate unit to an unconnected state; and assign the scan enable pin signal of the gate unit a value of 0;

[0131] S25: Obtain the connection relationship of the first OR gate unit;

[0132] S26: Delete the connection relationship corresponding to the gate unit under the general library logic unit structure;

[0133] S27: Create an integrated clock gating standard library unit;

[0134] S28: Connect the created integrated clock gating standard library units according to the obtained connection relationships.

[0135] The foregoing has described in detail various embodiments of the gating unit generation method. Based on this, this application also discloses a gating unit generation apparatus corresponding to the above-described method. Figure 5 This is a structural diagram of a gating unit generation device provided in an embodiment of this application. Figure 5 As shown, the gating unit generation device includes:

[0136] The first parsing module 11 is used to receive the first instruction from the synthesis tool and parse the first connection relationship of the boundary port of the first gate unit under the general library logic unit structure.

[0137] The second parsing module 12 is used to receive the second instruction from the synthesis tool and parse the second connection relationship between the latches in the first gate unit and the AND gate unit under the general library logic unit structure.

[0138] Establish module 13, which is used to pre-establish the first mapping relationship between the pin signals of the corresponding gate units under the standard library unit structure and the general library logic unit structure;

[0139] Module 14 is created to create a second gated unit of the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship, so as to complete the generation process of the gated unit.

[0140] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0141] For a description of the gating unit generation apparatus provided in this application, please refer to the above method embodiments. This application will not repeat the description here, as it has the same beneficial effects as the above gating unit generation method.

[0142] Figure 6 A structural diagram of a gating unit generation device provided in an embodiment of this application is shown below. Figure 6As shown, the device includes:

[0143] Memory 21 is used to store computer programs;

[0144] Processor 22 is used to implement the steps of the gating unit generation method when executing a computer program.

[0145] The device for generating the gate control unit provided in this embodiment may include, but is not limited to, a tablet computer, a laptop computer, or a desktop computer.

[0146] The processor 22 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 22 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array. The processor 22 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 22 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 22 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0147] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 21 is used to store at least the following computer program 211, which, after being loaded and executed by the processor 22, is capable of implementing the relevant steps of the gating unit generation method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. The operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include, but is not limited to, the data involved in the gating unit generation method, etc.

[0148] In some embodiments, the gating unit generating device may further include a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.

[0149] Those skilled in the field can understand, Figure 6 The structure shown does not constitute a limitation on the device for generating the gating unit and may include more or fewer components than shown.

[0150] The processor 22 implements the gating unit generation method provided in any of the above embodiments by calling instructions stored in the memory 21.

[0151] For a description of the gating unit generation device provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the above gating unit generation method.

[0152] Furthermore, this application also provides a computer-readable storage medium storing a computer program, which, when executed by processor 22, implements the steps of the gating unit generation method described above.

[0153] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0154] For a description of the computer-readable storage medium provided in this application, please refer to the above method embodiments. This application will not repeat the description here, but it has the same beneficial effects as the above-described gating unit generation method.

[0155] Furthermore, this application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of a gating unit generation method.

[0156] For an introduction to the computer program product provided in this application, please refer to the above method embodiments. This application will not repeat the details here, but it has the same beneficial effects as the above-described gating unit generation method.

[0157] The foregoing has provided a detailed description of a method, apparatus, and medium for generating a gate control unit according to this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

[0158] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A method for generating a gating unit, characterized in that, include: Receive the first instruction from the synthesis tool and parse it to obtain the first connection relationship of the boundary port of the first gate unit under the general library logic unit structure; Receive the second instruction from the synthesis tool and parse it to obtain the second connection relationship between the latches in the first gate unit and the ports between the AND gate units under the general library logic unit structure; A first mapping relationship is pre-established between the pin signals of the corresponding gate units under the standard library unit structure and the general library logic unit structure; The second gating unit of the standard library unit structure is created based on the first connection relationship, the second connection relationship, and the first mapping relationship to complete the generation process of the gating unit.

2. The method for generating a gate control unit according to claim 1, characterized in that, The process of determining the first connection relationship includes: The current operational hierarchy of the hierarchical structure is determined according to the first instruction; In the current operation hierarchy, the first sub-operation instruction is received to obtain the port signal of the target first gate control unit; The first connection relationship of the boundary port of the target first gating unit is obtained based on the port signal.

3. The method for generating a gating unit according to claim 2, characterized in that, The second instruction includes a second sub-operation instruction, a third sub-operation instruction, and a fourth sub-operation instruction. The process of determining the second connection relationship includes: The first latch is obtained by parsing the second sub-operation instruction; The first AND gate is obtained by parsing the third sub-operation instruction; The second connection relationship between the first latch and the first AND gate is obtained by parsing the fourth sub-operation instruction.

4. The method for generating a gating unit according to claim 1, characterized in that, A first mapping relationship is pre-established between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure, including: Establish a mapping between the clock input pin signal of the gated unit under the standard library unit structure and the clock enable pin signal of the gated unit under the general library logic unit structure; Establish a mapping between the gate enable pin signal of the gate unit under the standard library unit structure and the enable pin signal of the gate unit under the general library logic unit structure; Establish a mapping between the test enable pin signal of the gated unit under the standard library unit structure and the scan enable pin signal of the gated unit under the general library logic unit structure; The output pin signals of the gated unit under the standard library unit structure are mapped to the gated clock output pin signals of the gated unit under the general library logic unit structure to complete the establishment of the first mapping relationship.

5. The method for generating a gating unit according to claim 3, characterized in that, The second gating unit of the standard library unit structure is created based on the first connection relationship, the second connection relationship, and the first mapping relationship, including: The connection relationship corresponding to the data input pin signal of the first latch is obtained according to the second connection relationship; Determine whether the connection relationship corresponding to the data input pin signal of the first latch is the same as the first connection relationship of the boundary port of the target first gate control unit; If they are the same, it is determined that the general library logic unit structure does not have an OR gate unit; a preset gated unit under the standard library unit structure is obtained; the gate enable pin signal of the preset gated unit is connected to the enable pin signal of the first latch; the scan enable pin signal of the preset gated unit is in an unconnected state; and the scan enable pin signal of the preset gated unit is assigned a value of 0; the first connection relationship and the second connection relationship under the general library logic unit structure are disconnected; the preset gated unit after assignment is processed according to the first mapping relationship to generate the second gated unit; If they are different, add the first OR gate unit under the general library logic unit structure; create the second OR gate unit of the standard library unit structure according to the connection relationship of the first OR gate unit, and use it in combination with the second gate unit to generate the final gate unit.

6. The method for generating a gating unit according to claim 5, characterized in that, Based on the connection relationship of the first OR gate unit, a second OR gate unit of the standard library unit structure is created, including: Receive the third instruction from the integrated tool; The third connection relationship of the first OR gate unit under the general library logic unit structure is obtained by parsing the third instruction. A second mapping relationship is pre-established between the pin signals of the corresponding OR gate units under the standard library unit structure and the general library logic unit structure; The second OR gate unit of the standard library unit structure is created based on the second mapping relationship and the third connection relationship.

7. The method for generating a gating unit according to claim 6, characterized in that, After generating the second gating unit, the following is also included: Receive the fourth instruction from the integrated tool; The fourth connection relationship of the first NOT gate unit under the general library logic unit structure is obtained by parsing the fourth instruction. A third mapping relationship is pre-established between the pin signals of the corresponding NOT gate units under the standard library unit structure and the general library logic unit structure; Based on the third mapping relationship and the fourth connection relationship, a second NOT gate unit of the standard library unit structure is created and used in conjunction with the second gating unit to generate the final gating unit.

8. A gating unit generation device, characterized in that, include: The first parsing module is used to receive the first instruction from the synthesis tool and parse the first connection relationship of the boundary port of the first gate unit under the general library logic unit structure. The second parsing module is used to receive the second instruction from the synthesis tool and parse the second connection relationship between the latches in the first gate unit and the ports between the AND gate units under the general library logic unit structure. A module is established to pre-establish a first mapping relationship between the pin signals of the corresponding gated units under the standard library unit structure and the general library logic unit structure. A creation module is used to create a second gating unit of the standard library unit structure based on the first connection relationship, the second connection relationship, and the first mapping relationship, so as to complete the generation process of the gating unit.

9. A gating unit generation device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the gating unit generation method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the gating unit generation method as described in any one of claims 1 to 7.

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