Process simulation method and system of chip and server

Abstract

The invention provides a chip process simulation method and system and a server, and relates to the technical field of virtual reality, and the method comprises the steps: building a three-dimensional simulation model of an entity object in a chip process based on preset performance parameters; importing the three-dimensional simulation model into a Unity engine, and performing dynamic scene construction on the three-dimensional simulation model in the Unity engine to obtain a chip process simulation scene; configuring a plurality of operation steps in the chip process for the chip process simulation scene through a Unity engine; and configuring control strategies of different entry modes for the chip process simulation scene after the configuration operation step to obtain a target chip process simulation scene. According to the invention, by constructing the target chip process simulation scene, the cost and risk of pre-post training of personnel in the chip process can be reduced, and the training efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of virtual reality technology, and in particular to a chip process simulation method, system, and server. Background Technology

[0002] With the booming development of the chip industry, rigorous and effective pre-job training for employees is crucial. Currently, industry training mainly relies on classroom-style training based on theoretical textbooks and multimedia courseware (such as PPTs and videos). This approach lacks intuitive operational demonstrations and the severity of consequences of errors, making it difficult to effectively link theoretical knowledge with application scenarios. Once on the actual production line, due to varying employee skills and levels of knowledge, violations or errors may occur during operation, leading to material problems and serious losses.

[0003] In recent years, some technologies combining virtual and reality have emerged to recreate operational processes in real workshops. However, these technologies are mostly presented from a third-person perspective, generally suffering from poor immersion and weak interactivity. At the same time, they are mostly linear processes, unable to respond to unconventional or erroneous operational instructions from employees or simulate their real consequences. Consequently, they fail to enable employees to fully understand the seriousness of violations, limiting the warning and preventative effects of training.

[0004] Therefore, current pre-job training for practitioners is characterized by high cost, high risk, and low efficiency. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a chip process simulation method, system and server. The method can reduce the cost and risk of pre-job training for personnel in chip process by constructing a target chip process simulation scenario, and improve training efficiency.

[0006] In a first aspect, embodiments of the present invention provide a chip process simulation method, the method comprising: Based on preset performance parameters, construct a three-dimensional simulation model of the physical objects in the chip process; The 3D simulation model is imported into the Unity engine, and a dynamic scene is constructed on the 3D simulation model in the Unity engine to obtain a chip process simulation scene. Using the Unity engine, multiple operation steps in the chip process are configured for the chip process simulation scenario; For the chip process simulation scenario configured with the above operation steps, control strategies for different entry modes are configured to obtain the target chip process simulation scenario.

[0007] Optionally, the method further includes: In response to the target user's selection of the entry mode, the target chip process simulation scenario is entered under the target mode; wherein, the entry mode includes: learning mode, practice mode and exam mode; In the target chip process simulation scenario, the operation behavior of the target user is collected based on the control strategy of the target mode to obtain behavioral data.

[0008] Optionally, the step of constructing a dynamic scene from the 3D simulation model in the Unity engine to obtain a chip process simulation scene includes: In the Unity engine, a material sphere is created for the 3D simulation model, and a texture map of the 3D simulation model is made based on the material sphere; Place the textured 3D simulation model at the designated location; Global ray rendering is performed on the three-dimensional simulation model to obtain a chip process simulation scene.

[0009] Optionally, configuring multiple operation steps in the chip process simulation scenario through the Unity engine includes: Using the Unity engine, multiple operational steps in the chip process are added to the chip process simulation scenario. Add interactive information to each of the aforementioned operation steps; wherein, the interactive information includes at least: interactive components and teaching resources; Configure the execution order of each of the aforementioned operation steps; Configure the response time for the execution results of each of the aforementioned operation steps.

[0010] Optionally, configuring control strategies for different entry modes for the chip process simulation scenario after configuring the above operation steps to obtain the target chip process simulation scenario includes: Configure a selection control for entering the learning mode for the chip process simulation scenario after configuring the above operation steps; In the learning mode, the teaching resources and operation prompts corresponding to each operation step in the chip process are configured to obtain the target chip process simulation scenario in the learning mode.

[0011] Optionally, configuring control strategies for different entry modes for the chip process simulation scenario after configuring the above operation steps to obtain the target chip process simulation scenario includes: Configure a selection control for entering the practice mode for the chip process simulation scenario after configuring the above operation steps; In the practice mode, the question-and-answer controls and answer verification strategies corresponding to each operation step in the chip process are configured to obtain the target chip process simulation scenario in the practice mode; wherein, the answer verification strategy includes at least: condition verification, step jump control, answer prompt information, risk consequences of operation errors, and operation prompt controls.

[0012] Optionally, configuring control strategies for different entry modes for the chip process simulation scenario after configuring the above operation steps to obtain the target chip process simulation scenario includes: Configure a selection control for entering the exam mode for the chip process simulation scenario after configuring the above operation steps; In the examination mode, the questions and scores corresponding to each operation step in the chip process are configured to obtain the target chip process simulation scenario under the examination mode.

[0013] Optionally, the three-dimensional simulation model includes at least: a softening soaking equipment model, a spin dryer model, an electroplating equipment model, an auxiliary material model, and a task role model.

[0014] Secondly, the present invention provides a chip process simulation system, the system comprising: The model building module is used to construct three-dimensional simulation models of physical objects in chip manufacturing processes based on preset performance parameters. The scene construction module is used to import the three-dimensional simulation model into the Unity engine, and to construct a dynamic scene of the three-dimensional simulation model in the Unity engine to obtain a chip process simulation scene. The operation step configuration module is used to configure multiple operation steps in the chip process simulation scenario through the Unity engine; The mode configuration module is used to configure control strategies for different entry modes for the chip process simulation scenario after configuring the operation steps, so as to obtain the target chip process simulation scenario.

[0015] Thirdly, embodiments of the present invention also provide a server, which includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, and the processor executing the computer-executable instructions to implement the steps of the process simulation method for the chip provided in the first aspect.

[0016] Fourthly, embodiments of the present invention also provide a storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the steps of the chip process simulation method provided in the first aspect.

[0017] This invention provides a chip process simulation method, system, and server. The solution includes: constructing a three-dimensional simulation model of a physical object in the chip process based on preset performance parameters; importing the three-dimensional simulation model into a Unity engine; constructing a dynamic scene of the three-dimensional simulation model in the Unity engine to obtain a chip process simulation scene; configuring multiple operation steps in the chip process for the chip process simulation scene through the Unity engine; and configuring control strategies for different entry modes for the chip process simulation scene after configuring the operation steps to obtain a target chip process simulation scene.

[0018] This technical solution, by constructing a 3D simulation model and a target chip process simulation scenario, eliminates the need to build a physical training production line and consume chip framework materials. This fundamentally eliminates economic losses such as material scrap, equipment damage, and production interruptions caused by operational errors, significantly reducing training costs and potential risks. In constructing the target chip process simulation scenario, configuring multiple operational steps in the chip process ensures standardized and consistent operation procedures; configuring control strategies for different entry modes adapts to the needs of different learning stages. Within the constructed target chip process simulation scenario, trainees can repeatedly practice high-risk, high-difficulty operational steps without considering safety consequences or consuming actual production resources. This trial-and-error learning method greatly deepens trainees' understanding and memory of chip process principles and operational points, consolidating training effectiveness and effectively improving training efficiency. Therefore, this invention, by constructing a target chip process simulation scenario, can reduce the cost and risk of pre-job training for personnel in chip processes and improve training efficiency.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating a chip process simulation method provided in an embodiment of the present invention; Figure 2 A schematic diagram of a three-dimensional simulation model provided in an embodiment of the present invention; Figure 3 A flowchart illustrating an operation method using a target chip process simulation scenario, provided as an embodiment of the present invention; Figure 4A schematic diagram of an interface for a target chip process simulation scenario provided in an embodiment of the present invention; Figure 5 A schematic diagram of the structure of a chip process simulation system provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a server provided in an embodiment of the present invention.

[0022] icon: 310 - Model Building Module; 320 - Scene Building Module; 330 - Operation Step Configuration Module; 340 - Mode Configuration Module; 101 - Processor; 102 - Memory; 103 - Bus; 104 - Communication interface. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] With the booming development of the chip industry, the requirements for practitioners have become more stringent. At the same time, the consequences of problems have become more severe. Therefore, the training process for practitioners cannot be entirely conducted on the production line; rigorous and effective pre-job training is necessary. Due to the unique nature of the chip industry, current training methods suffer from high costs, high risks, and low efficiency.

[0025] To address the aforementioned issues, this disclosure provides a chip process simulation method, system, and server. This solution constructs a target chip process simulation scenario based on virtual simulation technology. This target chip process simulation scenario can meet the basic training needs of employees in the chip industry. Employees can simulate operations in the target chip process simulation scenario, which can avoid serious consequences caused by employees' unfamiliarity with the steps, reduce training risks and costs, and improve training efficiency.

[0026] To facilitate understanding of this embodiment, a chip process simulation method disclosed in this embodiment will first be described in detail, such as... Figure 1 As shown, the method includes: Step S101: Based on preset performance parameters, construct a three-dimensional simulation model of the physical object in the chip process.

[0027] To construct a 3D simulation model that better reflects real-world application scenarios, this embodiment analyzes the requirements and training objectives related to the chip frame electroplating process to determine the functions and content that need virtual simulation. For example, connections are established with third parties such as companies, schools, and training institutions in the integrated circuit industry to analyze their specific needs and objectives for operational training, thereby determining the functions and content that require virtual simulation.

[0028] Based on the above requirements analysis, this embodiment utilizes 3D modeling software (such as 3ds Max, Maya, and Blender) to construct 3D simulation models of the physical objects involved in the entire chip frame electroplating process. The 3D simulation models include at least: a softening immersion equipment model, a spin dryer model, an electroplating equipment model, auxiliary material models, and task role models.

[0029] More specifically, the 3D simulation models of the aforementioned entities may include, but are not limited to, the following: (a) 3D simulation models representing entities such as workbenches, shelves, and workshop environments in a 3D scene; wherein, Figure 2 The above-mentioned 3D simulation models are shown in a 3D scene. (b) 3D simulation models corresponding to the entity objects of the role, such as the task role model as the virtual avatar of the operator. (c) 3D simulation models corresponding to the entity objects of the process equipment, such as softening soaking equipment, spin dryer, electroplating equipment, etc. (d) 3D simulation models corresponding to the entity objects of auxiliary materials, such as chip frame, separator, number plate, etc.

[0030] To ensure a balance between smooth interaction and highly realistic visual performance in a virtual reality environment, this embodiment allows for the pre-setting of key performance parameters for the 3D simulation model, such as the number of facets, model accuracy, and texture resolution.

[0031] In a specific example, this embodiment can set the number of faces of the 3D simulation model (such as an electroplating equipment model) to no more than 500,000. The number of faces allows control over the rendering load, ensuring a high refresh rate on mainstream hardware and preventing users from experiencing dizziness.

[0032] For the 3D simulation models of critical physical objects in the electroplating process, such as the 3D simulation model of the chip frame used in the electroplating process, this embodiment can set the model accuracy to the 0.1 mm level. This model accuracy ensures that the 3D simulation model will not exhibit edge distortion under close observation on a display device and can accurately match high-precision interactive logic.

[0033] To enhance the realism of surface textures in 3D simulation models, this embodiment allows setting the 3D simulation model to use PBR material maps at a target resolution (e.g., 2K resolution, 2048x2048 pixels). These include color maps, normal maps, metallicity maps, and roughness maps, used to accurately simulate the physical properties of solid object surfaces such as color, microscopic bumps, and reflective characteristics within the Unity engine, thereby enabling the 3D simulation model to present a realistic visual appearance under virtual lighting.

[0034] This embodiment models physical objects such as scenes, characters, equipment models, and auxiliary materials. During the modeling process, performance parameters such as the number of model faces, model accuracy, and material texture resolution are preset, thereby ensuring the detail and realism of the 3D simulation model and improving the quality of the 3D simulation model.

[0035] Step S102: Import the 3D simulation model into the Unity engine, and construct a dynamic scene for the 3D simulation model in the Unity engine to obtain the chip process simulation scene.

[0036] In this embodiment, the 3D simulation model is imported into the Unity engine. Within the Unity engine, a dynamic scene is constructed from the 3D simulation model. This includes: creating material spheres for the 3D simulation model and applying corresponding textures; arranging a 3D virtual scene and placing the 3D simulation model at a designated position within the 3D virtual scene; adding lights to simulate lighting effects in a real scene; and baking the scene. Through the construction of this dynamic scene, a chip process simulation scene is ultimately obtained.

[0037] In one implementation, a dynamic scene is constructed from the 3D simulation model in the Unity engine to obtain a chip process simulation scene, as can be seen below.

[0038] (1) In the Unity engine, create a material ball for the 3D simulation model and make a texture of the 3D simulation model based on the material ball.

[0039] Specifically, in the Unity engine, a material sphere is created for each 3D simulation model, matching material properties are determined for different 3D simulation models, and then target textures are added to the 3D simulation models through the Unity engine's URP rendering pipeline.

[0040] For example, for an electroplating equipment model with a metal surface, its material properties may include: a metallicity of 0.8-1.0, a smoothness of 0.6-0.8, and the addition of a 2K resolution metal texture map and normal map to enhance the surface texture.

[0041] For a spin dryer model with a plastic surface, its material properties can include: metallicity of 0.1-0.3, smoothness of 0.3-0.5, and the addition of 2K plastic texture maps and ambient occlusion maps to simulate the matte texture of real plastic.

[0042] For chip frame models, since a model precision of 0.1 mm is required, detail textures can be added to restore the subtle textures on the frame surface, such as pin spacing and electroplating pretreatment marks.

[0043] This embodiment creates a material sphere on the 3D simulation model and then creates a texture map of the 3D simulation model based on the material sphere. This ensures that the specular and diffuse reflection effects on the surface of the 3D simulation model match the lighting characteristics of the real environment, ultimately forming a material instance with industrial-grade visual precision.

[0044] (2) Set the textured 3D simulation model to the specified location.

[0045] In this embodiment, the spatial layout of the 3D simulation model can be arranged according to the actual physical layout of each entity object in the chip frame electroplating workshop in the scene view of the Unity engine.

[0046] In practice, the position parameters such as the position, rotation, and scaling of the 3D simulation model can be adjusted to place the 3D simulation model at a specified location so that the 3D simulation model conforms to the actual physical layout of the corresponding entity object in the workshop.

[0047] (3) Perform global ray rendering on the three-dimensional simulation model to obtain the chip process simulation scene.

[0048] To achieve lighting effects that closely resemble real-world scenes, this embodiment allows for global lighting rendering of the 3D simulation model within the Unity engine's scene view. Specifically, this includes configuring components that simulate realistic light sources, such as directional lights, point lights, and area lights, and setting attribute parameters such as light intensity, color temperature, and attenuation.

[0049] Furthermore, the global ray rendering in this embodiment also includes light baking. During the light baking process, the Unity engine simulates complex optical phenomena such as direct illumination, indirect reflection, and soft shadows of light in the scene through path tracing or irradiance calculation, and stores the calculation results in the form of light maps and applies them to the static 3D simulation model in the scene.

[0050] This embodiment generates highly realistic static lighting maps by configuring light sources such as directional lights and point lights to simulate real physical properties, and combining them with lighting baking. This makes the lighting effects in the chip process simulation scene much closer to the real industrial environment, effectively improving the visual immersion and realism of the scene.

[0051] Step S103: Configure multiple operation steps in the chip process simulation scene using the Unity engine.

[0052] This embodiment may include the following: Using the Unity engine, add multiple operation steps in the chip process simulation scene; add interactive information to each operation step; the interactive information includes at least: interactive components and teaching resources; configure the execution order of each operation step; configure the response time of the execution result of each operation step.

[0053] Specifically, the Unity engine incorporates various interactive features to enable learners to study the steps involved in chip frame electroplating. Based on this, this embodiment uses the Unity engine to add operational steps from the chip manufacturing process to a chip process simulation scenario. These steps include, for example: receiving the frame, operating the softening and soaking equipment, operating the spin dryer, operating the electroplating equipment, performing post-electroplating visual inspection, entering the logistics system, and placing it on the shelf.

[0054] Interactive components and teaching resources are added to each operation step. Interactive components are those that allow users to interact with the chip process simulation scenario, such as audible and visual alarms triggered by operational errors, confirmation buttons, and run buttons. Teaching resources can be in the form of text, audio, images, and video, and the content can be rich and diverse, including operation instructions, explanations of principles, teaching cases, and task cases.

[0055] It is understandable that the execution order of each operation step in the chip frame electroplating process is very important. Based on this, this embodiment needs to configure the execution order of each operation step to restrict the jump order of operation steps. Only after the current operation step is executed correctly can the jump to the next operation step be triggered. This can logically guarantee the standardization and integrity of the operation process, eliminate violations such as skipping steps and missing steps, and ensure the standardization of training.

[0056] To ensure smooth operation and real-time feedback in the chip process simulation scenario, this embodiment configures the response time of the execution results of each operation step in the chip framework electroplating process to achieve timing control. Specifically, the user's execution result for the current operation step can be captured within a pre-configured response time (e.g., 100 milliseconds); if the user's execution result is captured and verified within the response time, the next operation step can be unlocked. Based on this, by configuring the response time, this embodiment can control the response time of each operation step within a reasonable range, thereby effectively avoiding operational lag and ensuring the immersion of the training process and the real-time nature of human-computer interaction.

[0057] Step S104: Configure control strategies for different entry modes for the chip process simulation scenario after configuring the operation steps to obtain the target chip process simulation scenario.

[0058] To meet the needs of different application scenarios, this embodiment can configure different entry mode control strategies for the chip process simulation scenario, resulting in a final target chip process simulation scenario available to the user. The entry modes can include: learning mode, practice mode, and exam mode; different entry modes correspond to different control strategies.

[0059] This embodiment includes: configuring a selection control for entering the learning mode for the chip process simulation scene after configuring the operation steps; configuring the teaching resources and operation prompts corresponding to each operation step in the chip process in the learning mode to obtain the target chip process simulation scene in the learning mode.

[0060] In the configuration scheme for the learning mode control strategy, this embodiment can configure the teaching resources corresponding to each operation step. Based on this, in practical applications, when the operation step is triggered by the user, the preset teaching resources for the operation step can be pushed through the UI interface. The teaching resources are, for example, multimedia explanation information.

[0061] This embodiment can also configure operation prompts for each operation step. These prompts can be automatically displayed as guidance for the next operation step via a UI floating window, such as: placing the chip frame into the immersion tank. After the current step is completed, the operation prompts automatically and clearly indicate the content of the next operation step to the user, guiding the user to complete the entire chip frame electroplating process, ensuring the continuity of learning and the linear progression of the process.

[0062] This embodiment includes: configuring a selection control for entering the practice mode for a chip process simulation scenario after configuring the operation steps; configuring the question-and-answer control and answer verification strategy corresponding to each operation step in the chip process in the practice mode to obtain the target chip process simulation scenario in the practice mode; wherein, the answer verification strategy includes at least: condition verification, step jump control, answer prompt information, risk consequences of operation errors, and operation prompt control.

[0063] In practice mode, there is no need to explain the operation steps. Instead, you need to focus on the question and answer control strategies for each operation step.

[0064] In the configuration scheme for the control strategy of the practice mode, this embodiment can configure a question and answer control for the operation steps. Specifically, the question and answer control can pop up a question pop-up window during the operation, and the user can enter the answer based on the question pop-up window.

[0065] This embodiment can also configure an answer verification strategy for the operation steps. The answer verification strategy includes at least: condition verification, step jump control, answer prompt information, risk consequences of operation errors, and operation prompt controls.

[0066] The conditional validation configured for the operation steps can be: performing conditional judgments on the user's input or answer. The step jump control configured for the operation steps can be: if the user's input is correct, jump normally to the next operation step; if the user's input is incorrect, prevent the operation step from jumping, that is, do not enter the next operation step.

[0067] The answer prompts configured for the operation steps can be: record the number of times the user enters incorrect information, and push the parsing information when the number of errors exceeds the first threshold (e.g., 3 times); push the correct answer when the number of errors exceeds the second threshold (e.g., 5 times).

[0068] The risk consequences of operational errors configured in the operation steps can be as follows: if the user's input is determined to be incorrect, the corresponding risk consequences caused by the incorrect operation will be triggered, such as direct economic losses, equipment damage, etc.

[0069] The operation prompt control configured for the operation steps can be: adding an operation prompt control so that when users do not know how to proceed to the next operation step, they can get relevant operation prompts for the next operation step by clicking the operation prompt control.

[0070] This embodiment includes: configuring a selection control for entering the examination mode for the chip process simulation scenario after configuring the operation steps; configuring the questions and scores corresponding to each operation step in the chip process in the examination mode to obtain the target chip process simulation scenario in the examination mode.

[0071] Under the examination model, the target chip process simulation scenario runs as a closed and quantifiable evaluation environment. Each operation step and question needs to be assigned a score. No prompts will be given regardless of whether the operation is correct or not. When all operations are completed, the score is displayed, and the scores of each step can be viewed at the same time.

[0072] Based on this, in the configuration scheme for the control strategy of the examination mode, this embodiment can configure the questions and scores corresponding to each operation step; specifically, each operation step can be bound to a corresponding question, and the score of that question can be set.

[0073] Through the above embodiments, target chip process simulation scenarios under learning mode, practice mode and examination model have been constructed, which can meet the training needs of users at different stages such as learning, practice and examination.

[0074] After constructing the target chip process simulation scenario, professionals and trainees can be invited to test and evaluate it, and feedback can be collected to improve and refine the scenario. Through continuous testing and optimization, the stability and smoothness of the target chip process simulation scenario can be ensured. Subsequently, the developed target chip process simulation scenario will be promoted to enterprises, schools, and training technicians in the integrated circuit industry for practical application.

[0075] The above embodiments mainly describe the construction process of the target chip process simulation scenario. After the target chip process simulation scenario is constructed, as follows: Figure 3 As shown in the figure, this embodiment can also provide an operation method for using the target chip process simulation scenario, as shown below.

[0076] Step S201: In response to the target user's selection operation for the entry mode, enter the target chip process simulation scenario under the target mode; wherein, the entry modes include: learning mode, practice mode and exam mode.

[0077] like Figure 4 The diagram illustrates a target chip process simulation scenario in learning mode. The interface of the target chip process simulation scenario in learning mode can include a 3D simulation model, information about the target user (operator: Luntek), information about the current operation step, and prompts for the next operation step, such as: "Go to the large screen to view the production schedule."

[0078] Step S202: In the target chip process simulation scenario, the operation behavior of the target user is collected based on the control strategy of the target mode to obtain behavioral data.

[0079] For example, in learning mode, based on a control strategy that utilizes teaching resources and operational prompts, users can access teaching resources for each operational step, and are constantly prompted with operational prompts for the next step. During this process, the user's learning progress can be collected as behavioral data.

[0080] In practice mode, based on its question-and-answer control and answer verification strategy, users can obtain the questions displayed by the control and input their answers during operation. Furthermore, this embodiment can collect the user's input answers and perform a judgment on them. If the user inputs incorrectly, the next operation step will not be initiated, and the number of errors will be recorded. When the number of errors exceeds a first threshold, the parsing information for the current operation step can be displayed; if the user continues to input incorrectly and exceeds a second threshold, the correct answer can be displayed. Simultaneously, in the event of user input errors, the corresponding risk consequences of the erroneous operation will be triggered. An operation prompt control is displayed in the target chip process simulation scenario; users can click this control to obtain operation prompts for the next operation step.

[0081] In exam mode, based on its question and score control strategy, the target chip process simulation scenario stops the explanation of teaching resources, operation prompts, and simulation of risk consequences in learning and practice modes. The operation of each step depends entirely on user input. The system judges the correctness of user input, and only records incorrect or invalid input without responding to or blocking it. After all operation steps are completed, a structured evaluation report is generated, including the score for each step, the total score, and the points deducted.

[0082] In the background system of the target chip process simulation scenario, a playback function can be provided to view the user's operation behavior, the score of each step, the total score and the points lost, so as to better understand the strengths and weaknesses of each student and conduct targeted teaching and training.

[0083] Based on the above embodiments, a possible example scenario is provided here. Taking the operation of an electroplating machine in an integrated circuit manufacturing workshop as an example, after the trainee completes the spin-drying process, the dried chip frame is placed on the table. The trainee then sequentially places the numbered tags, separators, chip frame, separators, and chip frame (3D simulation models) onto the loading position of the electroplating equipment. The trainee needs to operate the display screen on the electroplating equipment to set the length, width, thickness, and movement speed of the chip frame, and then set the loading platform height (errors in this parameter will be reflected in the subsequent visual inspection). Current and voltage parameters are set for each electroplating zone, and the trainee clicks "OK". Clicking the "Run" button causes the frame on the loading platform to gradually move forward until it reaches the front, then moves laterally and is clamped by the fixtures of the starting electroplating equipment. It then begins to move gradually through each zone of the electroplating equipment. Finally, the fixtures are released at the unloading position, the chip frame is placed on the unloading position, and the chip frame is returned to the original frame. This completes the electroplating machine operation task.

[0084] The target chip process simulation scenario constructed in this embodiment, by simulating the standard operations of each step in the chip process and adding teaching resources, allows practitioners to quickly master the operational steps and knowledge. Furthermore, due to the human-computer interaction required, the immersive experience is better than reading books or using PowerPoint presentations, thus increasing learning interest. For non-standard operations, steps involving violations are added, along with demonstrations of the potential risks and consequences of these violations, to reinforce the necessity of correct operation. This approach enhances practitioners' understanding of the operational procedures before entering the production line internship, thereby reducing the occurrence of problems among newly trained practitioners on the production line.

[0085] In summary, the chip process simulation method provided in this disclosure includes: constructing a three-dimensional simulation model of the physical object in the chip process based on preset performance parameters; importing the three-dimensional simulation model into the Unity engine, and constructing a dynamic scene for the three-dimensional simulation model in the Unity engine to obtain a chip process simulation scene; configuring multiple operation steps in the chip process for the chip process simulation scene through the Unity engine; and configuring control strategies for different entry modes for the chip process simulation scene after configuring the operation steps to obtain a target chip process simulation scene.

[0086] This technical solution, by constructing a 3D simulation model and a target chip process simulation scenario, eliminates the need to build a physical training production line and consume chip framework materials. This fundamentally eliminates economic losses such as material scrap, equipment damage, and production interruptions caused by operational errors, significantly reducing training costs and potential risks. In constructing the target chip process simulation scenario, configuring multiple operational steps in the chip process ensures standardized and consistent operation procedures; configuring control strategies for different entry modes adapts to the needs of different learning stages. Within the constructed target chip process simulation scenario, trainees can repeatedly practice high-risk, high-difficulty operational steps without considering safety consequences or consuming actual production resources. This trial-and-error learning method greatly deepens trainees' understanding and memory of chip process principles and operational key points, consolidating training effectiveness and effectively improving training efficiency. Therefore, this disclosure, by constructing a target chip process simulation scenario, can reduce the cost and risk of pre-job training for personnel in chip processes and improve training efficiency.

[0087] Corresponding to the above-described chip process simulation method embodiments, this invention also provides a chip process simulation system, such as... Figure 5 As shown, the system includes: The model building module 310 is used to build a three-dimensional simulation model of the physical object in the chip process based on preset performance parameters. Scene construction module 320 is used to import the three-dimensional simulation model into the Unity engine, and to construct a dynamic scene of the three-dimensional simulation model in the Unity engine to obtain a chip process simulation scene. The operation step configuration module 330 is used to configure multiple operation steps in the chip process for the chip process simulation scenario through the Unity engine; The mode configuration module 340 is used to configure control strategies for different entry modes for the chip process simulation scenario after configuring the operation steps, so as to obtain the target chip process simulation scenario.

[0088] As demonstrated by the aforementioned chip process simulation system, this system, by constructing a 3D simulation model and a target chip process simulation scenario, eliminates the need to build a physical training production line or consume chip framework materials. This fundamentally eliminates economic losses such as material scrap, equipment damage, and production interruptions caused by operational errors, significantly reducing training costs and potential risks. In constructing the target chip process simulation scenario, configuring multiple operational steps in the chip process ensures standardized and consistent chip process operation procedures; configuring control strategies for different entry modes adapts to the needs of different learning stages. Within the constructed target chip process simulation scenario, trainees can repeatedly practice high-risk, high-difficulty operational steps without considering safety consequences or consuming actual production resources. This trial-and-error learning method greatly deepens trainees' understanding and memory of chip process principles and operational key points, consolidating training effects and effectively improving training efficiency. Therefore, this disclosure, by constructing a target chip process simulation scenario, can reduce the cost and risk of pre-job training for personnel in chip processes and improve training efficiency.

[0089] The chip process simulation system provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned chip process simulation method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned chip process simulation method embodiment.

[0090] This embodiment also provides a server, the structural diagram of which is shown below. Figure 6 As shown, the device includes a processor 101 and a memory 102; wherein, the memory 102 is used to store one or more computer instructions, which are executed by the processor to implement the steps of the above-mentioned chip process simulation method.

[0091] Figure 6 The server shown also includes a bus 103 and a communication interface 104. The processor 101, the communication interface 104, and the memory 102 are connected via the bus 103.

[0092] The memory 102 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The bus 103 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0093] The communication interface 104 is used to connect to at least one user terminal and other network units through a network interface, and to send encapsulated IPv4 packets or IPv4 packets to the user terminal through the network interface.

[0094] Processor 101 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 101 or by instructions in software form. The processor 101 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 102. The processor 101 reads the information in memory 102 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0095] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the chip process simulation method described in the foregoing embodiments.

[0096] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, devices, and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0097] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0098] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0099] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip process simulation method, characterized in that, The method includes: Based on preset performance parameters, construct a three-dimensional simulation model of the physical objects in the chip process; The 3D simulation model is imported into the Unity engine, and a dynamic scene is constructed on the 3D simulation model in the Unity engine to obtain a chip process simulation scene. Using the Unity engine, multiple operation steps in the chip process are configured for the chip process simulation scenario; For the chip process simulation scenario configured with the above operation steps, control strategies for different entry modes are configured to obtain the target chip process simulation scenario.

2. The chip process simulation method according to claim 1, characterized in that, The method further includes: In response to the target user's selection of the entry mode, the target chip process simulation scenario is entered under the target mode; wherein, the entry mode includes: learning mode, practice mode and exam mode; In the target chip process simulation scenario, the operation behavior of the target user is collected based on the control strategy of the target mode to obtain behavioral data.

3. The chip process simulation method according to claim 1, characterized in that, The process of constructing a dynamic scene from the 3D simulation model in the Unity engine to obtain a chip process simulation scene includes: In the Unity engine, a material sphere is created for the 3D simulation model, and a texture map of the 3D simulation model is made based on the material sphere; Place the textured 3D simulation model at the designated location; Global ray rendering is performed on the three-dimensional simulation model to obtain a chip process simulation scene.

4. The chip process simulation method according to claim 1, characterized in that, The configuration of multiple operation steps in the chip process simulation scenario using the Unity engine includes: Using the Unity engine, multiple operational steps in the chip process are added to the chip process simulation scenario. Add interactive information to each of the aforementioned operation steps; wherein, the interactive information includes at least: interactive components and teaching resources; Configure the execution order of each of the aforementioned operation steps; Configure the response time for the execution results of each of the aforementioned operation steps.

5. The chip process simulation method according to claim 1, characterized in that, The process of configuring the chip process simulation scenario after configuring the above operation steps, and configuring control strategies for different entry modes to obtain the target chip process simulation scenario, includes: Configure a selection control for entering the learning mode for the chip process simulation scenario after configuring the above operation steps; In the learning mode, the teaching resources and operation prompts corresponding to each operation step in the chip process are configured to obtain the target chip process simulation scenario in the learning mode.

6. The chip process simulation method according to claim 1, characterized in that, The process of configuring the chip process simulation scenario after configuring the above operation steps, and configuring control strategies for different entry modes to obtain the target chip process simulation scenario, includes: Configure a selection control for entering the practice mode for the chip process simulation scenario after configuring the above operation steps; In the practice mode, the question-and-answer controls and answer verification strategies corresponding to each operation step in the chip process are configured to obtain the target chip process simulation scenario in the practice mode; wherein, the answer verification strategy includes at least: condition verification, step jump control, answer prompt information, risk consequences of operation errors, and operation prompt controls.

7. The chip process simulation method according to claim 1, characterized in that, The process of configuring the chip process simulation scenario after configuring the above operation steps, and configuring control strategies for different entry modes to obtain the target chip process simulation scenario, includes: Configure a selection control for entering the exam mode for the chip process simulation scenario after configuring the above operation steps; In the examination mode, the questions and scores corresponding to each operation step in the chip process are configured to obtain the target chip process simulation scenario under the examination mode.

8. The chip process simulation method according to claim 1, characterized in that, The three-dimensional simulation model includes at least: a softening soaking equipment model, a spin dryer model, an electroplating equipment model, an auxiliary material model, and a task role model.

9. A chip process simulation system, characterized in that, The system includes: The model building module is used to construct three-dimensional simulation models of physical objects in chip manufacturing processes based on preset performance parameters. The scene construction module is used to import the three-dimensional simulation model into the Unity engine, and to construct a dynamic scene of the three-dimensional simulation model in the Unity engine to obtain a chip process simulation scene. The operation step configuration module is used to configure multiple operation steps in the chip process simulation scenario through the Unity engine; The mode configuration module is used to configure control strategies for different entry modes for the chip process simulation scenario after configuring the operation steps, so as to obtain the target chip process simulation scenario.

10. A server, characterized in that, The server includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the steps of the process simulation method for the chip according to any one of claims 1 to 8.

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