Gate driver, display device including the same, and electronic device including the display device

Abstract

The invention relates to a gate driver, a display device including the gate driver, and an electronic device including the display device. The gate driver may include a plurality of stages for outputting a first gate signal and a second gate signal, each of the plurality of stages including: a control circuit configured to control a voltage of a pull-up control node and a voltage of a first pull-down control node in response to an input signal and a first clock signal, the carry output node is configured to output a carry signal at the carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node; a first output circuit configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and a second output circuit configured to output a second gate signal at a second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a gate driver, a display device including a gate driver, and an electronic device including a display device. Background Technology

[0002] Typically, a display device may include a display panel and a display panel driver. The display panel may include gate lines, data lines, and pixels. The display panel driver may include a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a drive controller that controls the gate driver and the data driver.

[0003] Gate drivers can include transistors. As the number of transistors included in a gate driver increases, the power consumption and dead time of the display device also increase. Furthermore, as the number of transistors in the same area increases, the size of the transistors decreases. With the decrease in transistor size, the amplitude of the drive current can also decrease, and the rise and fall times of the gate signal output from the gate driver increase. Therefore, the transistor may output incorrect values.

[0004] Therefore, when the gate driver comprises a relatively large number of transistors, each of the transistors can appropriately have a relatively small size, and thus the reliability of the gate driver may be reduced. Summary of the Invention

[0005] One aspect of this disclosure provides a gate driver that has high stability and reliability while reducing power consumption and dead time in the display device.

[0006] Another aspect of this disclosure provides a display device including a gate driver.

[0007] Another aspect of this disclosure provides an electronic device including a display device.

[0008] However, the scope of this disclosure is not limited to the above objectives and can be extended in various ways without departing from the spirit and scope of this disclosure.

[0009] According to embodiments, the gate driver of this disclosure may include multiple stages, each outputting two or more gate signals. Each of the multiple stages may include: a control circuit configured to control the voltage of a pull-up control node and the voltage of a first pull-down control node in response to an input signal and a first clock signal, and configured to output a carry signal at a carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node; a first output circuit configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and a second output circuit configured to output a second gate signal at a second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

[0010] The control circuit may include: a first transistor, including a control electrode configured to receive a first clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a buffer node; a second transistor, including a control electrode connected to a buffer node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a pull-up control node; a third transistor, including a control electrode, a first electrode connected to a pull-up control node, and a second electrode configured to receive a second power supply voltage; a fourth transistor, including a control electrode configured to receive a second power supply voltage, a first electrode connected to a buffer node, and a second electrode connected to a first pull-down control node; a fifth transistor, including a control electrode connected to a pull-up control node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a carry output node; a sixth transistor, including a control electrode connected to a first pull-down control node, a first electrode connected to a carry output node, and a second electrode configured to receive a second power supply voltage; a first capacitor, including a first electrode configured to receive a first power supply voltage and a second electrode connected to a pull-up control node; and a second capacitor, including a first electrode connected to a carry output node and a second electrode connected to a first pull-down control node.

[0011] The control electrode of the third transistor can be connected to the first pull-down control node.

[0012] The control electrode of the third transistor can be connected to the buffer node.

[0013] The third transistor may include an N-channel metal-oxide-semiconductor (NMOS) transistor.

[0014] The first output circuit may include: a seventh transistor, including a control electrode configured to receive a second power supply voltage, a first electrode connected to a carry output node, and a second electrode connected to a second pull-down control node; an eighth transistor, including a control electrode connected to a pull-up control node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a first output node; a ninth transistor, including a control electrode connected to a second pull-down control node, a first electrode connected to a first output node, and a second electrode configured to receive a second clock signal; and a third capacitor, including a first electrode connected to the first output node and a second electrode connected to the second pull-down control node.

[0015] The channel width to channel length ratio of at least one of the seventh, eighth, and ninth transistors may be different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

[0016] The channel width to channel length ratio of at least one of the seventh, eighth, and ninth transistors may be greater than the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

[0017] The second output circuit may include: a tenth transistor, including a control electrode configured to receive a second power supply voltage, a first electrode connected to a carry output node, and a second electrode connected to a third pull-down control node; an eleventh transistor, including a control electrode connected to a pull-up control node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the second output node; a twelfth transistor, including a control electrode connected to the third pull-down control node, a first electrode connected to the second output node, and a second electrode configured to receive a third clock signal; and a fourth capacitor, including a first electrode connected to the second output node and a second electrode connected to the third pull-down control node.

[0018] The channel width to channel length ratio of at least one of the tenth, eleventh, and twelfth transistors may be different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

[0019] The channel width to channel length ratio of at least one of the tenth, eleventh, and twelfth transistors may be greater than the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

[0020] According to embodiments, the display device of this disclosure may include: a display panel including pixels; a data driver configured to provide a data voltage to the display panel; a gate driver configured to provide a gate signal to the display panel; and a drive controller configured to control the data driver and the gate driver. The gate driver may include multiple stages, each outputting two or more gate signals.

[0021] Each of the multiple stages may include: a control circuit configured to control the voltage of a pull-up control node and the voltage of a first pull-down control node in response to an input signal and a first clock signal, and configured to output a carry signal at a carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node; a first output circuit configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and a second output circuit configured to output a second gate signal at a second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

[0022] The control circuit may include: a first transistor, including a control electrode configured to receive a first clock signal, a first electrode configured to receive an input signal, and a second electrode connected to a buffer node; a second transistor, including a control electrode connected to a buffer node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a pull-up control node; a third transistor, including a control electrode, a first electrode connected to a pull-up control node, and a second electrode configured to receive a second power supply voltage; a fourth transistor, including a control electrode configured to receive a second power supply voltage, a first electrode connected to a buffer node, and a second electrode connected to a first pull-down control node; a fifth transistor, including a control electrode connected to a pull-up control node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a carry output node; a sixth transistor, including a control electrode connected to a first pull-down control node, a first electrode connected to a carry output node, and a second electrode configured to receive a second power supply voltage; a first capacitor, including a first electrode configured to receive a first power supply voltage and a second electrode connected to a pull-up control node; and a second capacitor, including a first electrode connected to a carry output node and a second electrode connected to a first pull-down control node.

[0023] The control electrode of the third transistor can be connected to the first pull-down control node.

[0024] The first output circuit may include: a seventh transistor, including a control electrode configured to receive a second power supply voltage, a first electrode connected to a carry output node, and a second electrode connected to a second pull-down control node; an eighth transistor, including a control electrode connected to a pull-up control node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to a first output node; a ninth transistor, including a control electrode connected to a second pull-down control node, a first electrode connected to a first output node, and a second electrode configured to receive a second clock signal; and a third capacitor, including a first electrode connected to the first output node and a second electrode connected to the second pull-down control node.

[0025] The channel width to channel length ratio of at least one of the seventh, eighth, and ninth transistors may be different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

[0026] The second output circuit may include: a tenth transistor, including a control electrode configured to receive a second power supply voltage, a first electrode connected to a carry output node, and a second electrode connected to a third pull-down control node; an eleventh transistor, including a control electrode connected to a pull-up control node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the second output node; a twelfth transistor, including a control electrode connected to the third pull-down control node, a first electrode connected to the second output node, and a second electrode configured to receive a third clock signal; and a fourth capacitor, including a first electrode connected to the second output node and a second electrode connected to the third pull-down control node.

[0027] The channel width to channel length ratio of at least one of the tenth, eleventh, and twelfth transistors may be different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

[0028] According to embodiments, the electronic device of this disclosure may include: a processor configured to output input control signals and input image data; a display panel including pixels; a data driver configured to provide data voltage to the display panel; a gate driver configured to provide gate signals to the display panel; and a drive controller configured to control the data driver and the gate driver based on the input control signals and the input image data. The gate driver may include multiple stages, each outputting two or more gate signals, and each of the multiple stages may include: a control circuit configured to control the voltage of a pull-up control node and the voltage of a first pull-down control node in response to an input signal and a first clock signal, and configured to output a carry signal at a carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node; a first output circuit configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and a second output circuit configured to output a second gate signal at a second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

[0029] Therefore, the gate driver, display device, and electronic device according to the embodiments can reduce the number of transistors included in the gate driver by allowing the first output circuit and the second output circuit of the gate driver to share the control circuit, thereby reducing the power consumption and dead zone of the display device.

[0030] As the dead zone of the display device decreases, the ratio of channel width to channel length of each transistor in the first or second output circuit of the gate driver can be increased. Therefore, the drive current of each transistor in the gate driver can be increased.

[0031] Furthermore, as the drive current of each transistor included in the gate driver increases, the rise time and fall time of the gate signal output from the gate driver can be reduced. Therefore, each transistor included in the gate driver can output a precise output value, thereby improving the stability and reliability of the gate driver.

[0032] However, this disclosure is not limited to the above aspects and can be extended in various ways without departing from the spirit and scope of this disclosure. Attached Figure Description

[0033] The above and other aspects of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to an embodiment; Figure 2 It is shown that it includes Figure 1A block diagram of one or more embodiments of a gate driver in a display device; Figure 3 It is shown that it includes Figure 2 A block diagram of the stages in the gate driver; Figure 4 It is shown Figure 3 A circuit diagram of one or more implementations of the level; Figure 5 It is shown Figure 2 Timing diagram of the gate driver operation; Figure 6 It is shown that it includes Figure 1 A circuit diagram of one or more embodiments of pixels in a display device; Figure 7 It is shown Figure 3 A circuit diagram of one or more implementations of the level; Figure 8 It is shown that it includes Figure 1 A block diagram of one or more embodiments of a gate driver in a display device; Figure 9 It is shown that it includes Figure 8 A block diagram of the stages in the gate driver; Figure 10 This is a block diagram illustrating an electronic device according to an embodiment; and Figure 11 It is shown that Figure 10 The diagram shows one or more embodiments of the electronic device being implemented as a smartphone. Detailed Implementation

[0034] Some aspects of this disclosure and methods of implementing it can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. The described embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects of this disclosure to those skilled in the art. Therefore, redundant processes, elements, and techniques that are irrelevant or unrelated to the description of the embodiments, or that are not essential for a person of ordinary skill in the art to fully understand the aspects of this disclosure, may be omitted. Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore, their repeated descriptions may be omitted.

[0035] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. In describing embodiments, the use of "can," "may," or "may not" corresponds to one or more embodiments of this disclosure.

[0036] In light of the whole of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in any suitable way in combination with each other, unless otherwise stated or implied.

[0037] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In other words, because the dimensions and thicknesses of elements in the drawings are arbitrarily shown for ease of description, this disclosure is not limited thereto.

[0038] It will be understood that when a component, layer, region, or assembly (e.g., device, apparatus, circuit, wiring, electrode, terminal, conductive film, etc.) is referred to as being "formed" on, "on," "connected to," or "(operationally, functionally, or communicatively) coupled to" another component, layer, region, or assembly, it can be directly formed on, directly connected to, or directly coupled to said other component, layer, region, or assembly, or indirectly formed on, indirectly connected to, or indirectly coupled to said other component, layer, region, or assembly, such that one or more intervening components, layers, regions, or assemblies may exist. Furthermore, this can refer collectively to direct or indirect connections or linkages, as well as integral or non-integral connections or linkages.

[0039] For example, when a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly coupled to said other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. One or more intervening components may include switches, transistors, resistors, inductors, capacitors, diodes, etc. Therefore, the connection is not limited to the connections illustrated in the drawings or detailed description, and may also include other types of connections. In describing embodiments, unless explicitly described as a direct connection, the expression for connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on..." means that one component is directly connected to or directly coupled to another component or directly on another component, without any intermediate components.

[0040] On the other hand, other expressions describing relationships between components, such as "between," "directly between," or "adjacent to," can be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between those two elements or layers, or there can be one or more intervening elements or layers.

[0041] For the purposes of this disclosure, expressions such as “at least one of…”, “any one of…”, or “one or more of…” following a list of elements modify the entire list of elements, not individual elements within the list. For example, “at least one of X, Y, and Z” and “at least one selected from X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z, such as, for example, XYZ, XY, YZ, and XZ, or any variations thereof. Similarly, the expression “at least one of A and B” can include A, B, or A and B. As used herein, “or” generally means “and / or”, and the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Similarly, expressions such as “at least one of…”, “a plurality of,” “one of…”, and other prepositional phrases following a list of elements modify the entire list of elements, not individual elements within the list. When “C to D” is stated, unless otherwise specified, it means that C or greater and D or less.

[0042] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position, or priority, and are used only to distinguish one element, component, assembly, region, area, layer, segment, or part from another. Therefore, the first element, first assembly, first region, first layer, or first part described below may be referred to as a second element, second assembly, second region, second layer, or second part without departing from the spirit and scope of this disclosure. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0043] In the example, the D1 axis, D2 axis, etc., are not limited to the axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the D1 axis, D2 axis, etc., can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, the second direction, and / or the third direction.

[0044] The terminology used herein is for descriptive purposes only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, and the plural forms are intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprising,” “including,” “having,” “possessing,” “including,” and “comprise” designate the presence of the stated feature, integral, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0045] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than as terms of degree and are intended to explain the inherent deviations of measured or calculated values ​​that will be recognized by those skilled in the art. For example, “substantially” can include a range of ±5% of the corresponding value. Given the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein includes the value and means within an acceptable range of deviation for a particular value as determined by those skilled in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” Additionally, the expression “identical” can mean “substantially identical.” In other words, the expression “identical” can include a range acceptable to those skilled in the art. Other expressions may also be derived from those that omit “substantially.”

[0046] In some embodiments, well-known structures and devices may be described in the accompanying drawings for one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that these functional blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. These may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Functional blocks, units, and / or modules implemented by microprocessors or other similar hardware may be programmed and controlled by software to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Furthermore, each functional block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) performing functions different from those of the dedicated hardware. Additionally, in some embodiments, functional blocks, units, and / or modules may be physically divided into two or more interactive separate functional blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, in some embodiments, functional blocks, units, and / or modules may be physically combined into more complex functional blocks, units, and / or modules without departing from the scope of this disclosure.

[0047] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] Figure 1 This is a block diagram showing a display device 1 according to an embodiment.

[0049] refer to Figure 1 The display device 1 may include a display panel 100 and a display panel driver (e.g., a display panel driving circuit) 600. The display panel driver 600 may include a drive controller (e.g., a drive control circuit) 200, a gate driver (e.g., a gate driving circuit) 300, a gamma reference voltage generator (e.g., a gamma reference voltage generation circuit) 400, and a data driver (e.g., a data driving circuit) 500.

[0050] For example, the drive controller 200 and the data driver 500 can be integrated into a single chip. For example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrated into a single chip. A drive module that includes at least the drive controller 200 and the data driver 500 integrated into a single chip can be referred to as a timing controller embedded data driver (TED).

[0051] The display panel 100 may have a display area in which an image is displayed and a peripheral area adjacent to the display area. For example, the peripheral area may be referred to as a border.

[0052] The display panel 100 may include a gate line GL and a data line DL, and also includes pixels PX electrically connected to the gate line GL and the data line DL. The gate line GL may extend in a first direction D1, and the data line DL may extend in a second direction D2 intersecting the first direction D1.

[0053] The drive controller 200 can receive input image data IMG and input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. In some embodiments, the input image data IMG may also include white image data. In another embodiment, the input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0054] The drive controller 200 can generate gate control signal CONT1, data control signal CONT2, gamma control signal CONT3 and data signal DATA based on the input image data IMG and the input control signal CONT.

[0055] The drive controller 200 can generate a gate control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and can output the gate control signal CONT1 to the gate driver 300. The gate control signal CONT1 may include a vertical start signal and a gate clock signal.

[0056] The drive controller 200 can generate a data control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and can output the data control signal CONT2 to the data driver 500. The data control signal CONT2 may include a horizontal start signal and a load signal.

[0057] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0058] The drive controller 200 can generate a gamma control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and can output the gamma control signal CONT3 to the gamma reference voltage generator 400.

[0059] The gate driver 300 can generate a gate signal in response to a gate control signal CONT1 received from the drive controller 200. The gate driver 300 can output this gate signal to the gate line GL. For example, the gate driver 300 can sequentially output the gate signal to the gate line GL. For example, the gate driver 300 can be mounted on the peripheral area of ​​the display panel 100. For example, the gate driver 300 can be integrated into the peripheral area of ​​the display panel 100.

[0060] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to the gamma control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500.

[0061] In one or more embodiments, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0062] The data driver 500 can receive the data control signal CONT2 and the data signal DATA from the drive controller 200, and can receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the digital data signal DATA into an analog data voltage VDATA. The data driver 500 can then output this data voltage VDATA to the data line DL.

[0063] Figure 2 It is shown that it includes Figure 1 A block diagram of one or more embodiments of the gate driver 300a in the display device 1.

[0064] refer to Figure 2The gate driver 300a can receive input signals, a first clock signal CLK1, a second clock signal CLK2, a third clock signal CLK3, and a fourth clock signal CLK4, and can include outputting gate signals GW[1], GW[2], GW[3], GW[4]... sequentially to the stages STAGE1, STAGE2, STAGE3, STAGE4... of the pixel PX. The input signal can be a start signal FLM or a carry signal from the previous stage.

[0065] Each of the STAGE1, STAGE2, STAGE3, STAGE4... can output two gate signals.

[0066] For example, the first clock signal CLK1 can be applied to the first clock terminal CLK1T of the first stage STAGE1, the second clock signal CLK2 can be applied to the second clock terminal CLK2T of the first stage STAGE1, the third clock signal CLK3 can be applied to the third clock terminal CLK3T of the first stage STAGE1, and the start signal FLM can be applied to the input terminal Carry_GWT of the first stage STAGE1. The first stage STAGE1 can output the first gate signal GW[1], the second gate signal GW[2], and the first carry signal Carry_GW[1].

[0067] For example, the third clock signal CLK3 can be applied to the first clock terminal CLK1T of the second stage STAGE2, the fourth clock signal CLK4 can be applied to the second clock terminal CLK2T of the second stage STAGE2, the first clock signal CLK1 can be applied to the third clock terminal CLK3T of the second stage STAGE2, and the first carry signal Carry_GW[1] of the first stage STAGE1 can be applied to the input terminal Carry_GWT of the second stage STAGE2. The second stage STAGE2 can output the third gate signal GW[3], the fourth gate signal GW[4], and the second carry signal Carry_GW[2].

[0068] For example, the first clock signal CLK1 can be applied to the first clock terminal CLK1T of the third stage STAGE3, the second clock signal CLK2 can be applied to the second clock terminal CLK2T of the third stage STAGE3, the third clock signal CLK3 can be applied to the third clock terminal CLK3T of the third stage STAGE3, and the second carry signal Carry_GW[2] of the second stage STAGE2 can be applied to the input terminal Carry_GWT of the third stage STAGE3. The third stage STAGE3 can output the fifth gate signal GW[5], the sixth gate signal GW[6], and the third carry signal Carry_GW[3].

[0069] For example, the third clock signal CLK3 can be applied to the first clock terminal CLK1T of the fourth stage STAGE4, ​​the fourth clock signal CLK4 can be applied to the second clock terminal CLK2T of the fourth stage STAGE4, ​​the first clock signal CLK1 can be applied to the third clock terminal CLK3T of the fourth stage STAGE4, ​​and the third carry signal Carry_GW[3] of the third stage STAGE3 can be applied to the input terminal Carry_GWT of the fourth stage STAGE4. The fourth stage STAGE4 can output the seventh gate signal GW[7], the eighth gate signal GW[8], and the fourth carry signal Carry_GW[4].

[0070] Figure 3 It is shown that it includes Figure 2 Block diagram of stage 310 in gate driver 300a.

[0071] refer to Figure 3 Stage 310 may include a control circuit 311, a first output circuit 312, and a second output circuit 313.

[0072] Control circuit 311 can receive either the first clock signal CLK1 or the third clock signal CLK3 at the first clock terminal CLK1T. For ease of explanation, in... Figure 3 The diagram shows a first clock signal CLK1 being applied to a first clock terminal CLK1T. For example, the control circuit 311 for odd-numbered STAGE1, STAGE3... can receive the first clock signal CLK1 at the first clock terminal CLK1T, and the control circuit 311 for even-numbered STAGE2, STAGE4... can receive the third clock signal CLK3 at the first clock terminal CLK1T.

[0073] The control circuit 311 can receive the previous carry signal Carry_GW[n-1], which serves as the carry signal for the previous stage, at the input terminal Carry_GWT, or it can receive the start signal FLM at the input terminal Carry_GWT. For example, the control circuit 311 for the first stage STAGE1 can receive the start signal FLM at the input terminal Carry_GWT. For example, the control circuit 311 for the nth stage (where n is an integer greater than or equal to 2) can receive the previous carry signal Carry_GW[n-1] at the input terminal Carry_GWT.

[0074] The carry output node NC of the control circuit 311 can be connected to the first output circuit 312 and the second output circuit 313. The carry output node NC of the control circuit 311 can output the carry signal Carry_GW[n].

[0075] The first output circuit 312 can receive either the second clock signal CLK2 or the fourth clock signal CLK4 at the second clock terminal CLK2T. For ease of explanation, in... Figure 3 The diagram shows a second clock signal CLK2 being applied to a second clock terminal CLK2T. For example, the first output circuit 312 of odd-numbered stages STAGE1, STAGE3... can receive the second clock signal CLK2 at the second clock terminal CLK2T, and the first output circuit 312 of even-numbered stages STAGE2, STAGE4... can receive the fourth clock signal CLK4 at the second clock terminal CLK2T.

[0076] The first output circuit 312 can output the first gate signal GW[2n-1] at the first output node NO1 based on the clock signal CLK2 or CLK4 applied to the second clock terminal CLK2T, the voltage of the pull-up control node QB, and the voltage of the carry output node NC.

[0077] The second output circuit 313 can receive either the third clock signal CLK3 or the first clock signal CLK1 at the third clock terminal CLK3T. For ease of explanation, in... Figure 3 The diagram shows a third clock signal CLK3 being applied to a third clock terminal CLK3T. For example, the second output circuit 313 of odd-numbered stages STAGE1, STAGE3... can receive the third clock signal CLK3 at the third clock terminal CLK3T, and the second output circuit 313 of even-numbered stages STAGE2, STAGE4... can receive the first clock signal CLK1 at the third clock terminal CLK3T.

[0078] The second output circuit 313 can output the second gate signal GW[2n] at the second output node NO2 based on the clock signal CLK3 or CLK1, the voltage of the pull-up control node QB and the voltage of the carry output node NC.

[0079] Since the first output circuit 312 and the second output circuit 313 share the control circuit 311, the display device 1 can reduce the number of control circuits 311 included in the gate driver 300a. As the number of control circuits 311 included in the gate driver 300a decreases, the number of transistors included in the gate driver 300a can also be reduced. Furthermore, as the number of transistors included in the gate driver 300a decreases, the power consumption of the display device 1 can also be reduced.

[0080] Furthermore, as the number of transistors included in the gate driver 300a decreases, the dead zone of the display device 1 can also be reduced. With the reduction in the dead zone of the display device 1, the ratio of the channel width to the channel length of each of the transistors included in the first output circuit 312 or the second output circuit 313 can be increased. Therefore, the drive current of each of the transistors included in the gate driver 300a can be increased.

[0081] Furthermore, as the drive current of each transistor included in the gate driver 300a increases, the rise time and fall time of the gate signal output from the gate driver 300a can be reduced. Therefore, each transistor included in the gate driver 300a can output a precise output value, thereby improving the stability and reliability of the gate driver 300a.

[0082] Figure 4 It is shown Figure 3 Circuit diagrams of one or more embodiments of stage 310.

[0083] refer to Figure 4 Stage 310a may include control circuit 311a, first output circuit 312 and second output circuit 313.

[0084] The control circuit 311a can control the voltage of the pull-up control node QB and the voltage of the first pull-down control node Q1 in response to the input signal and the first clock signal CLK1.

[0085] The voltage level of the second power supply voltage VGL can be lower than the voltage level of the first power supply voltage VGH. For example, the first power supply voltage VGH can be a voltage with a high voltage level, and the second power supply voltage VGL can be a voltage with a low voltage level that is lower than the high voltage level.

[0086] The control circuit 311a can output a carry signal Carry_GW[n] at the carry output node NC in response to the voltage of the pull-up control node QB and the voltage of the first pull-down control node Q1.

[0087] The control circuit 311a may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2.

[0088] The first transistor T1 may include a control electrode for receiving a first clock signal CLK1, a first electrode for receiving an input signal, and a second electrode connected to buffer node A. When the first clock signal CLK1 has an active level (e.g., a low level), the first transistor T1 can be turned on and the input signal can be transmitted to buffer node A.

[0089] The second transistor T2 may include a control electrode connected to buffer node A, a first electrode for receiving a first power supply voltage VGH, and a second electrode connected to a pull-up control node QB. When the second transistor T2 is turned on in response to the voltage of buffer node A, it can transmit the first power supply voltage VGH to the pull-up control node QB. For example, when the voltage of buffer node A is at a low level, the second transistor T2 can transmit the first power supply voltage VGH to the pull-up control node QB.

[0090] The third transistor T3 may include a control electrode connected to the first pull-down control node Q1, a first electrode connected to the pull-up control node QB, and a second electrode for receiving the second power supply voltage VGL. When the third transistor T3 is turned on in response to the voltage of the first pull-down control node Q1, the third transistor T3 can transmit the second power supply voltage VGL to the pull-up control node QB. For example, when the voltage of the first pull-down control node Q1 has a high voltage level, the third transistor T3 can transmit the second power supply voltage VGL to the pull-up control node QB.

[0091] The type of the third transistor T3 can be different from the types of each of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. For example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be implemented as P-channel metal-oxide-semiconductor (PMOS) transistors, and the third transistor T3 can be implemented as an N-channel metal-oxide-semiconductor (NMOS) transistor.

[0092] The fourth transistor T4 may include a control electrode for receiving the second power supply voltage VGL, a first electrode connected to the buffer node A, and a second electrode connected to the first pull-down control node Q1.

[0093] When the voltage of the first pull-down control node Q1 is bootstrapped, the channel current of the fourth transistor T4 can be zero. When the voltage of the first pull-down control node Q1 is bootstrapped, the fourth transistor T4 can be turned off, and the electrical connection between the buffer node A and the control electrode of the sixth transistor T6 can be disconnected. On the other hand, when the voltage of the first pull-down control node Q1 is not bootstrapped, the fourth transistor T4 can be turned on, and the fourth transistor T4 can electrically connect the buffer node A and the control electrode of the sixth transistor T6.

[0094] The fifth transistor T5 may include a control electrode connected to the pull-up control node QB, a first electrode for receiving the first power supply voltage VGH, and a second electrode connected to the carry output node NC. When the fifth transistor T5 is turned on in response to the voltage of the pull-up control node QB, the fifth transistor T5 can transmit the first power supply voltage VGH to the carry output node NC. For example, when the voltage of the pull-up control node QB is at a low level, the fifth transistor T5 can transmit the first power supply voltage VGH to the carry output node NC. A carry signal Carry_GW[n] with a high level can be output from the carry output node NC.

[0095] The sixth transistor T6 may include a control electrode connected to the first pull-down control node Q1, a first electrode connected to the carry output node NC, and a second electrode for receiving the second power supply voltage VGL. When the sixth transistor is turned on in response to the voltage of the first pull-down control node Q1, the sixth transistor T6 can transmit the second power supply voltage VGL to the carry output node NC. For example, when the voltage of the first pull-down control node Q1 is low, the sixth transistor T6 can transmit the second power supply voltage VGL to the carry output node NC. A carry signal Carry_GW[n] with a low level can be output from the carry output node NC.

[0096] The first capacitor C1 may include a first electrode for receiving a first power supply voltage VGH and a second electrode connected to a pull-up control node QB. The first capacitor C1 may store the difference between the first power supply voltage VGH and the voltage of the pull-up control node QB.

[0097] The second capacitor C2 may include a first electrode connected to the carry output node NC and a second electrode connected to the first pull-down control node Q1. When the carry signal Carry_GW[n] changes from the first power supply voltage VGH to the second power supply voltage VGL, the second capacitor C2 may bootstrap the voltage of the first pull-down control node Q1 based on the change in the voltage of the carry output node NC.

[0098] The first output circuit 312 can be connected to the pull-up control node QB and the carry output node NC of the control circuit 311a.

[0099] The first output circuit 312 may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a third capacitor C3.

[0100] The seventh transistor T7 may include a control electrode for receiving the second power supply voltage VGL, a first electrode connected to the carry output node NC, and a second electrode connected to the second pull-down control node Q2.

[0101] When the voltage of the second pull-down control node Q2 is bootstrapping, the channel current of the seventh transistor T7 can be zero. When the voltage of the second pull-down control node Q2 is bootstrapping, the seventh transistor T7 can be turned off, and the electrical connection between the carry output node NC and the control electrode of the ninth transistor T9 can be disconnected. On the other hand, when the voltage of the second pull-down control node Q2 is not bootstrapping, the seventh transistor T7 can be turned on, and the seventh transistor T7 can electrically connect the carry output node NC and the control electrode of the ninth transistor T9.

[0102] The eighth transistor T8 may include a control electrode connected to the pull-up control node QB, a first electrode for receiving a first power supply voltage VGH, and a second electrode connected to the first output node NO1. When the eighth transistor T8 is turned on in response to the voltage of the pull-up control node QB, the eighth transistor T8 can transmit the first power supply voltage VGH to the first output node NO1. For example, when the voltage of the pull-up control node QB has a low voltage level, the eighth transistor T8 can transmit the first power supply voltage VGH to the first output node NO1. A first gate signal GW[2n-1] with a high level can be output from the first output node NO1.

[0103] The ninth transistor T9 may include a control electrode connected to the second pull-down control node Q2, a first electrode connected to the first output node NO1, and a second electrode for receiving the second clock signal CLK2. When the ninth transistor T9 is turned on in response to the voltage of the second pull-down control node Q2, the ninth transistor T9 can transmit the second clock signal CLK2 to the first output node NO1. For example, when the voltage of the second pull-down control node Q2 has a low voltage level, the ninth transistor T9 can transmit the second clock signal CLK2 to the first output node NO1. A first gate signal GW[2n-1] equivalent to the second clock signal CLK2 can be output from the first output node NO1.

[0104] The third capacitor C3 may include a first electrode connected to the first output node NO1 and a second electrode connected to the second pull-down control node Q2. When the level of the second clock signal CLK2 changes from high to low, the third capacitor C3 may bootstrap the voltage of the second pull-down control node Q2 based on the change in voltage of the first output node NO1.

[0105] As the number of transistors included in the gate driver 300a is reduced (e.g., compared to a conventional gate driver), the dead zone of the display device 1 can also be reduced. Furthermore, the ratio of the channel width to the channel length of at least one of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be adjusted accordingly by reducing the dead zone of the display device 1.

[0106] The channel width to channel length ratio of at least one of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may differ from the channel width to channel length ratio of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. For example, the channel width to channel length ratio of at least one of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 may be greater than the channel width to channel length ratio of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0107] When the ratio of the channel width to the channel length of at least one of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 is greater than the ratio of the channel width to the channel length of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, the amplitude of the current flowing through the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be increased. When the amplitude of the current flowing through the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 increases, the rise time and fall time of the first gate signal GW[2n-1] can be reduced, and therefore the first gate signal GW[2n-1] can be output stably.

[0108] The second output circuit 313 can be connected to the pull-up control node QB and the carry output node NC of the control circuit 311a.

[0109] The second output circuit 313 may include a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a fourth capacitor C4.

[0110] The tenth transistor T10 may include a control electrode for receiving a second power supply voltage VGL, a first electrode connected to a carry output node NC, and a second electrode connected to a third pull-down control node Q3.

[0111] When the voltage of the third pull-down control node Q3 is bootstrapping, the channel current of the tenth transistor T10 can be zero. When the voltage of the third pull-down control node Q3 is bootstrapping, the tenth transistor T10 can be turned off, and the electrical connection between the carry output node NC and the control electrode of the twelfth transistor T12 can be disconnected. On the other hand, when the voltage of the third pull-down control node Q3 is not bootstrapping, the tenth transistor T10 can be turned on, and the tenth transistor T10 can electrically connect the carry output node NC and the control electrode of the twelfth transistor T12.

[0112] The eleventh transistor T11 may include a control electrode connected to the pull-up control node QB, a first electrode for receiving a first power supply voltage VGH, and a second electrode connected to the second output node NO2. When the eleventh transistor T11 is turned on in response to the voltage of the pull-up control node QB, the eleventh transistor T11 can transmit the first power supply voltage VGH to the second output node NO2. For example, when the voltage of the pull-up control node QB has a low voltage level, the eleventh transistor T11 can transmit the first power supply voltage VGH to the second output node NO2. A second gate signal GW[2n] with a high level can be output from the second output node NO2.

[0113] The twelfth transistor T12 may include a control electrode connected to the third pull-down control node Q3, a first electrode connected to the second output node NO2, and a second electrode for receiving the third clock signal CLK3. When the twelfth transistor T12 is turned on in response to the voltage of the third pull-down control node Q3, the twelfth transistor T12 can transmit the third clock signal CLK3 to the second output node NO2. For example, when the voltage of the third pull-down control node Q3 has a low voltage level, the twelfth transistor T12 can transmit the third clock signal CLK3 to the second output node NO2. A second gate signal GW[2n] equivalent to the third clock signal CLK3 can be output from the second output node NO2.

[0114] The fourth capacitor C4 may include a first electrode connected to the second output node NO2 and a second electrode connected to the third pull-down control node Q3. When the level of the third clock signal CLK3 changes from high to low, the fourth capacitor C4 can bootstrap the voltage of the third pull-down control node Q3 based on the change in the voltage of the second output node NO2.

[0115] As the number of transistors included in the gate driver 300a is reduced (e.g., compared to a conventional gate driver), the dead zone of the display device 1 can also be reduced. Furthermore, the ratio of the channel width to the channel length of at least one of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 can be adjusted accordingly by reducing the dead zone of the display device 1.

[0116] The channel width to channel length ratio of at least one of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be different from the channel width to channel length ratio of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. For example, the channel width to channel length ratio of at least one of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 may be greater than the channel width to channel length ratio of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0117] When the channel width to channel length ratio of at least one of the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 is greater than the channel width to channel length ratio of at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, the amplitude of the current flowing through the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 can be increased. When the amplitude of the current flowing through the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 increases, the rise time and the fall time of the second gate signal GW[2n] can be reduced, and therefore the second gate signal GW[2n] can be output stably.

[0118] Figure 5 It is shown Figure 2 Timing diagram of the operation of gate driver 300a.

[0119] refer to Figure 5 The period during which the signal is applied to the gate driver 300a may include a first period TP1, a second period TP2, a third period TP3, and a fourth period TP4.

[0120] In the first cycle TP1, the input signal and the first clock signal CLK1 can be at a low level. The second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 can be at a high level.

[0121] In the first cycle TP1, the first transistor T1 can be turned on based on the first clock signal CLK1 with a low level. Therefore, the input signal can be transmitted to buffer node A. The input signal can be transmitted from buffer node A to the first pull-down control node Q1 via the fourth transistor T4, and the voltage of the first pull-down control node Q1 can have a low voltage level. The sixth transistor T6 can be turned on in response to the voltage of the first pull-down control node Q1. The second power supply voltage VGL can be transmitted to the carry output node NC. The carry output node NC can output a carry signal Carry_GW[n] with a low level.

[0122] The seventh transistor T7 can transmit the voltage of the carry output node NC to the second pull-down control node Q2, and the voltage of the second pull-down control node Q2 can have a low voltage level. The ninth transistor T9 can be turned on in response to the voltage of the second pull-down control node Q2. The ninth transistor T9 can transmit the second clock signal CLK2 to the first output node NO1. A first gate signal GW[2n-1] with a high level can be output from the first output node NO1.

[0123] The tenth transistor T10 can transmit the voltage of the carry output node NC to the third pull-down control node Q3. The voltage of the third pull-down control node Q3 can be at a low voltage level. The twelfth transistor T12 can be turned on in response to the voltage of the third pull-down control node Q3. The twelfth transistor T12 can transmit the third clock signal CLK3 to the second output node NO2. A second gate signal GW[2n] with a high level can be output from the second output node NO2.

[0124] During the second cycle TP2, the input signal and the second clock signal CLK2 can be at a low level. Furthermore, the first clock signal CLK1, the third clock signal CLK3, and the fourth clock signal CLK4 can be at a high level.

[0125] In the second cycle TP2, when the ninth transistor T9 is turned on, the ninth transistor T9 can transmit the second clock signal CLK2 with a low level to the first output node NO1. The first gate signal GW[2n-1] with a low level can be output from the first output node NO1.

[0126] In the second cycle TP2, when the twelfth transistor T12 is turned on, the twelfth transistor T12 can transmit the third clock signal CLK3 with a high level to the second output node NO2. The second gate signal GW[2n] with a high level can be output from the second output node NO2.

[0127] In the third cycle TP3, the third clock signal CLK3 can be low. Furthermore, the input signal, the first clock signal CLK1, the second clock signal CLK2, and the fourth clock signal CLK4 can be high.

[0128] In the third cycle TP3, when the ninth transistor T9 is turned on, the ninth transistor T9 can transmit the second clock signal CLK2 with a high level to the first output node NO1. The first gate signal GW[2n-1] with a high level can be output from the first output node NO1.

[0129] In the third cycle TP3, when the twelfth transistor T12 is turned on, the twelfth transistor T12 can transmit the third clock signal CLK3 with a low level to the second output node NO2. The second gate signal GW[2n] with a low level can be output from the second output node NO2.

[0130] In the fourth cycle TP4, the first clock signal CLK1 can be low. Furthermore, the input signal, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 can be high.

[0131] In the fourth cycle TP4, the first transistor T1 can be turned on in response to a first clock signal CLK1 with a high level. The input signal can be transmitted to buffer node A. The input signal can be transmitted from buffer node A to the first pull-down control node Q1 through the fourth transistor T4, and the voltage of the first pull-down control node Q1 can have a high voltage level. The third transistor T3 can be turned on in response to the voltage of the first pull-down control node Q1. The third transistor T3 can transmit the second power supply voltage VGL to the pull-up control node QB. The voltage of the pull-up control node QB can have a low voltage level. The fifth transistor T5 can be turned on in response to the voltage of the pull-up control node QB. The fifth transistor T5 can transmit the first power supply voltage VGH to the carry output node NC. The voltage of the carry output node NC can have a high voltage level. A carry signal Carry_GW[n] with a high level can be output from the carry output node NC.

[0132] The eighth transistor T8 can be turned on in response to the voltage of the pull-up control node QB. The eighth transistor T8 can transmit the first power supply voltage VGH to the first output node NO1. A first gate signal GW[2n-1] with a high level can be output from the first output node NO1.

[0133] The eleventh transistor T11 can be turned on in response to the voltage of the pull-up control node QB. The eleventh transistor T11 can transmit the first power supply voltage VGH to the second output node NO2. A second gate signal GW[2n] with a high level can be output from the second output node NO2.

[0134] Figure 6 It is shown that it includes Figure 1 Circuit diagram of one or more embodiments of pixel PX in display device 1.

[0135] refer to Figure 6 Pixel PX may include first pixel transistors PT1 to seventh pixel transistors PT7, storage capacitor CST, and light-emitting element EL. Assuming... Figure 6 The pixel PX shown is connected to the k-th gate line, where k is an integer between 1 and 2n.

[0136] The first pixel transistor PT1 may include a control electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The first pixel transistor PT1 can generate a drive current corresponding to the data voltage VDATA.

[0137] The second pixel transistor PT2 may include a control electrode for receiving a data write gate signal GW[k], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the second node N2. When the second pixel transistor PT2 is turned on in response to the data write gate signal GW[k], the second pixel transistor PT2 can provide the data voltage VDATA to the second node N2.

[0138] The third pixel transistor PT3 may include a control electrode for receiving a compensation gate signal GC[k], a first electrode connected to the third node N3, and a second electrode connected to the first node N1. When the third pixel transistor PT3 is turned on in response to the compensation gate signal GC[k], the third pixel transistor PT3 may be diode connected to the first pixel transistor PT1.

[0139] The fourth pixel transistor PT4 may include a control electrode for receiving an initialization gate signal GI[k], a first electrode for receiving an initialization voltage VINT, and a second electrode connected to the first node N1. When the fourth pixel transistor PT4 is turned on in response to the initialization gate signal GI[k], the fourth pixel transistor PT4 may provide the initialization voltage VINT to the first node N1.

[0140] The fifth pixel transistor PT5 may include a control electrode for receiving the transmit signal EM[k], a first electrode for receiving the first drive voltage ELVDD, and a second electrode connected to the second node N2.

[0141] The sixth pixel transistor PT6 may include a control electrode for receiving the transmitted signal EM[k], a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0142] The fifth pixel transistor PT5 and the sixth pixel transistor PT6 can control the light emission of the light-emitting element EL in response to the emission signal EM[k].

[0143] The seventh pixel transistor PT7 may include a control electrode for receiving the previous data write gate signal GW[k-1], a first electrode for receiving the anode initialization voltage VAINT, and a second electrode connected to the fourth node N4. When the seventh pixel transistor PT7 is turned on in response to the previous data write gate signal GW[k-1], the seventh pixel transistor PT7 can provide the anode initialization voltage VAINT to the fourth node N4.

[0144] The storage capacitor CST may include a first electrode for receiving a first drive voltage ELVDD and a second electrode connected to a first node N1. The storage capacitor CST may store a data voltage VDATA.

[0145] The light-emitting element EL may include an anode connected to the fourth node N4 and a cathode for receiving a second driving voltage ELVSS. The light-emitting element EL may emit light based on the driving current generated by the first pixel transistor PT1.

[0146] In one or more embodiments, the first pixel transistor PT1, the second pixel transistor PT2, and the fifth pixel transistors PT5 through PT7 can be implemented as PMOS transistors, and the third pixel transistor PT3 and the fourth pixel transistor PT4 can be implemented as NMOS transistors, but this disclosure is not limited thereto. For example, all of the first pixel transistors PT1 through PT7 can be implemented as PMOS transistors. In another example, all of the first pixel transistors PT1 through PT7 can be implemented as NMOS transistors.

[0147] A pixel PX is shown to include seven transistors PT1 to PT7 and a storage capacitor CST, but a pixel PX is not limited to this. For example, a pixel PX may include two or more transistors and one or more capacitors.

[0148] Figure 7 It is shown Figure 3 Circuit diagrams of one or more embodiments of stage 310.

[0149] refer to Figure 7Stage 310b may include control circuit 311b, first output circuit 312, and second output circuit 313. Except for the connection relationship of the control electrode of the third transistor T3 and the operation of the gate driver 300a, stage 310b is essentially connected to… Figure 4 The same as level 310a. Therefore, the same reference numerals will be used to refer to those relating to... Figure 4 The components described are the same as or similar to those described above, and any repeated descriptions of the above components will be omitted.

[0150] The third transistor T3 included in the control circuit 311b may include a control electrode connected to the buffer node A, a first electrode connected to the pull-up control node QB, and a second electrode for receiving the second power supply voltage VGL. When the third transistor T3 is turned on in response to the voltage of the buffer node A, the third transistor T3 can transmit the second power supply voltage VGL to the pull-up control node QB.

[0151] Since the first output circuit 312 and the second output circuit 313 share the control circuit 311b, the display device 1 can reduce the number of control circuits 311b included in the gate driver 300a. As the number of control circuits 311b included in the gate driver 300a decreases, the number of transistors included in the gate driver 300a can also be reduced. Furthermore, as the number of transistors included in the gate driver 300a decreases, the power consumption of the display device 1 can also be reduced.

[0152] Furthermore, as the number of transistors included in the gate driver 300a decreases, the dead zone of the display device 1 can also be reduced. With the reduction in the dead zone of the display device 1, the ratio of the channel width to the channel length of each of the transistors included in the first output circuit 312 or the second output circuit 313 can be increased. Therefore, the drive current of each of the transistors included in the gate driver 300a can be increased.

[0153] Furthermore, as the drive current of each transistor included in the gate driver 300a increases, the rise time and fall time of the gate signal output from the gate driver 300a can be reduced. Therefore, each transistor included in the gate driver 300a can output a precise output value, thereby improving the stability and reliability of the gate driver 300a.

[0154] Figure 8 It is shown that it includes Figure 1 A block diagram of one or more embodiments of the gate driver 300 in the display device 1.

[0155] refer to Figure 8The gate driver 300b can receive input signals, a first clock signal CLK1, a second clock signal CLK2, ..., a (m+1)th clock signal CLK(m+1) and a (m+2)th clock signal CLK(m+2), where m is an integer greater than or equal to 4, and the gate driver 300b can include stages STAGE1, STAGE2, STAGE3... that sequentially output gate signals GW[1], GW[2], GW[3], GW[4]... to the pixel PX. The input signal can be a start signal FLM or a carry signal from the previous stage. Figure 8 The diagram illustrates the application of a first clock signal CLK1 to a (m+2)th clock signal CLK(m+2), but this disclosure is not limited thereto. For example, gate driver 300b may receive a first clock signal CLK1, a second clock signal CLK2, ... to a (m+1)th clock signal CLK(m+1).

[0156] Each of the STAGE1, STAGE2, STAGE3... can output a gate signal.

[0157] The first stage STAGE1 can output the first gate signal GW[1], the second gate signal GW[2], ... up to the m-th gate signal GW[m]. For example, the first stage STAGE1 can output the first gate signal GW[1] from the first output node NO1. The first stage STAGE1 can output the second gate signal GW[2] from the second output node NO2. In this way, the first stage STAGE1 can output the m-th gate signal GW[m] from the m-th output node NOm.

[0158] The second stage STAGE2 can output the (m+1)th gate signal GW[m+1], the (m+2)th gate signal GW[m+2], ... up to the 2mth gate signal GW[2m]. For example, the second stage STAGE2 can output the (m+1)th gate signal GW[m+1] from the first output node NO1. The second stage STAGE2 can output the (m+2)th gate signal GW[m+2] from the second output node NO2. In this way, the second stage STAGE2 can output the 2mth gate signal GW[2m] from the mth output node NOm.

[0159] The third stage STAGE3 can output the (2m+1)th gate signal GW[2m+1], the (2m+2)th gate signal GW[2m+2], ... up to the 3mth gate signal GW[3m]. For example, the third stage STAGE3 can output the (2m+1)th gate signal GW[2m+1] from the first output node NO1. The third stage STAGE3 can output the (2m+2)th gate signal GW[2m+2] from the second output node NO2. In this way, the third stage STAGE3 can output the 3mth gate signal GW[3m] from the mth output node NOm.

[0160] Each of the STAGE1, STAGE2, STAGE3... can output a carry signal.

[0161] For example, the first stage STAGE1 can output the first carry signal Carry_GW[1]. For example, the second stage STAGE2 can output the second carry signal Carry_GW[2]. For example, the third stage STAGE3 can output the third carry signal Carry_GW[3].

[0162] Figure 9 It is shown that it includes Figure 8 Block diagram of stage 320 in gate driver 300b.

[0163] refer to Figure 9 Stage 320 may include control circuitry 321 and output circuitry 322, 323, and 324. For ease of explanation, it is assumed that stage 320 is the first stage STAGE1 used to receive the start signal FLM via the input terminal Carry_GWT.

[0164] The control circuit 321 can receive the first clock signal CLK1 through the first clock terminal CLK1T. The control circuit 321 can receive the start signal FLM through the input terminal Carry_GWT. The carry output node NC of the control circuit 321 can be connected to the output circuits 322, 323 and 324, and the pull-up control node QB can be connected to the output circuits 322, 323 and 324. The control circuit 321 can output the first carry signal Carry_GW at the carry output node NC[1].

[0165] The first output circuit 322 can receive the second clock signal CLK2 through the second clock terminal CLK2T. The first output circuit 322 can output the first gate signal GW[1] in response to the second clock signal CLK2 applied to the second clock terminal CLK2T, the voltage of the pull-up control node QB and the voltage of the carry output node NC.

[0166] The second output circuit 323 can receive the third clock signal CLK3 through the third clock terminal CLK3T. The second output circuit 323 can output the second gate signal GW in response to the third clock signal CLK3 applied to the third clock terminal CLK3T, the voltage of the pull-up control node QB and the voltage of the carry output node NC[2].

[0167] Each stage other than STAGE1 can receive the carry signal from the previous stage via the input terminal Carry_GWT. Furthermore, each of the clock terminals CLK1T, CLK2T, ..., CLK(m+1)T of the control circuit 321 and the output circuits 322, 323, and 324 can receive one of the clock signals. For example, each of the clock terminals CLK1T, CLK2T, ..., CLK(m+1)T of the control circuit 321 and the output circuits 322, 323, and 324 can receive one of the first clock signal CLK1, the second clock signal CLK2, ... up to the (m+1)th clock signal CLK(m+1). For example, each of the clock terminals CLK1T, CLK2T, ..., CLK(m+1)T of the control circuit 321 and the output circuits 322, 323 and 324 can receive one of the first clock signal CLK1, the second clock signal CLK2, ..., the (m+1)th clock signal CLK(m+1) and the (m+2)th clock signal CLK(m+2).

[0168] Since output circuits 322, 323, and 324 share control circuit 321, the display device 1 can reduce the number of control circuits 321 included in the gate driver 300b. As the number of control circuits 321 included in the gate driver 300b decreases, the number of transistors included in the gate driver 300b can also be reduced. Furthermore, as the number of transistors included in the gate driver 300b decreases, the power consumption of the display device 1 can also be reduced.

[0169] Furthermore, as the number of transistors included in the gate driver 300b decreases, the dead zone of the display device 1 can also be reduced. With the reduction in the dead zone of the display device 1, the ratio of the channel width to the channel length of each of the transistors included in each of the output circuits 322, 323, and 324 can be increased. Therefore, the drive current of each of the transistors included in the gate driver 300b can be increased.

[0170] Furthermore, as the drive current of each transistor included in the gate driver 300b increases, the rise time and fall time of the gate signal output from the gate driver 300b can be reduced. Therefore, each transistor included in the gate driver 300b can output a precise output value, thereby improving the stability and reliability of the gate driver 300b.

[0171] Figure 10 This is a block diagram illustrating an electronic device 1000 according to an embodiment, and Figure 11 It is shown that Figure 10 The electronic device 1000 is implemented as one or more embodiments of a smartphone.

[0172] refer to Figure 10 and Figure 11 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 The display device 1. In addition, the electronic device 1000 may also include a port for communicating with a graphics card, sound card, memory card, universal serial bus (USB) device, other electronic devices, etc.

[0173] In one or more embodiments, such as Figure 11 As shown, the electronic device 1000 can be implemented as a smartphone. However, the electronic device 1000 is not limited to this. For example, the electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet computer, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0174] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. According to one or more embodiments, processor 1010 can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0175] For example, such as Figure 1 As shown, processor 1010 can output input image data IMG and input control signal CONT to a device including... Figure 1 The drive controller 200 in the display device 1.

[0176] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and so on.

[0177] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, etc.

[0178] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, mouse, etc., and output devices such as a speaker, printer, etc. In some embodiments, I / O device 1040 may include display device 1060.

[0179] Power supply 1050 can provide power for the operation of electronic device 1000.

[0180] The display device 1060 can be connected to other components via a bus or other communication link.

[0181] The display device 1060 may include a gate driver 300a, and the gate driver 300a may include stages STAGE1, STAGE2, STAGE3, STAGE4... that sequentially output gate signals GW[1], GW[2], GW[3], GW[4]... to the pixel PX. Each of stages STAGE1, STAGE2, STAGE3, STAGE4... may output two or more gate signals. For example, each of stages STAGE1, STAGE2, STAGE3, STAGE4... included in the gate driver 300a may include a control circuit 311, a first output circuit 312 that outputs a first gate signal GW[2n-1], and a second output circuit 313 that outputs a second gate signal GW[2n].

[0182] Since the first output circuit 312 and the second output circuit 313 share the control circuit 311, the display device 1060 can reduce the number of control circuits 311 included in the gate driver 300a. As the number of control circuits 311 included in the gate driver 300a decreases, the number of transistors included in the gate driver 300a can also be reduced. Furthermore, as the number of transistors included in the gate driver 300a decreases, the power consumption of the display device 1060 can also be reduced.

[0183] Furthermore, as the number of transistors included in the gate driver 300a decreases, the dead zone of the display device 1060 can also be reduced. With the reduction in the dead zone of the display device 1060, the ratio of the channel width to the channel length of each of the transistors included in the first output circuit 312 or the second output circuit 313 can be increased. Therefore, the drive current of each of the transistors included in the gate driver 300a can be increased.

[0184] Furthermore, as the drive current of each transistor included in the gate driver 300a increases, the rise time and fall time of the gate signal output from the gate driver 300a can be reduced. Therefore, each transistor included in the gate driver 300a can output a precise output value, thereby improving the stability and reliability of the gate driver 300a.

[0185] This disclosure may relate to display devices and electronic devices including display devices. For example, this disclosure may be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet computers, car navigation systems, televisions, computer monitors, laptop computers, etc.

[0186] The foregoing description is intended to be illustrative of the present disclosure and should not be construed as limiting it. Although several embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without substantially departing from the aspects of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims, and their functional equivalents are included therein. In the claims, means-plus-function clauses are intended to cover structures performing the functions as described herein, and include not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing description is intended to be illustrative of the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the appended claims, and the equivalents of the claims are included therein.

Claims

1. A gate driver, comprising: Multiple stages, each outputting two or more gate signals. Each of the plurality of levels includes: The control circuit is configured to control the voltage of the pull-up control node and the voltage of the first pull-down control node in response to an input signal and a first clock signal, and is configured to output a carry signal at the carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node. A first output circuit is configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and The second output circuit is configured to output a second gate signal at the second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

2. The gate driver according to claim 1, wherein, The control circuit includes: The first transistor includes a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a buffer node; The second transistor includes a control electrode connected to the buffer node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the pull-up control node. The third transistor includes a control electrode, a first electrode connected to the pull-up control node, and a second electrode configured to receive a second power supply voltage. The fourth transistor includes a control electrode configured to receive the second power supply voltage, a first electrode connected to the buffer node, and a second electrode connected to the first pull-down control node; The fifth transistor includes a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the carry output node; The sixth transistor includes a control electrode connected to the first pull-down control node, a first electrode connected to the carry output node, and a second electrode configured to receive the second power supply voltage; A first capacitor includes a first electrode configured to receive the first power supply voltage and a second electrode connected to the pull-up control node; and The second capacitor includes a first electrode connected to the carry output node and a second electrode connected to the first pull-down control node.

3. The gate driver according to claim 2, wherein, The control electrode of the third transistor is connected to the first pull-down control node.

4. The gate driver according to claim 2, wherein, The control electrode of the third transistor is connected to the buffer node.

5. The gate driver according to claim 2, wherein, The third transistor includes an N-channel metal-oxide-semiconductor transistor.

6. The gate driver according to claim 2, wherein, The first output circuit includes: The seventh transistor includes a control electrode configured to receive the second power supply voltage, a first electrode connected to the carry output node, and a second electrode connected to the second pull-down control node; The eighth transistor includes a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the first output node; The ninth transistor includes a control electrode connected to the second pull-down control node, a first electrode connected to the first output node, and a second electrode configured to receive a second clock signal; and The third capacitor includes a first electrode connected to the first output node and a second electrode connected to the second pull-down control node.

7. The gate driver according to claim 6, wherein, The channel width to channel length ratio of at least one of the seventh, eighth, and ninth transistors is different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

8. The gate driver according to claim 7, wherein, The ratio of the channel width to the channel length of at least one of the seventh, eighth, and ninth transistors is greater than the ratio of the channel width to the channel length of at least one of the first, second, third, fourth, fifth, and sixth transistors.

9. The gate driver according to claim 2, wherein, The second output circuit includes: The tenth transistor includes a control electrode configured to receive the second power supply voltage, a first electrode connected to the carry output node, and a second electrode connected to the third pull-down control node; The eleventh transistor includes a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the second output node; The twelfth transistor includes a control electrode connected to the third pull-down control node, a first electrode connected to the second output node, and a second electrode configured to receive a third clock signal; and The fourth capacitor includes a first electrode connected to the second output node and a second electrode connected to the third pull-down control node.

10. The gate driver according to claim 9, wherein, The channel width to channel length ratio of at least one of the tenth, eleventh, and twelfth transistors is different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

11. The gate driver of claim 10, wherein, The ratio of the channel width to the channel length of at least one of the tenth, eleventh, and twelfth transistors is greater than the ratio of the channel width to the channel length of at least one of the first, second, third, fourth, fifth, and sixth transistors.

12. A display device, comprising: Display panel, including pixels; A data driver configured to provide data voltage to the display panel; A gate driver configured to provide a gate signal to the display panel; as well as The drive controller is configured to control the data driver and the gate driver. The gate driver includes multiple stages, each outputting two or more of the gate signals.

13. The display device according to claim 12, wherein, Each of the plurality of levels includes: The control circuit is configured to control the voltage of the pull-up control node and the voltage of the first pull-down control node in response to an input signal and a first clock signal, and is configured to output a carry signal at the carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node. A first output circuit is configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and The second output circuit is configured to output a second gate signal at the second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

14. The display device according to claim 13, wherein, The control circuit includes: The first transistor includes a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a buffer node; The second transistor includes a control electrode connected to the buffer node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the pull-up control node. The third transistor includes a control electrode, a first electrode connected to the pull-up control node, and a second electrode configured to receive a second power supply voltage. The fourth transistor includes a control electrode configured to receive the second power supply voltage, a first electrode connected to the buffer node, and a second electrode connected to the first pull-down control node; The fifth transistor includes a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the carry output node; The sixth transistor includes a control electrode connected to the first pull-down control node, a first electrode connected to the carry output node, and a second electrode configured to receive the second power supply voltage; A first capacitor includes a first electrode configured to receive the first power supply voltage and a second electrode connected to the pull-up control node; and The second capacitor includes a first electrode connected to the carry output node and a second electrode connected to the first pull-down control node.

15. The display device according to claim 14, wherein, The control electrode of the third transistor is connected to the first pull-down control node.

16. The display device according to claim 14, wherein, The first output circuit includes: The seventh transistor includes a control electrode configured to receive the second power supply voltage, a first electrode connected to the carry output node, and a second electrode connected to the second pull-down control node; The eighth transistor includes a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the first output node; The ninth transistor includes a control electrode connected to the second pull-down control node, a first electrode connected to the first output node, and a second electrode configured to receive a second clock signal; and The third capacitor includes a first electrode connected to the first output node and a second electrode connected to the second pull-down control node.

17. The display device according to claim 16, wherein, The channel width to channel length ratio of at least one of the seventh, eighth, and ninth transistors is different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

18. The display device according to claim 14, wherein, The second output circuit includes: The tenth transistor includes a control electrode configured to receive the second power supply voltage, a first electrode connected to the carry output node, and a second electrode connected to the third pull-down control node; The eleventh transistor includes a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the second output node; The twelfth transistor includes a control electrode connected to the third pull-down control node, a first electrode connected to the second output node, and a second electrode configured to receive a third clock signal; and The fourth capacitor includes a first electrode connected to the second output node and a second electrode connected to the third pull-down control node.

19. The display device according to claim 18, wherein, The channel width to channel length ratio of at least one of the tenth, eleventh, and twelfth transistors is different from the channel width to channel length ratio of at least one of the first, second, third, fourth, fifth, and sixth transistors.

20. An electronic device comprising: The processor is configured to output input control signals and input image data; Display panel, including pixels; A data driver configured to provide data voltage to the display panel; A gate driver configured to provide a gate signal to the display panel; as well as The drive controller is configured to control the data driver and the gate driver based on the input control signal and the input image data. The gate driver includes multiple stages, each outputting two or more of the gate signals, and Each of the plurality of levels includes: The control circuit is configured to control the voltage of the pull-up control node and the voltage of the first pull-down control node in response to an input signal and a first clock signal, and is configured to output a carry signal at the carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node. A first output circuit is configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and the voltage of the carry output node; and The second output circuit is configured to output a second gate signal at the second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

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