Display device

Abstract

There is provided a display device including: a substrate including a first pixel circuit region and a second pixel circuit region adjacent to each other; pixel circuits on the substrate and including a first pixel circuit in the first pixel circuit region, a second pixel circuit in the second pixel circuit region; and a light emitting element connected to the pixel circuits, in which each of the pixel circuits includes: a first transistor connected to the driving voltage line and the light emitting element, and for supplying a current to the light emitting element; a second transistor connected to the data line and the first transistor; a third transistor connected to a gate and a second terminal of the first transistor; and a fourth transistor connected to a gate of the first transistor and a first initialization voltage line; and the third transistor and the fourth transistor of the first pixel circuit are in line symmetry with the third transistor and the fourth transistor of the second pixel circuit respectively.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0105707, filed on August 7, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Aspects of embodiments of the present disclosure relate to a structure of a display device. BACKGROUND

[0003] A display device can include a plurality of pixels. Each of the plurality of pixels can include a light emitting diode and a pixel circuit for controlling brightness of the light emitting diode. The pixel circuit can include a transistor and a capacitor connected to a wiring such as a data line, a gate line, and a voltage line.

[0004] Recently, display devices have become thinner and lighter in weight, and thus, can be applied to various electronic devices. As display devices have become widely used, various types of display devices are being designed.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the application, and therefore can include information that does not constitute prior art. SUMMARY

[0006] Aspects of some embodiments of the present disclosure relate to a display device having improved display quality. However, this is merely an example, and the scope of the disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows, and will be apparent from the description, or can be learned by practice of the presented embodiments of the disclosure.

[0008] According to some embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate including a first pixel circuit region and a second pixel circuit region adjacent to the first pixel circuit region along a first direction; a pixel circuit on the substrate and including a first pixel circuit in the first pixel circuit region and a second pixel circuit in the second pixel circuit region; and a light emitting element connected to the pixel circuit, wherein each of the first pixel circuit and the second pixel circuit includes: a first transistor electrically connected to a driving voltage line and the light emitting element and configured to control a current supplied to the light emitting element; a second transistor electrically connected to a data line and a first terminal of the first transistor; a third transistor electrically connected to a gate of the first transistor and a second terminal of the first transistor; and a fourth transistor electrically connected to the gate of the first transistor and a first initialization voltage line; and wherein, in a plan view, the third transistor of the first pixel circuit and the fourth transistor of the first pixel circuit are respectively line-symmetric with the third transistor of the second pixel circuit and the fourth transistor of the second pixel circuit with respect to an imaginary straight line extending in a second direction crossing the first direction.

[0009] In some embodiments, the driving voltage line and the data line can be arranged in each of the first pixel circuit region and the second pixel circuit region and extend along the second direction.

[0010] In some embodiments, the display device can further include a second initialization voltage line extending along the second direction, wherein the second initialization voltage line is on a boundary between the first pixel circuit region and the second pixel circuit region, and wherein a portion of the second initialization voltage line is in the first pixel circuit region and another portion of the second initialization voltage line is in the second pixel circuit region.

[0011] In some embodiments, the display device can further include a first gate line connected to the gate of the third transistor, wherein the first gate line includes: a first trunk portion extending along the first direction; a first branch portion branching from the first trunk portion within the first pixel circuit region and extending in the second direction; and a second branch portion branching from the first trunk portion within the second pixel circuit region and extending in the second direction.

[0012] In some embodiments, a distance from the boundary between the first pixel circuit region and the second pixel circuit region to the first branch portion can be substantially the same as a distance from the boundary between the first pixel circuit region and the second pixel circuit region to the second branch portion.

[0013] In some embodiments, the third transistor may include a first sub-transistor and a second sub-transistor connected in series, wherein the gate of the first sub-transistor may be formed in a portion of the first branch portion or a portion of the second branch portion, and the gate of the second sub-transistor may be formed in a portion of the first trunk portion.

[0014] In some embodiments, the display device may further include a second gate line connected to the gate of the fourth transistor, wherein the second gate line includes: a second trunk portion extending along a first direction; a third branch portion branching from the second trunk portion within a first pixel circuit region and extending in a second direction; and a fourth branch portion branching from the second trunk portion within a second pixel circuit region and extending in a second direction.

[0015] In some embodiments, the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the third branch portion may be approximately the same as the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the fourth branch portion.

[0016] In some embodiments, the fourth transistor may include a third sub-transistor and a fourth sub-transistor connected in series, the gate of the third sub-transistor may be formed in a portion of the second main branch, and the gate of the fourth sub-transistor may be formed in a portion of the third branch or a portion of the fourth branch.

[0017] In some embodiments, the light-emitting element may include a pixel electrode, an intermediate layer on the pixel electrode, and a counter electrode on the intermediate layer, wherein, in a plan view, the pixel electrode may be stacked with at least a portion of a third transistor and a fourth transistor.

[0018] In some embodiments, the light-emitting element may include a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode that emit light of different colors. The first and third light-emitting diodes may be arranged alternately in a first row extending in a first direction, and the second light-emitting diode may be arranged repeatedly in a second row parallel to the first row, and may be arranged between the first and third light-emitting diodes relative to the first direction.

[0019] In some embodiments, the pixel electrode that is at least partially superimposed on the third transistor and the fourth transistor may be the pixel electrode of the first light-emitting diode or the pixel electrode of the third light-emitting diode.

[0020] According to some embodiments of this disclosure, a display device is provided, the display device comprising: a substrate including a first pixel circuit region and a second pixel circuit region arranged adjacent to the first pixel circuit region along a first direction; a first gate line on the substrate and extending along the first direction; a driving voltage line extending along a second direction intersecting the first direction; a pixel circuit including a first pixel circuit in the first pixel circuit region and a second pixel circuit in the second pixel circuit region; and a light-emitting element connected to the pixel circuit and including a pixel electrode, an intermediate layer on the pixel electrode, and a counter electrode on the intermediate layer; wherein each of the first pixel circuit and the second pixel circuit includes: a driving transistor electrically connected to the driving voltage line and the light-emitting element; and a compensation transistor including a gate connected to the first gate line and connected to the gate of the driving transistor and a second terminal of the driving transistor, wherein, in a plan view, the compensation transistor of the first pixel circuit and the compensation transistor of the second pixel circuit may be linearly symmetrical to each other with respect to an imaginary straight line extending in the second direction, and a portion of the pixel electrode is superimposed on the compensation transistor.

[0021] In some embodiments, the display device may further include: a data line extending along a second direction; and a vertical initialization voltage line extending along the second direction, wherein the data line and the driving voltage line may both be in the first pixel circuit region and the second pixel circuit region, and the vertical initialization voltage line may be on the boundary between the first pixel circuit region and the second pixel circuit region, and may be above the first pixel circuit region and the second pixel circuit region.

[0022] In some embodiments, the first gate line may include: a first trunk portion extending along a first direction; a first branch portion branching from the first trunk portion within a first pixel circuit region and extending in a second direction; and a second branch portion branching from the first trunk portion within a second pixel circuit region and extending in a second direction.

[0023] In some embodiments, the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the first branch portion may be approximately the same as the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the second branch portion.

[0024] In some embodiments, the compensation transistor may include a first sub-transistor and a second sub-transistor connected in series, the gate of the first sub-transistor may be formed in a portion of a first branch portion or a portion of a second branch portion, and the gate of the second sub-transistor may be formed in a portion of a first trunk portion.

[0025] In some embodiments, a portion of the pixel electrode may cover both the first sub-transistor and the second sub-transistor.

[0026] In some embodiments, the display device may further include a second gate line and a horizontal initialization voltage line extending along a first direction. Each of the first pixel circuit and the second pixel circuit may further include an initialization transistor, which includes a gate connected to the second gate line and electrically connected to the gate of the driving transistor and the horizontal initialization voltage line. In a plan view, the initialization transistor of the first pixel circuit and the initialization transistor of the second pixel circuit may be linearly symmetrical to each other with respect to an imaginary straight line extending in the second direction.

[0027] In some embodiments, the second gate line may include: a second trunk portion extending along a first direction; a third branch portion branching from the second trunk portion within a first pixel circuit region and extending in a second direction; and a fourth branch portion branching from the second trunk portion within a second pixel circuit region and extending in a second direction.

[0028] In some embodiments, the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the third branch portion may be approximately the same as the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the fourth branch portion.

[0029] In some embodiments, the initialization transistor may include a third sub-transistor and a fourth sub-transistor connected in series, the gate of the third sub-transistor may be formed in a portion of the second main branch, and the gate of the fourth sub-transistor may be formed in a portion of the third branch or a portion of the fourth branch.

[0030] In some embodiments, a portion of the pixel electrode may cover at least one of the third and fourth sub-transistors.

[0031] In some embodiments, the semiconductor layer of the driving transistor and the semiconductor layer of the compensation transistor may be integrally formed, and the semiconductor layer of the driving transistor and the semiconductor layer of the compensation transistor may comprise silicon-based semiconductor materials.

[0032] According to some embodiments of this disclosure, an electronic device is provided, comprising: an input module configured to receive input data from a user; a memory configured to store the input data; a processor configured to perform calculations based on the input data and provide output data; and a display module configured to display an image to the user in part based on the input data and the output data. The display module includes: a substrate including a first pixel circuit region and a second pixel circuit region adjacent to the first pixel circuit region along a first direction; pixel circuits on the substrate, including the first pixel circuit in the first pixel circuit region and the second pixel circuit in the second pixel circuit region; and a light-emitting element connected to the pixel circuits. In the first pixel circuit and the second pixel circuit, each includes: a first transistor electrically connected to a driving voltage line and a light-emitting element, and configured to control the current supplied to the light-emitting element; a second transistor electrically connected to a data line and a first terminal of the first transistor; a third transistor electrically connected to the gate of the first transistor and a second terminal of the first transistor; and a fourth transistor electrically connected to the gate of the first transistor and a first initialization voltage line; and wherein, in a plan view, the third transistor of the first pixel circuit and the fourth transistor of the first pixel circuit are respectively symmetrical with respect to an imaginary straight line extending in a second direction intersecting the first direction with respect to the line of the third transistor of the second pixel circuit and the line of the fourth transistor of the second pixel circuit.

[0033] In some embodiments, the electronic device may be a smartphone. Attached Figure Description

[0034] The above and other aspects, features, and advantages of certain disclosed embodiments will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 A schematic plan view of a display device according to some embodiments of the present disclosure is shown; Figure 2 This is a schematic diagram illustrating a concept of a display device according to some embodiments of the present disclosure; Figure 3A and Figure 3B This is an equivalent circuit diagram illustrating a pixel in a display device according to some embodiments of the present disclosure; Figure 4 This is a layout diagram schematically illustrating a portion of a display device according to some embodiments of the present disclosure; Figures 5 to 9 These are all schematic illustrations of some embodiments according to this disclosure. Figure 4 A layout diagram of a portion of each layer of the display device; Figure 10 This is a layout diagram schematically illustrating a portion of a display device according to some embodiments of the present disclosure; Figure 11 This is a schematic cross-sectional view illustrating a portion of a display device according to some embodiments of the present disclosure; Figure 12 These are block diagrams of an electronic device according to some embodiments of the present disclosure; and Figure 13 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0035] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals throughout refer to the same elements. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are unnecessary for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure are omitted. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore, redundant descriptions are omitted.

[0036] When an embodiment can be implemented differently, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0037] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. Spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” and “upper” are used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, then an element or feature described as “below,” “under,” or “below” other elements or features will then be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0038] In the accompanying diagram, the x, y, and z directions are not limited to the directions corresponding to the three axes of a Cartesian coordinate system, and can be interpreted in a broader sense. For example, the x, y, and z directions can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0040] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, it can be directly on, directly connected to, or directly bonded to the other element or layer, or there can be one or more intermediary elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or indirectly electrically connected to the other layer, region, or element, with one or more intermediary layers, regions, or elements present in between. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, there can be only one element or layer between the two elements or layers, or there can be one or more intermediary elements or layers.

[0041] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “including,” and “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. When a statement such as “at least one of…” precedes a list of elements, it modifies the entire list of elements, rather than individual elements within the list. For example, the expressions “at least one of a, b and c” and “at least one of the group consisting of a, b and c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0042] As used herein, the terms “basically,” “approximately (or about),” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measurements or calculations that will be recognized by one of ordinary skill in the art. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively.

[0043] The electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate. Additionally, various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices, such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media, such as CD-ROMs or flash drives. Furthermore, those skilled in the art will recognize that, without departing from the spirit and scope of the exemplary embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant technology and / or this specification, and shall not be interpreted in an idealized or overly formal sense. In this specification, the term “on” as used in association with a component state may refer to the active state of the component, and the term “off” may refer to the deactivated state of the component. The term “on” as used in conjunction with a signal received by the component may refer to a signal used to activate the component, and the term “off” may refer to a signal used to deactivate the component. The component may be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it should be understood that the “on” voltages for P-type transistors and N-type transistors have opposite (high and low) voltage levels.

[0045] Figure 1 A schematic plan view of a display device according to some embodiments of the present disclosure is shown.

[0046] Reference Figure 1The display device 1 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display device 1 can provide a specific image by using light emitted from a plurality of pixels located in the display area DA. In some embodiments, each pixel may emit red, green, or blue light. In some other embodiments, each pixel may emit red, green, blue, or white light.

[0047] In a plan view, the display area DA can be quadrilateral. In some other embodiments, the display area DA can be a polygonal shape, a circular shape, an elliptical shape, or an irregular shape other than a quadrilateral. The display area DA can have a shape with rounded corners or square corners.

[0048] In some embodiments, the display area DA of the display device 1 may have a length in the first direction (e.g., the x direction) that is smaller than its length in the second direction (e.g., the y direction). In some other embodiments, the display area DA of the display device 1 may have a length in the first direction (e.g., the x direction) that is larger than its length in the second direction (e.g., the y direction).

[0049] The peripheral region PA may be located around the display region DA and may surround at least a portion of the display region DA. In some embodiments, the peripheral region PA may be a non-display area without positioned pixels. Various wiring, circuitry, and pads (“pads”, “solder pads”) to which printed circuit boards or driver integrated circuit (IC) chips are attached for transmitting electrical signals to be applied to the display region DA may be located in the peripheral region PA.

[0050] While the display device 1 according to some embodiments may be an organic light-emitting display device including organic light-emitting diodes, the disclosed display device 1 is not limited thereto. In some other embodiments, the disclosed display device 1 may include inorganic light-emitting diodes or may include quantum dot light-emitting diodes.

[0051] Figure 2 This is a schematic diagram illustrating a concept of a display device according to some embodiments of the present disclosure.

[0052] Reference Figure 2 According to some embodiments, the display device 1 may include a pixel region 11, a gate driving circuit 13, a data driving circuit 15, a power supply circuit 17, and a controller 19.

[0053] Pixel region 11 may correspond to display region DA (for example, see...) Figure 1 ).like Figure 2As shown, multiple gate lines GL, multiple data lines DL, and multiple pixels PX connected thereto can be arranged in pixel region 11. The multiple pixels PX can be arranged in various forms (such as stripe arrangement, penTile arrangement, diamond arrangement, and mosaic arrangement) to display an image. Each pixel PX can include an organic light-emitting diode (OLED) as a display element (e.g., a light-emitting element), and the OLED can be connected to the pixel circuitry. The pixel PX can emit, for example, red, green, blue, or white light through the OLED. Each pixel PX can be connected to at least one corresponding gate line of the multiple gate lines GL and at least one corresponding data line of the multiple data lines DL.

[0054] A pixel circuit may include a plurality of transistors and at least one capacitor. In some embodiments, the plurality of transistors included in the pixel circuit may be silicon thin-film transistors. In some other embodiments, the plurality of transistors included in the pixel circuit may be oxide thin-film transistors. In still other embodiments, one or more of the plurality of transistors included in the pixel circuit may be oxide thin-film transistors, and one or more of the plurality of transistors included in the pixel circuit may be silicon thin-film transistors.

[0055] A silicon thin-film transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor in which the semiconductor layer includes polycrystalline silicon. An oxide thin-film transistor can be a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the semiconductor layer includes oxide. However, these are examples, and silicon thin-film transistors and oxide thin-film transistors are not limited thereto.

[0056] Each gate line GL can extend in the x-direction (e.g., row direction) and can be connected to a pixel PX located in the same row. Gate lines GL can be configured to transmit gate signals to pixels PX in the same row. Each data line DL can extend in the y-direction (e.g., column direction) and can be connected to pixels PX located in the same column. Each data line DL can be configured to transmit data signals to each pixel PX in the same column synchronously with the gate signals.

[0057] In some embodiments, the peripheral region PA (e.g., see...) Figure 1 This can be a non-display area where no pixels PX are arranged. It is configured such that transmission will be applied to the display area DA (e.g., see...). Figure 1 Various wires for electrical signals, external circuitry electrically connected to pixel circuitry, and pads to which printed circuit boards or driver integrated circuit (IC) chips are attached can be located in the peripheral area PA (e.g., see...). Figure 1 In, for example, gate drive circuit 13, data drive circuit 15, power supply circuit 17 and controller 19 may be located in the peripheral region PA (e.g., see...).Figure 1 )middle.

[0058] Gate drive circuit 13 can be connected to multiple gate lines GL and can be configured to generate gate signal GS in response to drive control signal GCS from controller 19, and sequentially supply gate signal GS to gate lines GL. Gate lines GL can be connected to the gates of transistors included in pixel PX. Gate signal GS can be a gate control signal for controlling the on and off states (e.g., for turning on or off transistors) of transistors having gates connected to gate lines GL. Gate signal GS can be a square wave signal including a gate on voltage that can turn on transistors and a gate off voltage that can turn off transistors. In some embodiments, the gate on voltage can be a high-level voltage or a low-level voltage.

[0059] although Figure 2 A pixel PX connected to a gate line GL is shown, but this is merely an example, and the pixel PX can be connected to two or more gate lines, and the gate drive circuit 13 can be configured to supply two or more gate signals that differ in the timing of applying the gate turn-on voltage to the corresponding gate lines.

[0060] The data driving circuit 15 can be connected to multiple data lines DL and can be configured to supply data signals DATA to the data lines DL in response to a drive control signal DCS from the controller 19. The data signal DATA supplied to the data lines DL can be supplied to the pixel PX to which the gate signal GS is supplied. The data driving circuit 15 can be configured to convert grayscale input image data from the controller 19 into a data signal DATA in the form of voltage or current.

[0061] The power supply circuit 17 can be configured to generate a voltage for driving the pixel PX in response to a drive control signal PCS from the controller 19. The power supply circuit 17 can be configured to generate a drive voltage ELVDD and a common voltage ELVSS, and supply them to the pixel PX. The drive voltage ELVDD can be a high-level voltage supplied to a terminal of a drive transistor connected to a first electrode (e.g., a pixel electrode or anode) of the display element included in the pixel PX. The common voltage ELVSS can be a low-level voltage supplied to a second electrode (e.g., a counter electrode or cathode) of the display element included in the pixel PX.

[0062] The controller 19 can generate drive control signals GCS, DCS, and PCS based on signals input from an external source, and supply them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The drive control signal GCS output to the gate drive circuit 13 may include multiple clock signals and a gate start signal. The drive control signal DCS output to the data drive circuit 15 may include multiple clock signals and a data start signal.

[0063] Display device 1 may include a display panel, and the display panel may include a substrate. Pixels PX may be arranged in the display area DA of the substrate (e.g., see...). Figure 1 In the display area DA of the substrate (e.g., see...). Figure 1 During the process of forming transistors constituting pixel circuits in the substrate, transistors can be formed in the peripheral region PA of the substrate (e.g., see...). Figure 2 The gate drive circuit 13 may be formed directly within the substrate. The data drive circuit 15, power supply circuit 17, and controller 19 may each be a separate IC chip or a single IC chip, and may be disposed on a flexible printed circuit board (FPCB) electrically connected to a pad disposed on one side of the substrate. In some other embodiments, the data drive circuit 15, power supply circuit 17, and controller 19 may be disposed directly on the substrate in a chip-on-glass (COG) or chip-on-plastic (COP) manner.

[0064] Figure 3A and Figure 3B This is an equivalent circuit diagram of a pixel in a display device according to some embodiments of the present disclosure.

[0065] Reference Figure 3A and Figure 3B The pixel circuit PC may include first transistors T1 through T7 and a storage capacitor Cst. Depending on the transistor type (e.g., P-type or N-type) and / or operating conditions, the first terminal of each of the first transistors T1 through T7 may be a source or a drain, and the second terminal may be a different terminal from the first terminal. For example, when the first terminal is a source, the second terminal may be a drain. The first transistor T1 may be a drive transistor in which the magnitude of the source-drain current is determined based on the gate-source voltage, and the second transistors T2 through T7 may be switching transistors for transmitting signals.

[0066] The pixel circuit PC can be connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GILn-1 for transmitting the (n-1)th second gate signal GIn-1, the second gate line GILn for transmitting the nth second gate signal GIn, the light emission control line EML for transmitting the emission control signal EM, the data line DL for transmitting the data signal DATA, the drive voltage line PL for transmitting the drive voltage ELVDD, the first initialization voltage line VL1 for transmitting the first initialization voltage VINT, and the second initialization voltage line VL2 for transmitting the second initialization voltage VAINT.

[0067] The first transistor T1 can be electrically connected between the drive voltage line PL and the light-emitting diode ED. The first transistor T1 may include: a first terminal electrically connected to the drive voltage line PL via a fifth transistor T5; a second terminal electrically connected to the light-emitting diode ED via a sixth transistor T6; and a gate electrode connected to a storage capacitor Cst. The first transistor T1 can be configured to receive a data signal DATA according to the switching operation of the second transistor T2, and can supply drive current to the light-emitting diode ED. That is, the first transistor T1 can be defined as a drive transistor.

[0068] A second transistor T2 can be electrically connected between the data line DL and the first terminal of the first transistor T1. The second transistor T2 may include: a gate electrode connected to the first gate line GWL; a first terminal connected to the data line DL; and a second terminal connected to the first terminal of the first transistor T1. The second terminal of the second transistor T2 can be connected to the first terminal of the first transistor T1 and can be connected to the drive voltage line PL via a fifth transistor T5. The second transistor T2 can be turned on according to (e.g., in response to) a first gate signal GW received through the first gate line GWL to perform a switching operation for transmitting the data signal DATA transmitted to the data line DL to the first transistor T1. That is, the second transistor T2 can be defined as a switching transistor.

[0069] A third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second terminal of the first transistor T1. The third transistor T3 may include: a first terminal connected to the second terminal of the first transistor T1; a second terminal connected to the gate electrode of the first transistor T1; and a gate electrode connected to a first gate line GWL. The third transistor T3 can be turned on according to (e.g., in response to) a first gate signal GW transmitted through the first gate line GWL, to connect the gate electrode and the second terminal of the first transistor T1 to each other, thereby diode-connecting the first transistor T1. That is, the third transistor can be defined as a compensation transistor.

[0070] The third transistor T3 may include a first sub-transistor T3-1 and a second sub-transistor T3-2. The first sub-transistor T3-1 and the second sub-transistor T3-2 may be connected in series between the gate electrode of the first transistor T1 and the second terminal of the first transistor T1.

[0071] The first sub-transistor T3-1 may include: a first terminal connected to the second terminal of the second sub-transistor T3-2; a second terminal connected to the gate electrode of the first transistor T1; and a gate electrode connected to the first gate line GWL. The second terminal of the first sub-transistor T3-1 may correspond to the second terminal of the third transistor T3. The second sub-transistor T3-2 may include: a first terminal connected to the second terminal of the first transistor T1; a second terminal connected to the first terminal of the first sub-transistor T3-1; and a gate electrode connected to the first gate line GWL. The first terminal of the second sub-transistor T3-2 may correspond to the first terminal of the third transistor T3.

[0072] A fourth transistor T4 can be electrically connected between the gate electrode of the first transistor T1 and the first initialization voltage line VL1. The fourth transistor T4 may include: a first terminal connected to the gate electrode of the first transistor T1; a second terminal connected to the first initialization voltage line VL1 to which the first initialization voltage VINT is transmitted; and a gate electrode connected to the (n-1)th second gate line GILn-1. The first terminal of the fourth transistor T4 can be connected to the gate electrode of the first transistor T1, the second terminal of the third transistor T3, and the storage capacitor Cst. The fourth transistor T4 can be turned on according to (e.g., in response to) the (n-1)th second gate signal GIn-1 transmitted through the (n-1)th second gate line GILn-1 to transmit the first initialization voltage VINT to the gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1. That is, the fourth transistor T4 can be defined as a first initialization transistor.

[0073] The fourth transistor T4 may include a third sub-transistor T4-1 and a fourth sub-transistor T4-2. The third sub-transistor T4-1 and the fourth sub-transistor T4-2 may be connected in series between the gate electrode of the first transistor T1 and the first initialization voltage line VL1.

[0074] The third sub-transistor T4-1 may include: a first terminal connected to the gate electrode of the first transistor T1; a second terminal connected to the fourth sub-transistor T4-2; and a gate electrode connected to the (n-1)th second gate line GILn-1. The first terminal of the third sub-transistor T4-1 may correspond to the first terminal of the fourth transistor T4. The fourth sub-transistor T4-2 may include: a first terminal connected to the third sub-transistor T4-1; a second terminal connected to the first initialization voltage line VL1; and a gate electrode connected to the (n-1)th second gate line GILn-1. The second terminal of the fourth sub-transistor T4-2 may correspond to the second terminal of the fourth transistor T4.

[0075] The fifth transistor T5 can be electrically connected between the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include: a first terminal connected to the drive voltage line PL; a second terminal connected to the first terminal of the first transistor T1; and a gate electrode connected to the light emission control line EML.

[0076] The sixth transistor T6 can be electrically connected between the first transistor T1 and the light-emitting diode ED. The sixth transistor T6 may include: a first terminal connected to the first transistor T1; a second terminal connected to the pixel electrode of the light-emitting diode ED; and a gate electrode connected to the light-emitting control line EML.

[0077] The fifth transistor T5 and the sixth transistor T6 can be turned on concurrently (e.g., simultaneously or substantially simultaneously) according to (e.g., in response to) the emitter control signal EM transmitted through the emitter control line EML, such that the drive voltage ELVDD is transmitted to the light-emitting diode ED and the drive current flows through the light-emitting diode ED. That is, the fifth transistor T5 can be defined as the drive control transistor and the sixth transistor T6 can be defined as the emitter control transistor.

[0078] Reference Figure 3A In some embodiments, a seventh transistor T7 may be connected between the second initialization voltage line VL2 and the light-emitting diode ED. The seventh transistor T7 may include: a first terminal connected to the second initialization voltage line VL2, through which the second initialization voltage VAINT is transmitted; a second terminal connected to the light-emitting diode ED; and a gate electrode connected to the nth second gate line GILn. The second terminal of the seventh transistor T7 may be connected to the sixth transistor T6 and the light-emitting diode ED. The seventh transistor T7 may be turned on according to (e.g., in response to) the nth second gate signal GIn transmitted via the nth second gate line GILn to initialize the pixel electrode of the light-emitting diode ED. That is, the seventh transistor T7 may be defined as a second initialization transistor.

[0079] In some other embodiments, reference is made to Figure 3BThe seventh transistor T7 can be electrically connected between the fourth transistor T4 and the sixth transistor T6. The seventh transistor T7 may include: a first terminal connected to the fourth transistor T4; a second terminal connected to the sixth transistor T6; and a gate electrode connected to the nth second gate line GILn. In this case, the first terminal of the seventh transistor T7 can be electrically connected to the first initialization voltage line VL1 together with the fourth transistor T4, and the second terminal of the seventh transistor T7 can be electrically connected to the light-emitting diode ED together with the sixth transistor T6.

[0080] exist Figure 3A and Figure 3B In this embodiment, the fourth transistor T4 and the seventh transistor T7 are connected to the (n-1)th second gate line GILn-1 and the nth second gate line GILn, respectively, but the disclosure is not limited thereto. In some other embodiments, both the fourth transistor T4 and the seventh transistor T7 may be connected to the (n-1)th second gate line GILn-1 and may be driven according to (e.g., in response to) the (n-1)th second gate signal GIn-1.

[0081] The storage capacitor Cst may include a first electrode and a second electrode. The first electrode of the storage capacitor Cst may be connected to the gate electrode of the first transistor T1, the second terminal of the third transistor T3, and the first terminal of the fourth transistor T4. The second electrode of the storage capacitor Cst may be connected to the drive voltage line PL.

[0082] A light-emitting diode (ED) may include a pixel electrode (e.g., an anode) and a counter electrode (e.g., a cathode) facing the pixel electrode. The counter electrode of the ED may receive a common voltage ELVSS. The ED may receive a drive current from a first transistor T1 and may emit light to display an image.

[0083] Pixel circuit PC is not limited to reference Figure 3A and Figure 3B The number of transistors and storage capacitors described, as well as the circuit design, are shown, and the number and circuit design can vary. The driving display area DA can be provided in the same or different ways (e.g., see...). Figure 1 The pixel circuit PC of pixel PX in ).

[0084] Figure 4 This is a layout diagram schematically illustrating a portion of a display device according to some embodiments of the present disclosure. Figures 5 to 9 These are all schematic illustrations of some embodiments according to this disclosure. Figure 4 A layout diagram of a portion of each layer of the display device.

[0085] First, refer to Figure 4The display device 1 may include a first pixel circuit region PCA1 in which a first pixel circuit PC1 is disposed, and a second pixel circuit region PCA2 in which a second pixel circuit PC2 is disposed. A layer or component of the display device 1 (e.g., substrate 100) may correspondingly include the first pixel circuit region PCA1 and the second pixel circuit region PCA2. The first pixel circuit region PCA1 and the second pixel circuit region PCA2 may be arranged side-by-side in a first direction (e.g., the x-direction). That is, the first pixel circuit PC1 and the second pixel circuit PC2 may be pixel circuits disposed in the same pixel circuit row. The first pixel circuit PC1 and the second pixel circuit PC2 may constitute a single pixel circuit unit. The unit region including the first pixel circuit region PCA1 and the second pixel circuit region PCA2 may be repeatedly arranged in the first direction (e.g., the x-direction) and the second direction (e.g., the y-direction).

[0086] Each of the first pixel circuit PC1 and the second pixel circuit PC2 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst. Each of the first pixel circuit PC1 and the second pixel circuit PC2 may also include a conductive pattern for connecting the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst to gate lines, voltage lines, data lines and pixel electrodes.

[0087] Unless otherwise described, each of the first pixel circuit PC1 and the second pixel circuit PC2 may include substantially the same or similar components. Although the components of the first pixel circuit PC1 have been described primarily for ease of explanation, components corresponding to those of the first pixel circuit PC1 may be included in the second pixel circuit PC2.

[0088] The first pixel circuit PC1 and the second pixel circuit PC2 may have a flip structure (e.g., a specular reflection structure or a mirror structure). For example, the first pixel circuit PC1 and the second pixel circuit PC2 may be substantially line-symmetrical to each other with respect to an imaginary straight line IML extending in a second direction (e.g., the y-direction) along the boundary between the first pixel circuit PC1 and the second pixel circuit PC2. For example, in the first pixel circuit PC1, the second transistor T2 may be located to the left (-x direction) relative to the first transistor T1, and in the second pixel circuit PC2, the second transistor T2 may be located to the right (+x direction) relative to the first transistor T1.

[0089] In some embodiments, the third transistor T3 of the first pixel circuit PC1 may be symmetrical with respect to an imaginary straight line IML extending in the second direction (e.g., the y-direction) with respect to the third transistor T3 of the second pixel circuit PC2. Similarly, the fourth transistor T4 of the first pixel circuit PC1 may be symmetrical with respect to an imaginary straight line IML extending in the second direction (e.g., the y-direction) with respect to the fourth transistor T4 of the second pixel circuit PC2. (Refer to...) Figures 5 to 9 The flip structure described above is described in detail.

[0090] The first pixel circuit PC1 and the second pixel circuit PC2 can be connected to gate lines, data lines, and voltage lines. The gate lines may include a first gate line GWL, a second gate line GIL, and a light emission control line EML. The first gate line GWL, the second gate line GIL, and the light emission control line EML may extend in a first direction (e.g., the x-direction).

[0091] The voltage lines may include a first initialization voltage line VL1, a second initialization voltage line VL2, and a driving voltage line PL. The first initialization voltage line VL1 may extend along a first direction (e.g., the x-direction), and the second initialization voltage line VL2 and the driving voltage line PL may extend along a second direction (e.g., the y-direction). The driving voltage line PL may include a first driving voltage line PL1 and a second driving voltage line PL2. The first driving voltage line PL1 may be connected to a first pixel circuit PC1, and the second driving voltage line PL2 may be connected to a second pixel circuit PC2.

[0092] In some embodiments, the first pixel circuit PC1 and the second pixel circuit PC2 may share a second initialization voltage line VL2. For example, the second initialization voltage line VL2 extending in a second direction (e.g., the y-direction) may be disposed on the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2. Therefore, a portion of the second initialization voltage line VL2 may be disposed in the first pixel circuit region PCA1 to connect to the first pixel circuit PC1, and other portions of the second initialization voltage line VL2 may be disposed in the second pixel circuit region PCA2 to connect to the second pixel circuit PC2.

[0093] The data line DL may include a first data line DL1 and a second data line DL2. The data line DL may be configured to extend in a second direction (e.g., the y-direction). The first data line DL1 may be disposed in a first pixel circuit region PCA1 to connect to the first pixel circuit PC1, and the second data line DL2 may be disposed in a second pixel circuit region PCA2 to connect to the second pixel circuit PC2.

[0094] Reference Figure 5The first semiconductor layer 1100 may be disposed on the substrate. The first semiconductor layer 1100 may include a silicon-based semiconductor material, such as amorphous silicon or polycrystalline silicon.

[0095] The first semiconductor layer 1100 may include a first semiconductor pattern 1110. For ease of explanation, the first semiconductor pattern 1110 disposed in the first pixel circuit region PCA1 may be referred to as the first-1 semiconductor pattern 1110a, and the first semiconductor pattern 1110 disposed in the second pixel circuit region PCA2 may be referred to as the first-2 semiconductor pattern 1110b.

[0096] Reference Figure 6 The first conductive layer 1200 may be disposed on the first semiconductor layer 1100. The first conductive layer 1200 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or a single layer including the above materials. The first conductive layer 1200 may include a first gate line GWL, a second gate line GIL, a light-emitting control line EML, and a first conductive pattern 1230.

[0097] The first conductive pattern 1230 may have an isolated shape (island-shaped) in the planar view. The first conductive pattern 1230 may include a first-1 conductive pattern 1230a disposed in the first pixel circuit region PCA1 and a first-2 conductive pattern 1230b disposed in the second pixel circuit region PCA2. The first gate line GWL, the second gate line GIL, and the light emission control line EML may extend in a first direction (e.g., the x-direction) to pass through the first pixel circuit region PCA1 and the second pixel circuit region PCA2. The first gate line GWL may transmit a first gate signal GW to the first pixel circuit PC1 and the second pixel circuit PC2 disposed in the same pixel circuit row (e.g., see...). Figure 3A The second gate line GIL can transmit second gate signals GIn and GIn-1 to the first pixel circuit PC1 and the second pixel circuit PC2 located in the same pixel circuit row (for example, see...). Figure 3A ).

[0098] In some embodiments, the first gate line GWL may include a first trunk portion 1210 extending in a first direction (e.g., the x-direction), a first branch portion 1211a branching from the first trunk portion 1210 in the first pixel circuit region PCA1 and extending in a second direction (e.g., the y-direction), and a second branch portion 1211b branching from the first trunk portion 1210 in the second pixel circuit region PCA2 and extending in the second direction (e.g., the y-direction). Similarly, the second gate line GIL may include a second trunk portion 1220 extending in a first direction (e.g., the x-direction), a third branch portion 1221a branching from the second trunk portion 1220 in the first pixel circuit region PCA1 and extending in the second direction (e.g., the y-direction), and a fourth branch portion 1221b branching from the second trunk portion 1220 in the second pixel circuit region PCA2 and extending in the second direction (e.g., the y-direction).

[0099] For ease of explanation, Figure 7 A first semiconductor layer 1100 and a first conductive layer 1200 stacked on top of each other are shown. (Refer to...) Figure 7 Each of the first-1 semiconductor pattern 1110a and the first-2 semiconductor pattern 1110b may include a first channel region A1 of the first transistor T1, a second channel region A2 of the second transistor T2, a third-1 channel region A3 of the first sub-transistor T3-1, a third-2 channel region A3' of the second sub-transistor T3-2, a fourth-1 channel region A4 of the third sub-transistor T4-1, a fourth-2 channel region A4' of the fourth sub-transistor T4-2, a fifth channel region A5 of the fifth transistor T5, a sixth channel region A6 of the sixth transistor T6, and a seventh channel region A7 of the seventh transistor T7. The source and drain regions may be located on either side of each of the first channel regions A1 to the seventh channel regions A7. The first channel region A1 to the seventh channel region A7 of the first pixel circuit PC1 can be integrally disposed to form the first-1 semiconductor pattern 1110a, and the first channel region A1 to the seventh channel region A7 of the second pixel circuit PC2 can be integrally disposed to form the first-2 semiconductor pattern 1110b.

[0100] The first channel region A1 of the first transistor T1 may be stacked with the first conductive pattern 1230. In some embodiments, the first channel region A1 of the first-1 semiconductor pattern 1110a and the first channel region A1 of the first-2 semiconductor pattern 1110b may have a curved shape. However, the disclosure is not limited thereto, and in some other embodiments, the first channel region A1 of the first-1 semiconductor pattern 1110a and the first channel region A1 of the first-2 semiconductor pattern 1110b may have a linear shape. The first conductive pattern 1230 may be the first gate electrode G1 of the first transistor T1. The first source region S1 and the first drain region D1 may be disposed on both sides of the first channel region A1 of the first transistor T1.

[0101] The second channel region A2 of the second transistor T2 can be stacked with a portion of the first gate line GWL. The portion of the first gate line GWL that is stacked with the second channel region A2 can be the second gate electrode G2 of the second transistor T2. The second source region S2 and the second drain region D2 can be respectively disposed on both sides of the second channel region A2 of the second transistor T2. The first source region S1 of the first transistor T1 can be disposed between the first channel region A1 of the first transistor T1 and the second channel region A2 of the second transistor T2.

[0102] The third transistor T3 may include a first sub-transistor T3-1 and a second sub-transistor T3-2. The 3-1 channel region A3 of the first sub-transistor T3-1 and the 3-2 channel region A3' of the second sub-transistor T3-2 may be superimposed on a portion of the first gate line GWL. For example, the portion of the first branch 1211a of the first gate line GWL superimposed on the 3-1 channel region A3 may be the 3-1 gate electrode G3 of the first sub-transistor T3-1. The portion of the first main branch 1210 of the first gate line GWL superimposed on the 3-2 channel region A3' may be the 3-2 gate electrode G3' of the second sub-transistor T3-2. The 3-1 source region S3 and the 3-1 drain region D3 may be respectively disposed on both sides of the 3-1 channel region A3 of the first sub-transistor T3-1. The 3-2 source region S3' and the 3-2 drain region D3' may be respectively disposed on both sides of the 3-2 channel region A3' of the second sub-transistor T3-2.

[0103] In some embodiments, the third transistor T3 of the first pixel circuit PC1 and the third transistor T3 of the second pixel circuit PC2 may have a flip structure. That is, the third transistor T3 of the first pixel circuit PC1 and the third transistor T3 of the second pixel circuit PC2 may be linearly symmetrical to each other with respect to an imaginary straight line IML disposed at the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2. For example, the first sub-transistor T3-1 of the first pixel circuit PC1 may be linearly symmetrical to the first sub-transistor T3-1 of the second pixel circuit PC2, and the second sub-transistor T3-2 of the first pixel circuit PC1 may be linearly symmetrical to the second sub-transistor T3-2 of the second pixel circuit PC2. For example, the distance from the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 to the first branch portion 1211a may be the same as or substantially the same as the distance from the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 to the second branch portion 1211b.

[0104] Relative to the first direction (e.g., the x-direction), the third transistor T3 can be positioned closer to the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 compared to the second transistor T2. For example, the third transistor T3 of the first pixel circuit PC1 can be positioned to the right of the second transistor T2 in the first direction (e.g., the x-direction), and the third transistor T3 of the second pixel circuit PC2 can be positioned to the left of the second transistor T2 in the first direction (e.g., the x-direction).

[0105] The fourth transistor T4 may include a third sub-transistor T4-1 and a fourth sub-transistor T4-2. The 4-1 channel region A4 of the third sub-transistor T4-1 and the 4-2 channel region A4' of the fourth sub-transistor T4-2 may be stacked with a portion of the second gate line GIL. For example, the portion of the second main branch 1220 of the second gate line GIL that is stacked with the 4-1 channel region A4 may be the 4-1 gate electrode G4 of the third sub-transistor T4-1. The portion of the third branch 1221a of the second gate line GIL that is stacked with the 4-2 channel region A4' may be the 4-2 gate electrode G4' of the fourth sub-transistor T4-2. The 4-1 source region S4 and the 4-1 drain region D4 may be respectively disposed on both sides of the 4-1 channel region A4 of the third sub-transistor T4-1. The 4-2 source region S4' and the 4-2 drain region D4' may be respectively disposed on both sides of the 4-2 channel region A4' of the fourth sub-transistor T4-2.

[0106] In some embodiments, the fourth transistor T4 of the first pixel circuit PC1 and the fourth transistor T4 of the second pixel circuit PC2 may have a flip structure. That is, the fourth transistor T4 of the first pixel circuit PC1 and the fourth transistor T4 of the second pixel circuit PC2 may be linearly symmetrical to each other with respect to an imaginary straight line IML disposed at the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2. For example, the third sub-transistor T4-1 of the first pixel circuit PC1 may be linearly symmetrical to the third sub-transistor T4-1 of the second pixel circuit PC2, and the fourth sub-transistor T4-2 of the first pixel circuit PC1 may be linearly symmetrical to the fourth sub-transistor T4-2 of the second pixel circuit PC2. For example, the distance from the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 to the third branch portion 1221a may be the same as or substantially the same as the distance from the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 to the fourth branch portion 1221b.

[0107] The fifth channel region A5 of the fifth transistor T5 and the sixth channel region A6 of the sixth transistor T6 can be superimposed on a portion of the light-emitting control line EML. The portion of the light-emitting control line EML superimposed on the fifth channel region A5 can be the fifth gate electrode G5 of the fifth transistor T5, and the portion of the light-emitting control line EML superimposed on the sixth channel region A6 can be the sixth gate electrode G6 of the sixth transistor T6. The fifth source region S5 and the fifth drain region D5 can be respectively disposed on both sides of the fifth channel region A5 of the fifth transistor T5. The sixth source region S6 and the sixth drain region D6 can be respectively disposed on both sides of the sixth channel region A6 of the sixth transistor T6.

[0108] Relative to the first direction (e.g., the x-direction), the sixth transistor T6 can be positioned closer to the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 compared to the fifth transistor T5. For example, the sixth transistor T6 of the first pixel circuit PC1 can be positioned to the right of the fifth transistor T5 in the first direction (e.g., the x-direction), and the sixth transistor T6 of the second pixel circuit PC2 can be positioned to the left of the fifth transistor T5 in the first direction (e.g., the x-direction).

[0109] The seventh channel region A7 of the seventh transistor T7 can be stacked with a portion of the second gate line GIL. The portion of the second gate line GIL that is stacked with the seventh channel region A7 can be the seventh gate electrode G7 of the seventh transistor T7. For example, the seventh gate electrode G7 can be a portion of the second main branch 1220. The seventh source region S7 and the seventh drain region D7 can be respectively disposed on both sides of the seventh channel region A7 of the seventh transistor T7.

[0110] Relative to the first direction (e.g., the x-direction), the seventh transistor T7 can be positioned closer to the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 compared to the fourth transistor T4. For example, the seventh transistor T7 of the first pixel circuit PC1 can be positioned to the right of the fourth transistor T4 in the first direction (e.g., the x-direction), and the seventh transistor T7 of the second pixel circuit PC2 can be positioned to the left of the fourth transistor T4 in the first direction (e.g., the x-direction).

[0111] Reference Figure 8 The second conductive layer 1300 may be disposed on the first conductive layer 1200. The second conductive layer 1300 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or a single layer including the above materials. The second conductive layer 1300 may include a first initialization voltage line VL1, a second conductive pattern 1310, and a third conductive pattern 1320.

[0112] The first initialization voltage line VL1 may extend in a first direction (e.g., the x-direction) and pass through the first pixel circuit region PCA1 and the second pixel circuit region PCA2. The first initialization voltage line VL1 may transmit a first initialization voltage VINT to the first pixel circuit PC1 and the second pixel circuit PC2 disposed in the same pixel circuit row (e.g., see...). Figure 3A The first initialization voltage line VL1 can also be called the horizontal initialization voltage line.

[0113] The second conductive pattern 1310 may extend in a first direction (e.g., the x-direction) and pass through the first pixel circuit region PCA1 and the second pixel circuit region PCA2. The second conductive pattern 1310 may include a first main body portion 1310a disposed in the first pixel circuit region PCA1, a second main body portion 1310b disposed in the second pixel circuit region PCA2, and a horizontal connecting portion 1310c connecting the first main body portion 1310a and the second main body portion 1310b.

[0114] The first body portion 1310a and the second body portion 1310b may be superimposed on the first conductive pattern 1230 in a planar view to form a storage capacitor Cst (e.g., see...). Figure 4 For example, the first conductive pattern 1230 can be used as a storage capacitor Cst (e.g., see...). Figure 4 The first electrode of the first body portion 1310a can be used as a storage capacitor Cst (e.g., see...). Figure 4 The second electrode of the capacitor is also present. Similarly, the second body portion 1310b can also be used as a storage capacitor Cst (e.g., see...). Figure 4The second electrode of the first body portion 1310a and the second body portion 1310b may define a first hole 1310H that exposes a portion of the first conductive pattern 1230.

[0115] The third conductive pattern 1320 may have an isolated shape in the planar view. The third conductive pattern 1320 may be disposed on the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2. For example, the third conductive pattern 1320 may be shared by the first pixel circuit PC1 and the second pixel circuit PC2. The third conductive pattern 1320 may be stacked with a common region of the first semiconductor layer 1100 and may form a stable capacitor, the common region being disposed between the 3-1 source region S3 of the first sub-transistor T3-1 and the 3-2 drain region D3' of the second sub-transistor T3-2 (e.g., see...). Figure 7 The stabilizing capacitor can hold the second terminal of the first sub-transistor T3-1 and the first terminal of the second sub-transistor T3-2 (for example, see...). Figure 7 The relatively constant voltage level of the third transistor T3. Therefore, the stabilizing capacitor can reduce the leakage current of the third transistor T3 and improve the performance of the third transistor T3 (e.g., see...). Figure 7 (performance)

[0116] Reference Figure 9 The third conductive layer 1400 may be disposed on the second conductive layer 1300. The third conductive layer 1400 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be a multilayer or a single layer comprising the above materials. The third conductive layer 1400 may include a data line DL, a drive voltage line PL, a second initialization voltage line VL2, a fourth conductive pattern 1410, a fifth conductive pattern 1420, and a sixth conductive pattern 1430. The fourth conductive pattern 1410, the fifth conductive pattern 1420, and the sixth conductive pattern 1430 may have isolated shapes in a planar view (e.g., they may be spaced apart from each other).

[0117] The fourth conductive pattern 1410 may be a connection electrode that connects the first gate electrode G1 of the first transistor T1, the third-first drain region D3 of the first sub-transistor T3-1, and the fourth-first source region S4 of the third sub-transistor T4-1. The fourth conductive pattern 1410 may be connected to the first semiconductor pattern 1110 via the first contact hole CNT1a, and to the first conductive pattern 1230 via the first contact hole CNT1b. The fourth conductive pattern 1410 may include a fourth-first conductive pattern 1410a disposed in the first pixel circuit region PCA1 and a fourth-second conductive pattern 1410b disposed in the second pixel circuit region PCA2. The fourth-first conductive pattern 1410a and the fourth-second conductive pattern 1410b may be linearly symmetrical with respect to the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2.

[0118] The fifth conductive pattern 1420 may be a connection electrode connecting the 4-2nd drain region D4' of the fourth sub-transistor T4-2 to the first initialization voltage line VL1. The fifth conductive pattern 1420 may be connected to the first semiconductor pattern 1110 via the 2-1st contact hole CNT2a, and to the first initialization voltage line VL1 via the 2-2nd contact hole CNT2b. The fifth conductive pattern 1420 may include a 5-1st conductive pattern 1420a disposed in the first pixel circuit region PCA1 and a 5-2nd conductive pattern 1420b disposed in the second pixel circuit region PCA2. The 5-1st conductive pattern 1420a and the 5-2nd conductive pattern 1420b may be linearly symmetrical with respect to the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2.

[0119] The sixth conductive pattern 1430 may be the sixth drain region D6 of the sixth transistor T6, the seventh drain region D7 of the seventh transistor T7, and the pixel electrode 210 (for example, see...). Figure 10 The sixth conductive pattern 1430 may include a 6-1 conductive pattern 1430a disposed in the first pixel circuit region PCA1 and a 6-2 conductive pattern 1430b disposed in the second pixel circuit region PCA2. The sixth conductive pattern 1430 can be connected to the first semiconductor pattern 1110 through the 3-1 contact hole CNT3a, and can be connected to the pixel electrode 210 through the 3-2 contact hole CNT3b (for example, see...). Figure 10 ).

[0120] The data line DL can extend in a second direction (e.g., the y-direction). The data line DL may include a first data line DL1 disposed in the first pixel circuit region PCA1 and a second data line DL2 disposed in the second pixel circuit region PCA2. The data line DL can be connected to the second source region S2 of the second transistor T2 through the fourth contact hole CNT4.

[0121] The driving voltage line PL may extend in a second direction (e.g., the y-direction). The driving voltage line PL may include a first driving voltage line PL1 disposed in the first pixel circuit region PCA1 and a second driving voltage line PL2 disposed in the second pixel circuit region PCA2. The driving voltage line PL can be connected to the fifth source region S5 of the fifth transistor T5 through the 5-1 contact hole CNT5a, and can be connected to the first conductive pattern 1230 through the 5-2 contact hole CNT5b. For example, the first conductive pattern 1230 can be used as a storage capacitor Cst (e.g., see...). Figure 3A The first electrode of ).

[0122] In some embodiments, compared to the data line DL, the driving voltage line PL can be positioned relatively closer to the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2. For example, compared to the first driving voltage line PL1, the first data line DL1 can be positioned further to the left (in the -x direction) of the first pixel circuit PC1, and compared to the second driving voltage line PL2, the second data line DL2 can be positioned further to the right (in the +x direction) of the second pixel circuit PC2.

[0123] The second initialization voltage line VL2 can extend in a second direction (e.g., the y-direction). Therefore, the second initialization voltage line VL2 can be referred to as the vertical initialization voltage line. The second initialization voltage line VL2 can be positioned above the first pixel circuit region PCA1 and the second pixel circuit region PCA2. For example, the first pixel circuit PC1 and the second pixel circuit PC2 can share a single second initialization voltage line VL2. The second initialization voltage line VL2 can be positioned on the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2. For example, a portion of the second initialization voltage line VL2 can be positioned in the first pixel circuit region PCA1, and another portion of the second initialization voltage line VL2 can be positioned in the second pixel circuit region PCA2. The second initialization voltage line VL2 can be connected to the seventh source region S7 of the seventh transistor T7 through the 6-1 contact hole CNT6a, and can be connected to the third conductive pattern 1320 through the 6-2 contact hole CNT6b.

[0124] Figure 10 This is a layout diagram schematically illustrating a portion of a display device according to some embodiments of the present disclosure. For example,Figure 10 This schematically shows that the pixel electrode 210 is located in... Figure 4 A diagram of the structure on a portion of the display device 1 shown.

[0125] Reference Figure 10 The pixel electrode 210 may be disposed on the third conductive layer 1400. The pixel electrode 210 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or compounds thereof (e.g., alloys or combinations thereof), and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may include ITO / Ag / ITO. The pixel electrode 210 may include a first pixel electrode 210a, a second pixel electrode 210b, and a third pixel electrode 210c.

[0126] The first pixel electrode 210a (included in the first light-emitting diode), the second pixel electrode 210b (included in the second light-emitting diode), and the third pixel electrode 210c (included in the third light-emitting diode) can be arranged in a prismatic pentile array. For example, the first pixel electrode 210a and the third pixel electrode 210c can be alternately arranged in the nth row extending along a first direction (e.g., the x-direction). The second pixel electrode 210b can be repeatedly arranged in the (n+1)th row extending along the first direction (e.g., the x-direction) and parallel to the nth row. Based on a second direction (e.g., the y-direction), the nth row and the (n+1)th row can be arranged repeatedly. For example, the second pixel electrode 210b can be disposed between the first pixel electrode 210a and the third pixel electrode 210c based on the first direction (e.g., the x-direction). In other words, the second pixel electrode 210b disposed in the (n+1)th row can be alternately disposed with the first pixel electrode 210a and the third pixel electrode 210c disposed in the nth row.

[0127] A first emitting region EA1 emitting red light may be defined in a first pixel electrode 210a, a second emitting region EA2 emitting green light may be defined in a second pixel electrode 210b, and a third emitting region EA3 emitting blue light may be defined in a third pixel electrode 210c. Except for the portion connected to the pixel circuit, each of the first pixel electrode 210a and the third pixel electrode 210c may have a generally rectangular shape in a planar view, and except for the portion connected to the pixel circuit, the second pixel electrode 210b may have a generally chamfered rectangular shape in a planar view. However, the shapes of the first pixel electrode 210a, the second pixel electrode 210b, and the third pixel electrode 210c are not limited to these.

[0128] In some embodiments, a portion of the pixel electrode 210 may be configured in a plan view to overlap with at least a portion of the third transistor T3 and the fourth transistor T4. For example, the pixel electrode 210 may be configured to cover both the first sub-transistor T3-1 and the second sub-transistor T3-2. Furthermore, the pixel electrode 210 may be configured to cover at least one of the third sub-transistor T4-1 and the fourth sub-transistor T4-2. For example, as... Figure 10 As shown, the third pixel electrode 210c can be configured to cover (e.g., completely cover) all of the first sub-transistor T3-1, the second sub-transistor T3-2, the third sub-transistor T4-1, and the fourth sub-transistor T4-2. The first pixel electrode 210a can be configured to cover all of the first sub-transistor T3-1, the second sub-transistor T3-2, and the third sub-transistor T4-1.

[0129] As described above, each of the third transistor T3 and the fourth transistor T4 may include two sub-transistors. Similar to the cases of the third transistor T3 and the fourth transistor T4, when the gate electrodes of each of the sub-transistors are spaced apart in a planar diagram and a common-source-drain region exists between them, a recoil phenomenon may occur. In this recoil phenomenon, when the sub-transistors are turned on and off, the voltage in the common-source-drain region momentarily increases, thereby causing leakage current and flickering in the display device 1. For example, when a transistor located in the leakage current path is illuminated by external light or leakage light from adjacent pixels, photo-leakage current can flow through the transistor, which may exacerbate the flickering problem.

[0130] At this time, when the pixel electrode 210 is arranged to cover the third transistor T3 and the fourth transistor T4 as disclosed, the pixel electrode 210 can block light from flowing into the third transistor T3 and the fourth transistor T4. Due to this light-blocking effect of the pixel electrode 210 of the display device 1 according to some embodiments, leakage current can be reduced, and flickering can be prevented or substantially reduced.

[0131] For example, the display device 1 may include not only light-emitting elements such as light-emitting diodes (LEDs), but also sensing elements such as fingerprint sensors or illuminance sensors. Sensing elements such as fingerprint sensors can receive or output optical signals from external sources. In this case, because pixel electrodes 210 can block light incident on the sensing elements, if the planar area of ​​pixel electrodes 210 is excessively widened to cover the third transistor T3 and the fourth transistor T4, there may be a problem of reduced transmittance of the optical signal used for sensing by the fingerprint sensor.

[0132] However, as described above, according to some embodiments, the third transistor T3 and the fourth transistor T4 of the first pixel circuit PC1 can form a flip structure (e.g., a mirror structure) with the third transistor T3 and the fourth transistor T4 of the second pixel circuit PC2. That is, the distance from the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 to the third transistor T3 of the first pixel circuit region PCA1 can be the same as the distance from the boundary between the first pixel circuit region PCA1 and the second pixel circuit region PCA2 to the third transistor T3 of the second pixel circuit PC2. Therefore, as the third transistor T3 of the first pixel circuit PC1 is positioned closer to the boundary, the third transistor T3 of the second pixel circuit PC2 can also be positioned closer to the boundary. Thus, the distance between the third transistor T3 of the first pixel circuit PC1 and the third transistor T3 of the second pixel circuit PC2 can be shortened.

[0133] In some embodiments, if the first pixel circuit PC1 and the second pixel circuit PC2 are not formed in a flip structure but arranged in the same structure, the third transistor T3 of the first pixel circuit PC1 is set to be closer to the boundary, and the third transistor T3 of the second pixel circuit PC2 is set to be farther away from the boundary. That is, if the first pixel circuit PC1 and the second pixel circuit PC2 are arranged in the same structure, the distance between the third transistor T3 of the first pixel circuit PC1 and the third transistor T3 of the second pixel circuit PC2 will not be shortened.

[0134] For example, due to such Figure 10 The display device 1 shown has a flip-flop structure forming a first pixel circuit PC1 and a second pixel circuit PC2. This allows for a reduction in the distance between the third transistor T3 of the first pixel circuit PC1 and the third transistor T3 of the second pixel circuit PC2, and consequently, a reduction in the area of ​​the pixel electrode 210 covering the third transistor T3. Therefore, since the pixel electrode 210 covers both the third transistor T3 and the fourth transistor T4, the display device 1 according to some embodiments can both minimize or substantially reduce the area of ​​the pixel electrode 210 to increase light signal transmittance and minimize or substantially reduce leakage current to form an anti-flicker structure.

[0135] Figure 11 This is a schematic cross-sectional view illustrating a portion of a display device according to some embodiments of the present disclosure.

[0136] Reference Figure 11 A pixel circuit PC, a light-emitting diode (ED) connected to the pixel circuit PC, and an encapsulation layer 300 covering the ED can be disposed on a substrate 100. The substrate 100 may comprise glass or a polymer resin. A substrate 100 comprising a polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may have a multilayer structure comprising an inorganic layer and an organic layer containing a polymer resin.

[0137] A buffer layer 201 may be disposed on the substrate 100. The buffer layer 201 can reduce or prevent the penetration of foreign matter, moisture, or external air from the lower part of the substrate 100 and can provide a flat surface on the substrate 100. The buffer layer 201 may comprise inorganic materials, organic materials, or organic / inorganic composite materials such as oxides or nitrides, and may be formed as a single-layer or multi-layer structure of inorganic and organic materials. For example, the buffer layer 201 may have a structure in which multiple buffer layers are stacked, and in this case, the multiple buffer layers may be made of different materials. For example, one of the multiple buffer layers may include, for example, SiN. x Silicon nitride. Another buffer layer in a plurality of buffer layers may contain, for example, SiO2. x Silica.

[0138] First semiconductor layer 1100 (e.g., see...) Figure 5 The first semiconductor layer 1100 (e.g., see [reference]) can be disposed on the buffer layer 201. Figure 5 The first semiconductor layer 1100 may include a first channel region A1 and a sixth channel region A6. (For example, see...) Figure 5 This can include low-temperature polycrystalline silicon (LTPS). Polycrystalline silicon materials have high electron mobility (e.g., approximately 100 cm⁻¹). 2 ( / Vs or higher), low power consumption, and excellent reliability. In some embodiments, the first semiconductor layer 1100 (e.g., see...) Figure 5 The first semiconductor layer 1100 may include amorphous silicon (a-Si) and / or oxide semiconductor materials. (See, for example, [reference needed]) Figure 5 This can include the channel region and the source and drain regions on either side of the channel region. For example, such as... Figure 11 As shown, the first semiconductor layer 1100 (for example, see...) Figure 5 It may include the sixth channel region A6 and the sixth source region S6 and the sixth drain region D6 on both sides of the sixth channel region A6.

[0139] The first gate insulating layer 203 may be disposed in the first semiconductor layer 1100 (e.g., see...).Figure 5 The first gate insulating layer 203 may include an inorganic material comprising oxides or nitrides. For example, the first gate insulating layer 203 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0140] First conductive layer 1200 (for example, see...) Figure 6 It can be disposed on the first gate insulating layer 203. For example... Figure 11 As shown, the first conductive layer 1200 (for example, see...) Figure 6 The sixth gate electrode (G6) of the sixth transistor T6 and the first electrode (CE1) of the storage capacitor Cst can be included. For example, the sixth gate electrode G6 can be the light-emitting control line EML (see, for example, see...). Figure 6 The first electrode CE1 of the storage capacitor Cst may be part of the first conductive pattern 1230. The first conductive layer 1200 (e.g., see...) Figure 6 It may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti), and may be formed as a single layer or multiple layers.

[0141] The second gate insulating layer 205 may be disposed in the first conductive layer 1200 (for example, see...). Figure 6 The second gate insulating layer 205 may include an inorganic material comprising an oxide or a nitride. For example, the second gate insulating layer 205 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and / or zinc oxide (ZnO2), etc.

[0142] The second conductive layer 1300 (for example, see...) Figure 8 The second gate insulating layer 1300 can be disposed on the second gate insulating layer 205. The second conductive layer 1300 (e.g., see...) Figure 8 ) can include, for example Figure 11 The second electrode CE2 of the storage capacitor Cst shown. In this case, the second electrode CE2 of the storage capacitor Cst may be part of the second conductive pattern 1310. The second conductive layer 1300 (e.g., see...) Figure 8 It may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti), and may be formed as a single layer or multiple layers.

[0143] The first interlayer insulating layer 207 may be disposed in the second conductive layer 1300 (for example, see...). Figure 6The first interlayer insulating layer 207 may include an inorganic material comprising oxides or nitrides. For example, the first interlayer insulating layer 207 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x Examples of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2) are included.

[0144] The third conductive layer 1400 (for example, see...) Figure 9 The third conductive layer 1400 (e.g., see [reference]) can be disposed on the first interlayer insulating layer 207. Figure 9 ) can include, for example Figure 11 The sixth conductive pattern 1430 shown. The sixth conductive pattern 1430 can be a connection electrode for connecting the pixel circuit PC and the light-emitting diode ED. The third conductive layer 1400 (for example, see...) Figure 9 It may include at least one of molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti), and may be formed as a single layer or multiple layers.

[0145] The first planarization layer 209 may be disposed in the third conductive layer 1400 (for example, see...). Figure 9 The first planarization layer 209 may include an organic insulating material, such as a general-purpose polymer (such as silver polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof. In some embodiments, the first planarization layer 209 may include polyimide. In some embodiments, in addition to the sixth conductive pattern 1430, additional connection electrodes and additional planarization layers may be provided to connect the pixel circuit PC and the light-emitting diode ED.

[0146] The light-emitting diode (ED) can be disposed on the first planarization layer 209. The ED may include a pixel electrode 210, an intermediate layer 220 on the pixel electrode 210, and a counter electrode 230 on the intermediate layer 220.

[0147] Pixel electrode 210 may be disposed on the first planarization layer 209. Pixel electrode 210 may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In some embodiments, pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In some embodiments, pixel electrode 210 may also include a film formed of ITO, IZO, ZnO, or In2O3 above / below the aforementioned reflective layer.

[0148] A pixel defining layer 215 may be formed on the pixel electrode 210. The pixel defining layer 215 may include an opening exposing the upper surface of the pixel electrode 210 and may cover the edges of the pixel electrode 210. The pixel defining layer 215 may include an organic insulating material. In some embodiments, the pixel defining layer 215 may include an inorganic insulating material, such as silicon nitride (SiN). x ), silicon oxynitride (SiON) or silicon oxide (SiO) x In some embodiments, the pixel defining layer 215 may include organic insulating materials and inorganic insulating materials.

[0149] The intermediate layer 220 may include an emitting layer 220b. The intermediate layer 220 may include a first functional layer 220a disposed below the emitting layer 220b and / or a second functional layer 220c disposed on the emitting layer 220b. The emitting layer 220b may include a polymer or a low molecular weight organic material that emits light of a color (e.g., a set or preset color).

[0150] The first functional layer 220a can be a single layer or multiple layers. For example, when the first functional layer 220a is formed of a polymer material, it is a single-layer structure used as a hole transport layer (HTL) and can be formed of polyethylene dihydroxythiophene (PEDOT) or polyaniline (PAN). When the first functional layer 220a is formed of a low molecular weight material, it can include a hole injection layer (HIL) and a hole transport layer (HTL).

[0151] In some embodiments, the second functional layer 220c may be omitted. For example, the second functional layer 220c may be preferable when the first functional layer 220a and the emitter layer 220b are formed of a polymer material. The second functional layer 220c may be a single layer or multiple layers. The second functional layer 220c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0152] The emitter layer 220b of the intermediate layer 220 can be configured for each pixel in the display area DA. The emitter layer 220b can be patterned to correspond to the pixel electrode 210. The first functional layer 220a and / or the second functional layer 220c of the intermediate layer 220 can be integrally formed on the substrate 100.

[0153] The counter electrode 230 can be made of a conductive material with low work function. For example, the counter electrode 230 may include a transparent (e.g., translucent) layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), lithium (Li), chromium (Cr), calcium (Ca), or alloys thereof. For example, the counter electrode 230 may also include a layer such as ITO, IZO, ZnO, or In2O3 on the transparent layer comprising the above materials. The counter electrode 230 can be integrally formed on the substrate 100. The first functional layer 220a, the second functional layer 220c, and the counter electrode 230 can be formed by thermal vapor deposition.

[0154] The capping layer 240 may be located on the counter electrode 230. For example, the capping layer 240 may comprise LiF and may be formed by thermal deposition. In some embodiments, the capping layer 240 may be omitted.

[0155] Spacers 217 may be formed on pixel defining layer 215. Spacers 217 may include organic insulating materials such as polyimide. In some embodiments, spacers 217 may include inorganic insulating materials, or may include both organic and inorganic insulating materials.

[0156] The spacer 217 may comprise a material different from that of the pixel defining layer 215, or it may comprise the same material as that of the pixel defining layer 215. For example, the pixel defining layer 215 and the spacer 217 may be formed together in a masking process using a halftone mask. In some embodiments, the pixel defining layer 215 and the spacer 217 may comprise polyimide.

[0157] Light-emitting diodes (EDs) can be covered by encapsulation components. Figure 11 The illustration shows a light-emitting diode (ED) covered with a packaging component such as an encapsulation layer 300, but the disclosure is not limited thereto. In some embodiments, the ED may be shielded from external air by an encapsulation component such as an upper substrate and a glass frit.

[0158] The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer, and Figure 11The encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 therebetween. In some embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be varied.

[0159] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic material, such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers comprising the above-mentioned materials.

[0160] The organic encapsulation layer 320 may include monomeric or polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. In some embodiments, the organic encapsulation layer 320 may include acrylates.

[0161] The display device according to the embodiments can be applied to various electronic devices. Electronic devices according to embodiments of this disclosure may include the above-described display device (e.g., Figure 1 The display device 1) may also include modules or devices with additional functions in addition to the display device.

[0162] Figure 12 This is a block diagram of an electronic device according to some embodiments of the present disclosure.

[0163] Reference Figure 12 The electronic device 1000 according to the embodiment may include a display module 1001, a processor 1002, a memory 1003, and a power module 1004.

[0164] The processor 1002 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0165] The memory 1003 can store data information required for the operation of the processor 1002 or the display module 1001. When the processor 1002 executes the application stored in the memory 1003, image data signals and / or input control signals can be transmitted to the display module 1001, and the display module 1001 can process the received signals and output image information through the display screen.

[0166] The power module 1004 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power necessary for the operation of the electronic device 1000.

[0167] At least one of the components of the electronic device 1000 described above may be included in the display device according to the embodiments described above. Furthermore, a portion of the various modules functionally included in the electronic device 1000 may be included in the display device, while another portion may be disposed separately from the display device. For example, the display device may include a display module 1001, while the processor 1002, memory 1003, and power module 1004 may be disposed in the electronic device 1000 as other devices besides the display device.

[0168] In an embodiment, the display module 1001 included in the electronic device 1000 can be driven based on image data signals and input control signals received from the processor 1002.

[0169] Figure 13 These are schematic diagrams of electronic devices according to various embodiments.

[0170] Reference Figure 13 The various electronic devices to which the display device according to the embodiment is applied may include not only image display electronic devices such as smartphone 1000a, tablet PC 1000b, laptop computer 1000c, TV 1000d and desktop monitor 1000e, but also wearable electronic devices including display modules such as smart glasses 1000f, head-mounted display 1000g and smartwatch 1000h, and vehicle electronic devices 1000i including dashboard, central instrument panel and display modules such as CID (Central Information Display) and interior mirror display disposed in the dashboard.

[0171] The display device according to some embodiments may have improved display quality and a more robust structure. However, these are merely examples, and the scope of disclosure is not limited thereto.

[0172] Although the disclosure has been described with reference to the embodiments shown in the accompanying drawings, these are merely examples, and those skilled in the art will understand that various modifications can be made to the embodiments accordingly. Therefore, the true scope of protection of the disclosure should be determined by the technical concept of the appended patent claims.

[0173] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: The substrate includes a first pixel circuit region and a second pixel circuit region adjacent to the first pixel circuit region along a first direction; A pixel circuit, on the substrate, and including a first pixel circuit in the first pixel circuit region and a second pixel circuit in the second pixel circuit region; as well as The light-emitting element is connected to the pixel circuit. Each of the first pixel circuit and the second pixel circuit includes: A first transistor is electrically connected to the drive voltage line and the light-emitting element, and is configured to control the current supplied to the light-emitting element; The second transistor is electrically connected to the data line and the first terminal of the first transistor; A third transistor is electrically connected to the gate of the first transistor and a second terminal of the first transistor; and A fourth transistor is electrically connected to the gate of the first transistor and the first initialization voltage line; and In the plan view, the third transistor and the fourth transistor of the first pixel circuit are respectively symmetrical with respect to the imaginary straight line extending in the second direction intersecting the first direction.

2. The display device according to claim 1, wherein the second initialization voltage line extends along the second direction. in, The driving voltage line and the data line are arranged in each of the first pixel circuit region and the second pixel circuit region, and extend along the second direction. Wherein, the second initialization voltage line is located on the boundary between the first pixel circuit region and the second pixel circuit region, and Wherein, a portion of the second initialization voltage line is in the first pixel circuit region, and another portion of the second initialization voltage line is in the second pixel circuit region.

3. The display device according to claim 1, further comprising a first gate line connected to the gate of the third transistor. in, The first gate line includes: The first main section extends along the first direction; The first branch portion branches off from the first trunk portion within the first pixel circuit region and extends in the second direction; and The second branch portion branches off from the first trunk portion within the second pixel circuit region and extends in the second direction.

4. The display device according to claim 3, wherein, The distance from the boundary between the first pixel circuit region and the second pixel circuit region to the first branch portion is the same as the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the second branch portion.

5. The display device according to claim 3, wherein, The third transistor includes a first sub-transistor and a second sub-transistor connected in series. Wherein, the gate of the first sub-transistor is formed in a portion of the first branch portion or a portion of the second branch portion, and The gate of the second sub-transistor is formed in a portion of the first main section.

6. The display device according to claim 1, further comprising a second gate line connected to the gate of the fourth transistor, in, The second gate line includes: The second main section extends along the first direction; The third branch portion branches off from the second main branch portion within the first pixel circuit region and extends in the second direction; and The fourth branch portion branches off from the second main portion within the second pixel circuit region and extends in the second direction.

7. The display device according to claim 6, wherein, The distance from the boundary between the first pixel circuit region and the second pixel circuit region to the third branch is the same as the distance from the boundary between the first pixel circuit region and the second pixel circuit region to the fourth branch.

8. The display device according to claim 6, wherein, The fourth transistor includes a third sub-transistor and a fourth sub-transistor connected in series. The gate of the third sub-transistor is formed in a portion of the second main branch, and The gate of the fourth sub-transistor is formed in a portion of the third branch or a portion of the fourth branch.

9. The display device according to claim 1, wherein, The light-emitting element includes a pixel electrode, an intermediate layer on the pixel electrode, and a counter electrode on the intermediate layer. In the planar view, the pixel electrode is superimposed on at least a portion of the third transistor and the fourth transistor.

10. The display device according to claim 9, wherein, The light-emitting element includes a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode that emit different colors of light. The first light-emitting diode and the third light-emitting diode are alternately arranged in a first row extending along the first direction. The second light-emitting diode is repeatedly arranged in a second row parallel to the first row, and is positioned between the first and third light-emitting diodes relative to the first direction. The pixel electrode, which is at least partially superimposed on the third transistor and the fourth transistor, is either the pixel electrode of the first light-emitting diode or the pixel electrode of the third light-emitting diode.

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