Deviation method and device for verifying signal eye height amplitude margin and related assembly

Abstract

The invention discloses a bias method and device for verifying a signal eye height amplitude margin and a related assembly, and the method comprises the steps: obtaining a batch of samples to be detected, and determining an eye pattern template and a reference voltage corresponding to a received signal; for each to-be-tested sample, the reference voltage is pulled upwards and downwards until the received signal is abnormal, and an upper limit voltage when the received signal is abnormal after the reference voltage is pulled upwards and a lower limit voltage when the received signal is abnormal after the reference voltage is pulled downwards are recorded; screening out the minimum upper limit voltage from all the upper limit voltages, and screening out the maximum lower limit voltage from all the lower limit voltages; calculating a difference value between the minimum upper limit voltage and the maximum lower limit voltage, and comparing the difference value with the eye height range of the eye pattern template; and if the difference value is greater than the eye height range of the eye pattern template, judging that the high-speed signal eye height amplitude margin of the to-be-detected sample meets the design requirement. According to the method, the consistency deviation of the materials can be tolerated after the products are delivered on a large scale, and the robustness is better.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method, apparatus and related components for verifying the high amplitude margin of a signal eye. Background Technology

[0002] In the research and development and production of storage and various high-speed signal transmission related products, signal integrity is the core indicator that determines product reliability and compatibility. As a key parameter for evaluating high-speed signal integrity, the accurate evaluation of this parameter is crucial for quality control after mass production.

[0003] In existing technologies, to ensure sufficient margin for high-speed signal integrity, the conventional technical approach is as follows: first, a simulation model is built based on the printed circuit board (PCB) and core components to conduct signal integrity (SI) simulation analysis; then, actual signal waveform measurements are performed on finished module samples, and the signal margin is evaluated by comparing it with a preset eye diagram template standard; after the evaluation is qualified, the product is put into mass production.

[0004] However, the aforementioned conventional technical solutions have significant shortcomings: On the one hand, conventional methods are difficult to accurately assess the signal quality of batch samples, and cannot promptly identify signal quality deviations caused by factors such as device errors, PCB material performance fluctuations, and changes in testing and application environments during the production process. Consequently, they cannot accurately define the deviation boundaries of signal quality, making it difficult to reserve sufficient margin redundancy during the product design stage. When the finished product shipment volume reaches a certain level, there is often a certain probability of bit error-type defects, affecting the batch delivery quality of products. On the other hand, for small-package integrated storage products such as embedded multimedia cards (EMMC) and general-purpose flash memory (USF), due to the limitations of package size and structural characteristics, it is impossible to directly test their internal signal waveforms through physical means. Signal quality can only be accepted indirectly by relying on SI simulation results, eye diagram template virtual evaluation, and data verification. Similarly, it is impossible to accurately obtain the eye height deviation boundary of signal quality, making it difficult to identify signal integrity risks in advance and take targeted preventive measures, thus posing potential risks to product reliability. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, and related components for verifying the eye height amplitude margin of a signal, aiming to solve the problems of insufficient batch evaluation capability and blurred margin boundary in current eye height amplitude margin evaluation methods.

[0006] In a first aspect, embodiments of the present invention provide a method for verifying the high amplitude margin of a signal eye by biasing the signal, comprising: Acquire a batch of test samples, train the received signals of the test samples, and determine the eye diagram template and reference voltage corresponding to the received signals; For each of the samples to be tested, the reference voltage is pulled upward and downward according to a preset step until the received signal becomes abnormal. The upper limit voltage when the received signal becomes abnormal after the upward pull and the lower limit voltage when the received signal becomes abnormal after the downward pull are recorded. The minimum upper limit voltage is selected from the upper limit voltages of all test samples, and the maximum lower limit voltage is selected from the lower limit voltages of all test samples. Calculate the difference between the minimum upper limit voltage and the maximum lower limit voltage, and compare the difference with the eye height range of the eye diagram template; If the difference is greater than the eye height range of the eye diagram template, then it is determined that the eye height amplitude margin of the high-speed signal corresponding to the test sample meets the design requirements. If the difference is less than or equal to the eye height range of the eye diagram template, then the eye height amplitude margin of the high-speed signal is determined to be unsatisfactory.

[0007] Secondly, embodiments of the present invention provide a deflection device for verifying the high amplitude margin of a signal eye, comprising: The acquisition unit is used to acquire a batch of samples to be tested, train the received signals of the samples to be tested, and determine the eye diagram template and reference voltage corresponding to the received signals. The biasing unit is used to bias the reference voltage upward and downward according to a preset step for each of the test samples until the received signal is abnormal. It records the upper limit voltage when the received signal is abnormal after the upward bias and the lower limit voltage when the received signal is abnormal after the downward bias. The screening unit is used to screen out the minimum upper limit voltage from all the upper limit voltages of the test samples and the maximum lower limit voltage from all the lower limit voltages of the test samples. The calculation unit is used to calculate the difference between the minimum upper limit voltage and the maximum lower limit voltage, and compare the difference with the size of the eye height range of the eye diagram template; The first determination unit is used to determine that if the difference is greater than the eye height range of the eye diagram template, the eye height amplitude margin of the high-speed signal corresponding to the test sample meets the design requirements. The second determination unit is used to determine that the eye height amplitude margin of the high-speed signal does not meet the design requirements if the difference is less than or equal to the eye height range of the eye diagram template.

[0008] Thirdly, embodiments of the present invention provide a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the method for adjusting the high amplitude margin of the verification signal eye as described in the first aspect.

[0009] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method for adjusting the high amplitude margin of the verification signal eye as described in the first aspect.

[0010] This invention discloses a method, apparatus, and related components for verifying the high-speed signal eye height amplitude margin. The method includes: acquiring a batch of test samples, training the received signals of the test samples, and determining the eye diagram template and reference voltage corresponding to the received signals; for each test sample, adjusting the reference voltage upwards and downwards according to preset steps until the received signal becomes abnormal, and recording the upper limit voltage when the received signal becomes abnormal after upward adjustment and the lower limit voltage when the received signal becomes abnormal after downward adjustment; selecting the smallest upper limit voltage from all the upper limit voltages of the test samples, and selecting the largest lower limit voltage from all the lower limit voltages of the test samples; calculating the difference between the smallest upper limit voltage and the largest lower limit voltage, and comparing the difference with the eye height range of the eye diagram template; if the difference is greater than the eye height range of the eye diagram template, it is determined that the high-speed signal eye height amplitude margin corresponding to the test sample meets the design requirements; if the difference is less than or equal to the eye height range of the eye diagram template, it is determined that the high-speed signal eye height amplitude margin does not meet the design requirements. This invention employs batch sample pull-off testing, sets a deviation degradation digital eye diagram eye height, narrows the eye height margin to its limit, and records the degradation results to comprehensively evaluate the safety of the signal integrity design. This ensures that the product can tolerate material consistency deviations and has better compatibility and robustness after mass production. The embodiments of this invention also provide a pull-off device for verifying the signal eye height amplitude margin, a computer-readable storage medium, and a computer device, which have the above-mentioned beneficial effects, and will not be elaborated further here. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating the method for adjusting the high amplitude margin of the signal eye; Figure 2 A schematic diagram illustrating the principle of the biasing method for high amplitude margin of the signal eye; Figure 3 This is a schematic diagram illustrating the principle of upward pulling; Figure 4 This is a schematic diagram illustrating the principle of downward deflection; Figure 5 A schematic block diagram of a deflection device used to verify the high amplitude margin of the signal eye. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] It should be understood that, when used in this specification and the appended claims, the terms “comprising” and “including” indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more of its features, integrals, steps, operations, elements, components and / or collections thereof.

[0015] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0016] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0017] Please see Figures 1-4 This embodiment provides a method for verifying the high amplitude margin of a signal eye by biasing the signal, including: S101: Acquire a batch of test samples, train the received signals of the test samples, and determine the eye diagram template and reference voltage corresponding to the received signals; Specifically, no fewer than n samples are randomly selected from the production batch to ensure that the samples cover different process parameters (such as PCB material batches and device package types) and environmental conditions (such as temperature and humidity).

[0018] Next, a training process is performed on the received signal of each test sample, including clock recovery, equalization parameter adjustment, and bit error rate calibration. The detailed process is as follows: clock recovery extracts the clock from the received signal through an adaptive phase-locked loop and adjusts the loop bandwidth to align the clock phase with the data symbol; based on the extracted clock signal, the gain parameters of the continuous-time linear equalizer and the tap coefficients of the digital equalizer are dynamically adjusted to compensate for the frequency-selective attenuation of the transmission path; after equalization adjustment, data is sent using a pseudo-random binary sequence test mode, the bit error rate is measured, and the equalization parameters are iteratively optimized until the bit error rate is stably lower than the preset threshold.

[0019] Then, at least 3000 consecutive data cycles are acquired using an oscilloscope. The acquired waveforms are then superimposed and averaged to generate the corresponding eye diagram template. The eye diagram template includes characteristic parameters such as rising edge slope, falling edge slope, eye height, and eye width.

[0020] The reference voltage Vref is then calculated based on the center position of the eye diagram template. Specifically, the average voltage at the intersection of the rising and falling edges of the eye diagram template is taken as the decision reference voltage for the received signal. If the eye diagram template is asymmetrical, the reference voltage Vref is calculated after adjusting the equalizer gain to make the intersection points more symmetrical.

[0021] Then, based on the upper and lower boundaries of the eye diagram template, determine the size of the eye height range Vtotal of the eye diagram template. The specific steps are as follows: Extract the maximum signal amplitude Vmax and minimum signal amplitude Vmin from the eye diagram template; Calculate Vtotal = Vmax - Vmin; If the eye diagram template has jitter that causes the boundary to be blurred, a Gaussian fitting algorithm is used to smooth the boundary fluctuations, and then Vtotal is calculated using the corrected Vmax' and Vmin'.

[0022] Next, the Vref and Vtotal of the 20 samples were cross-compared to remove outliers caused by anomalies in a single sample. If the Vref of a sample deviates from the mean by more than ±5% or the Vtotal deviates by more than ±10%, the training data of that sample was re-acquired and the received signal of the sample to be tested was re-trained to determine the eye diagram template, reference voltage, and voltage range corresponding to the received signal.

[0023] This embodiment ensures that each test link is in its optimal state by performing a standardized training process for each sample, including clock recovery, equalization adjustment, and bit error rate calibration. Adaptive phase-locked loop and alignment operations guarantee the accuracy of timing synchronization. Dynamic adjustment of equalizer parameters actively compensates for signal loss caused by differences in transmission paths among different samples. Finally, a convergence criterion of bit error rate below a preset threshold is used, providing an objective and quantitative standard for judging signal quality. This process ensures that all samples are tested under fair and optimal configuration, avoiding test errors introduced by insufficient training or inconsistent states, thus making the boundary data obtained after subsequent biasing reliable.

[0024] The preset threshold for bit error rate calibration is pre-set according to industry testing specifications for high-speed communication interfaces. For example, for standards such as PCIe and USB, a threshold of 1×10 is used. -6 This threshold serves as a benchmark for determining abnormal bit error rates. It is determined by combining system-level design requirements with historical test data, ensuring that samples with abnormal signal quality can be effectively screened during batch testing, while avoiding reduced testing efficiency due to an overly stringent threshold.

[0025] S102: For each of the test samples, the reference voltage is pulled upward and downward according to a preset step until the received signal is abnormal. The upper limit voltage when the received signal is abnormal after the upward pull and the lower limit voltage when the received signal is abnormal after the downward pull are recorded. Specifically, for each sample to be tested, the reference voltage is pulled upwards and downwards according to preset steps until the received signal becomes abnormal. The upper limit voltage at which the received signal becomes abnormal after upward pulling and the lower limit voltage at which the received signal becomes abnormal after downward pulling are recorded, including: Use the first step value to shift the reference voltage upward to generate the first upward shift voltage sequence; The initial upward abnormal voltage point at which the received signal first shows an anomaly is determined based on the first upward offset voltage sequence; Starting from the initial upward abnormal voltage point, the reference voltage is shifted upward using a second step value to generate a second upward shifted voltage sequence; wherein, the second step value is smaller than the first step value; The upper limit voltage when the received signal is abnormal after upward deflection is determined based on the second upward offset voltage sequence.

[0026] More specifically, for each sample to be tested, a first step value ΔV_initial is set, and the subsequent second step value ΔV_fine is 1 / 2 to 1 / 5 of ΔV_initial.

[0027] Starting from the reference voltage Vref, the voltage is shifted upwards sequentially by ΔV_initial to generate the first upward-shifted voltage sequence. For example, when ΔV_initial is 1V, the sequence is Vref+1V, Vref+2V, Vref+3V, and so on, until the preset termination voltage.

[0028] Next, a received signal test is performed on each voltage point in the first upward offset voltage sequence. The signal is assessed for anomalies using quantization parameters such as bit error rate (BER), eye diagram closure (EC), and jitter (TJ) amplitude. If any parameter meets a preset anomaly threshold (e.g., BER ≥ 1 × 10⁻⁶), an anomaly is detected. -6 When EC ≤ 80% eye diagram closure and TJ ≥ 15% UI, record the current voltage point as the preliminary upward abnormal voltage point Vref_up_preliminary.

[0029] Then, starting from Vref_up_preliminary, the voltage is shifted upwards by ΔV_fine to generate a second upward-shifted voltage sequence. For example, when ΔV_fine is 0.2V, the sequence is Vref_up_preliminary+0.2V, Vref_up_preliminary+0.4V, Vref_up_preliminary+0.6V, until the preset termination voltage.

[0030] The received signal test is then repeated for each voltage point in the second upward offset voltage sequence. When the received signal anomaly occurs for the first time, the current voltage point is recorded as the final upper limit voltage Vref_up_final. If no anomalies are triggered at any of the sequence voltage points, the last voltage point in the sequence is taken as Vref_up_final.

[0031] Repeat the above steps for each sample to obtain the corresponding Vref_up_final. Perform statistical analysis on the Vref_up_final data of all samples for subsequent margin assessment.

[0032] Furthermore, for each sample to be tested, the reference voltage is pulled upwards and downwards according to preset steps until the received signal becomes abnormal. The upper limit voltage at which the received signal becomes abnormal after upward pulling and the lower limit voltage at which the received signal becomes abnormal after downward pulling are recorded, including: The reference voltage is offset downwards using the third step value to generate the first downward offset voltage sequence; The initial downward anomalous voltage point at which the received signal first shows an anomaly is determined based on the first downward offset voltage sequence; Starting from the initial downward abnormal voltage point, the reference voltage is shifted downward using the fourth step value to generate the second downward shifted voltage sequence; wherein, the fourth step value is less than the third step value; The lower limit voltage when the received signal is abnormal after downward pull-off is determined based on the second downward offset voltage sequence.

[0033] Specifically, for each sample to be tested, a third step value ΔV3 is set, and the subsequent fine fourth step value ΔV4 is 1 / 2 to 1 / 5 of Δ3.

[0034] Then, starting from the reference voltage Vref, the voltage is shifted downwards sequentially by Δ3 to generate the first downward shifted voltage sequence. For example, when Δ3 is 1V, the sequence is Vref-1V, Vref-2V, Vref-3V... until the preset termination voltage.

[0035] Then, a received signal test is performed on each voltage point in the first downward offset voltage sequence. The signal abnormality is determined using quantization parameters such as bit error rate (BER), eye diagram closure (EC), and jitter (TJ) amplitude. If any parameter meets a preset abnormality threshold (e.g., BER ≥ 1 × 10⁻⁶), the signal is considered abnormal. -6 When EC ≤ 80% eye diagram closure and TJ ≥ 15% UI, record the current voltage point as the preliminary downward abnormal voltage point Vref_down_preliminary.

[0036] Next, starting from Vref_down_preliminary, the voltage is shifted downwards by Δ4 to generate a second downward-shifted voltage sequence. For example, when Δ4 is ​​0.2V, the sequence is Vref_down_pre Vref_down_preliminary-0.2V, Vref_down_preliminary-0.4V, Vref_down_preliminary-0.6V... until the preset termination voltage.

[0037] The received signal test is then repeated for each voltage point in the second downward offset voltage sequence. When the received signal anomaly is first detected, the current voltage point is recorded as the final lower limit voltage. If no anomalies are triggered at any of the sequence voltage points, the last voltage point in the sequence is used as the final lower limit voltage.

[0038] Repeat the above steps for each sample to obtain the corresponding final lower limit voltage. Perform statistical analysis on the final lower limit voltage data and the final upper limit voltage data of all samples for subsequent margin assessment.

[0039] In this embodiment, a large step size is initially used to quickly locate the approximate range of anomalies, significantly reducing the number of invalid scans. Subsequently, a small step size is used near the anomaly point to improve the measurement accuracy of the boundary voltage through fine scanning. Compared with the traditional fixed step size method, the overall test time is significantly shortened, and the confirmation of the upper and lower voltage limits is more accurate.

[0040] In this embodiment, abnormal received signal conditions specifically include at least one of the following situations: The bit error rate of the received signal exceeds the preset bit error rate threshold; The cumulative duration for which the received signal waveform deviates from the eye diagram template within a preset period exceeds a predetermined duration; The amplitude of the jitter in the received signal waveform exceeds a predetermined proportion of the voltage range.

[0041] Specifically, a pseudo-random binary sequence (PRBS) test is performed on the received signal of each test sample, and the number of bit errors received per unit time is counted. When the bit error rate (BER) exceeds a preset BER threshold (e.g., 1 × 10⁻⁶), the test is terminated. -6 When the current voltage point triggers an abnormal bit error rate, the voltage point is recorded as a preliminary abnormal point.

[0042] Next, the waveform data of the received signal is continuously acquired using an oscilloscope, and the waveform is compared with the preset eye diagram template cycle by cycle. When the total deviation time of the signal waveform in 20 consecutive data cycles exceeds the preset duration (such as 80% of the eye diagram cycle duration), it is determined that the current voltage point triggers an abnormal deviation of the eye diagram template, and this voltage point is recorded as the initial abnormal point.

[0043] Next, extract the total jitter (TJ) amplitude of the received signal and calculate its proportion of the eye height range Vtotal of the eye diagram template. When this proportion exceeds a preset threshold (e.g., 15% Vtotal), it is determined that the current voltage point triggers an abnormal jitter amplitude, and this voltage point is recorded as a preliminary abnormal point.

[0044] During the voltage bias test, if any voltage point triggers one of the following conditions: abnormal bit error rate, abnormal eye diagram template deviation duration, or abnormal jitter amplitude ratio, that voltage point is determined to be an abnormal point in the received signal. The voltage values ​​corresponding to all abnormal points are recorded, and the minimum abnormal voltage value is used as the initial boundary voltage.

[0045] Next, starting from the initial boundary voltage, a second scan is performed according to the second or fourth step value, repeatedly executing the bit error rate test, eye diagram template deviation duration analysis, and jitter amplitude ratio calculation. When any abnormal situation occurs for the first time during the second scan, the current voltage point is recorded as the final boundary voltage (upper or lower limit).

[0046] Subsequently, statistical analysis was performed on the final boundary voltage of all samples to calculate the margin distribution characteristics of the batch of samples, which was used for subsequent design optimization and process adjustment.

[0047] In some embodiments, it also includes: The impedance change data of the transmission line is collected in real time by a time domain reflectometer, and an impedance change curve containing the location and magnitude of impedance abrupt change points is generated. By jointly analyzing the impedance variation curve with the pre-measured frequency domain parameters, comprehensive channel evaluation parameters are generated. Based on the comprehensive evaluation parameters of the channel, the pull-off step value under the current test state is calculated through an adaptive algorithm.

[0048] Specifically, a step pulse signal is sent to the transmission line of the sample under test using a time-domain reflectometer (TDR), and the reflected signal waveform is acquired in real time. Based on the relationship between the reflection coefficient and the characteristic impedance of the transmission line, the instantaneous impedance value at each sampling point is calculated. The impedance values ​​of consecutive sampling points are plotted as an impedance-distance curve, and the locations of impedance abrupt changes and their corresponding amplitude changes are marked.

[0049] Next, the frequency domain S-parameter test results of the sample under test are obtained (frequency domain S-parameters are complex matrix parameters that describe the signal transmission and reflection characteristics of a multi-port network in the frequency domain, and their core function is to reflect the amplitude and phase relationship between the incident and scattered waves at different frequencies), and the insertion loss S21 curve is extracted. The frequency bands in the S21 curve that are higher than a preset frequency threshold are divided into multiple sub-bands, and the average insertion loss value of each sub-band is calculated. The location of impedance abrupt change points is mapped to the corresponding S21 average loss value of the frequency band to generate a frequency domain-time domain joint analysis matrix.

[0050] Based on the joint analysis matrix, the channel comprehensive evaluation parameter ZFI (impedance fluctuation index) is defined, and the calculation formula is as follows: ZFI = α × N + β × ΔS21; Where N is the number of impedance abrupt change points per unit length, ΔS21 is the average loss slope of S21 in the corresponding frequency band, and α and β are weighting coefficients (e.g., α=0.6, β=0.4).

[0051] Next, the pull step ΔV is dynamically adjusted based on the current ZFI value. Specifically: When ZFI ≥ preset threshold T1 (e.g., T1 = 0.8), it indicates that there is significant impedance fluctuation in the transmission path. Adjust ΔV to 1 / 3 to 1 / 2 of the initial step. When ZFI < preset threshold T2 (e.g., T2 = 0.3), it indicates that the transmission path stability is high, and ΔV is adjusted to 1.2 to 1.5 times the initial step. When ZFI is in the interval [T2,T1], the initial step size remains unchanged.

[0052] During the bias test, the impedance change curve is acquired in real time and the ZFI value is updated. After each voltage offset is completed, the step value is recalculated to ensure that the subsequent test steps always match the current channel state.

[0053] This embodiment achieves intelligent and efficient signal integrity testing through real-time impedance monitoring, multi-dimensional data fusion, and dynamic step adjustment, providing more accurate margin assessment and risk warning capabilities for high-speed circuit design.

[0054] S103: Select the minimum upper limit voltage from all the upper limit voltages of the test samples, and select the maximum lower limit voltage from all the lower limit voltages of the test samples. Specifically, the upward pull test results (Vref_up_final) and downward pull test results (Vref_down_final) of all the samples to be tested are stored as independent datasets to ensure data integrity and consistency.

[0055] Next, the Vref_up_final dataset is sorted in ascending order, and adjacent data points are compared sequentially to determine the minimum upper voltage value, Vref_up_min. If multiple minimum values ​​exist in the dataset, one of them is selected as Vref_up_min.

[0056] The Vref_down_final dataset is then sorted in ascending order, and adjacent data points are compared sequentially to determine the maximum lower limit voltage value, Vref_down_min. If multiple minimum values ​​exist in the dataset, one of them is selected as Vref_down_min.

[0057] S104: Calculate the difference between the minimum upper limit voltage and the maximum lower limit voltage, and compare the difference with the size of the eye height range of the eye diagram template; S105: If the difference is greater than the eye height range of the eye diagram template, it is determined that the eye height amplitude margin of the high-speed signal corresponding to the test sample meets the design requirements. S106: If the difference is less than or equal to the eye height range of the eye diagram template, then it is determined that the eye height amplitude margin of the high-speed signal does not meet the design requirements.

[0058] The upward pull-up test results (Vref_up_final) and downward pull-down test results (Vref_down_final) of the batch of samples to be tested are stored in separate arrays to ensure that each array contains the test data of all samples and that the data format is consistent.

[0059] Calculate the difference ΔV margin between Vref_up_final and Vref_down_final for each sample using the following formula: ΔV margin=Vref_up_final-Vref_down_final.

[0060] Next, obtain the eye height range Vtotal of the eye diagram template corresponding to the sample, and compare the relationship between ΔV margin and the size of the eye height range Vtotal of the eye diagram template: If ΔV margin > Vtotal, then the high-amplitude margin of the high-speed signal eye of the sample is determined to meet the design requirements. If ΔV margin ≤ Vtotal, the margin of the sample is deemed insufficient, requiring retesting or process adjustment.

[0061] Samples that meet the design requirements are marked as qualified, and a summary report containing the sample number, ΔV margin, and judgment result is generated. Samples with insufficient margin are marked as abnormal for subsequent process optimization or design correction.

[0062] In some embodiments, it also includes: Obtain the sample to be tested; Frequency domain parameter tests are performed on the sample under test to obtain the insertion loss curve of the transmission path; Perform time-domain eye diagram testing on the sample to be tested to generate the corresponding eye diagram template and closure curve; The frequency bands in the insertion loss curve that are higher than the preset frequency threshold are divided into multiple sub-bands, and the average insertion loss value corresponding to each sub-band is calculated. The average insertion loss value of each sub-band is correlated with the closure change rate of the corresponding band in the eye diagram template to generate a frequency domain and time domain mapping matrix. Based on the positive correlation between the average insertion loss value and the rate of change of closure in the frequency-time domain mapping matrix, the dominant factors of high-frequency signal distortion are determined. The dominant factors include impedance abrupt change points, abnormal dielectric loss regions, or connector defect locations in the transmission path.

[0063] Specifically, representative samples were obtained from the same production batch. A vector network analyzer was used to test the frequency domain parameters of the signal transmission path of the samples, and the S-parameters were obtained through a complete port scan. The insertion loss curve was then precisely extracted from this S-parameter. This curve fully characterizes the attenuation characteristics of the channel at different frequency components.

[0064] Meanwhile, on the time-domain test platform, a high-speed oscilloscope or bit error rate analyzer is used to perform time-domain eye diagram tests on the sample under test. By sending and receiving high-speed pseudo-random codes, a sufficient number of data bits are acquired to generate a clear eye diagram. Based on this eye diagram, not only is an eye diagram template for margin assessment generated, but also a closure curve that can quantify the trend of eye diagram opening with time or conditions is generated by analyzing the changes of the template edge with sampling time.

[0065] After completing the basic data acquisition, the correlation analysis phase begins. The frequency bands in the insertion loss curve that are above a preset frequency threshold—that is, the regions where the signal attenuates significantly at high frequencies—are uniformly divided into multiple sub-bands. For each sub-band, the corresponding average insertion loss value is calculated, thus transforming the continuous loss curve into a set of discrete characteristic values ​​representing the attenuation intensity of each frequency band.

[0066] Subsequently, a correlation model between the frequency domain and the time domain is established. The average insertion loss value of each sub-frequency band is matched and correlated with the closure change rate of the corresponding frequency band in the eye diagram template. Through multivariate regression or matrix operations, a frequency-time domain mapping matrix is ​​generated. This matrix clearly reveals, in a quantitative form, the specific contribution of signal attenuation in different frequency bands to the deterioration of eye diagram closure (i.e., the degradation of signal quality in the time domain).

[0067] Finally, root cause diagnosis is performed based on the frequency-time domain mapping matrix. By analyzing the strength and distribution pattern of the positive correlation between the average insertion loss value and the rate of change in closure revealed in the matrix, the dominant factors causing high-frequency signal distortion can be accurately identified. For example, if correlation analysis indicates that a sharp increase in insertion loss at a specific resonant frequency is the main cause of eye diagram closure, then an impedance abrupt change point in the transmission path can be identified; if a sustained high loss over a wide bandwidth is correlated with eye diagram closure, the dominant factor may point to an abnormal dielectric loss region; and if the correlation features show a periodic reflection pattern corresponding to a specific structure (such as a connector), the defect can be precisely located at the connector position. This diagnostic result provides clear and quantitative evidence for subsequent hardware design improvements and optimizations, achieving a leap from symptom monitoring to root cause localization.

[0068] As signal rates continue to increase, high-frequency effects in the channel become increasingly complex, with various losses, reflections, and coupling effects intertwined. The method described above, through fine-grained segmentation and correlation analysis of the high-frequency band, can identify the most critical dominant factors in this complex interaction. This allows design teams to identify potential high-risk design flaws early on, enabling them to take targeted preventative measures before mass production, effectively reducing the cost and risk of major failures due to signal issues later on.

[0069] In some embodiments, a harmonic component capture module is added to the frequency domain parameter testing stage. The S-parameters of the transmission path at the fundamental frequency (e.g., 5 GHz) and its third harmonic (15 GHz) are collected through the harmonic scanning mode of the vector network analyzer. The insertion loss curve is subjected to spectral decomposition to extract the amplitude ratio of the fundamental wave to the third harmonic and the harmonic phase shift, and a composite loss model containing nonlinear characteristics is constructed. In the time-domain eye diagram test, the third harmonic excitation signal is injected synchronously, and the composite eye diagram containing harmonic components is captured by a high-bandwidth oscilloscope. The increase in eye diagram closure after harmonic superposition is calculated. Cross-correlation analysis was performed on the amplitude attenuation of the third harmonic and the rate of change of the horizontal broadening of the eye diagram to generate a modified mapping matrix containing nonlinear compensation coefficients. In the Monte Carlo simulation, a harmonic distortion weighting factor is introduced. By adjusting the transmission line dielectric constant and skin effect parameters, the cumulative effect of higher harmonics on signal margin is simulated. The improved frequency-time mapping matrix was used for convergence verification. When the simulation error rate after third harmonic compensation was reduced by ≥40% compared with the original model, the nonlinear compensation was deemed effective.

[0070] This embodiment solves the problem of difficulty in quantifying high-frequency nonlinear distortion in traditional signal integrity assessment by capturing harmonic components, modeling nonlinear compensation, and verifying through co-simulation. It provides a more accurate and practical margin assessment scheme for high-speed circuit design.

[0071] In some embodiments, it also includes: The minimum upper limit voltage and the maximum lower limit voltage of at least three samples under test are obtained by step reverse bias test to construct the true boundary matrix. The deviation between the actual boundary matrix and the predicted values ​​of the initial simulation model is compared, and the residual distribution of the device model parameters and transmission line impedance is calculated. The 3σ principle of residual distribution is used to screen outlier samples and extract effective residual datasets. The Monte Carlo algorithm is used to statistically weight the effective residual dataset to generate a calibration factor library; The calibration factor library is iteratively injected into the initial simulation model, the eye diagram parameters are recalculated and convergence is verified with the updated true boundary until the simulation error rate is lower than the preset threshold.

[0072] Specifically, three general-purpose flash memory products from the same production batch that passed initial testing were selected as test samples. A stepped reverse bias voltage test was performed on each sample. The reverse bias voltage range was set from 0V to 5V, with a step value of 0.2V. After each bias level was held for 30 seconds, the reference voltage was pulled up and down according to a preset step, and the upper and lower limit voltages when the received signal was abnormal were recorded. The test data for each sample were processed, and their minimum upper limit voltage and maximum lower limit voltage were selected. The minimum upper limit voltage and maximum lower limit voltage of the three samples were arranged by sample number to construct a 3x2 true boundary matrix, where the matrix elements correspond to the critical boundary voltage values ​​of different samples.

[0073] Next, the initial simulation model of this type of finished product is retrieved. This model is constructed based on PCB design parameters, device data, and transmission line theory, and includes device model parameters (such as parasitic capacitance and series resistance) and transmission line impedance parameters. The initial simulation model is run to obtain the predicted values ​​corresponding to the true boundary matrix, forming the predicted boundary matrix. The difference between the corresponding elements in the true boundary matrix and the predicted boundary matrix is ​​calculated to obtain the device model parameter residuals and transmission line impedance residuals. A residual distribution curve is generated by fitting a probability density function, and the curve reflects the numerical range and probability of occurrence of the residuals.

[0074] Then, the standard deviation σ is calculated based on the residual distribution curve. The outlier threshold is determined according to the 3σ principle; samples with an absolute residual value exceeding 3σ are considered outlier samples. The residual data of the three samples are then screened to remove the residuals corresponding to outlier samples, retaining the remaining residual data to form a valid residual dataset, ensuring the statistical validity of the dataset.

[0075] The Monte Carlo algorithm is then used to process the effective residual dataset. The number of random samplings is set to 10,000, with each sampling weighted according to the probability of the residual occurrence. A weighted average is calculated for different residual intervals. A calibration factor library is generated based on the weighted results. This library contains calibration coefficients for device model parameters (parasitic capacitance, series resistance) and transmission line impedance, with each coefficient corresponding to a correction value for a specific residual interval.

[0076] Subsequently, calibration coefficients from the calibration factor library are proportionally injected into the initial simulation model to update the device parameters and transmission line impedance parameters in the model. The model is then rerun to calculate the eye diagram parameters (eye height, eye width, and closure). The latest true boundary data of the sample under test is collected at this point (obtained through a second bias test). The updated simulated eye diagram parameters are compared with the latest true boundary data, and the error rate between the two is calculated. If the error rate is higher than a preset threshold (set to 5%), the weight allocation of the calibration factor library is adjusted, the model is injected again, and verification is performed. If the error rate is lower than 5%, the model is considered to have converged, the initial simulation model calibration is completed, and the calibrated model is output for subsequent product design simulation.

[0077] Through a closed-loop process of iteratively injecting a calibration factor library and verifying convergence, the initial simulation model is continuously optimized until the simulation error rate falls below a preset threshold. This ensures that the calibrated model accurately matches the characteristics of real products, significantly improving the reliability of simulation results. The calibrated simulation model can be directly used for subsequent product design iterations, reducing the cost and time required for physical sample testing. Simultaneously, it can predict signal integrity risks in advance, providing a scientific basis for parameter control in mass production and improving product reliability and mass production yield.

[0078] In some embodiments, for each test sample that has completed signal training, a sampling clock phase bias test is performed while keeping the reference voltage Vref constant. Using an initial phase step value, the sampling clock phase is offset in both the advance and delay directions at preset intervals.

[0079] Next, the quality of the received signal is monitored, and the initial early phase boundary and the initial delayed phase boundary are recorded when the signal first shows an anomaly. Subsequently, a more refined second phase step value is used to perform a precise scan near the initial boundaries to determine the final early phase boundary point Φ_early and the delayed phase boundary point Φ_late, respectively.

[0080] Then, the measured eye width boundary for each sample is calculated: T_eye_width = Φ_late - Φ_early. By performing the same test on a batch of samples, the smallest T_eye_width value among all samples is selected as the guaranteed eye width for that batch of products.

[0081] Next, the guaranteed eye width is compared with the minimum eye width threshold required by the product specification to evaluate the timing design margin. Combined with the previously obtained eye height amplitude margin evaluation results, this constitutes a complete margin verification of the signal eye diagram in both voltage amplitude and time axis dimensions, forming a comprehensive signal eye diagram margin evaluation method.

[0082] This embodiment uses batch samples to conduct pull-off tests, sets the eye height of the deviation degradation digital eye diagram, narrows the eye height margin to the limit, and records the degradation results to comprehensively evaluate the safety of the signal integrity design. This ensures that the product can tolerate material consistency deviations and has better compatibility and robustness after mass production.

[0083] Please see Figure 5 This embodiment provides a deflection device 200 for verifying the high amplitude margin of a signal eye, comprising: The acquisition unit 201 is used to acquire a batch of samples to be tested, train the received signals of the samples to be tested, and determine the eye diagram template and reference voltage corresponding to the received signals. The biasing unit 202 is used to bias the reference voltage upward and downward according to a preset step for each of the test samples until the received signal is abnormal, and to record the upper limit voltage when the received signal is abnormal after the upward bias and the lower limit voltage when the received signal is abnormal after the downward bias. The screening unit 203 is used to screen out the minimum upper limit voltage from all the upper limit voltages of the test samples and to screen out the maximum lower limit voltage from all the lower limit voltages of the test samples. The calculation unit 204 is used to calculate the difference between the minimum upper limit voltage and the maximum lower limit voltage, and compare the difference with the size of the eye height range of the eye diagram template; The first determination unit 205 is used to determine that the eye height amplitude margin of the high-speed signal corresponding to the test sample meets the design requirements if the difference is greater than the eye height range of the eye diagram template. The second determination unit 206 is used to determine that the eye height amplitude margin of the high-speed signal does not meet the design requirements if the difference is less than or equal to the eye height range of the eye diagram template.

[0084] Furthermore, the biasing unit 202 includes: The first offset subunit is used to offset the reference voltage upward using the first step value to generate a first upward offset voltage sequence; The first determining subunit is used to determine the initial upward abnormal voltage point at which the received signal first shows an abnormality based on the first upward offset voltage sequence; The second offset subunit is used to offset the reference voltage upward using a second step value, starting from the initial upward abnormal voltage point, to generate a second upward offset voltage sequence; wherein the second step value is smaller than the first step value; The voltage determination subunit is used to determine the upper limit voltage when the received signal is abnormal after the upward pull-off voltage sequence.

[0085] Furthermore, the biasing unit 202 also includes: The third offset subunit is used to offset the reference voltage downward using a third step value to generate a first downward offset voltage sequence; The second determining subunit is used to determine the initial downward abnormal voltage point at which the received signal first shows an abnormality based on the first downward offset voltage sequence; A sequence generation subunit is used to generate a second downward offset voltage sequence by using the initial downward abnormal voltage point as the starting point and offsetting the reference voltage downward using a fourth step value; wherein the fourth step value is less than the third step value; A pull-down biasing subunit is used to determine the lower limit voltage when the received signal is abnormal after pull-down biasing, based on the second downward offset voltage sequence.

[0086] Furthermore, the abnormality in the received signal specifically includes at least one of the following situations: The bit error rate of the received signal exceeds the preset bit error rate threshold; The cumulative duration for which the received signal waveform deviates from the eye diagram template within a preset period exceeds a predetermined duration; The amplitude of the jitter in the received signal waveform exceeds a predetermined proportion of the voltage range.

[0087] Furthermore, it also includes: The data acquisition unit is used to acquire transmission line impedance change data in real time through a time domain reflectometer and generate an impedance change curve that includes the location and magnitude of impedance abrupt change points. The joint analysis unit is used to perform joint analysis of the impedance change curve with the pre-measured frequency domain parameters to generate channel comprehensive evaluation parameters; The step value calculation unit is used to calculate the pull step value under the current test state based on the channel comprehensive evaluation parameters and through an adaptive algorithm.

[0088] Furthermore, it also includes: The sample acquisition unit is used to acquire the sample to be tested. The curve acquisition unit is used to perform frequency domain parameter testing on the sample under test and acquire the insertion loss curve of the transmission path. The eye diagram testing unit is used to perform a time-domain eye diagram test on the sample to be tested and generate a corresponding eye diagram template and closure curve. The frequency band division unit is used to divide the frequency bands in the insertion loss curve that are higher than a preset frequency threshold into multiple sub-frequency bands, and calculate the average insertion loss value corresponding to each sub-frequency band respectively. The correlation analysis unit is used to perform correlation analysis between the average insertion loss value of each sub-frequency band and the closure change rate of the corresponding frequency band in the eye diagram template, and generate a frequency domain time domain mapping matrix. The factor determination unit is used to determine the dominant factors of high-frequency signal distortion based on the positive correlation between the average insertion loss value and the rate of change of closure in the frequency-domain and time-domain mapping matrix. The dominant factors include impedance abrupt change points, abnormal dielectric loss regions, or connector defect locations in the transmission path.

[0089] Furthermore, it also includes: The matrix construction unit is used to obtain the minimum upper limit voltage and the maximum lower limit voltage of at least three samples under test through a stepped reverse bias test, and to construct the true boundary matrix. The comparison unit is used to compare the deviation between the true boundary matrix and the predicted value of the initial simulation model, and to calculate the residual distribution of the device model parameters and transmission line impedance. The extraction unit is used to filter out abnormal deviation samples based on the 3σ principle of the residual distribution and extract the effective residual dataset; The statistical weighting unit is used to perform statistical weighting on the effective residual dataset using the Monte Carlo algorithm to generate a calibration factor library. An iterative unit is used to iteratively inject the calibration factor library into the initial simulation model, recalculate the eye diagram parameters, and perform convergence verification with the updated true boundary until the simulation error rate is lower than a preset threshold.

[0090] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described apparatus and unit can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0091] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, can implement the methods provided in the above embodiments. The storage medium may include various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0092] The present invention also provides a computer device, which may include a memory and a processor. The memory stores a computer program, and when the processor calls the computer program in the memory, it can implement the methods provided in the above embodiments. Of course, the computer device may also include various network interfaces, power supplies, and other components.

[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this invention.

[0094] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusivity.

[0095] The term "comprises" implies that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for verifying the high amplitude margin of a signal eye by deflection, characterized in that, include: Acquire a batch of test samples, train the received signals of the test samples, and determine the eye diagram template and reference voltage corresponding to the received signals; For each of the test samples, the reference voltage is pulled upward and downward according to a preset step until the received signal becomes abnormal. The upper limit voltage when the received signal becomes abnormal after the upward pull and the lower limit voltage when the received signal becomes abnormal after the downward pull are recorded. The minimum upper limit voltage is selected from the upper limit voltages of all test samples, and the maximum lower limit voltage is selected from the lower limit voltages of all test samples. Calculate the difference between the minimum upper limit voltage and the maximum lower limit voltage, and compare the difference with the eye height range of the eye diagram template; If the difference is greater than the eye height range of the eye diagram template, then it is determined that the eye height amplitude margin of the high-speed signal corresponding to the test sample meets the design requirements. If the difference is less than or equal to the eye height range of the eye diagram template, then the eye height amplitude margin of the high-speed signal is determined to be unsatisfactory.

2. The method for deflecting the high amplitude margin of the verification signal eye according to claim 1, characterized in that, For each sample to be tested, the reference voltage is pulled upwards and downwards according to preset steps until the received signal becomes abnormal. The upper limit voltage when the received signal becomes abnormal after upward pulling and the lower limit voltage when the received signal becomes abnormal after downward pulling are recorded as follows: The reference voltage is shifted upward using the first step value to generate a first upward shifted voltage sequence; The initial upward abnormal voltage point at which the received signal first shows an anomaly is determined based on the first upward offset voltage sequence; Starting from the initial upward abnormal voltage point, a second upward offset voltage sequence is generated by using a second step value to offset the reference voltage upward; wherein, the second step value is less than the first step value. The upper limit voltage when the received signal is abnormal after upward deflection is determined based on the second upward offset voltage sequence.

3. The method for deflecting the high amplitude margin of the verification signal eye according to claim 1, characterized in that, For each sample to be tested, the reference voltage is pulled upwards and downwards according to preset steps until the received signal becomes abnormal. The upper limit voltage when the received signal becomes abnormal after upward pulling and the lower limit voltage when the received signal becomes abnormal after downward pulling are recorded as follows: The reference voltage is shifted downward using the third step value to generate a first downward shifted voltage sequence; The initial downward abnormal voltage point at which the received signal first shows an anomaly is determined based on the first downward offset voltage sequence; Starting from the initial downward abnormal voltage point, a second downward offset voltage sequence is generated by offsetting the reference voltage downward using a fourth step value; wherein, the fourth step value is less than the third step value. The lower limit voltage when the received signal is abnormal after downward pull-off is determined based on the second downward offset voltage sequence.

4. The method for deflecting the high amplitude margin of the verification signal eye according to claim 1, characterized in that, The abnormality in the received signal specifically includes at least one of the following situations: The bit error rate of the received signal exceeds the preset bit error rate threshold; The cumulative duration for which the received signal waveform deviates from the eye diagram template within a preset period exceeds a predetermined duration; The amplitude of the jitter in the received signal waveform exceeds a predetermined proportion of the voltage range.

5. The method for deflecting the high amplitude margin of the verification signal eye according to claim 1, characterized in that, Also includes: The impedance change data of the transmission line is collected in real time by a time domain reflectometer, and an impedance change curve containing the location and magnitude of impedance abrupt change points is generated. The impedance variation curve is combined with the pre-measured frequency domain parameters to generate comprehensive channel evaluation parameters. Based on the comprehensive evaluation parameters of the channel, the pull-off step value under the current test state is calculated by an adaptive algorithm.

6. The method for deflecting the high amplitude margin of the verification signal eye according to claim 1, characterized in that, Also includes: Obtain the sample to be tested; Frequency domain parameter testing is performed on the sample under test to obtain the insertion loss curve of the transmission path; Perform a time-domain eye diagram test on the sample to be tested to generate the corresponding eye diagram template and closure curve; The frequency bands in the insertion loss curve that are higher than a preset frequency threshold are divided into multiple sub-frequency bands, and the average insertion loss value corresponding to each sub-frequency band is calculated. The average insertion loss value of each sub-band is correlated with the closure change rate of the corresponding frequency band in the eye diagram template to generate a frequency domain and time domain mapping matrix. Based on the positive correlation between the average insertion loss value and the rate of change of closure in the frequency-time domain mapping matrix, the dominant factors of high-frequency signal distortion are determined. The dominant factors include impedance abrupt change points, abnormal dielectric loss regions, or connector defect locations in the transmission path.

7. The method for deflecting the high amplitude margin of the verification signal eye according to claim 1, characterized in that, Also includes: The minimum upper limit voltage and the maximum lower limit voltage of at least three samples under test are obtained by step reverse bias test to construct the true boundary matrix. The deviation between the actual boundary matrix and the predicted values ​​of the initial simulation model is compared, and the residual distribution of the device model parameters and transmission line impedance is calculated. Based on the 3σ principle of the residual distribution, abnormal deviation samples are screened to extract the effective residual dataset; The Monte Carlo algorithm is used to statistically weight the effective residual dataset to generate a calibration factor library; The calibration factor library is iteratively injected into the initial simulation model, the eye diagram parameters are recalculated and convergence verification is performed with the updated true boundary until the simulation error rate is lower than a preset threshold.

8. A deflection device for verifying the high amplitude margin of a signal eye, characterized in that, include: The acquisition unit is used to acquire a batch of samples to be tested, train the received signals of the samples to be tested, and determine the eye diagram template, reference voltage and voltage range corresponding to the received signals. The biasing unit is used to bias the reference voltage upward and downward according to a preset step for each of the test samples until the received signal is abnormal. It records the upper limit voltage when the received signal is abnormal after the upward bias and the lower limit voltage when the received signal is abnormal after the downward bias. The screening unit is used to screen out the minimum upper limit voltage from all the upper limit voltages of the test samples and the maximum lower limit voltage from all the lower limit voltages of the test samples. The calculation unit is used to calculate the difference between the minimum upper limit voltage and the maximum lower limit voltage, and compare the difference with the size of the eye height range of the eye diagram template; The first determination unit is used to determine that if the difference is greater than the eye height range of the eye diagram template, the eye height amplitude margin of the high-speed signal corresponding to the test sample meets the design requirements. The second determination unit is used to determine that the eye height amplitude margin of the high-speed signal does not meet the design requirements if the difference is less than or equal to the eye height range of the eye diagram template.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method for adjusting the high amplitude margin of the verification signal eye as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the biasing method for verifying the high amplitude margin of the signal eye as described in any one of claims 1 to 7.

Images