Column readout circuit, chip, image sensor, and imaging device
By designing a column readout circuit, including a buffer, load line, and multiplexer, the problems of large area and high cost of column readout circuits were solved, achieving high performance in low-cost projects.
CN121506209BActive Publication Date: 2026-06-02MAGVISION SEMICON (BEIJING) INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MAGVISION SEMICON (BEIJING) INC
- Filing Date
- 2025-11-17
- Publication Date
- 2026-06-02
AI Technical Summary
Technical Problem
Existing column readout circuits are costly and have a large area due to the use of low threshold voltage devices, making it difficult to maintain high performance in low-cost projects.
Method used
By designing a column readout circuit, including a buffer, load line, multiplexer, and cache sub-circuit corresponding to the column storage cell, the load size of the buffer load line is reduced, and a metal load line and integrated multiplexer are used to reduce the circuit area.
Benefits of technology
It effectively reduces the overall area of the column memory circuit, significantly lowers the cost, and at the same time improves the signal setup speed while maintaining high performance.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN121506209B_ABST
Abstract
The application provides a column readout circuit, a chip, an image sensor and an imaging device. The column readout circuit comprises a buffer corresponding to a column storage unit of a column memory, at least two load lines, a multiplexer, a cache sub-circuit and a shift register, a first end of each buffer is configured to receive readout data of the column storage unit corresponding to the buffer, a second end of each buffer is coupled to a first end of the load line corresponding to the buffer, one or more buffers are coupled to each load line, a second end of the load line is coupled to an input end of the multiplexer, an output end of the multiplexer is coupled to a first node with an input end of the cache sub-circuit, an output end of the cache sub-circuit is coupled to a second node with the shift register, and the shift register is configured to output readout data. The application can effectively reduce the overall area of the column memory circuit and significantly reduce the cost. The application can also effectively improve the signal establishment speed.
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