Current-limiting protection circuit and CAN bus transceiver

Abstract

The invention relates to the field of CAN (Controller Area Network) bus transceivers, in particular to a current-limiting protection circuit and a CAN bus transceiver, comprising a high-voltage side current-limiting protection unit, a low-voltage side current-limiting protection unit and a driving unit, the high-voltage side current-limiting protection unit, the low-voltage side current-limiting protection unit and the driving unit are electrically connected with an external power supply VCC; the driving unit comprises a driving assembly, an enabling switch assembly, a current mirror assembly and a high-voltage side current-limiting protection unit, the low-voltage side current-limiting protection unit pulls up the voltage of a driving signal PDRIVER and the voltage of a driving signal NDRIVER when triggering short-circuit current-limiting protection, fault current is limited, dependence on thermal turn-off is avoided, and the reliability of short-circuit current-limiting protection is improved. And meanwhile, by reducing CL or Rload through the common-gate amplifier, extremely high bandwidth can be obtained, and faster system response can be obtained. And symmetrical high-voltage side current-limiting protection and low-voltage side current-limiting protection are arranged, so that the consistency of the protection capability of the CANH to ground short circuit and the protection capability of the CANL to high-voltage short circuit is ensured.

Description

Technical Field

[0001] This invention relates to the field of CAN bus transceivers, and more specifically to a current limiting protection circuit and a CAN bus transceiver. Background Technology

[0002] The CAN bus transceiver is a key component in a CAN (Controller Area Network) bus communication system. As the interface between the controller and the physical bus, it is responsible for converting the logic-level signals output by the controller into differential signals conforming to the CAN protocol specification, and simultaneously restoring the differential signals transmitted on the bus back to logic levels for controller processing. Its core function is to achieve signal level conversion and electrical isolation, ensuring communication reliability and interference immunity. In a CAN network, the transceiver typically uses differential transmission, transmitting complementary voltage signals through two signal lines (CAN_H and CAN_L). This design effectively suppresses common-mode noise and improves electromagnetic interference immunity, making it particularly suitable for highly interference-prone environments such as industrial automation and automotive electronics.

[0003] However, the current limiting protection mechanism of existing CAN bus transceivers is based on the current limiting protection circuit of traditional voltage comparators, which requires a stable reference voltage source, a high-gain amplifier and a comparator, increasing the response delay, chip design complexity and static power consumption. In addition, it relies on thermal shutdown protection, which has a slow response speed and cannot prevent instantaneous overshoot. Summary of the Invention

[0004] The purpose of this invention is to provide a current limiting protection circuit and a CAN bus transceiver, aiming to improve the problems of slow protection response and reliance on thermal shutdown in conventional current limiting protection circuits and CAN bus transceivers.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A current limiting protection circuit includes a high-voltage side current limiting protection unit, a low-voltage side current limiting protection unit, and a drive unit; the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, and the drive unit are all electrically connected to an external power supply VCC; the drive unit includes a drive component, an enable switch component, and a current mirror component; Signals TXDP and TXDN are input to the drive component, and signals STBP and STBN are input to the enable switch component. The signal input terminal of the high-voltage side current limiting protection unit acquires the current sensing signal PBACK of the high-voltage side, and the signal input terminal of the low-voltage side current limiting protection unit acquires the current sensing signal NBACK of the low-voltage side. The output terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit are electrically connected to the drive component. The enable switch assembly is electrically connected to the control terminals of the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, the current mirror assembly, and the drive assembly; the first output terminal of the current mirror assembly is electrically connected to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit; the second and third output terminals of the current mirror assembly are both electrically connected to the output terminals of the drive assembly; and the output terminals of the drive assembly output drive signals PDRIVER and NDRIVER.

[0006] Furthermore, the high-voltage side current limiting protection unit includes MOSFETs P4, P5, P6, P7, N4, N5, N6, and N7, and resistor R4; The source of MOSFET P6, the source of MOSFET P7, and one end of resistor R4 are all electrically connected to the external power supply VCC; the source of MOSFET P4 acquires the current sensing signal PBACK from the high-voltage side; the gate of MOSFET P6 is electrically connected to the first output terminal of the current mirror assembly. The other end of resistor R4 is electrically connected to the source of MOSFET P5 and the low-voltage side current limiting protection unit. The gate and drain of MOSFET P5 are both electrically connected to the gate of MOSFET P4 and the drain of MOSFET N5. The drain of MOSFET P4 is electrically connected to the drain of MOSFET N4 and serves as the output terminal, electrically connected to the driving component. The gate of MOSFET N4 is electrically connected to the gate of MOSFET N5, the drain of MOSFET P6, the gate and drain of MOSFET N6, and the gate of MOSFET N7, and is electrically connected to the enable switch component. The gate and drain of MOSFET P7 are both electrically connected to the drain of MOSFET N7 and are electrically connected to the enable switch component and the low-voltage side current limiting protection unit. The sources of MOSFETs N4, N5, N6, and N7 are all grounded.

[0007] Furthermore, the low-voltage side current limiting protection unit includes MOSFETs P8, P9, P10, P11, P14, N8, N9, N11, N12, N13 and resistor R5; The sources of MOSFETs P8, P9, P10, P11, and P14 are all electrically connected to the external power supply VCC; the source of MOSFET N8 acquires the current sensing signal NBACK from the low-voltage side; and the gate of MOSFET P14 is electrically connected to the first output terminal of the current mirror assembly. The gate of MOSFET P8 is electrically connected to the gates of MOSFET P9 and MOSFET P7, and is electrically connected to the enable switch assembly. The drain of MOSFET P8 is electrically connected to the drain of MOSFET N8, and serves as the output terminal, electrically connected to the drive assembly. The gate of MOSFET N8 is electrically connected to the gate, drain, and drain of MOSFET N9 and MOSFET P9. The source of MOSFET N9 is electrically connected to one end of resistor R5 and the drain of MOSFET P10. The gate of MOSFET P10 is electrically connected to the gate, drain, and drain of MOSFET P11 and MOSFET N11, and is electrically connected to the enable switch assembly. The drain of MOSFET P14 is electrically connected to the gate and drain of MOSFET N13, the gate of MOSFET N12, and the gate of MOSFET N11, and is electrically connected to the enable switch assembly; the drain of MOSFET N12 is electrically connected to the other end of resistor R4. The source of MOS transistor N11, the source of MOS transistor N12, the source of MOS transistor N13, and the other end of resistor R5 are all grounded.

[0008] Furthermore, the following condition is satisfied: (W / L) P4 = (W / L) P5 = (W / L) P6 = (W / L) P7 = (W / L) P8 = (W / L) P9 ; (W / L) N4 = (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 = (W / L) N9 ; Among them, (W / L) P4 The width-to-length ratio (W / L) of MOSFET P4 P5 The width-to-length ratio (W / L) of MOSFET P5 P6 The width-to-length ratio (W / L) of MOSFET P6 P7 The width-to-length ratio (W / L) of MOSFET P7. P8 The width-to-length ratio (W / L) of MOSFET P8 P9 The width-to-length ratio (W / L) of MOSFET P9. N4 The width-to-length ratio (W / L) of MOSFET N4 N5 The width-to-length ratio (W / L) of MOSFET N5 N6 The width-to-length ratio (W / L) of MOSFET N6 N7 The width-to-length ratio (W / L) of MOSFET N7N8 The width-to-length ratio (W / L) of MOSFET N8 N9 This refers to the width-to-length ratio of MOSFET N9.

[0009] Furthermore, the driving unit includes MOS transistors P21, P22, P23, N23, N25, and N26; The sources of MOSFETs P21, P22, and P23 are all electrically connected to the external power supply VCC; the output of the high-voltage side current limiting protection unit is electrically connected to the gate of MOSFET P21, and the output of the low-voltage side current limiting protection unit is electrically connected to the gate of MOSFET N25; the signal TXDP is input to the gate of MOSFET P22, and the signal TXDN is input to the gate of MOSFET N26; the drain of MOSFET P23 is electrically connected to the drain of MOSFET N23, and is also electrically connected to the enable switch assembly. The drain of MOSFET P21 is electrically connected to the drain of MOSFET P22, the gate of MOSFET P23, the second output terminal of the current mirror assembly, and the enable switch assembly, and serves as the output terminal to output the drive signal PDRIVER; the drain of MOSFET N25 is electrically connected to the drain of MOSFET N26, the gate of MOSFET N23, the third output terminal of the current mirror assembly, and the enable switch assembly, and serves as the output terminal to output the drive signal NDRIVER. The sources of MOS transistors N23, N25, and N26 are all grounded.

[0010] Furthermore, the enable switch assembly includes MOSFETs P12, P13, P24, P25, P26, P27, N10, N15, N20, N21, and N22, and transmission gates TG1 and TG2. The signal STBP is input to the gates of MOSFETs P12, P13, P24, P25, P26, and P27, and pin 1 of transmission gate TG1 and pin 1 of transmission gate TG2; the signal STBN is input to the gates of MOSFETs N10, N15, N20, N21, and N22, and pin 2 of transmission gate TG2 and pin 2 of transmission gate TG1; the sources of MOSFETs P12, P13, P24, P25, P26, and P27 are all electrically connected to the external power supply VCC. The drain of MOSFET P12 is electrically connected to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit. The drains of MOSFET P13 and MOSFET N15 are both electrically connected to the control terminals of the low-voltage side current limiting protection unit. The drain of MOSFET N10 is electrically connected to the control terminal of the high-voltage side current limiting protection unit. The drains of MOSFETs P24, P25, P26, N20, and N21 are all electrically connected to the control terminal of the current mirror assembly; the drain of MOSFET P27 and pin 3 of transmission gate TG1 are both electrically connected to the gate of MOSFET P23; the drain of MOSFET N22 and pin 4 of transmission gate TG2 are both electrically connected to the gate of MOSFET N23; and pin 4 of transmission gate TG1 and pin 3 of transmission gate TG2 are both electrically connected to the drains of MOSFETs P23 and N23. The sources of MOSFETs N10, N15, N20, N21, and N22 are all grounded.

[0011] Furthermore, the current mirror assembly includes MOSFETs P15, P16, P17, P18, P19, P20 and N14, N16, N17, N18, N19, and N24. The sources of MOSFETs P15, P16, P17, P18, P19, and P20 are all electrically connected to the external power supply VCC. The gate and drain of MOSFET P15 are electrically connected to the gate of MOSFET P16, the drain of MOSFET N14, and the drain of MOSFET P24, and are electrically connected as the first output terminal to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit; an external constant bias voltage VB2 is input to the gate of MOSFET N14; the drain of MOSFET P16 is electrically connected to the gate and drain of MOSFET N16, the gate of MOSFET N17, and the drain of MOSFET N20; the drain of MOSFET N17 is connected to the gate and drain of MOSFET P17, and the drain of MOSFET P18... The gate of MOSFET P18 is electrically connected to the drain of MOSFET P25; the drain of MOSFET P18 is electrically connected to the gate and drain of MOSFET N18, the gate of MOSFET N19, the gate of MOSFET N24, and the drain of MOSFET N21; the drain of MOSFET N19 is electrically connected to the gate and drain of MOSFET P19, the gate of MOSFET P20, and the drain of MOSFET P26; the drains of MOSFET P20 and MOSFET N24 are respectively used as the third output terminal and the second output terminal, and are electrically connected to the drains of MOSFET N25 and MOSFET P21. The sources of MOSFET N14, N16, N17, N18, N19, and N24 are all grounded.

[0012] To achieve the above objectives, the present invention also adopts the following technical solution: A CAN bus transceiver includes the current limiting protection circuit and the signal receiving module output module; An external input signal TXD and an enable signal STB are input to a signal receiving module. The signal receiving module outputs signals TXDP and TXDN to a drive component. The signal receiving module outputs signals STBP and STBN to an enable switch component. The output terminal of the drive component outputs drive signals PDRIVER and NDRIVER to an output module. The output module outputs signals CANH and CANL.

[0013] Furthermore, the signal receiving module includes MOS transistors P2, P3, N2, and N3, inverters U100, U101, U103, U104, U105, and U106, NOR gate U102, and resistors R2 and R3. The sources of MOSFET P2 and MOSFET P3 are both electrically connected to the external power supply VCC; the external input signal TXD is input to one end of resistor R2, the external enable signal STB is input to one end of resistor R3; the external bias voltage VB1 is input to the gate of MOSFET N3. The gate and drain of MOS transistor P2 are electrically connected to the gate of MOS transistor P3 and the drain of MOS transistor N3. The drain of MOS transistor P3 is electrically connected to the gate, source, and input terminal of inverter U100 of MOS transistor N2. The other end of resistor R2 is electrically connected to the drain of MOS transistor N2. The output terminal of inverter U100 is electrically connected to the input terminal of inverter U101, the output terminal of inverter U101 is electrically connected to the first input terminal of NOR gate U102, the other end of resistor R3 is electrically connected to the input terminal of inverter U105 and the second input terminal of NOR gate U102, and the output terminal of NOR gate U102 is electrically connected to the input terminal of inverter U103. The output terminal of inverter U103 is electrically connected to the input terminal of inverter U104, and outputs a signal TXDP to the drive component. The output terminal of inverter U104 outputs a signal TXDN to the drive component. The output terminal of inverter U105 is electrically connected to the input terminal of inverter U106, and outputs a signal STBP to the enable switch component. The output terminal of inverter U106 outputs a signal STBN to the enable switch component. The source of the MOS transistor N3 is grounded.

[0014] Furthermore, the output module includes MOSFETs P0, P1, N100, N0, N1, and N101, and resistors R0 and R1. The source of the MOSFET P1 and one end of the resistor R0 are both electrically connected to the external power supply VCC. The other end of the resistor R0 is electrically connected to the source of the MOSFET P0 and to the signal input terminal of the high-voltage side current limiting protection unit. The signal input terminal of the low-voltage side current limiting protection unit is electrically connected to one end of the resistor R1 and the source of the MOSFET N0. The drive component outputs a drive signal PDRIVER to the gate of MOS transistor P0 and the gate of MOS transistor P1. The drain of MOS transistor P0 and the drain of MOS transistor P1 are electrically connected to the gate and source of MOS transistor N100. The drain of MOS transistor N100 outputs a signal CANH. The driving component outputs a driving signal NDRIVER to the gate of MOS transistor N0 and the gate of MOS transistor N1. The drains of MOS transistor N0 and MOS transistor N1 are electrically connected to the drain of MOS transistor N101. The gate and source of MOS transistor N101 output a signal CANL. The other end of the resistor R1 and the source of the MOS transistor N1 are both grounded.

[0015] By adopting the above technical solution, the present invention has the following advantages compared with the prior art: 1. When the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit trigger short-circuit current limiting protection, they increase the voltage drop across the sensing resistor, increase the voltage of the drive signal PDRIVER, and decrease the voltage of the drive signal NDRIVER, weakening the conduction of the drive transistor and thus limiting the fault current. This current limiting protection is a continuous clamping process, and the drive transistor still maintains a relatively small dominant current under the current limiting state. The bus physical layer remains in a dominant state and will not cause bus error frames, retransmissions, or communication interruptions due to node protection. This avoids relying on thermal shutdown protection, which directly cuts off current conduction, improving system communication reliability and meeting the functional safety requirements for communication continuity. At the same time, by utilizing the characteristics of the common-gate amplifier—no Miller effect and the fact that the gain term does not appear in the denominator of the bandwidth formula—extremely high bandwidth can be obtained by reducing CL or Rload, resulting in a faster system response. Symmetrical high-voltage side current limiting protection and low-voltage side current limiting protection are set to ensure consistent protection capabilities against CANH to ground short circuits and CANL to high-voltage short circuits.

[0016] 2. When the external input signal TXD is left floating, a constant current source charges the pin, pulling its voltage up to near VCC, thus reliably identifying it as a logic high. Due to this constant current, if the MCU loses its driving capability, the external input signal TXD voltage will be immediately and definitively pulled high, and the CAN bus transceiver will automatically enter a recessive state, preventing the bus from being accidentally locked in a dominant state and paralyzing the entire network. When the external enable signal STB is high, the CAN bus transceiver enters a recessive state; when STB is low, the CAN bus transceiver enters a dominant state. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of the current limiting protection circuit described in this invention; Figure 2 This is a circuit diagram of the CAN bus transceiver described in this invention; Figure 3 This is a circuit diagram of the signal receiving module of the CAN bus transceiver described in this invention. Figure 4 This is a simulation diagram of the CAN bus transceiver described in this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0019] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0020] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0021] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0022] Please refer to Figure 1 As shown, this embodiment provides a current-limiting protection circuit, including a high-voltage side current-limiting protection unit, a low-voltage side current-limiting protection unit, and a drive unit. All three units are electrically connected to an external power supply VCC. The drive unit includes a drive assembly, an enable switch assembly, and a current mirror assembly. Signals TXDP and TXDN are input to the drive assembly, and signals STBP and STBN are input to the enable switch assembly. The signal input terminal of the high-voltage side current-limiting protection unit acquires the current-sensing signal PBACK from the high-voltage side, and the signal input terminal of the low-voltage side current-limiting protection unit acquires the current-sensing signal NBACK from the low-voltage side. The output terminals of the high-voltage side and low-voltage side current-limiting protection units are electrically connected to the drive assembly. The enable switch assembly is electrically connected to the control terminals of the high-voltage side current-limiting protection unit, the low-voltage side current-limiting protection unit, the current mirror assembly, and the drive assembly. The first output terminal of the current mirror assembly is electrically connected to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit. The second and third output terminals of the current mirror assembly are both electrically connected to the output terminals of the drive assembly. The output terminals of the drive assembly output drive signals PDRIVER and NDRIVER.

[0023] Specifically, the high-voltage side current limiting protection unit includes MOSFETs P4, P5, P6, P7, N4, N5, N6, and N7, and resistor R4.

[0024] The source of MOSFET P6, the source of MOSFET P7, and one end of resistor R4 are all electrically connected to the external power supply VCC; the source of MOSFET P4 acquires the current sensing signal PBACK from the high-voltage side; the gate of MOSFET P6 is electrically connected to the first output terminal of the current mirror assembly.

[0025] The other end of resistor R4 is electrically connected to the source of MOSFET P5 and the low-voltage side current limiting protection unit. The gate and drain of MOSFET P5 are both electrically connected to the gate of MOSFET P4 and the drain of MOSFET N5. The drain of MOSFET P4 is electrically connected to the drain of MOSFET N4 and serves as the output terminal, electrically connected to the drive component. The gate of MOSFET N4 is electrically connected to the gate of MOSFET N5, the drain of MOSFET P6, the gate and drain of MOSFET N6, and the gate of MOSFET N7, and is electrically connected to the enable switch component. The gate and drain of MOSFET P7 are both electrically connected to the drain of MOSFET N7, and are electrically connected to the enable switch component and the low-voltage side current limiting protection unit. The sources of MOSFETs N4, N5, N6, and N7 are all grounded.

[0026] In this amplifier, MOSFETs P4, P5, N4, and N5 form a common-gate amplifier. Resistor R4 and MOSFET P5 form an active-load common-source amplifier, providing voltage bias for the gate of MOSFET P4. MOSFETs P6, P7, N6, and N7 form a bias network used to set the operating points of MOSFETs N4 and N5.

[0027] The low-voltage side current limiting protection unit includes MOSFETs P8, P9, P10, P11, P14, N8, N9, N11, N12, and N13, and resistor R5.

[0028] The sources of MOSFETs P8, P9, P10, P11, and P14 are all electrically connected to the external power supply VCC; the source of MOSFET N8 acquires the current sensing signal NBACK from the low-voltage side; and the gate of MOSFET P14 is electrically connected to the first output terminal of the current mirror assembly.

[0029] The gate of MOSFET P8 is electrically connected to the gates of MOSFETs P9 and P7, and is also electrically connected to the enable switch assembly. The drain of MOSFET P8 is electrically connected to the drain of MOSFET N8, and serves as the output terminal, electrically connected to the drive assembly. The gate of MOSFET N8 is electrically connected to the gate, drain, and P9 of MOSFET N9. The source of MOSFET N9 is electrically connected to one end of resistor R5 and the drain of MOSFET P10. The gate of MOSFET P10 is electrically connected to the gate, drain, and N11 of MOSFETs P11, and is also electrically connected to the enable switch assembly. The drain of MOSFET P14 is electrically connected to the gate, drain, N13, N12, and N11 of MOSFETs, and is also electrically connected to the enable switch assembly. The drain of MOSFET N12 is electrically connected to the other end of resistor R4.

[0030] The source of MOSFET N11, the source of MOSFET N12, the source of MOSFET N13, and the other end of resistor R5 are all grounded.

[0031] MOSFETs P8, P9, N8, and N9 form a common-gate amplifier. Resistor R5 and MOSFET N9 form an active-load common-source amplifier to provide voltage bias for the gate of MOSFET N8. MOSFETs P10, P11, P14, N12, and N13 form a bias network to set the operating point of MOSFET N11.

[0032] The following conditions must be met. (W / L) P4 = (W / L) P5 = (W / L) P6 = (W / L) P7 = (W / L) P8 = (W / L) P9 ; (W / L) N4 = (W / L) N5 = (W / L) N6 = (W / L) N7 = (W / L) N8 = (W / L) N9 ; Among them, (W / L) P4 The width-to-length ratio (W / L) of MOSFET P4 P5 The width-to-length ratio (W / L) of MOSFET P5 P6 The width-to-length ratio (W / L) of MOSFET P6 P7 The width-to-length ratio (W / L) of MOSFET P7. P8 The width-to-length ratio (W / L) of MOSFET P8P9 The width-to-length ratio (W / L) of MOSFET P9. N4 The width-to-length ratio (W / L) of MOSFET N4 N5 The width-to-length ratio (W / L) of MOSFET N5 N6 The width-to-length ratio (W / L) of MOSFET N6 N7 The width-to-length ratio (W / L) of MOSFET N7 N8 The width-to-length ratio (W / L) of MOSFET N8 N9 This refers to the width-to-length ratio of MOSFET N9.

[0033] Specifically, the driving unit includes MOSFETs P21, P22, P23, N23, N25, and N26.

[0034] The sources of MOSFETs P21, P22, and P23 are all electrically connected to the external power supply VCC. The output of the high-voltage side current limiting protection unit is electrically connected to the gate of MOSFET P21, meaning the drain of MOSFET P4 is electrically connected to the gate of MOSFET P21. The output of the low-voltage side current limiting protection unit is electrically connected to the gate of MOSFET N25, meaning the drain of MOSFET N8 is electrically connected to the gate of MOSFET N25. The signal TXDP is input to the gate of MOSFET P22, and the signal TXDN is input to the gate of MOSFET N26. The drain of MOSFET P23 is electrically connected to the drain of MOSFET N23 and is also electrically connected to the enable switch assembly.

[0035] The drain of MOSFET P21 is electrically connected to the drain of MOSFET P22, the gate of MOSFET P23, the second output terminal of the current mirror assembly, and the enable switch assembly, and serves as the output terminal to output the drive signal PDRIVER; the drain of MOSFET N25 is electrically connected to the drain of MOSFET N26, the gate of MOSFET N23, the third output terminal of the current mirror assembly, and the enable switch assembly, and serves as the output terminal to output the drive signal NDRIVER.

[0036] The sources of MOSFETs N23, N25, and N26 are all grounded.

[0037] Specifically, the enable switch assembly includes MOSFETs P12, P13, P24, P25, P26, P27, N10, N15, N20, N21, and N22, and transmission gates TG1 and TG2.

[0038] The signal STBP is input to the gates of MOSFETs P12, P13, P24, P25, P26, and P27, as well as pin 1 of transmission gate TG1 and pin 1 of transmission gate TG2. The signal STBN is input to the gates of MOSFETs N10, N15, N20, N21, and N22, as well as pin 2 of transmission gate TG2 and pin 2 of transmission gate TG1. The sources of MOSFETs P12, P13, P24, P25, P26, and P27 are all electrically connected to the external power supply VCC.

[0039] The drain of MOSFET P12 is electrically connected to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit. Specifically, the drain of MOSFET P12 is electrically connected to the gate and drain of MOSFET P7, the gate of MOSFET P8, and the gate of MOSFET P9. The drains of MOSFET P13 and MOSFET N15 are both electrically connected to the control terminals of the low-voltage side current limiting protection unit. That is, the drain of MOSFET P13 is electrically connected to the gate of MOSFET P10, the gate and drain of MOSFET P11, and the drain of MOSFET N11; the drain of MOSFET N15 is electrically connected to the gate and drain of MOSFET N13, the gate of MOSFET N12, and the drain of MOSFET P14. The drain of MOSFET N10 is electrically connected to the control terminal of the high-voltage side current limiting protection unit. The drain of MOSFET N10 is also electrically connected to the gate and drain of MOSFET N6, the gate of MOSFET N4, the gate of MOSFET N5, the gate of MOSFET N7, and the drain of MOSFET P6.

[0040] The drains of MOSFETs P24, P25, P26, N20, and N21 are all electrically connected to the control terminal of the current mirror assembly. The drain of MOSFET P27 and pin 3 of transmission gate TG1 are electrically connected to the gate of MOSFET P23. The drain of MOSFET N22 and pin 4 of transmission gate TG2 are both electrically connected to the gate of MOSFET N23. Pin 4 of transmission gate TG1 and pin 3 of transmission gate TG2 are both electrically connected to the drains of MOSFETs P23 and N23.

[0041] The sources of MOSFETs N10, N15, N20, N21, and N22 are all grounded.

[0042] When the signal STB is 0, the enable switch component is in the off state, and the overall current limiting protection circuit is in the linear state; when STB=VCC, the enable switch component is in the on state, the gates of the PMOS transistors of the current mirror component are all shorted to the power supply, and the gates of the NMOS transistors of the current mirror component are all shorted to ground; this turns off the drive component and the current mirror component, and the overall current limiting protection circuit is in the invisible state, effectively reducing power consumption.

[0043] Specifically, the current mirror assembly includes MOSFETs P15, P16, P17, P18, P19, P20, N14, N16, N17, N18, N19, and N24.

[0044] The sources of MOSFETs P15, P16, P17, P18, P19, and P20 are all electrically connected to the external power supply VCC.

[0045] The gate and drain of MOSFET P15 are electrically connected to the gate of MOSFET P16, the drain of MOSFET N14, and the drain of MOSFET P24, and are electrically connected as the first output terminal to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit; that is, the gate and drain of MOSFET P15 are electrically connected to the gate of MOSFET P16, the drain of MOSFET N14, the drain of MOSFET P24, the gate of MOSFET P14, and the gate of MOSFET P6. An external constant bias voltage VB2 is input to the gate of MOSFET N14; the external constant bias voltage VB2 is used to control MOSFET N14 to provide a constant drain current I_BIAS, specifically, I_BIAS≈0.5*μn*Cox*(W / L). N14 *(VB2-Vth) 2 Where μn is the electron migration rate, Cox is the gate oxide capacitance per unit area, and Vth is the NMOS threshold voltage (W / L). N14 This represents the width-to-length ratio of the MOSFET N14.

[0046] The drain of MOSFET P16 is electrically connected to the gate and drain of MOSFET N16, the gate of MOSFET N17, and the drain of MOSFET N20. The drain of MOSFET N17 is electrically connected to the gate and drain of MOSFET P17, the gate of MOSFET P18, and the drain of MOSFET P25. The drain of MOSFET P18 is electrically connected to the gate and drain of MOSFET N18, the gate of MOSFET N19, the gate of MOSFET N24, and the drain of MOSFET N21. The drain of MOSFET N19 is electrically connected to the gate and drain of MOSFET P19, the gate of MOSFET P20, and the drain of MOSFET P26. The drains of MOSFET P20 and MOSFET N24 are respectively connected as the third and second output terminals, and are electrically connected to the drains of MOSFET N25 and MOSFET P21.

[0047] The sources of MOSFETs N14, N16, N17, N18, N19, and N24 are all grounded. The current mirror assembly provides a constant drive current to the drive assembly.

[0048] For further details, please refer to the appendix. Figure 2-4 This embodiment also discloses a CAN bus transceiver, including the above-mentioned current limiting protection circuit and signal receiving module output module; External input signal TXD and enable signal STB are input to the signal receiving module. The signal receiving module outputs signals TXDP and TXDN to the drive component. The signal receiving module outputs signals STBP and STBN to the enable switch component. The drive component outputs drive signals PDRIVER and NDRIVER to the output module. The output module outputs signals CANH and CANL.

[0049] Please refer to the appendix. Figure 3 Specifically, the signal receiving module includes MOSFETs P2, P3, N2, and N3, inverters U100, U101, U103, U104, U105, and U106, NOR gate U102, and resistors R2 and R3.

[0050] The sources of MOSFETs P2 and P3 are both electrically connected to the external power supply VCC; the external input signal TXD is input to one end of resistor R2, and the external enable signal STB is input to one end of resistor R3; the external bias voltage VB1 is input to the gate of MOSFET N3 to set the operating point of MOSFET N3.

[0051] The gate and drain of MOSFET P2 are electrically connected to the gate of MOSFET P3 and the drain of MOSFET N3. The drain of MOSFET P3 is electrically connected to the gate, source, and input terminal of inverter U100 of MOSFET N2. The other end of resistor R2 is electrically connected to the drain of MOSFET N2.

[0052] The output terminal of inverter U100 is electrically connected to the input terminal of inverter U101. The output terminal of inverter U101 is electrically connected to the first input terminal of NOR gate U102. The other end of resistor R3 is electrically connected to the input terminal of inverter U105 and the second input terminal of NOR gate U102. The output terminal of NOR gate U102 is electrically connected to the input terminal of inverter U103.

[0053] The output of inverter U103 is electrically connected to the input of inverter U104, and outputs signal TXDP to the drive component. The output of inverter U104 outputs signal TXDN to the drive component. The output of inverter U105 is electrically connected to the input of inverter U106, and outputs signal STBP to the enable switch component. The output of inverter U106 outputs signal STBN to the enable switch component. The source of MOSFET N3 is grounded.

[0054] Resistor R2, MOSFET N2, and resistor R3 form an input surge protection structure to protect against transient overshoot. MOSFETs N3, P2, and P3 form a current mirror, acting as a constant current source. When the external input signal TXD is left floating, the constant current source charges the pin, pulling its voltage up to near VCC, thus reliably identifying it as a logic high. Due to this constant current, if the MCU loses its driving capability, the external input signal TXD voltage will be immediately and definitively pulled high, and the CAN bus transceiver will automatically enter a recessive state, preventing the bus from being accidentally locked in a dominant state and paralyzing the entire network. When the external enable signal STB is high, the CAN bus transceiver enters a recessive state; when STB is low, the CAN bus transceiver enters a dominant state.

[0055] Please refer to the appendix. Figure 2 Specifically, the output module includes MOSFETs P0, P1, N100, N0, N1, and N101, and resistors R0 and R1.

[0056] The source of MOSFET P1 and one end of resistor R0 are both electrically connected to the external power supply VCC. The other end of resistor R0 is electrically connected to the source of MOSFET P0 and also electrically connected to the signal input terminal of the high-voltage side current limiting protection unit; that is, the other end of resistor R0 is electrically connected to the source of MOSFET P0 and the source of MOSFET P4. The signal input terminal of the low-voltage side current limiting protection unit is electrically connected to one end of resistor R1 and the source of MOSFET N0; that is, the source of MOSFET N8 is electrically connected to one end of resistor R1 and the source of MOSFET N0.

[0057] The drive component outputs a drive signal PDRIVER to the gates of MOSFETs P0 and P1. The drains of MOSFETs P0 and P1 are electrically connected to the gate and source of MOSFET N100. The drain of MOSFET N100 outputs a signal CANH. The drive component outputs a drive signal NDRIVER to the gates of MOSFETs N0 and N1. The drains of MOSFETs N0 and N1 are electrically connected to the drain of MOSFET N101. The gate and source of MOSFET N101 output a signal CANL. The other end of resistor R1 and the source of MOSFET N1 are both grounded.

[0058] MOSFETs N100 and N101 are both diode-connected NMOS transistors, using a body diode for output reverse protection. Resistors R0 and R1 are sensing resistors; MOSFETs P0 and N0 are current sampling transistors. MOSFETs P1 and N1 are output power transistors.

[0059] In this embodiment, all MOSFETs are SOI MOSFETs, meaning they are supplied using Silicon-On-Insulator (SOI) technology. In practical applications, the CANH and CANL pins typically need to withstand high positive and negative voltages. Traditional bulk silicon CMOS vertical DMOS structures usually have an inherent parasitic body diode that conducts when the pin voltage is lower than the substrate potential. If a bulk silicon CMOS process is used, when the CANH and CANL pins are connected to a negative high voltage, a huge leakage current will flow from GND to the negative voltage pin, disrupting the high-resistance state and normal function of the circuit. By adding a buried oxide layer on the traditional bulk silicon CMOS substrate to create dielectric isolation, in SOI, each NMOS or PMOS is an isolation island surrounded by silicon dioxide. Its body region is insulated from the substrate, thus eliminating the parasitic PN junction diode from the source / drain region to the common substrate, preventing large leakage currents during forward conduction. Taking high-voltage side current limiting protection as an example, V_PBACK is the induced voltage on the high-voltage side. In the small-signal model, the voltage gain AV of the common-gate amplifier on the high-voltage side is AV = Vout / V_PBACK ≈ gm4*Rload, where Vout is the drain voltage of MOSFET P4, which is also the output voltage of the common-gate amplifier, gm4 is the transconductance of MOSFET P4, Rload is the equivalent load resistance seen from the drain of MOSFET P4, and * is the multiplication operator.

[0060] Therefore, the drain voltage Vout of MOSFET P4 is approximately gm4*Rload*V_PBACK. Since gm4*Rload is much greater than 1, the small voltage fluctuation of V_PBACK at the signal input terminal of the high-voltage side current limiting protection unit can be rapidly amplified into a large voltage change, thereby increasing the ability to drive the subsequent MOSFET P21.

[0061] When short-circuit current limiting protection is triggered, the induced current on PBACK increases, the voltage drop across the sensing resistor R0 increases, and V_PBACK decreases. Therefore, the output voltage of the common-gate amplifier is also momentarily pulled down, increasing the absolute negative value of the gate voltage of MOSFET P21, thus enhancing the conduction of MOSFET P21. This enhanced conduction of MOSFET P21 pulls up the drive signal PDRIVER, causing the absolute negative value of the gate voltage of MOSFETs P0 and P1 to decrease, thereby weakening their conduction and limiting the fault current. At this time, MOSFETs P0 and P1 are not completely turned off, but maintain a small dominant current. The bus physical layer remains in a dominant state, preventing bus error frames, retransmissions, or communication interruptions caused by node protection. This continuous and smooth clamping adjustment avoids the oscillation problem caused by frequent toggling near the threshold when using digital comparators, and also avoids the risk of voltage spikes on the bus caused by direct turn-off.

[0062] Meanwhile, the -3dB bandwidth f of a traditional comparator −3dB≈gm / (2pi*CM*AV), where pi is the mathematical constant pi, gm is the transconductance of the comparator, CM is the Miller capacitance, and AV is the gain of the comparator. To achieve high-precision comparison, high gain is required, which directly leads to narrower bandwidth and slower response. The -3dB bandwidth f of the common-gate amplifier composed of MOSFETs P4, P5, N4, and N5 is approximately 1 / (2pi*Rload*CL). Here, pi is the mathematical constant pi, Rload is the equivalent load resistance seen from the drain of MOSFET P4, and CL is the equivalent load capacitance of the output node. Therefore, while obtaining the necessary gain, extremely high bandwidth can be achieved by reducing CL or Rload. Since the system response time is inversely proportional to the bandwidth, high bandwidth results in a faster system response, effectively overcoming the slow response of current limiting protection and reliance on thermal shutdown in existing CAN bus transceivers. Similarly, low-voltage side current limiting protection ensures consistent protection capabilities against CANH short circuits to ground and CANL high-voltage short circuits by setting symmetrical high-voltage side and low-voltage side current limiting protection.

[0063] Please refer to the appendix. Figure 4 , attached Figure 4 This is a simulation diagram of a CAN bus transceiver using the current-limiting protection circuit disclosed in this embodiment. In this embodiment, the external power supply voltage VCC = 5V, TXD is connected to a square wave signal, STB = 0 is the enabled state, CANH is short-circuited to ground, and CANL is short-circuited to the high voltage of 20V. (See attached diagram.) Figure 4 It can be seen that the short-circuit current on the high-voltage side and the low-voltage side are basically the same in magnitude and the response speed is also basically the same. The high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit ensure that the current limiting threshold is symmetrical, ensuring that the maximum transient power consumption that the chip can withstand is balanced under different faults and ensuring symmetrical response speed, avoiding additional heat accumulation and stress caused by slow response on one side.

[0064] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A current-limiting protection circuit, characterized in that, It includes a high-voltage side current limiting protection unit, a low-voltage side current limiting protection unit, and a drive unit; the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, and the drive unit are all electrically connected to an external power supply VCC; the drive unit includes a drive assembly, an enable switch assembly, and a current mirror assembly; Signals TXDP and TXDN are input to the drive component, and signals STBP and STBN are input to the enable switch component. The signal input terminal of the high-voltage side current limiting protection unit acquires the current sensing signal PBACK of the high-voltage side, and the signal input terminal of the low-voltage side current limiting protection unit acquires the current sensing signal NBACK of the low-voltage side. The output terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit are electrically connected to the drive component. The enable switch assembly is electrically connected to the control terminals of the high-voltage side current limiting protection unit, the low-voltage side current limiting protection unit, the current mirror assembly, and the drive assembly; the first output terminal of the current mirror assembly is electrically connected to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit; the second and third output terminals of the current mirror assembly are both electrically connected to the output terminals of the drive assembly; and the output terminals of the drive assembly output drive signals PDRIVER and NDRIVER.

2. The current limiting protection circuit according to claim 1, characterized in that: The high-voltage side current limiting protection unit includes MOSFETs P4, P5, P6, P7, N4, N5, N6, and N7, and resistor R4. The source of MOSFET P6, the source of MOSFET P7, and one end of resistor R4 are all electrically connected to the external power supply VCC; the source of MOSFET P4 acquires the current sensing signal PBACK from the high-voltage side; the gate of MOSFET P6 is electrically connected to the first output terminal of the current mirror assembly. The other end of resistor R4 is electrically connected to the source of MOSFET P5 and the low-voltage side current limiting protection unit. The gate and drain of MOSFET P5 are both electrically connected to the gate of MOSFET P4 and the drain of MOSFET N5. The drain of MOSFET P4 is electrically connected to the drain of MOSFET N4 and serves as the output terminal, electrically connected to the driving component. The gate of MOSFET N4 is electrically connected to the gate of MOSFET N5, the drain of MOSFET P6, the gate and drain of MOSFET N6, and the gate of MOSFET N7, and is electrically connected to the enable switch component. The gate and drain of MOSFET P7 are both electrically connected to the drain of MOSFET N7 and are electrically connected to the enable switch component and the low-voltage side current limiting protection unit. The sources of MOSFETs N4, N5, N6, and N7 are all grounded.

3. The current limiting protection circuit according to claim 2, characterized in that: The low-voltage side current limiting protection unit includes MOSFETs P8, P9, P10, P11, P14, N8, N9, N11, N12, N13 and resistor R5; The sources of MOSFETs P8, P9, P10, P11, and P14 are all electrically connected to the external power supply VCC; the source of MOSFET N8 acquires the current sensing signal NBACK from the low-voltage side; and the gate of MOSFET P14 is electrically connected to the first output terminal of the current mirror assembly. The gate of MOSFET P8 is electrically connected to the gates of MOSFET P9 and MOSFET P7, and is electrically connected to the enable switch assembly. The drain of MOSFET P8 is electrically connected to the drain of MOSFET N8, and serves as the output terminal, electrically connected to the drive assembly. The gate of MOSFET N8 is electrically connected to the gate, drain, and drain of MOSFET N9 and MOSFET P9. The source of MOSFET N9 is electrically connected to one end of resistor R5 and the drain of MOSFET P10. The gate of MOSFET P10 is electrically connected to the gate, drain, and drain of MOSFET P11 and MOSFET N11, and is electrically connected to the enable switch assembly. The drain of MOSFET P14 is electrically connected to the gate and drain of MOSFET N13, the gate of MOSFET N12, and the gate of MOSFET N11, and is electrically connected to the enable switch assembly; the drain of MOSFET N12 is electrically connected to the other end of resistor R4. The source of MOS transistor N11, the source of MOS transistor N12, the source of MOS transistor N13, and the other end of resistor R5 are all grounded.

4. The current limiting protection circuit according to claim 3, characterized in that: The following conditions must be met. (W / L) P4 =(W / L) P5 =(W / L) P6 =(W / L) P7 =(W / L) P8 =(W / L) P9 ; (W / L) N4 =(W / L) N5 =(W / L) N6 =(W / L) N7 =(W / L) N8 =(W / L) N9 ; Among them, (W / L) P4 The width-to-length ratio (W / L) of MOSFET P4 P5 The width-to-length ratio (W / L) of MOSFET P5 P6 The width-to-length ratio (W / L) of MOSFET P6 P7 The width-to-length ratio (W / L) of MOSFET P7. P8 The width-to-length ratio (W / L) of MOSFET P8 P9 The aspect ratio of MOSFET P9; (W / L) N4 The width-to-length ratio (W / L) of MOSFET N4 N5 The width-to-length ratio (W / L) of MOSFET N5 N6 The width-to-length ratio (W / L) of MOSFET N6 N7 The width-to-length ratio (W / L) of MOSFET N7 N8 The width-to-length ratio (W / L) of MOSFET N8 N9 This refers to the width-to-length ratio of MOSFET N9.

5. The current limiting protection circuit according to claim 1, characterized in that: The driving unit includes MOSFETs P21, P22, P23, N23, N25, and N26; The sources of MOSFETs P21, P22, and P23 are all electrically connected to the external power supply VCC; the output of the high-voltage side current limiting protection unit is electrically connected to the gate of MOSFET P21, and the output of the low-voltage side current limiting protection unit is electrically connected to the gate of MOSFET N25; the signal TXDP is input to the gate of MOSFET P22, and the signal TXDN is input to the gate of MOSFET N26; the drain of MOSFET P23 is electrically connected to the drain of MOSFET N23, and is also electrically connected to the enable switch assembly. The drain of MOSFET P21 is electrically connected to the drain of MOSFET P22, the gate of MOSFET P23, the second output terminal of the current mirror assembly, and the enable switch assembly, and serves as the output terminal to output the drive signal PDRIVER; the drain of MOSFET N25 is electrically connected to the drain of MOSFET N26, the gate of MOSFET N23, the third output terminal of the current mirror assembly, and the enable switch assembly, and serves as the output terminal to output the drive signal NDRIVER. The sources of MOS transistors N23, N25, and N26 are all grounded.

6. The current limiting protection circuit according to claim 5, characterized in that: The enable switch assembly includes MOSFETs P12, P13, P24, P25, P26, P27, N10, N15, N20, N21, and N22, and transmission gates TG1 and TG2. The signal STBP is input to the gates of MOSFETs P12, P13, P24, P25, P26, and P27, and pin 1 of transmission gate TG1 and pin 1 of transmission gate TG2; the signal STBN is input to the gates of MOSFETs N10, N15, N20, N21, and N22, and pin 2 of transmission gate TG2 and pin 2 of transmission gate TG1; the sources of MOSFETs P12, P13, P24, P25, P26, and P27 are all electrically connected to the external power supply VCC. The drain of MOSFET P12 is electrically connected to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit. The drains of MOSFET P13 and MOSFET N15 are both electrically connected to the control terminals of the low-voltage side current limiting protection unit. The drain of MOSFET N10 is electrically connected to the control terminal of the high-voltage side current limiting protection unit. The drains of MOSFETs P24, P25, P26, N20, and N21 are all electrically connected to the control terminal of the current mirror assembly; the drain of MOSFET P27 and pin 3 of transmission gate TG1 are both electrically connected to the gate of MOSFET P23; the drain of MOSFET N22 and pin 4 of transmission gate TG2 are both electrically connected to the gate of MOSFET N23; and pin 4 of transmission gate TG1 and pin 3 of transmission gate TG2 are both electrically connected to the drains of MOSFETs P23 and N23. The sources of MOSFETs N10, N15, N20, N21, and N22 are all grounded.

7. The current limiting protection circuit according to claim 6, characterized in that: The current mirror assembly includes MOSFETs P15, P16, P17, P18, P19, P20, N14, N16, N17, N18, N19, and N24. The sources of MOSFETs P15, P16, P17, P18, P19, and P20 are all electrically connected to the external power supply VCC. The gate and drain of MOSFET P15 are electrically connected to the gate of MOSFET P16, the drain of MOSFET N14, and the drain of MOSFET P24, and are electrically connected as the first output terminal to the control terminals of the high-voltage side current limiting protection unit and the low-voltage side current limiting protection unit; an external constant bias voltage VB2 is input to the gate of MOSFET N14; the drain of MOSFET P16 is electrically connected to the gate and drain of MOSFET N16, the gate of MOSFET N17, and the drain of MOSFET N20; the drain of MOSFET N17 is connected to the gate and drain of MOSFET P17, and the drain of MOSFET P18... The gate of MOSFET P18 is electrically connected to the drain of MOSFET P25; the drain of MOSFET P18 is electrically connected to the gate and drain of MOSFET N18, the gate of MOSFET N19, the gate of MOSFET N24, and the drain of MOSFET N21; the drain of MOSFET N19 is electrically connected to the gate and drain of MOSFET P19, the gate of MOSFET P20, and the drain of MOSFET P26; the drains of MOSFET P20 and MOSFET N24 are respectively used as the third output terminal and the second output terminal, and are electrically connected to the drains of MOSFET N25 and MOSFET P21. The sources of MOSFETs N14, N16, N17, N18, N19, and N24 are all grounded.

8. A CAN bus transceiver, characterized in that, Includes the current limiting protection circuit and signal receiving module output module as described in any one of claims 1-7; An external input signal TXD and an enable signal STB are input to a signal receiving module. The signal receiving module outputs signals TXDP and TXDN to a drive component. The signal receiving module outputs signals STBP and STBN to an enable switch component. The output terminal of the drive component outputs drive signals PDRIVER and NDRIVER to an output module. The output module outputs signals CANH and CANL.

9. The CAN bus transceiver according to claim 8, characterized in that: The signal receiving module includes MOS transistors P2, P3, N2, and N3, inverters U100, U101, U103, U104, U105, and U106, NOR gate U102, and resistors R2 and R3. The sources of MOSFET P2 and MOSFET P3 are both electrically connected to the external power supply VCC; the external input signal TXD is input to one end of resistor R2, the external enable signal STB is input to one end of resistor R3; the external bias voltage VB1 is input to the gate of MOSFET N3. The gate and drain of MOS transistor P2 are electrically connected to the gate of MOS transistor P3 and the drain of MOS transistor N3. The drain of MOS transistor P3 is electrically connected to the gate, source, and input terminal of inverter U100 of MOS transistor N2. The other end of resistor R2 is electrically connected to the drain of MOS transistor N2. The output terminal of inverter U100 is electrically connected to the input terminal of inverter U101, the output terminal of inverter U101 is electrically connected to the first input terminal of NOR gate U102, the other end of resistor R3 is electrically connected to the input terminal of inverter U105 and the second input terminal of NOR gate U102, and the output terminal of NOR gate U102 is electrically connected to the input terminal of inverter U103. The output terminal of inverter U103 is electrically connected to the input terminal of inverter U104, and outputs a signal TXDP to the drive component. The output terminal of inverter U104 outputs a signal TXDN to the drive component. The output terminal of inverter U105 is electrically connected to the input terminal of inverter U106, and outputs a signal STBP to the enable switch component. The output terminal of inverter U106 outputs a signal STBN to the enable switch component. The source of the MOS transistor N3 is grounded.

10. The CAN bus transceiver according to claim 8, characterized in that: The output module includes MOSFETs P0, P1, N100, N0, N1, and N101, and resistors R0 and R1. The source of the MOSFET P1 and one end of the resistor R0 are both electrically connected to the external power supply VCC. The other end of the resistor R0 is electrically connected to the source of the MOSFET P0 and to the signal input terminal of the high-voltage side current limiting protection unit. The signal input terminal of the low-voltage side current limiting protection unit is electrically connected to one end of the resistor R1 and the source of the MOSFET N0. The drive component outputs a drive signal PDRIVER to the gate of MOS transistor P0 and the gate of MOS transistor P1. The drain of MOS transistor P0 and the drain of MOS transistor P1 are electrically connected to the gate and source of MOS transistor N100. The drain of MOS transistor N100 outputs a signal CANH. The driving component outputs a driving signal NDRIVER to the gate of MOS transistor N0 and the gate of MOS transistor N1. The drains of MOS transistor N0 and MOS transistor N1 are electrically connected to the drain of MOS transistor N101. The gate and source of MOS transistor N101 output a signal CANL. The other end of the resistor R1 and the source of the MOS transistor N1 are both grounded.

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