Current multiplexing type output amplifier
By designing a current-reused output amplifier and utilizing a self-biased diode pair and a PMOS/NMOS combination architecture, the problem of needing to double the bias current under large dynamic input conditions in traditional amplifiers is solved, achieving high slew rate and wide bandwidth while reducing power consumption.
Patent Information
- Application Number
- CN202511452635.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-12
- Publication Date
- 2026-02-10
AI Technical Summary
Traditional folded cascode Class AB output amplifiers require double the bias current to achieve high slew rate and wide bandwidth under large dynamic input range, resulting in increased power consumption.
A current-reused output amplifier is adopted, which replaces the floating voltage source with two self-biased diodes and combines a current-reused architecture of PMOS and NMOS to achieve efficient current reuse and reduce the number of bias circuits.
Under the same bias current conditions, the slew rate and unity-gain bandwidth are doubled, reducing power consumption and improving amplifier performance.
Smart Images
Figure CN121508462A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of amplifier technology, and in particular to a current-multiplexed output amplifier used in integrators. Background Technology
[0002] Delta-Sigma modulators, as the core architecture of high-precision analog-to-digital converters, rely heavily on the design of their internal integrators for performance. The integrator, a key module of the modulator, is responsible for accumulating the input signal and implementing the noise transfer function. The amplifier is the core component of the integrator, and its performance determines the accuracy and linearity of the integration. In applications of Delta-Sigma modulators with large dynamic input ranges, high slew rate and wide bandwidth amplifiers are crucial for achieving high linearity integration. There is a strong correlation between the amplifier's slew rate and bandwidth and power consumption; in traditional amplifier designs, high slew rate and wide bandwidth are often achieved at the expense of power consumption.
[0003] In traditional integrator designs, folded cascode Class AB output amplifiers are frequently employed. Class AB output stages possess strong drive capability, allowing the amplifier's slew rate to be unrestricted by the static bias current of the output stage. Folded cascode Class AB amplifiers, such as... Figure 1 As shown, the input stage is biased by a single bias current 2I, and the output of the first stage is a floating voltage source, which provides the bias voltage for the Class AB output stage. When the differential input signals VIP and VIN are large positive and negative pulses, the amplifier's outputs VOP and VON will exhibit a linear change during the response period; the slope of this change is the amplifier's slew rate. For this type of amplifier, since its output stage is a Class AB push-pull output, MOSFETs PM10, PM11, NM12, and NM13 can provide very large transient currents when large pulse signals are input. The slew rate depends on the ratio of the current flowing through the compensation capacitor to the compensation capacitor when the transient current of the input stage changes. The amplifier's bandwidth depends on the ratio of the transconductance of the input stage MOSFETs to the compensation capacitor.
[0004] When a large pulse signal is input, the change in amplifier current is as follows: Figure 2 As shown, when a positive pulse is input to VIP, PM1 is cut off; when a negative pulse is input to VIN, PM2 is in a low-impedance conducting state, and the entire input bias current 2I flows into PM2. The sum of the bias currents of the tail current sources NM4 and NM5 is 2I. Since the input transistor PM1 is cut off, the transient current decreases by I. To achieve current balance of the tail current sources, a current I needs to be drawn from the output terminal VOP. The gate potential of PM10 will decrease, increasing its output current I. QP, and reaches a steady state when a certain potential is reached. Two currents I / 2 flow from the branches of compensation capacitors C1 and C2 into the output terminal VOP of the first stage, and VOP rises with a linear variation slope of I / (2C1), i.e. the positive voltage slew rate is I / (2C1). The tail current sources NM6 and NM7, due to the transient current of the input tube PM2, increase by I, and in order to reach the balance of the tail current sources, the branch current I of PM9 and PM7 needs to flow into the output terminal VON. The gate potential of NM13 will increase, and its output current I will increase QN , and reaches a steady state when a certain potential is reached. Two currents I / 2 flow from the branches of compensation capacitors C1 and C2 into the output terminal VOP of the first stage, and VOP rises with a linear variation slope of I / (2C1), i.e. the positive voltage slew rate is I / (2C1). The tail current sources NM6 and NM7, due to the transient current of the input tube PM2, increase by I, and in order to reach the balance of the tail current sources, the branch current I of PM9 and PM7 needs to flow into the output terminal VON. The gate potential of NM13 will increase, and its output current I will increase , and reaches a steady state when a certain potential is reached. Two currents I / 2 flow from the branches of compensation capacitors C1 and C2 into the output terminal VOP of the first stage, and VOP rises with a linear variation slope of I / (2C1), i.e. the positive voltage slew rate is I / (2C1). The tail current sources NM6 and NM7, due to the transient current of the input tube PM2, increase by I, and in order to reach the balance of the tail current sources, the branch current I of PM9 and PM7 needs to flow into the output terminal VON. The gate potential of NM13 will increase, and its output current I will increase
[0005] Figure 1 The conventional folded cascode AB class output amplifier in the prior art has a voltage slew rate equal to the ratio of the current flowing through the compensation capacitor to the compensation capacitor when a large pulse signal is input, and a unit gain bandwidth equal to the ratio of the transconductance of the input MOS tube to the compensation capacitor. On the one hand, since the floating voltage source is always half on, the transient current I of the input stage is always divided into two paths to flow into or out of the output terminal (VOP or VON), so the voltage slew rate of a certain output terminal is equal to the ratio of half of the transient current I to the compensation capacitor. If a double voltage slew rate is expected, the bias current needs to be doubled. On the other hand, since the transconductance of the input stage is proportional to the bias current of the input stage, to achieve a double bandwidth, the bias current also needs to be doubled.
[0006] It should be noted that the information disclosed in the background section is only intended to deepen the understanding of the overall background of the present application, and should not be regarded as acknowledging or implying in any form that the information is prior art known to those skilled in the art. SUMMARY
[0007] The purpose of the present application is to provide a current multiplexing type output amplifier, which does not need to double the bias current, and can achieve a double voltage slew rate and a double unit gain bandwidth compared with the conventional amplifier under the condition of the same bias current.
[0008] The purpose of the present application is achieved by the following technical solutions:
[0009] The application discloses a current multiplexing output amplifier, which comprises a current multiplexing input stage, a first self-biased diode pair, a second self-biased diode pair, a first AB class output stage and a second AB class output stage.
[0010] Further, the current multiplexing output amplifier further comprises a static voltage bias circuit and a common mode feedback circuit; the static voltage bias circuit provides bias voltages nb1, nb2, pb1 and pb2 for the current multiplexing output amplifier; and the common mode feedback circuit provides a common mode feedback voltage fb for the current multiplexing output amplifier.
[0011] Further, the current multiplexing input stage comprises NMOS tubes NM1, NMOS tube NM2, NMOS tube NM11, NMOS tube NM12, PMOS tube PM1, PMOS tube PM2 and PMOS tube 11; the gate of the NMOS tube NM1 and the gate of the PMOS tube PM1 are connected with a positive input end, and the gate of the NMOS tube NM2 and the gate of the PMOS tube PM2 are connected with a negative input end; the drain of the NMOS tube NM1 and the drain of the PMOS tube PM1 are connected with a first output end, and the drain of the NMOS tube NM2 and the drain of the PMOS tube PM2 are connected with a second output end; the source and the substrate of the PMOS tube PM11 are connected with a power supply network, the gate is connected with a bias voltage pb1, and the drain is connected with the source and the substrate of the PMOS tube PM1 and the source and the substrate of the PMOS tube PM2 respectively; the substrate of the NMOS tube NM1 and the substrate of the NMOS tube NM2 are connected with a ground network; the source of the NMOS tube NM1 is connected with the source of the NMOS tube NM2, the drain of the NMOS tube NM12 and the drain of the NMOS tube NM11 respectively; the source and the substrate of the NMOS tube NM11 and the source and the substrate of the NMOS tube NM12 are connected with the ground network; the gate of the NMOS tube NM12 inputs a bias voltage nb1, and the gate of the NMOS tube NM11 inputs a common mode feedback voltage fb.
[0012] Further, the first self-bias diode pair comprises an NMOS NM3 and a PMOS PM3; the source of the NMOS NM3 and the source of the PMOS PM3 are connected and serve as one end of the first self-bias diode pair; the gate and the drain of the NMOS NM3 are connected, and the gate and the drain of the PMOS PM3 are connected, serving as the other end of the first self-bias diode pair; the substrate of the NMOS NM3 is connected to the ground network, and the drain is connected to the power supply network through a first current source; the substrate of the PMOS PM3 is connected to the power supply network, and the drain is connected to the ground network through a second current source.
[0013] Further, the first current source comprises a PMOS PM5 and a PMOS PM6; the drain of the PMOS PM6 is connected to the drain of the NMOS NM3, and the source of the PMOS PM6 is connected to the drain of the PMOS PM5; the source and the substrate of the PMOS PM5 and the substrate of the PMOS PM6 are connected to the power supply network; the gate of the PMOS PM6 is inputted with a bias voltage pb2, and the gate of the PMOS PM5 is inputted with a bias voltage pb1.
[0014] The second current source comprises an NMOS NM5 and an NMOS NM6; the drain of the NMOS NM5 is connected to the drain of the PMOS PM3, and the source of the NMOS NM5 is connected to the drain of the NMOS NM6; the source and the substrate of the NMOS NM6 and the substrate of the NMOS NM5 are connected to the ground network; the gate of the NMOS NM5 is inputted with a bias voltage nb2, and the gate of the NMOS NM6 is inputted with a bias voltage nb1.
[0015] Further, the second self-bias diode pair comprises an NMOS NM4 and a PMOS PM4; the source of the NMOS NM4 and the source of the PMOS PM4 are connected and serve as one end of the second self-bias diode pair; the gate and the drain of the NMOS NM4 are connected, and the gate and the drain of the PMOS PM4 are connected, serving as the other end of the second self-bias diode pair; the substrate of the NMOS NM4 is connected to the ground network, and the drain is connected to the power supply network through a third current source; the substrate of the PMOS PM4 is connected to the power supply network, and the drain is connected to the ground network through a fourth current source.
[0016] Further, the third current source comprises a PMOS PM7 and a PMOS PM8; the drain of the PMOS PM8 is connected to the drain of the NMOS NM4, and the source of the PMOS PM8 is connected to the drain of the PMOS PM7; the source and the substrate of the PMOS PM7 and the substrate of the PMOS PM8 are connected to the power supply network; the gate of the PMOS PM8 is inputted with a bias voltage pb2, and the gate of the PMOS PM7 is inputted with a bias voltage pb1.
[0017] The fourth current source includes NMOS transistors NM7 and NMOS transistors NM8; the drain of NMOS transistor NM7 is connected to the drain of PMOS transistor PM4, and the source of NMOS transistor NM7 is connected to the drain of NMOS transistor NM8; the source of NMOS transistor NM8 and its substrate, and the substrate of NMOS transistor NM7 are connected to the ground network; the gate input bias voltage of NMOS transistor NM7 is nb2, and the gate input bias voltage of NMOS transistor NM8 is nb1.
[0018] Furthermore, the first AB class output stage includes a PMOS transistor PM9, an NMOS transistor NM9, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2; the gate of the PMOS transistor PM9 and one end of the first resistor R1 are connected to the drain of the NMOS transistor NM3; the gate of the NMOS transistor NM9 and one end of the second resistor R2 are connected to the drain of the PMOS transistor PM3; the other end of the first resistor R1 is connected to the positive output terminal through the first capacitor C1, and the other end of the second resistor R2 is connected to the positive output terminal through the second capacitor C2; the drains of the PMOS transistor PM9 and the NMOS transistor NM9 are connected to the positive output terminal; the substrate and source of the PMOS transistor PM9 are connected to the power supply network, and the substrate and source of the NMOS transistor NM9 are connected to the ground network.
[0019] Furthermore, the second AB class output stage includes a PMOS transistor PM10, an NMOS transistor NM10, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4; the gate of the PMOS transistor PM10 and one end of the third resistor R3 are connected to the drain of the NMOS transistor NM4; the gate of the NMOS transistor NM10 and one end of the fourth resistor R4 are connected to the drain of the PMOS transistor PM4; the other end of the third resistor R3 is connected to the negative output terminal through the third capacitor C3, and the other end of the fourth resistor R4 is connected to the negative output terminal through the fourth capacitor C4; the drains of the PMOS transistor PM10 and the NMOS transistor NM10 are connected to the negative output terminal; the substrate and source of the PMOS transistor PM10 are connected to the power supply network, and the substrate and source of the NMOS transistor NM10 are connected to the ground network.
[0020] Furthermore, the static voltage bias circuit includes a bias current source, a fifth resistor R5, NMOS transistors NM13, NM14, NM15, NM16, NM17, NM18, NM19, NM20, NM21, NM22, NM23, and PMOS transistors PM12, PM13, PM14, PM15, PM16, and PM17. The bias current source generates a bias current that enters one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the NMOS transistors NM13, NM14, NM15, PM16, and PM17. The drain of NMOS transistor NM13, the gate of NMOS transistor NM14, and the gate of NMOS transistor NM16 are connected; the source of NMOS transistor NM13 is connected to the drain of NMOS transistor NM14; the substrate of NMOS transistor NM13, and the source and substrate of NMOS transistor NM14 are connected to the ground network; the gate of NMOS transistor NM13 is connected to the gate of NMOS transistor NM15; the source of NMOS transistor NM15 is connected to the drain of NMOS transistor NM16; the substrate of NMOS transistor NM15, and the source and substrate of NMOS transistor NM16 are connected to the ground network AVSS; the drain of NMOS transistor NM15 is connected to the drain and gate of PMOS transistor PM12, the gate of PMOS transistor PM13, and the gate of PMOS transistor PM14, respectively. The source and substrate of PMOS transistor PM12, the source and substrate of PMOS transistor PM13, the source and substrate of PMOS transistor PM14, the source and substrate of PMOS transistor PM15, the source and substrate of PMOS transistor PM16, and the substrate of PMOS transistor PM17 are connected to the power supply network. The drain of PMOS transistor PM13 is connected to the drain and gate of NMOS transistor NM17 and the gate of NMOS transistor NM18, generating a bias voltage nb2. The drain of PMOS transistor PM14 is connected to the gate of NMOS transistor NM19 and the drain of NMOS transistor NM18, generating a bias voltage nb1. The source of NMOS transistor NM18 is connected to the drain of NMOS transistor NM19. The gate and drain of transistor 15 are connected to the drain of NMOS transistor NM20 and the gate of PMOS transistor PM17, generating a bias voltage pb2; the source of NMOS transistor NM20 is connected to the drain of NMOS transistor NM21; the gates of NMOS transistor NM20 and NMOS transistor NM22 are biased by voltage nb2; the gates of NMOS transistor NM21 and NMOS transistor NM23 are biased by voltage nb1; the gate of PMOS transistor PM16 is connected to the drain of PMOS transistor PM17 and the drain of NMOS transistor NM22, generating a bias voltage pb1; the source of PM17 is connected to the drain of PMOS transistor PM16; the source of NMOS transistor NM22 is connected to the drain of NMOS transistor NM23.The substrate and source of NMOS transistor NM17, the substrate of NMOS transistor NM18, the source and substrate of NMOS transistor NM19, the substrate of NMOS transistor NM20, the source and substrate of NMOS transistor NM21, the substrate of NMOS transistor NM22, and the source and substrate of NMOS transistor NM23 are connected to the ground network.
[0021] Furthermore, the common-mode feedback circuit includes PMOS transistors PM18, PM19, PM20, NMOS transistors NM24 and NM25, a sixth resistor R6, a seventh resistor R7, a fifth capacitor C5, and a sixth capacitor C6; one end of the fifth capacitor C5 and one end of the sixth resistor R6 are connected to the positive output terminal; one end of the sixth capacitor C6 and one end of the seventh resistor R7 are connected to the negative output terminal; the other ends of the fifth capacitor C5, the sixth resistor R6, the sixth capacitor C6, and the seventh resistor R7 are connected together to form a common-mode detection voltage; PMOS... The source and substrate of S-channel transistor PM20 are connected to the power supply network, and the drain is connected to the source and substrate of PMOS transistor PM18 and PMOS transistor PM19, respectively. The gate of PMOS transistor PM18 receives the common-mode voltage. The gate of PMOS transistor PM19 receives the common-mode detection voltage. The drain of PMOS transistor PM18 is connected to the drain and gate of NMOS transistor NM24. The drain of PMOS transistor PM19 is connected to the drain and gate of NMOS transistor NM25, forming the common-mode feedback voltage fb. The source and substrate of NMOS transistor NM24 and the source and substrate of NMOS transistor NM25 are connected to the ground network.
[0022] The current-multiplexed output amplifier of this invention uses two self-biased diode pairs instead of the floating voltage source of the prior art. When a large pulse signal is input, one diode in each diode pair is in the cutoff state, so the transient current I flows into or out of the output terminal only from one branch. The slew rate is the ratio of the transient current I in the input stage to the compensation capacitor. Compared with conventional amplifiers, the slew rate is doubled under the same bias current conditions. Furthermore, since a floating voltage source is not required, two bias circuits for generating bias voltages are reduced. The input stage uses a current-multiplexed architecture combining PMOS and NMOS transistors to provide an input voltage near the common-mode potential to the self-biased diodes in the next stage. Under the same bias current, the equivalent input transconductance is the sum of the transconductances of the PMOS and NMOS transistors, and the unity-gain bandwidth is also doubled. Attached Figure Description
[0023] Figure 1 This is a schematic diagram of a folded common-source cascode Class AB output amplifier circuit from existing technology.
[0024] Figure 2 This is a schematic diagram of the current change process of an amplifier in the prior art when a large pulse signal is input.
[0025] Figure 3 This is a schematic diagram of the current-multiplexed output amplifier circuit of the present invention;
[0026] Figure 4 This is a circuit diagram of the static voltage bias circuit and common-mode feedback circuit of the present invention;
[0027] Figure 5 This is a diagram showing the current change process of the current-multiplexed output amplifier of the present invention when a large pulse signal is input. Detailed Implementation
[0028] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0029] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. When one element described in this invention is "connected" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Simple logical reversals and device substitutions, or simple changes in circuit structure connections that do not depart from the spirit of this invention, cannot be used to circumvent this invention.
[0030] like Figure 3 The diagram shows the circuit schematic of the current-multiplexed output amplifier of the present invention, which includes a current-multiplexed input stage, a first self-biased diode pair, a second self-biased diode pair, a first Class AB output stage, and a second Class AB output stage. The current-multiplexed input stage includes a positive input terminal VIP, a negative input terminal VIN, a first output terminal VN, and a second output terminal VP. Differential pulse signals are input to the positive input terminal VIP and the negative input terminal VIN. The first output terminal VN is connected to one end of the first self-biased diode pair, and the second output terminal VP is connected to one end of the second self-biased diode pair. The other end of the first self-biased diode pair is connected to the first Class AB output stage. The other end of the second self-biased diode pair is connected to the second Class AB output stage. The output terminal VOP of the first Class AB output stage is the positive output terminal, and the output terminal VON of the second Class AB output stage is the negative output terminal.
[0031] Furthermore, the current-multiplexed input stage includes NMOS transistors NM1, NMOS transistor NM2, NMOS transistor NM11, NMOS transistor NM12, PMOS transistors PM1, PM2, and PMOS transistor PM1. The gates of NMOS transistor NM1 and PM1 are connected to the positive input terminal VIP, and the gates of NMOS transistor NM2 and PM2 are connected to the negative input terminal VIN. The drains of NMOS transistor NM1 and PM1 are connected to the first output terminal VN, and the drains of NMOS transistor NM2 and PM2 are connected to the second output terminal VP. The source and substrate of PMOS transistor PM11 are connected to the power supply network AVDD, the gate is connected to the bias voltage pb1, and the drain is connected to the source and substrate of PMOS transistor PM1 and the source and substrate of PMOS transistor PM2, respectively. NMOS transistors NM1, NMOS transistor NM2, PMOS transistor PM1, and PMOS transistor PM2 together constitute the input stage of the current-multiplexed output amplifier of the present invention. The substrates of NMOS transistors NM1 and NM2 are connected to the ground network AVSS. The source of NMOS transistor NM1 is connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM12, and the drain of NMOS transistor NM11. NMOS transistors NM12 and NM11 together form the tail current source. The source and substrate of NMOS transistor NM11, and the source and substrate of NMOS transistor NM12 are connected to the ground network AVSS. The gate input bias voltage of NMOS transistor NM12 is nb1, and the gate input common-mode feedback voltage of NMOS transistor NM11 is fb.
[0032] Furthermore, the first self-biased diode pair includes an NMOS transistor NM3 and a PMOS transistor PM3. The sources of the NMOS transistor NM3 and the PMOS transistor PM3 are connected and serve as one end of the first self-biased diode pair. The gate and drain of the NMOS transistor NM3 are connected together to form a diode, and the gate and drain of the PMOS transistor PM3 are connected together to form a diode, serving as the other end of the first self-biased diode pair. The substrate of the NMOS transistor NM3 is connected to the ground network AVSS, and its drain is connected to the power network AVDD through a first current source. The substrate of the PMOS transistor PM3 is connected to the power network AVDD, and its drain is connected to the ground network AVSS through a second current source.
[0033] Furthermore, the first current source includes PMOS transistors PM5 and PM6. The drain of PMOS transistor PM6 is connected to the drain of NMOS transistor NM3, and the source of PMOS transistor PM6 is connected to the drain of PMOS transistor PM5. The source of PMOS transistor PM5 and its substrate, and the substrate of PMOS transistor PM6 are connected to the power supply network AVDD. The gate input bias voltage of PMOS transistor PM6 is pb2, and the gate input bias voltage of PMOS transistor PM5 is pb1.
[0034] Furthermore, the second current source includes NMOS transistors NM5 and NM6. The drain of NMOS transistor NM5 is connected to the drain of PMOS transistor PM3, and the source of NMOS transistor NM5 is connected to the drain of NMOS transistor NM6. The source of NMOS transistor NM6 and its substrate, and the substrate of NMOS transistor NM5 are connected to the ground network AVSS. The gate input bias voltage of NMOS transistor NM5 is nb2, and the gate input bias voltage of NMOS transistor NM6 is nb1.
[0035] Furthermore, the second self-biased diode pair includes an NMOS transistor NM4 and a PMOS transistor PM4. The sources of the NMOS transistor NM4 and the PMOS transistor PM4 are connected and serve as one end of the second self-biased diode pair. The gate and drain of the NMOS transistor NM4 are connected together to form a diode, and the gate and drain of the PMOS transistor PM4 are connected together to form a diode, serving as the other end of the second self-biased diode pair. The substrate of the NMOS transistor NM4 is connected to the ground network AVSS, and its drain is connected to the power network AVDD through a third current source. The substrate of the PMOS transistor PM4 is connected to the power network AVDD, and its drain is connected to the ground network AVSS through a fourth current source.
[0036] Furthermore, the third current source includes PMOS transistors PM7 and PM8. The drain of PMOS transistor PM8 is connected to the drain of NMOS transistor NM4, and the source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM7. The source of PMOS transistor PM7 and its substrate, and the substrate of PMOS transistor PM8 are connected to the power supply network AVDD. The gate input bias voltage of PMOS transistor PM8 is pb2, and the gate input bias voltage of PMOS transistor PM7 is pb1.
[0037] Furthermore, the fourth current source includes NMOS transistors NM7 and NMOS transistor NM8. The drain of NMOS transistor NM7 is connected to the drain of PMOS transistor PM4, and the source of NMOS transistor NM7 is connected to the drain of NMOS transistor NM8. The source of NMOS transistor NM8 and its substrate, and the substrate of NMOS transistor NM7 are connected to the ground network AVSS. The gate input bias voltage of NMOS transistor NM7 is nb2, and the gate input bias voltage of NMOS transistor NM8 is nb1.
[0038] Furthermore, the first Class AB output stage includes a PMOS transistor PM9, an NMOS transistor NM9, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. The gate of PMOS transistor PM9 and one end of the first resistor R1 are connected to the drain of NMOS transistor NM3. The gate of NMOS transistor NM9 and one end of the second resistor R2 are connected to the drain of PMOS transistor PM3. The other end of the first resistor R1 is connected to the positive output terminal through the first capacitor C1, and the other end of the second resistor R2 is connected to the positive output terminal through the second capacitor C2. The drains of PMOS transistor PM9 and NMOS transistor NM9 are connected to the positive output terminal. The substrate and source of PMOS transistor PM9 are connected to the power supply network AVDD, and the substrate and source of NMOS transistor NM9 are connected to the ground network AVSS.
[0039] Furthermore, the second Class AB output stage includes a PMOS transistor PM10, an NMOS transistor NM10, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4. The gate of PMOS transistor PM10 and one end of the third resistor R3 are connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM10 and one end of the fourth resistor R4 are connected to the drain of PMOS transistor PM4. The other end of the third resistor R3 is connected to the negative output terminal through the third capacitor C3, and the other end of the fourth resistor R4 is connected to the negative output terminal through the fourth capacitor C4. The drains of PMOS transistor PM10 and NMOS transistor NM10 are connected to the negative output terminal. The substrate and source of PMOS transistor PM10 are connected to the power supply network AVDD, and the substrate and source of NMOS transistor NM10 are connected to the ground network AVSS.
[0040] Furthermore, the current-multiplexed output amplifier of the present invention also includes a static voltage bias circuit and a common-mode feedback circuit, such as... Figure 4 As shown. The static voltage bias circuit includes a bias current source I. REF The fifth resistor R5, NMOS transistors NM13, NM14, NM15, NM16, NM17, NM18, NM19, NM20, NM21, NM22, NM23, PMOS transistors PM12, PM13, PM14, PM15, PM16, and PM17. Bias current source I. REFA bias current is generated and flows into one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the drain of NMOS transistor NM13, the gate of NMOS transistor NM14, and the gate of NMOS transistor NM16, respectively, providing a bias voltage to NM16. The source of NMOS transistor NM13 is connected to the drain of NMOS transistor NM14. The substrate of NMOS transistor NM13, and the source and substrate of NMOS transistor NM14 are connected to the ground network AVSS. The gate of NMOS transistor NM13 is connected to the gate of NMOS transistor NM15, providing a bias voltage to NM15. The source of NMOS transistor NM15 is connected to the drain of NMOS transistor NM16. The substrate of NMOS transistor NM15, and the source and substrate of NMOS transistor NM16 are connected to the ground network AVSS. The drain of NMOS transistor NM15 is connected to the drain and gate of PMOS transistor PM12, the gate of PMOS transistor PM13, and the gate of PMOS transistor PM14, respectively. The source and substrate of PMOS transistor PM12, the source and substrate of PMOS transistor PM13, the source and substrate of PMOS transistor PM14, the source and substrate of PMOS transistor PM15, the source and substrate of PMOS transistor PM16, and the substrate of PMOS transistor PM17 are connected to the power network AVDD. The drain of PMOS transistor PM13 is connected to the drain and gate of NMOS transistor NM17 and the gate of NMOS transistor NM18, generating a bias voltage nb2. The drain of PMOS transistor PM14 is connected to the gate of NMOS transistor NM19 and the drain of NMOS transistor NM18, generating a bias voltage nb1. The source of NMOS transistor NM18 is connected to the drain of NMOS transistor NM19. The gate and drain of PMOS transistor PM15 are connected to the drain of NMOS transistor NM20 and the gate of PMOS transistor PM17, generating a bias voltage pb2. The source of NMOS transistor NM20 is connected to the drain of NMOS transistor NM21. The gates of NMOS transistors NM20 and NM22 are biased by voltage nb2. The gates of NMOS transistors NM21 and NM23 are biased by voltage nb1. The gate of PMOS transistor PM16 is connected to the drain of PMOS transistor PM17 and the drain of NMOS transistor NM22, generating a bias voltage pb1. The source of PM17 is connected to the drain of PMOS transistor PM16. The source of NMOS transistor NM22 is connected to the drain of NMOS transistor NM23. The substrates and sources of NMOS transistors NM17, NM18, NM19, NM20, NM21, NM22, and NM23 are connected to the ground network AVSS.
[0041] The common-mode feedback circuit includes PMOS transistors PM18, PM19, and PM20, NMOS transistors NM24 and NM25, a sixth resistor R6, a seventh resistor R7, a fifth capacitor C5, and a sixth capacitor C6. The source and substrate of PMOS transistor PM20 are connected to the power supply network AVDD, and its drain is connected to the source and substrate of PMOS transistors PM18 and PM19, respectively. The gate of PMOS transistor PM18 is connected to the common-mode voltage VCM. The gate of PMOS transistor PM19 is connected to the common-mode detection voltage vcmfb. The drain of PMOS transistor PM18 is connected to the drain and gate of NMOS transistor NM24. The drain of PMOS transistor PM19 is connected to the drain and gate of NMOS transistor NM25, forming the common-mode feedback voltage fb. The source and substrate of NMOS transistor NM24 and the source and substrate of NMOS transistor NM25 are connected to the ground network AVSS. One end of the fifth capacitor C5 and one end of the sixth resistor R6 are connected to the positive output terminal VOP, and one end of the sixth capacitor C6 and one end of the seventh resistor R7 are connected to the negative output terminal VON. The other ends of the fifth capacitor C5, the sixth resistor R6, the sixth capacitor C6, and the seventh resistor R7 are connected together to form the common-mode detection voltage vcmfb.
[0042] The static bias circuit and common-mode feedback circuit are auxiliary circuits of the current-multiplexed output amplifier of this invention. The static bias circuit primarily provides the four static bias voltages nb1, nb2, pb1, and pb2 required by the current-multiplexed output amplifier. The common-mode feedback circuit provides the common-mode feedback voltage fb to the current-multiplexed output amplifier. The static bias voltage and common-mode feedback voltage of this invention can also be provided by other circuits in the prior art.
[0043] The current change process of the current-multiplexed output amplifier proposed in this invention when a large pulse signal is input is as follows: Figure 5 As shown. For a fair comparison, the bias current and compensation capacitor of each branch of the current-multiplexed output amplifier proposed in this invention are compared with... Figure 1The bias current and compensation capacitor of the existing amplifier shown are kept consistent. When a positive pulse is input to VIP, PM1 is cut off; when a negative pulse is input to VIN, NM2 is cut off. At this time, no current flows out of the drain of PM1, nor from the source of NM2. To balance the 2I bias current of NM12 and NM11, NM1 needs to draw 2I current from VN. When a positive pulse is input to VIP, VN drops rapidly, and the gate of PM9 drops to a stable potential to provide a large transient current IP. The gate potential of NM9 first drops and then rises to a stable potential. When PM3 is cut off, the bias current I of PM6 and PM5 and the current I from the VOP output (C1 and R1 branches) flow into VN to provide the 2I current required by NM1. Because PM3 is cut off, a current I flows from the C2 and R2 branches into NM5 and NM6 to balance their bias current I. Therefore, the slope of VOP's rise is I / C1, i.e., the slew rate is I / C1. At the other end, PM1 is cut off, and all the 2I current flows out from the drain of PM2. Simultaneously, NM2 is cut off, and all the 2I current flows into VP. When a negative pulse is input to VIN, VP rises rapidly, and the gate of NM10 rises to a stable potential to provide a large transient current IN. The gate potential of PM10 first rises and then falls to a stable potential. NM4 is cut off, and of the 2I current flowing into VP, a portion I enters the bias branch of NM7 and NM8, and the other portion I flows into the output terminal VON from the branch of R4 and C4. Since NM4 is cut off, the bias current I of PM8 and PM7 flows into the input terminal VON from the branch of R3 and C3. Therefore, the slope of VON's decrease at this time is I / C4, i.e., the slew rate is I / C4. The differential output slew rate of the current-multiplexed Class AB output amplifier proposed in this invention is 2I / C1 (the capacitance values of C1, C2, C3, and C4 in the figure are equal). Compared to the slew rate of a traditional amplifier of I / (2C1), the slew rate of the amplifier of this invention is doubled.
[0044] The input stage employs a current-multiplexed architecture combining PMOS and NMOS transistors. Under the same bias current, the equivalent input transconductance is the sum of the transconductances of the PMOS and NMOS transistors, meaning the transconductance is doubled (assuming the transconductances of the PMOS and NMOS transistors are the same). The unity-gain bandwidth of the current-multiplexed output amplifier of this invention is... gm is the transconductance of the input MOSFET. Compared to the gain and bandwidth of traditional amplifiers... Furthermore, the unity-gain bandwidth of the amplifier in this invention has also doubled.
[0045] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made without creative effort within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A current-multiplexed output amplifier, characterized in that, It includes a current-multiplexed input stage, a first self-biased diode pair, a second self-biased diode pair, a first Class AB output stage, and a second Class AB output stage; the current-multiplexed input stage includes a positive input terminal, a negative input terminal, a first output terminal, and a second output terminal; the positive input terminal and the negative input terminal receive differential pulse signals; The first output terminal is connected to one end of the first self-biased diode pair, and the second output terminal is connected to one end of the second self-biased diode pair; the other end of the first self-biased diode pair is connected to the first Class AB output stage; the other end of the second self-biased diode pair is connected to the second Class AB output stage; the output terminal of the first Class AB output stage is a positive output terminal, and the output terminal of the second Class AB output stage is a negative output terminal.
2. The current-multiplexed output amplifier according to claim 1, characterized in that, It also includes a static voltage bias circuit and a common-mode feedback circuit; the static voltage bias circuit provides bias voltages nb1, nb2, pb1, and pb2 for the current-multiplexed output amplifier; the common-mode feedback circuit provides a common-mode feedback voltage fb for the current-multiplexed output amplifier.
3. The current-multiplexed output amplifier according to claim 1 or 2, characterized in that, The current-multiplexed input stage includes NMOS transistors NM1, NMOS transistor NM2, NMOS transistor NM11, NMOS transistor NM12, PMOS transistors PM1, PM2, and PMOS transistor PM11. The gates of NMOS transistor NM1 and PM1 are connected to the positive input terminal, and the gates of NMOS transistor NM2 and PM2 are connected to the negative input terminal. The drains of NMOS transistor NM1 and PM1 are connected to the first output terminal, and the drains of NMOS transistor NM2 and PM2 are connected to the second output terminal. The source of PMOS transistor PM11 is connected to the substrate. The source network is connected to the bias voltage pb1 at the gate, and the drain is connected to the source and substrate of PMOS transistor PM1 and PMOS transistor PM2, respectively. The substrates of NMOS transistor NM1 and NMOS transistor NM2 are connected to the ground network. The source of NMOS transistor NM1 is connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM12, and the drain of NMOS transistor NM11, respectively. The source and substrate of NMOS transistor NM11 and the source and substrate of NMOS transistor NM12 are connected to the ground network. The gate input bias voltage of NMOS transistor NM12 is nb1, and the gate input common-mode feedback voltage of NMOS transistor NM11 is fb.
4. The current-multiplexed output amplifier according to claim 1 or 2, characterized in that, The first self-biased diode pair includes an NMOS transistor NM3 and a PMOS transistor PM3; the source of the NMOS transistor NM3 and the source of the PMOS transistor PM3 are connected and serve as one end of the first self-biased diode pair; the gate and drain of the NMOS transistor NM3 are connected, and the gate and drain of the PMOS transistor PM3 are connected, serving as the other end of the first self-biased diode pair; the substrate of the NMOS transistor NM3 is connected to the ground network, and the drain is connected to the power supply network through a first current source; the substrate of the PMOS transistor PM3 is connected to the power supply network, and the drain is connected to the ground network through a second current source.
5. The current-multiplexed output amplifier according to claim 4, characterized in that, The first current source includes PMOS transistor PM5 and PMOS transistor PM6; the drain of PMOS transistor PM6 is connected to the drain of NMOS transistor NM3, and the source of PMOS transistor PM6 is connected to the drain of PMOS transistor PM5; the source of PMOS transistor PM5 and the substrate, and the substrate of PMOS transistor PM6 are connected to the power supply network; the gate input bias voltage of PMOS transistor PM6 is pb2, and the gate input bias voltage of PMOS transistor PM5 is pb1. The second current source includes NMOS transistors NM5 and NMOS transistors NM6; the drain of NMOS transistor NM5 is connected to the drain of PMOS transistor PM3, and the source of NMOS transistor NM5 is connected to the drain of NMOS transistor NM6; the source of NMOS transistor NM6 and the substrate, and the substrate of NMOS transistor NM5 are connected to the ground network; the gate input bias voltage of NMOS transistor NM5 is nb2, and the gate input bias voltage of NMOS transistor NM6 is nb1.
6. The current-multiplexed output amplifier according to claim 1 or 2, characterized in that, The second self-biased diode pair includes an NMOS transistor NM4 and a PMOS transistor PM4; the source of the NMOS transistor NM4 and the source of the PMOS transistor PM4 are connected and serve as one end of the second self-biased diode pair; the gate and drain of the NMOS transistor NM4 are connected, and the gate and drain of the PMOS transistor PM4 are connected, serving as the other end of the second self-biased diode pair; the substrate of the NMOS transistor NM4 is connected to the ground network, and the drain is connected to the power supply network through a third current source; the substrate of the PMOS transistor PM4 is connected to the power supply network, and the drain is connected to the ground network through a fourth current source.
7. The current-multiplexed output amplifier according to claim 6, characterized in that, The third current source includes PMOS transistor PM7 and PMOS transistor PM8; the drain of PMOS transistor PM8 is connected to the drain of NMOS transistor NM4, and the source of PMOS transistor PM8 is connected to the drain of PMOS transistor PM7; the source of PMOS transistor PM7 and the substrate, and the substrate of PMOS transistor PM8 are connected to the power supply network; the gate input bias voltage of PMOS transistor PM8 is pb2, and the gate input bias voltage of PMOS transistor PM7 is pb1. The fourth current source includes NMOS transistors NM7 and NMOS transistors NM8; the drain of NMOS transistor NM7 is connected to the drain of PMOS transistor PM4, and the source of NMOS transistor NM7 is connected to the drain of NMOS transistor NM8; the source of NMOS transistor NM8 and its substrate, and the substrate of NMOS transistor NM7 are connected to the ground network; the gate input bias voltage of NMOS transistor NM7 is nb2, and the gate input bias voltage of NMOS transistor NM8 is nb1.
8. The current-multiplexed output amplifier according to claim 1 or 2, characterized in that, The first Class AB output stage includes a PMOS transistor PM9, an NMOS transistor NM9, a first capacitor C1, a second capacitor C2, a first resistor R1, and a second resistor R2. The gate of the PMOS transistor PM9 and one end of the first resistor R1 are connected to the drain of the NMOS transistor NM3. The gate of the NMOS transistor NM9 and one end of the second resistor R2 are connected to the drain of the PMOS transistor PM3. The other end of the first resistor R1 is connected to the positive output terminal through the first capacitor C1, and the other end of the second resistor R2 is connected to the positive output terminal through the second capacitor C2. The drains of the PMOS transistor PM9 and the NMOS transistor NM9 are connected to the positive output terminal. The substrate and source of the PMOS transistor PM9 are connected to the power supply network, and the substrate and source of the NMOS transistor NM9 are connected to the ground network.
9. The current-multiplexed output amplifier according to claim 1 or 2, characterized in that, The second Class AB output stage includes a PMOS transistor PM10, an NMOS transistor NM10, a third capacitor C3, a fourth capacitor C4, a third resistor R3, and a fourth resistor R4. The gate of the PMOS transistor PM10 and one end of the third resistor R3 are connected to the drain of the NMOS transistor NM4. The gate of the NMOS transistor NM10 and one end of the fourth resistor R4 are connected to the drain of the PMOS transistor PM4. The other end of the third resistor R3 is connected to the negative output terminal through the third capacitor C3, and the other end of the fourth resistor R4 is connected to the negative output terminal through the fourth capacitor C4. The drains of the PMOS transistor PM10 and the NMOS transistor NM10 are connected to the negative output terminal. The substrate and source of the PMOS transistor PM10 are connected to the power supply network, and the substrate and source of the NMOS transistor NM10 are connected to the ground network.
10. The current-multiplexed output amplifier according to claim 2, characterized in that, The static voltage bias circuit includes a bias current source, a fifth resistor R5, NMOS transistors NM13, NM14, NM15, NM16, NM17, NM18, NM19, NM20, NM21, NM22, NM23, and PMOS transistors PM12, PM13, PM14, PM15, PM16, and PM17. The bias current source generates a bias current that enters one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the drain of NMOS transistor NM13. The gates of NMOS transistors NM14 and NM16 are connected; the source of NMOS transistor NM13 is connected to the drain of NMOS transistor NM14; the substrate of NMOS transistor NM13, and the source and substrate of NMOS transistor NM14 are connected to the ground network; the gate of NMOS transistor NM13 is connected to the gate of NMOS transistor NM15; the source of NMOS transistor NM15 is connected to the drain of NMOS transistor NM16; the substrate of NMOS transistor NM15, and the source and substrate of NMOS transistor NM16 are connected to the ground network AVSS; the drain of NMOS transistor NM15 is connected to the drain and gate of PMOS transistor PM12, the gate of PMOS transistor PM13, and the gate of PMOS transistor PM14, respectively; P The source and substrate of MOSFET PM12, the source and substrate of PMOS transistors PM13, PM14, PM15, and PM16, and the substrate of PMOS transistor PM17 are connected to the power supply network. The drain of PMOS transistor PM13 is connected to the drain and gate of NMOS transistor NM17 and the gate of NMOS transistor NM18, generating a bias voltage nb2. The drain of PMOS transistor PM14 is connected to the gate of NMOS transistor NM19 and the drain of NMOS transistor NM18, generating a bias voltage nb1. The source of NMOS transistor NM18 is connected to the drain of NMOS transistor NM19. PMOS transistor PM1... The gate and drain of transistor 5 are connected to the drain of NMOS transistor NM20 and the gate of PMOS transistor PM17, generating a bias voltage pb2; the source of NMOS transistor NM20 is connected to the drain of NMOS transistor NM21; the gates of NMOS transistor NM20 and NMOS transistor NM22 are biased by voltage nb2; the gates of NMOS transistor NM21 and NMOS transistor NM23 are biased by voltage nb1; the gate of PMOS transistor PM16 is connected to the drain of PMOS transistor PM17 and the drain of NMOS transistor NM22, generating a bias voltage pb1; the source of PM17 is connected to the drain of PMOS transistor PM16; the source of NMOS transistor NM22 is connected to the drain of NMOS transistor NM23.The substrate and source of NMOS transistor NM17, the substrate of NMOS transistor NM18, the source and substrate of NMOS transistor NM19, the substrate of NMOS transistor NM20, the source and substrate of NMOS transistor NM21, the substrate of NMOS transistor NM22, and the source and substrate of NMOS transistor NM23 are connected to the ground network.
11. The current-multiplexed output amplifier according to claim 2, characterized in that, The common-mode feedback circuit includes PMOS transistors PM18, PM19, PM20, NMOS transistors NM24 and NM25, a sixth resistor R6, a seventh resistor R7, a fifth capacitor C5, and a sixth capacitor C6. One end of the fifth capacitor C5 and one end of the sixth resistor R6 are connected to the positive output terminal; one end of the sixth capacitor C6 and one end of the seventh resistor R7 are connected to the negative output terminal; the other ends of the fifth capacitor C5, the sixth resistor R6, the sixth capacitor C6, and the seventh resistor R7 are connected together to form a common-mode detection voltage; PMOS transistor P... The source and substrate of M20 are connected to the power supply network, and the drain is connected to the source and substrate of PMOS transistor PM18 and PMOS transistor PM19, respectively. The gate of PMOS transistor PM18 receives the common-mode voltage; the gate of PMOS transistor PM19 receives the common-mode detection voltage; the drain of PMOS transistor PM18 is connected to the drain and gate of NMOS transistor NM24; the drain of PMOS transistor PM19 is connected to the drain and gate of NMOS transistor NM25, forming the common-mode feedback voltage fb; the source and substrate of NMOS transistor NM24 and the source and substrate of NMOS transistor NM25 are connected to the ground network.