Digital closed-loop grid active real-time control driving device

Abstract

The invention relates to the technical field of third-generation grid-controlled power semiconductor devices, and discloses a digital closed-loop grid active real-time control driving device, which comprises a sampling element, a control element and an execution element, the input end of the sampling element is connected with a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, the output end of the sampling element is connected with the control element, the control element is connected with the execution element, and the sampling element is connected with the control element. The output end of the execution element is connected with the SiC MOSFET device, the control element receives an analog sampling signal of the sampling element, the analog sampling signal is processed to obtain an analog modulation signal, the analog modulation signal is sent to the execution element, and the execution element processes the analog modulation signal to regulate and control the gate-source voltage of the SiC MOSFET device. According to the digital closed-loop grid active real-time control driving device, in the submicrosecond transient process of a SiC MOSFET device, high-speed response and accurate control of grid active control driving are achieved based on existing software and hardware conditions, and therefore quantitative regulation and control of peak stress and switching loss in the transient process of the device are achieved.

Description

Technical Field

[0001] This invention relates to the field of third-generation gate-controlled power semiconductor device technology, specifically to a digital closed-loop gate active real-time control drive device. Background Technology

[0002] In recent years, silicon carbide power semiconductor devices have become a strategic focus in the construction of new energy systems due to their advantages such as high frequency and high voltage resistance. However, the switching transient process of these devices exhibits strongly nonlinear electromagnetic energy interaction characteristics, resulting in time delays and distortions in the actual response compared to ideal step signals. Significant switching losses and peak stresses caused by parasitic parameter coupling severely restrict the power quality and conversion efficiency of the devices. Against this backdrop, active gate control technology, as a non-intrusive control method, plays a crucial role in improving power density and ensuring system reliability.

[0003] In a digital closed-loop gate active control architecture, the performance of the control system is constrained by the coordinated optimization of three key modules: sampling elements, control elements, and execution elements. First, it should be noted that the sampling and execution elements, as the critical coupling interfaces between the power device and the drive circuit, directly affect control performance due to the degree of matching of their design parameters. On the one hand, existing gate active control drives have not yet established a connection between the measurement boundary or control boundary and the nonlinear parameters of the power device, thus hindering the reliability and universality of related drive schemes for practical applications. On the other hand, the total response delay of existing digital gate active control systems is no less than the order of hundreds of nanoseconds, which is close to the duration of the switching transient process of SiC MOSFET devices. This considerable delay significantly affects the phase margin of the control system and may even induce high-frequency oscillations. Specifically, existing gate active control technologies suffer from the following key problems: 1. The differential state signal received by the sampling element needs to pass through the input attenuation stage and the fully differential buffer stage in sequence. However, the imperfectly symmetrical resistors, capacitors, buffers and parasitic parameters will reduce the sampling accuracy. Second, the high-frequency modulation signal generated by the FPGA during the driving process needs to be accurately amplified into a driving signal to control the gate-source voltage of the SiCMOSFET device. However, the strong coupling and antagonistic relationship between high bandwidth and high gain always limits the design of the actuator. Third, gate active control driving digitization is a necessary condition for realizing real-time optimized control strategies and adaptive closed-loop control methods. However, digitization will bring additional signal conversion delay, which will affect the stability of control.

[0004] These combined factors ultimately limit the engineering application potential of gate active control technology in terms of high-speed transient response and precise control. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the above-mentioned technologies by providing a digital closed-loop gate active real-time control drive device. In the sub-microsecond transient process of SiC MOSFET devices, based on existing hardware and software conditions, it realizes high-speed response and precise control of gate active control drive, thereby achieving quantitative regulation of peak stress and switching losses in the transient process of the device.

[0006] To achieve the above objectives, the digital closed-loop gate active real-time control drive device designed in this invention includes a sampling element and a control element, as well as an execution element. The input terminal of the sampling element is connected to a SiC MOSFET device, the output terminal of the sampling element is connected to the control element, the control element is connected to the execution element, and the output terminal of the execution element is connected to the SiC MOSFET device. The control element receives the analog sampling signal from the sampling element, processes it to obtain an analog modulation signal, and sends it to the execution element. The execution element processes the analog modulation signal to regulate the gate-source voltage of the SiC MOSFET device.

[0007] Preferably, the sampling element includes two sampling signal paths, each sampling path including an input attenuation stage and a fully differential buffer stage. The input attenuation stage includes a pair of differential surface-mount RC differential input bridge arms. The two surface-mount RC differential input bridge arms of one input attenuation stage are respectively connected to the drain and source of the SiC MOSFET device, and the two surface-mount RC differential input bridge arms of the other input attenuation stage are respectively connected to the Kelvin terminal and source of the SiC MOSFET device. The output terminal of the input attenuation stage is connected to the input terminal of the fully differential buffer stage, and the output terminals of both fully differential buffer stages are connected to the input terminal of the control element.

[0008] Preferably, the surface-mount resistor-capacitor differential input bridge arm is formed by connecting multiple equal-value surface-mount resistor-capacitor groups in series. Each surface-mount resistor-capacitor group consists of a surface-mount resistor and a surface-mount capacitor connected in parallel. The output terminals of the two surface-mount resistor-capacitor differential input bridge arms in each input attenuation stage are each connected to a voltage-dividing surface-mount resistor and a frequency-compensating surface-mount capacitor. Both voltage-dividing surface-mount resistors are connected to a variable resistor with a grounded sliding terminal, and both frequency-compensating surface-mount capacitors are grounded.

[0009] Preferably, each of the fully differential buffer stages includes two field-effect transistor operational amplifiers and a fully differential operational amplifier connected to the field-effect transistor operational amplifiers. Each input terminal of the fully differential buffer stage is provided with a clamping diode, which is connected to the two field-effect transistor operational amplifiers. The feedback circuit of each of the two field-effect transistor operational amplifiers includes a fixed-value parallel resistor-capacitor group, which shares an adjustable-value parallel resistor-capacitor group with adjustable resistance and capacitance values. The feedback circuit of the fully differential operational amplifier includes two fixed-value parallel resistor-capacitor groups located upstream and two fixed-value parallel resistor-capacitor groups located downstream.

[0010] Preferably, the control element includes two ADCs, one DAC, one clock distributor, and one FPGA. The differential inputs of the two ADCs are respectively connected to the outputs of the two fully differential buffer stages. The outputs of the two ADCs are both connected to the FPGA. The output of the FPGA is connected to the output of the DAC. The output of the DAC is connected to the execution element. The clock distributor provides a global clock signal to the ADCs, DAC, and FPGA simultaneously.

[0011] Preferably, the clock distributor can eliminate clock jitter and provide at least four clock signals. The clock distributor is connected to a reference clock crystal and a voltage-controlled crystal. The reference clock crystal provides a reference clock signal to the clock distributor. At the same time, the clock distributor drives a phase-locked loop filter through a built-in charge pump to control the voltage-controlled crystal to output a clock signal with adjustable period and phase, which is then distributed to the FPGA, ADC and DAC.

[0012] Preferably, the ADC is a differential analog signal input with parallel LVDS digital signal output and low latency, the DAC is a differential analog signal output with parallel LVDS digital signal input and low latency, and the FPGA implements the control algorithm.

[0013] Preferably, the ADC converts the analog sampling signal into a low-latency parallel LVDS digital sampling signal and sends it to the FPGA. The FPGA converts the digital sampling signal into a parallel LVDS digital modulation signal according to the control algorithm and sends it to the DAC. The DAC converts the digital modulation signal into a low-latency analog modulation signal.

[0014] Preferably, the execution element includes a differential-to-single-ended operational amplifier and several parallel current-feedback operational amplifiers. The differential input terminal of the differential-to-single-ended operational amplifier is connected to the differential output terminal of the DAC in the control element. The single-ended output terminal of the differential-to-single-ended operational amplifier is connected to the input terminal of the current-feedback operational amplifier. The output terminals of the current-feedback operational amplifiers are all connected to the gate of the SiC MOSFET device via drive resistors. The common ground of the current-feedback operational amplifiers is connected to the Kelvin terminal of the SiC MOSFET device.

[0015] Preferably, the feedback circuit of the differential-to-single-ended operational amplifier consists of two fixed surface-mount resistors with the same comparison value. The differential-to-single-ended operational amplifier is connected to each current feedback operational amplifier through a small fixed surface-mount resistor. The feedback circuit of each current feedback operational amplifier consists of a pair of fixed surface-mount resistors.

[0016] Compared with the prior art, the present invention has the following advantages: 1. A closed-loop control system for the rate of change of state variables of SiC MOSFET devices is established through digital algorithms, thereby realizing real-time quantitative control of the transient characteristics (spikes and switching losses) of SiC MOSFET devices. 2. It possesses high-speed response and precise control capabilities; 3. It achieves high-precision direct measurement of the state variables (drain-source voltage and drain current change rate) required for closed-loop control, and further accurately reconstructs the drain current through an improved filtering algorithm, providing key hardware support for fine-grained partitioning and adaptive adjustment of control parameters in the closed-loop control stage. 4. It breaks through the limitations of traditional limited switching state combinations, laying the necessary hardware foundation for the realization of complex control algorithms. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the digital closed-loop gate active real-time control drive device of the present invention. Figure 2 for Figure 1 A schematic diagram of the input attenuation stage of the sampling element; Figure 3 for Figure 1 A schematic diagram of the fully differential buffer stage of the sampling element; Figure 4 This is a schematic diagram of the parasitic capacitance distribution of the sampling element in the digital closed-loop gate active real-time control drive device of the present invention. Figure 5 for Figure 1 A schematic diagram of the structure of the control element; Figure 6 for Figure 1 A schematic diagram of the structure of the actuator; Figure 7 This is a comparison diagram of the transient characteristics of low-voltage SiC MOSFET devices controlled by the digital closed-loop gate active real-time control drive device of the present invention and the conventional drive.

[0018] The components in the diagram are labeled as follows: Sampling Element 1, Input Attenuation Stage 11, Fully Differential Buffer Stage 12, Field-Effect Transistor Operational Amplifier 121, Fully Differential Operational Amplifier 122, Fixed Parallel Resistor-Capacitor Group 123, Adjustable Parallel Resistor-Capacitor Group 124, Surface Mount RC Differential Input Bridge Arm 13, Surface Mount Resistor-Capacitor Group 131, Surface Mount Resistor 132, Surface Mount Capacitor 133, Voltage Divider Surface Mount Resistor 14, Frequency Compensation Surface Mount Capacitor 15, Variable Resistor 16, Clamping Diode 17, Control Element 2, ADC 21, DAC 22, Clock Distributor 23, FPGA 24, Reference Clock Crystal 25, Voltage-Controlled Crystal 26, Phase-Locked Loop Filter 27, Actuator 3, Differential to Single-Ended Operational Amplifier 31, Current Feedback Operational Amplifier 32, Drive Resistor 33, Fixed Surface Mount Resistor 34, Small Fixed Surface Mount Resistor 35, Actuator Power Unit 36, SiC MOSFET Device 4, Drain 41, Source 42, Kelvin Terminal 43, Gate 44. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0021] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0022] like Figure 1 As shown, a digital closed-loop gate active real-time control drive device includes a sampling element 1 and a control element 2, and also includes an execution element 3. The input terminal of the sampling element 1 is connected to a SiC MOSFET device 4, and the output terminal of the sampling element 1 is connected to the control element 2. The control element 2 is connected to the execution element 3, and the output terminal of the execution element 3 is connected to the SiC MOSFET device 4. The control element 2 receives the analog sampling signal from the sampling element 1, processes it to obtain an analog modulation signal, and sends it to the execution element 3. The execution element 3 processes the analog modulation signal to regulate the gate-source voltage of the SiC MOSFET device 4.

[0023] Combination Figure 2 As shown, the sampling element 1 includes two sampling signal paths. Each sampling path includes an input attenuation stage 11 and a fully differential buffer stage 12. The input attenuation stage 11 includes a pair of differential surface-mount RC differential input bridge arms 13. The two surface-mount RC differential input bridge arms 13 of one input attenuation stage 11 are respectively connected to the drain 41 and source 42 of the SiC MOSFET device 4. The two surface-mount RC differential input bridge arms 13 of the other input attenuation stage 11 are respectively connected to the Kelvin terminal 43 and source 42 of the SiC MOSFET device 4. The output terminal of the input attenuation stage 11 is connected to the input terminal of the fully differential buffer stage 12. The output terminals of both fully differential buffer stages 12 are connected to the input terminal of the control element 2.

[0024] Combination Figure 2As shown, the surface-mount resistor-capacitor differential input bridge arm 13 is formed by connecting multiple surface-mount resistor and capacitor groups 131 of equal value in series. Each surface-mount resistor-capacitor group 131 consists of a surface-mount resistor 132 and a surface-mount capacitor 133 connected in parallel. The output terminals of the two surface-mount resistor-capacitor differential input bridge arms 13 in each input attenuation stage 11 are each connected to a voltage divider surface-mount resistor 14 and a frequency compensation surface-mount capacitor 15. A fixed attenuation ratio is provided by the two voltage divider surface-mount resistors 14. Both voltage divider surface-mount resistors 14 are connected to a variable resistor 16 with a sliding terminal grounded. Both frequency compensation surface-mount capacitors 15 are grounded.

[0025] The resistors and capacitors used in the input attenuation stage 11 include, but are not limited to, high-voltage surface-mount resistors and capacitors. Any circuit design structure that has multiple parallel resistors and capacitors of equal value connected in series, with an adjustable variable resistor 16 between the voltage-dividing surface-mount resistors 14 at the output, and a frequency-compensating surface-mount capacitor 15 grounded at the connection point with the subsequent field-effect transistor operational amplifier 121, falls under the category of the input attenuation stage 11 in this invention. Furthermore, the specific values ​​of the resistors and capacitors, and the corresponding attenuation ratios they constitute, can be chosen in various ways, as long as they can convert the rated voltage (thousands of volts) of the low-to-medium voltage SiC MOSFET device 4 to a voltage (several volts) suitable for signal conditioning. This embodiment does not impose any limitations on this. Combination Figure 3 As shown, each of the fully differential buffer stages 12 includes two field-effect transistor operational amplifiers 121 and a fully differential operational amplifier 122 connected to the field-effect transistor operational amplifiers 121. Each of the fully differential buffer stages 12 has a clamping diode 17 at its input terminal, which is connected to the two field-effect transistor operational amplifiers 121. The feedback circuit of each of the two field-effect transistor operational amplifiers 121 includes a fixed-value parallel resistor-capacitor group 123, which shares an adjustable-value parallel resistor-capacitor group 124 whose resistance and capacitance values ​​are adjustable. The feedback circuit of the fully differential operational amplifier 122 includes two fixed-value parallel resistor-capacitor groups 123 located upstream and two fixed-value parallel resistor-capacitor groups 123 located downstream. In this embodiment, the absolute error of the resistance of all fixed values ​​of the sampling element 1 is less than 0.1%, and the absolute error of the capacitance of all fixed values ​​is less than 1%.

[0026] Combination Figure 4 As shown, the non-ideal factors (parasitic capacitance) of the two field-effect transistor operational amplifiers 121 are... , The non-ideal factors of clamping diode 17 (junction capacitance) The input capacitor of the fully differential buffer stage, formed by the two surface-mount RC differential input bridge arms 13, forms a low-pass filter and limits the upper limit of the measurement bandwidth of the device. After adding the frequency compensation surface-mount capacitor 15 and grounding it, the poles caused by this low-pass filter are compensated. In this embodiment, the clamping diode 17 is used to limit the voltage range that exceeds the range available for signal conditioning. The two field-effect transistor operational amplifiers 121 act as a buffer stage, providing a large input resistance and a small output resistance to achieve impedance transformation. The fully differential operational amplifier 122 provides the function of DC coupling with the ADC 21.

[0027] Furthermore, the fully differential buffer stage 12 includes, but is not limited to, field-effect transistor operational amplifier 121 and fully differential operational amplifier 122. Any three-op-amp instrumentation amplifier structure that forms a DC-coupled differential output with a high-bandwidth operational amplifier (bandwidth greater than 20MHz) with a large input impedance and a small output impedance belongs to the fully differential buffer stage 12 in this embodiment of the invention. At the same time, there are various models of field-effect transistor operational amplifier 121 and fully differential operational amplifier 122 applicable to the fully differential buffer stage 12, as well as various resistance values ​​of the parallel resistor-capacitor structure in the feedback circuit. As long as the resistance of the fixed-value parallel resistor-capacitor group 123 and the adjustable-value parallel resistor-capacitor group 124 in the feedback circuit can meet the balance requirements of the differential structure (the absolute error of the fixed-value resistor in absolute position is less than 0.1%), this embodiment does not limit the specific value of the resistor in this feedback circuit or the specific selection of the sampling element operational amplifier. It is understandable that the capacitors of the fixed-value parallel resistor-capacitor group 123 and the adjustable-value parallel resistor-capacitor group 124 also play the role of frequency compensation (the basic principle is the same as the frequency compensation surface-mount capacitor 15 in the input attenuation stage 11, and the absolute position of the fixed-value capacitor has an absolute error of less than 1%).

[0028] Compared to traditional SiC MOSFET device state sampling devices, the sampling element 1 provided in this invention ensures uniform voltage division for each surface-mount resistor-capacitor group 13 on the two surface-mount resistor-capacitor differential input bridge arms 13 of the input attenuation stage 11, as the two surface-mount resistor-capacitor differential input bridge arms 13 are formed by multiple equal-value surface-mount resistor-capacitor groups 131 connected in series. Furthermore, the number of equal-value surface-mount resistor-capacitor groups 131 connected in series on the two surface-mount resistor-capacitor differential input bridge arms 13 not only satisfies that the sum of their rated voltages is greater than the rated voltage of the tested low-voltage SiC MOSFET device 4, but also that the heat dissipation of each surface-mount resistor-capacitor group 131 is less than its own thermal breakdown power, thus ensuring the normal operation of the input attenuation stage 11. Simultaneously, the voltage-dividing surface-mount resistors 14 in each differential structure are connected through a variable resistor 16 with a sliding terminal grounded. By adjusting the variable resistor 16, the reduction in common-mode rejection ratio caused by the asymmetry of the resistance values ​​of the two surface-mount resistor-capacitor differential input bridge arms 13 can be effectively avoided. Finally, the output of the input attenuation stage 11 is grounded through the frequency compensation surface-mount capacitor 15, which can effectively avoid bandwidth attenuation caused by the non-ideal factors of the two field-effect transistor operational amplifiers 121.

[0029] like Figure 5 As shown, control element 2 includes two ADCs 21, one DAC 22, a clock distributor 23, and an FPGA 24. The differential inputs of the two ADCs 21 are connected to the outputs of the two fully differential buffer stages 12, respectively. The outputs of both ADCs 21 are connected to the FPGA 24. The output of the FPGA 24 is connected to the output of the DAC 22. The output of the DAC 22 is connected to the execution element 3. The clock distributor 23 provides a global clock signal to the ADCs 21, DAC 22, and FPGA 24 simultaneously. The clock distributor 23 can eliminate clock jitter and provide at least four clock signals. The clock distributor 23 is connected to a reference clock crystal 25 and a voltage-controlled crystal 26. The reference clock crystal 25 provides a reference clock signal to the clock distributor 23. At the same time, the clock distributor 23 drives the phase-locked loop filter 27 through a built-in charge pump to control the voltage-controlled crystal 26 to output a clock signal with adjustable period and phase. The clock signal is then distributed to FPGA 24, ADC 21 and DAC 22 through the clock distributor 23, thereby achieving consistent global clock signal frequency and phase alignment for different timing devices (FPGA 24, ADC 21 and DAC 22).

[0030] Specifically, ADC21 is a differential analog signal input with parallel LVDS digital signal output and low latency; DAC22 is a differential analog signal output with parallel LVDS digital signal input and low latency. To minimize conversion delay and achieve real-time sampling and driving, compared to the JESD204B communication interface, the parallel LVDS communication interface of ADC21 and DAC22 has lower conversion delay and is proportional to the sampling period, ensuring a small and fixed total delay. Therefore, within the real-time detection requirements and high-speed communication range (greater than or equal to 100Msps and less than or equal to 500Msps), any high-speed ADC21 and DAC22 with parallel LVDS communication interface can be considered control element 2 in this embodiment. Furthermore, there are multiple implementation methods for the sampling computation stage; this embodiment does not impose any special model restrictions on the FPGA 24, ADC21, DAC 22, and clock distributor 23 that meet the sampling requirements.

[0031] FPGA24 implements the control algorithm, namely, the sampling calculation and filter circuit functions. It uses a digital filter to convert the sampled drain-source voltage and Kelvin-source voltage corresponding digital sampling signals into state variable change rates (drain-source voltage change rate and drain current change rate). The difference is then calculated with a preset value and fed into a digital compensation network designed based on the closed-loop control algorithm to obtain a digital modulation signal. ADC21 converts the analog sampling signal (i.e., the analog signals of drain-source voltage and Kelvin-source voltage) output from the fully differential buffer stage 12 into a low-latency parallel LVDS digital sampling signal and sends it to FPGA24. FPGA24, according to the control algorithm, converts the digital sampling signal into a parallel LVDS digital modulation signal and sends it to DAC22. DAC22 then converts the digital modulation signal into a low-latency analog modulation signal.

[0032] It should be noted that any control element 2 in this embodiment of the invention can be any device whose state change rate of SiC MOSFET 4 is selected as the direct or indirect control object. At the same time, the digital filter and the digital compensation network designed based on the closed-loop control algorithm can have a variety of different configurations. This embodiment does not impose any special limitations on the digital filter and the digital compensation network designed based on the closed-loop control algorithm.

[0033] like Figure 6As shown, the execution element 3 includes a differential-to-single-ended operational amplifier 31 and several parallel current-feedback operational amplifiers 32. The differential input terminal of the differential-to-single-ended operational amplifier 31 is connected to the differential output terminal of DAC21 in the control element 2. The single-ended output terminal of the differential-to-single-ended operational amplifier 31 is connected to the input terminal of the current-feedback operational amplifier 32. The output terminals of the current-feedback operational amplifiers 32 are all connected to the gate 44 of the SiC MOSFET device 4 via drive resistors 33. The common ground of the current-feedback operational amplifiers 32 is connected to the Kelvin terminal 43 of the SiC MOSFET device 4. The differential-to-single-ended operational amplifier 31 converts the analog differential modulation signal output by the control element 2 DAC21 into an analog single-ended modulation signal relative to the Kelvin terminal 43 of the SiC MOSFET device 4. The current-feedback operational amplifiers 32 amplify the analog single-ended modulation signal into a drive signal and apply it to the gate 44 of the SiC MOSFET device 4.

[0034] The feedback circuit of the differential-to-single-ended operational amplifier 31 consists of two fixed surface-mount resistors 34 with the same contrast value. This ensures that the high-frequency differential signal output by the control element 2DAC21 is accurately converted into a single-ended signal of the corresponding value and sent to multiple current-feedback operational amplifiers 32. Using single-ended signals can effectively reduce the size of the wiring and improve the integration of the driver. The differential-to-single-ended operational amplifier 31 and each current-feedback operational amplifier 32 are connected through a small fixed surface-mount resistor 35. When using the load sharing principle to increase the output power of the actuator 3, long-distance wiring is inevitably used to connect the output of the differential-to-single-ended operational amplifier 31 and the input of the current-feedback operational amplifier 32. For high-frequency applications, long transmission lines will introduce parasitic capacitance. To avoid modulation signal oscillation, the small fixed surface-mount resistor 35 in series can eliminate this problem caused by parasitic capacitance. The feedback circuit of each current-feedback operational amplifier 32 consists of a pair of fixed surface-mount resistors 34. In this embodiment, the absolute error of the fixed surface-mount resistor 34 in the actuator 3 is less than 0.1%, while the drive resistor must be a surface-mount resistor with a package size of 0806 or larger.

[0035] It should be noted that as long as the differential-to-single-ended operational amplifier 31 is selected and a small-value fixed surface-mount resistor 35 (less than or equal to 50 ohms) is connected to the output terminal of the differential-to-single-ended operational amplifier 31 and the input terminal of the current feedback type operational amplifier 32, both belong to the execution element 3 in this embodiment of the invention. Furthermore, there are various options for the model of the differential-to-single-ended operational amplifier 31 and the resistance value of the small-value fixed surface-mount resistor 35 suitable for the execution element 3. As long as the small-value fixed surface-mount resistor 35 in the interconnection circuit can effectively suppress the oscillation of the drive signal, it is acceptable. This embodiment does not limit the specific value of this small-value fixed surface-mount resistor 35 or the specific selection of the differential-to-single-ended operational amplifier 31.

[0036] Furthermore, the actuator power unit 36, composed of the drive resistor 33, the small fixed surface-mount resistor 35, a pair of fixed surface-mount resistors 34 in the feedback circuit of the current feedback operational amplifier 32, and the current feedback operational amplifier 32, is the smallest reproducible unit for realizing drive voltage regulation in gate active control technology. Figure 6 In the circuit, several power units 36 of the actuator are connected in parallel. The current feedback operational amplifier 32 has independent bandwidth and gain and has a high slew rate. It can not only provide higher signal gain without reducing the closed-loop bandwidth, but also effectively drive large capacitive loads, thereby ensuring precise control of the gate-source voltage of the SiC MOSFET device 4. At the same time, a suitable drive resistor 33 can ensure the stability and low distortion of the drive signal output by the actuator 3.

[0037] It should be noted that the number of power units 36 of the execution element is not limited to three. The specific number is determined by the input capacitance of the controlled object SiC MOSFET device 4 and the load-carrying capacity of the current feedback operational amplifier 32. As long as the current feedback operational amplifier 32 is configured, and the driving resistor 33 connects the output terminal of each current feedback operational amplifier 32 to the gate 44 of the SiC MOSFET device 4, all are considered execution elements 3 in this embodiment of the invention. Furthermore, there are various options for the model of the current feedback operational amplifier 32 and the resistance value of the driving resistor 33 suitable for the execution element 3. As long as the multiple current feedback operational amplifiers 32 and driving resistors 33 can meet the requirements of driving signal stability and low distortion, this embodiment does not limit the specific model of the current feedback operational amplifier 32 or the specific resistance value of the driving resistor 33.

[0038] This embodiment of the digital closed-loop gate active real-time control drive device has the ability to track and control the rate of change of constant main circuit state variables (drain current rate of change, drain-source voltage rate of change) in real time during transient processes, thereby realizing the quantitative control of switching loss and peak stress by controlling the switching trajectory of SiC MOSFET device 4 during transient characteristic change stages of tens to hundreds of nanoseconds. (See attached...) Figure 7The diagram shows a comparison between active gate control technology and traditional drive technology in terms of current spikes and switching losses during the turn-on and turn-off processes. While keeping the magnitudes of current and voltage spikes constant, active gate control can reduce turn-on losses from 24.7 mJ to 16.5 mJ (a reduction of 33.2%) and turn-off losses from 15.8 mJ to 11.6 mJ (a reduction of 26.6%). While maintaining constant turn-on and turn-off losses, active gate control can reduce the peak drain current spike by 30.1% and the peak drain-source voltage spike by 24.3% compared to conventional drive technology. In summary, the digital closed-loop active real-time gate control drive device designed in this invention achieves a significant breakthrough in key transient performance indicators compared to traditional drive technology. Its individual performance reaches the best value in similar research to date, and its overall performance is leading, demonstrating technological advancement and engineering application value in the field of power converter device drives.

[0039] It should be noted that the above description of the technical solutions is exemplary, and this specification may be embodied in different forms and should not be construed as limiting it to the technical solutions set forth herein. Rather, providing these descriptions will ensure that the disclosure of this invention is thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0040] For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and the above structures should all be considered to fall within the protection scope of the present invention.

Claims

1. A digital closed-loop gate active real-time control drive device, comprising a sampling element (1) and a control element (2), characterized in that: It also includes an execution element (3), the input terminal of the sampling element (1) is connected to a SiC MOSFET device (4), the output terminal of the sampling element (1) is connected to the control element (2), the control element (2) is connected to the execution element (3), the output terminal of the execution element (3) is connected to the SiC MOSFET device (4), the control element (2) receives the analog sampling signal from the sampling element (1), processes it to obtain an analog modulation signal, and sends it to the execution element (3), the execution element (3) processes the analog modulation signal to regulate the gate-source voltage of the SiC MOSFET device (4).

2. The digital closed-loop gate active real-time control drive device according to claim 1, characterized in that: The sampling element (1) includes two sampling signal paths. Each sampling path includes an input attenuation stage (11) and a fully differential buffer stage (12). The input attenuation stage (11) includes a pair of differential structure surface-mount RC differential input bridge arms (13). The two surface-mount RC differential input bridge arms (13) of one input attenuation stage (11) are respectively connected to the drain (41) and source (42) of the SiC MOSFET device (4). The two surface-mount RC differential input bridge arms (13) of the other input attenuation stage (11) are respectively connected to the Kelvin terminal (43) and source (42) of the SiC MOSFET device (4). The output terminal of the input attenuation stage (11) is connected to the input terminal of the fully differential buffer stage (12). The output terminals of both fully differential buffer stages (12) are connected to the input terminal of the control element (2).

3. The digital closed-loop gate active real-time control drive device according to claim 2, characterized in that: The surface-mount resistor-capacitor differential input bridge arm (13) is formed by connecting multiple surface-mount resistor-capacitor groups (131) of equal value in series. Each surface-mount resistor-capacitor group (131) is composed of a surface-mount resistor (132) and a surface-mount capacitor (133) connected in parallel. The output terminals of the two surface-mount resistor-capacitor differential input bridge arms (13) in each input attenuation stage (11) are each connected to a voltage divider surface-mount resistor (14) and a frequency compensation surface-mount capacitor (15). Both voltage divider surface-mount resistors (14) are connected to a variable resistor (16) with a sliding terminal grounded, and both frequency compensation surface-mount capacitors (15) are grounded.

4. The digital closed-loop gate active real-time control drive device according to claim 2, characterized in that: Each of the fully differential buffer stages (12) includes two field-effect transistor operational amplifiers (121) and a fully differential operational amplifier (122) connected to the field-effect transistor operational amplifiers (121). Each of the fully differential buffer stages (12) has a clamping diode (17) at its input terminal. The clamping diode (17) is connected to the two field-effect transistor operational amplifiers (121). The feedback circuit of each of the two field-effect transistor operational amplifiers (121) includes a fixed-value parallel resistor-capacitor group (123) and shares an adjustable-value parallel resistor-capacitor group (124) with adjustable resistance and capacitance values. The feedback circuit of the fully differential operational amplifier (122) includes two fixed-value parallel resistor-capacitor groups (123) located upstream and two fixed-value parallel resistor-capacitor groups (123) located downstream.

5. The digital closed-loop gate active real-time control drive device according to claim 2, characterized in that: The control element (2) includes two ADCs (21), one DAC (22), one clock distributor (23), and one FPGA (24). The differential input terminals of the two ADCs (21) are respectively connected to the output terminals of the two fully differential buffer stages (12). The output terminals of the two ADCs (21) are both connected to the FPGA (24). The output terminal of the FPGA (24) is connected to the output terminal of the DAC (22). The output terminal of the DAC (22) is connected to the execution element (3). The clock distributor (23) provides a global clock signal for the ADCs (21), DAC (22), and FPGA (24) simultaneously.

6. The digital closed-loop gate active real-time control drive device according to claim 5, characterized in that: The clock distributor (23) can eliminate clock jitter and provide at least four clock signals. The clock distributor (23) is connected to a reference clock crystal (25) and a voltage-controlled crystal (26). The reference clock crystal (25) provides a reference clock signal to the clock distributor (23). At the same time, the clock distributor (23) drives the phase-locked loop filter (27) through a built-in charge pump to control the voltage-controlled crystal (26) to output a clock signal with adjustable period and phase. The clock signal is then distributed to the FPGA (24), ADC (21) and DAC (22) through the clock distributor (23).

7. The digital closed-loop gate active real-time control drive device according to claim 5, characterized in that: The ADC (21) is a differential analog signal input with parallel LVDS digital signal output and low delay. The DAC (22) is a differential analog signal output with parallel LVDS digital signal input and low delay. The FPGA (24) implements the control algorithm.

8. The digital closed-loop gate active real-time control drive device according to claim 5, characterized in that: The ADC (21) converts the analog sampling signal into a low-latency parallel LVDS digital sampling signal and sends it to the FPGA (24). The FPGA (24) converts the digital sampling signal into a parallel LVDS digital modulation signal according to the control algorithm and sends it to the DAC (22). The DAC (22) converts the digital modulation signal into a low-latency analog modulation signal.

9. The digital closed-loop gate active real-time control drive device according to claim 5, characterized in that: The execution element (3) includes a differential-to-single-ended operational amplifier (31) and several parallel current-feedback operational amplifiers (32). The differential input terminal of the differential-to-single-ended operational amplifier (31) is connected to the differential output terminal of the DAC (21) in the control element (2). The single-ended output terminal of the differential-to-single-ended operational amplifier (31) is connected to the input terminal of the current-feedback operational amplifier (32). The output terminals of the current-feedback operational amplifier (32) are all connected to the gate (44) of the SiCMOSFET device (4) via driving resistors (33). The common ground of the current-feedback operational amplifier (32) is connected to the Kelvin terminal (43) of the SiCMOSFET device (4).

10. The digital closed-loop gate active real-time control drive device according to claim 9, characterized in that: The feedback circuit of the differential-to-single-ended operational amplifier (31) consists of two fixed surface-mount resistors (34) with the same comparison value. The differential-to-single-ended operational amplifier (31) and each current feedback operational amplifier (32) are connected through a small fixed surface-mount resistor (35). The feedback circuit of each current feedback operational amplifier (32) consists of a pair of fixed surface-mount resistors (34).

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