Signal isolator having a modulator circuit and method of operating the same

Abstract

The invention relates to a signal isolator with a modulator circuit and a method of operating the signal isolator. A circuit is disclosed. The circuit comprises: a modulator circuit referenced to a first ground and arranged to receive at least first and second state identifier signals, a pulse width modulation (PWM) signal, and a first bitstream signal, and to generate a modulated signal in response; an isolation capacitor coupled between the modulator circuit and the demodulator circuit, wherein the modulator circuit is arranged to transmit a modulated signal through the isolation capacitor to the demodulator circuit; and a clock generator circuit arranged to generate a clock signal (CK0) wherein the PWM signal and the first bit stream signal are synchronized with the CK0; and wherein the demodulator circuit refers to the second ground and is arranged to receive the modulated signal and to generate an output signal corresponding to the first and second identifier signals, the PWM signal and the first bitstream signal.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 681,490, filed August 9, 2024, entitled “Signal isolator with digital multiplexer and method of operating the same”, which is hereby incorporated by reference in its entirety for all purposes. Technical Field

[0003] The described implementations generally relate to electrical isolation in power converters, and more specifically, this implementation relates to a signal isolator having modulator circuitry and a method of operating the signal isolator. Background Technology

[0004] Electronic devices such as computers, servers, and televisions employ one or more power conversion circuits to convert one form of electrical energy into another. Some power conversion circuits use a circuit topology called a DC-DC converter to convert high (or low) DC voltage to lower (or higher) DC voltage. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, newer power converters can offer relatively high efficiency and a small size for newer electronic devices. Power converters can utilize isolators. Isolators can be implemented to separate circuits or sections of circuitry from each other, protecting them from unwanted influences such as, but not limited to, other circuits or sections of circuitry, to minimize the effects of common-mode transients (CMT), radiated or electromagnetic interference, and crosstalk between circuits or sections of circuitry. Capacitive isolation can be used for electrical isolation to isolate high voltages from each other or to isolate low-voltage command circuitry from high-voltage power supply circuitry. Summary of the Invention

[0005] In some embodiments, a circuit is disclosed. The circuit includes a modulator circuit referenced to a first ground and arranged to receive at least a first status identifier signal and a second status identifier signal, a pulse width modulated (PWM) signal, and a first bitstream signal, and in response produce a modulated signal; an isolation capacitor coupled between the modulator circuit and a demodulator circuit, wherein the modulator circuit is arranged to transmit the modulated signal through the isolation capacitor to the demodulator circuit; and a clock generator circuit arranged to produce a clock signal (CK0), wherein the PWM signal and the first bitstream signal are synchronized with CK0; and wherein the demodulator circuit is referenced to a second ground and arranged to receive the modulated signal and produce an output signal corresponding to the first and second identifier signals, the PWM signal, and the first bitstream signal.

[0006] In some embodiments, the demodulator circuit is arranged to detect CK0 when a reset-set sequence is detected within a first time period T1 following a rising edge of the PWM.

[0007] In some embodiments, the demodulator circuit is further arranged to set the first bitstream signal to 1 when a set is detected within a second time period following detection of CK0.

[0008] In some embodiments, the circuit further includes a second clock generator circuit arranged to produce a second clock signal.

[0009] In some embodiments, the demodulator circuit is further arranged to indicate that the second clock signal is active, and to indicate that the second status identifier signal is active when more than two consecutive sets or two consecutive reset signals are detected.

[0010] In some embodiments, the modulator circuit is further arranged to receive a second bitstream signal.

[0011] In some embodiments, the second clock signal is mixed with the second status identifier signal and with a third status identifier signal.

[0012] In some embodiments, the modulator circuit is disabled when the first status identifier signal is 1.

[0013] In some embodiments, the first status identifier signal corresponds to an isolated under-voltage lockout (UVLO) signal, and the second identifier signal corresponds to an isolated over-current status signal.

[0014] In some embodiments, a circuit is disclosed. The circuit includes: a plurality of isolated detectors arranged to detect system operating states and generate a plurality of digital signals; a pulse width generation circuit arranged to generate a pulse width modulation (PWM) signal; and at least one bit stream generator circuit arranged to generate at least a time-sensitive bit stream signal; and a modulator circuit arranged to receive the PWM signal and the time-sensitive bit stream signal, and in response, generate a single modulated signal using a sequence of set and reset commands, the modulator circuit being further arranged to asynchronously modulate the plurality of digital signals onto the single modulated signal to generate an output modulated signal, and to transmit the modulated output signal across an isolation capacitor to a demodulator circuit.

[0015] In some implementations, the demodulator circuit is arranged to receive the modulated output signal and extract a reference clock from the modulated output signal.

[0016] In some implementations, the demodulator circuit is arranged to regenerate the PWM signal, the time-sensitive bitstream signal, and the plurality of digital signals.

[0017] In some implementations, the modulator circuit operates with reference to a first ground.

[0018] In some implementations, the demodulator circuitry operates with reference to a second ground.

[0019] In some embodiments, a method for operating a circuit is disclosed. The method includes: providing a modulator circuit with a reference to a first ground; receiving at least a first state identifier signal and a second state identifier signal, a pulse width modulation (PWM) signal, and a first current signal by the modulator circuit; generating a modulated signal by the modulator circuit; providing an isolation capacitor coupled between the modulator circuit and a demodulator circuit; and transmitting the modulated signal from the modulator circuit through the isolation capacitor to the demodulator circuit.

[0020] In some implementations, the method further includes generating a clock signal (CK0) by a clock generator circuit.

[0021] In some implementations, the method further includes synchronizing the PWM signal and the first bit stream signal with CK0.

[0022] In some implementations, the method further includes receiving the modulated signal by the demodulator circuit.

[0023] In some implementations, the method further includes generating an output signal by the demodulator circuit that corresponds to the first identifier signal and the second identifier signal, the PWM signal, and the first bit stream signal. Attached Figure Description

[0024] Figure 1 An isolated gate driver circuit with a modulator is shown according to some implementation schemes;

[0025] Figure 2 This demonstrates the implementation of several schemes by Figure 1 The modulation scheme used in the modulator circuit and related circuit systems;

[0026] Figure 3 An isolated gate driver circuit with a modulator having multiple bit streams is shown according to some embodiments;

[0027] Figure 4 This demonstrates the implementation of several schemes by Figure 3 The modulation scheme used in the modulator circuit;

[0028] Figure 5 This demonstrates the implementation of several schemes by Figure 1 The modulation scheme used in the modulator circuit and related circuit system, in which the modulated signal can transmit analog information instead of a bit stream;

[0029] Figure 6 Modulation and demodulation schemes used in isolated gate drivers according to some implementation schemes are shown;

[0030] Figure 7 The modulation schemes according to certain implementation schemes are shown;

[0031] Figure 8 An isolated gate driver circuit with a modulator having multiple ∑ / Δ inputs is shown according to some embodiments; and

[0032] Figure 9 Demonstrating based on some implementation schemes Figure 8 The digital modulation scheme shown is a digital modulation scheme. Detailed Implementation

[0033] The circuits, structures, and related techniques disclosed herein generally relate to electrical isolation in power converters. More specifically, the circuits, devices, and related techniques disclosed herein relate to electrically isolated gate driver circuits used in power converters, wherein the gate driver circuitry may include modulator circuitry arranged to transmit time-sensitive information from the isolated side to the non-isolated side using an efficient modulation scheme. In some embodiments, the isolated side may be an isolated high-voltage side, and the non-isolated side may be a non-isolated low-voltage side. In various embodiments, the modulator circuitry and associated modulation techniques enable the use of isolators with a single isolation channel to multiplex signals and transmit them to the low-voltage side without any signal distortion. In this way, die area and system power can be saved.

[0034] In some implementations, isolators with multiplexing circuitry can be used to safely transmit control and / or bitstream signals from the high-voltage side of the system to the low-voltage side. The circuits and techniques disclosed herein can efficiently transmit various isolated system information (such as status, temperature, node voltages, and numerous current values) from the isolated high-voltage side to the non-isolated low-voltage side. In various implementations, several time-sensitive signals can be multiplexed over a single isolated channel, thereby minimizing signal distortion and without increasing die size. Furthermore, the techniques disclosed herein can be used in power converters where time-dependent signals can be generated from the same reference clock.

[0035] When the same reference clock is used for pulse width modulation (PWM) signals, the circuits and methods disclosed herein can be used to modulate these signals together with one or more bit streams (such as ∑Δ or other similar signals). Additionally, the techniques disclosed herein enable modulation of relatively slow, time-independent signals (such as status bits, for example, but not limited to, fault flags and / or UVLO ready signals on top of time-dependent fast signals). This is because for relatively slow, time-independent signals, propagation delay variations may not be critical. Various inventive embodiments, including methods, processes, systems, apparatuses, etc., are described herein.

[0036] Several illustrative embodiments will now be described with respect to the accompanying drawings, which form a part thereof. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of embodiments will provide those skilled in the art with a feasible description for implementing one or more embodiments. It should be understood that various changes may be made in terms of the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0037] In the current approach, isolators can be used to safely transmit control signals or bit stream signals between two segments of circuits operating relative to different ground levels. Each channel can use two pads and two bond wires to connect a primary die operating with a reference first ground (low voltage ground) to a secondary die operating with a reference second ground. When using several isolated independent channels, relatively large dies can be used to accommodate all these differential pads. In power switching applications, various information can be sent back, such as numerous status flags, isolated temperature measurements, isolated voltage measurements, and / or current measurements. In the current approach, timing information may be lost for this type of data. For example, a PWM signal may not be transmitted if the information is in duty cycle mode. It also cannot transmit Σ-Δ bit streams because it also uses a sampling clock. Transmitting several types of information, such as PWM and / or Σ-Δ bit streams, along with various quasi-static status flags, over a single digital isolator channel can be challenging.

[0038] The embodiments of this disclosure enable the transmission of a set of bits (such as several octets from various ADC converters) by combining a set of bits into a bit stream with a predefined protocol. A receiver can then receive the bit stream and decode it to determine which octets correspond to which data (such as isolated temperature and / or voltage). The techniques disclosed herein enable the mixing of two state information (such as UVLO and overcurrent state) and a PWM signal from a temperature sensor, as well as the addition of up to two bit streams, without any distortion. The PWM and bit stream frequencies can be the same. The embodiments of this disclosure enable modulation techniques independent of current consumption OOK methods. The embodiments of this disclosure enable the direct modulation of various time-sensitive signals. In some embodiments, two state information data plus a PWM signal can be combined / encoded together to form a single digital bit stream that can be transmitted to a modulator.

[0039] Figure 1 An isolated gate driver circuit with a modulator is illustrated according to some embodiments. The isolated gate driver circuit 100 may include a low-voltage section 101 and a high-voltage section 103 isolated by an isolation barrier 128. The low-voltage section 101 may include a modulator 126 arranged to transmit data to a demodulator 124 via an isolation capacitor 122. The high-voltage section 103 may include a modulator 114 arranged to transmit data to a demodulator 118 via an isolation capacitor 120. The high-voltage section 103 may include status indicators 102, 104, and up to 106 (status 1, 2, and n). The status indicators may be arranged to detect and report status information such as UVLO, overcurrent (OC), overtemperature (OT), power switch saturation operation condition (DESAT), and / or other system status indicators. The outputs of indicators 104 through 106 may be transmitted to a reference clock synchronizer circuit 116. Reference clock synchronizer circuit 116 can be arranged to synchronize status indicators 2 through n with reference clock CLKref. The outputs of indicator 102 and reference clock synchronizer circuit 116 can be coupled to modulator circuit 114. PWM generator circuit 108 can be coupled to modulator circuit 114, wherein the PWM circuit can be arranged to receive analog input IN1. Clock generator circuit 110 can be coupled to PWM circuit 108 and bitstream circuit 112. The outputs of indicator 102 and reference clock synchronizer circuit 116 can be transmitted to modulator circuit 114. Modulator circuit 114 can be coupled to isolation capacitor 120, wherein modulator circuit 114 can be arranged to transmit data to demodulator 118 through isolation capacitor 120.

[0040] Figure 2 A modulation scheme used by modulator circuit 114 and related circuitry according to some implementation schemes is shown. Figure 2 The PWM signal 202 and bit stream data 204 are shown. Graph 206 shows the result of combining the PWM signal 202 with the bit stream data 204. Figure 2The diagram further illustrates the authorized ClK region 208, the state 2 indicator 210, the modulator output 212 (with and without state 2), and the demodulator output 214. In the illustrated embodiment, the reset (R) signal is a falling edge (+ a few nanoseconds blanking), and the set signal (S) is a rising edge (+ a few nanoseconds blanking). If an RS sequence occurs within T1, the CK0 reference can be detected. If an S is detected within T2 after a previous event, the bit stream is set to 1; otherwise, it is set to 0. Outside of the T2 window, if more than two consecutive S or two consecutive R are detected, CKref is active, and state 2 is also active. If more than two states are used, the CKref frequency can be adjusted accordingly. Two consecutive identical pulses can then be obtained within a given time frame.

[0041] When the state 1 indicator is 1, the indicator can disable the modulator circuit 114. The receiver can detect the state 1 event if it does not receive a signal for at least the CK0 period (e.g., this can act as a watchdog). In some implementations, this state path may be relatively slow and may render all other data bit streams inactive. This may not be the case for states 2...n. In some implementations where there is more than one bit stream, several consecutive T2 windows can be repeated. When there is no PWM signal, CK0 (50% duty cycle) can be connected to D1. Then, a second T2 window of the second bit stream can be used after the SR sequence.

[0042] Figure 3 An isolated gate driver circuit with a modulator having multiple bit streams is shown according to some embodiments. The isolated gate driver circuit 300 is similar to the isolated gate driver circuit 100, except that it may include an additional bit stream. In addition to the other circuitry of the isolated gate driver circuit 100, the isolated gate driver circuit 300 may include bit stream 315.

[0043] Figure 4 This demonstrates the implementation of several schemes by Figure 3 The modulation scheme used in the modulator circuit. (Reference) Figure 3 and 4 The second bit stream 315 can be added to the PWM by adding (or not adding) pulses 402 and 404 in T2 after the SR sequence in T1. However, the clock reference can still reference the RS sequence because the SR timing depends on the PWM duty cycle.

[0044] Figure 5 Modulation schemes used by modulator circuit 114 and related circuitry according to some implementations are shown, wherein the modulated signal can transmit analog information instead of a bit stream. For example...Figure 5 The graph 506 shown can transmit analog information instead of a bit stream. Figure 5 Also shown is a graph 505 illustrating D2PWM. Figure 5 The PWM signal 502 and bit stream data 504 are shown. Graph 506 shows the result of combining the PWM signal 502 with the bit stream data 204. Figure 5 Further shown are the authorized ClK region 508, the state 2 indicator 510, the modulator output 512 (with and without state 2) and the demodulator output 514.

[0045] The D2 pulse 520 can be time-delayed instead of being placed (or not added) with a fixed delay compared to the previous pulse pattern, where the delay is proportional to the analog information used for transmission, so D2 can become another PWM. In some implementations, this scheme can impose a constraint on the minimum / maximum PWM (D1) duty cycle when the D2 pulse 520 appears before the next pattern 522 relative to D1. Figure 505 illustrates the D2 PWM pattern. Its rising edge can be synchronized with D1 PWM. Its falling edge may appear before the minimum D1 PWM. The falling edge of D2 can trigger a pulse above the modulation signal 505.

[0046] Figure 6 Modulation and demodulation schemes used in isolated gate drivers according to some implementation schemes are shown. Figure 6 A modulation method for generating a sequence of set-up and reset signals that can be used by modulator 114 is illustrated. Other modulation techniques can be used to generate similar set-up and reset patterns, as will be understood by those skilled in the art who benefit from this disclosure. Figure 602 shows the modulated signal, and Figure 604 shows the pulse received after isolation capacitor 120. In the illustrated embodiment, the set-up or reset is implemented on the polarity of each transition edge, as a second transition may be rejected when a short pulse is present. Once an S or R is detected, the receiver can be blanked for a few nanoseconds (the blanking portion shown on Figure 604) such that for a short pulse, only the first edge is detected. The demodulator can detect a series of non-interleaved S and R events. The demodulator can decode a sequence of S and R events. Logic and delay circuitry can demodulate the modulated data without distortion (constant delay) of signals D1, D2, and D3.

[0047] Figure 7 The modulation schemes according to certain implementation schemes are shown. Figure 7The technique shown may be advantageous because it can be relatively fast and can have a minimal number of transitions. Embodiments of this disclosure enable the generation of custom setting and reset patterns that can be used by the modulator circuit 114. In some embodiments, a single edge transition can be used for reset, and a single short pulse (e.g., two consecutive fast edges) is used for setting. In such embodiments, the information is no longer about edge polarity, but rather the number of consecutive edges. This can double the possible bit current of the disclosed isolator. It can also reduce the number of transitions, making it more current-efficient and saving power.

[0048] Figure 8 An isolated gate driver circuit with a modulator having multiple Σ / Δ inputs is shown according to some embodiments. The isolated gate driver circuit 800 is similar to the isolated gate driver circuit 300, except that it may include Σ / Δ inputs 812 and 815 instead of a bit stream.

[0049] Figure 9 Demonstrating based on some implementation schemes Figure 8 The digital modulation scheme shown is a digital modulation scheme. The modulation scheme shown is similar to... Figures 4-5 The scheme is similar to that in the previous one, except that it uses a ∑-Δ input instead of each bit stream in the bit stream, and changes the modulation technique to encode the set and reset events differently. Figure 9 Figures 902, 904, 906, 908, 910, and 912 are shown. In the illustrated implementation, a sequence of setups and resets can be generated at the modulator output shown in Figure 910, which can restore three analog input signals and a status signal. Alternatively, the first received S can be the turn-on of PWM D1 (and the reference clocks for two other bit streams). After the first S (a short pulse, active low or high, it doesn't matter), the signal is checked for the presence of another S within a given narrow time frame T2. In this way, the state of one bit stream in bit stream D2 can be defined. Subsequently, the presence of other consecutive S can represent state 2 high information. The first R (a single transition) is the turn-off of PWM D1. If a second R is received within a fixed time frame T2, it defines the value of the second bit stream D3. Any additional R represents state 2 high. The illustrated modulation technique can be relatively fast. In the illustrated scheme, the analog receiver can distinguish between a single edge and a short pulse.

[0050] In some implementations, combinations of the circuits and methods disclosed herein can be used to modulate the signal on the high-voltage side of the isolator and demodulate the signal on the low-voltage side of the isolator. Although circuits and methods are described and shown herein with respect to several specific configurations and modulation / demodulation schemes for gate driver modulators / demodulators, embodiments of this disclosure are applicable to other configurations using signal isolation modulation techniques with other power converter topologies.

[0051] In the foregoing description, numerous specific details have been described with reference to embodiments of this disclosure, which may vary depending on the specific implementation. Therefore, the description and drawings should be considered illustrative rather than restrictive. The unique and exclusive indication of the scope of this disclosure, and what the applicant wishes to define as the scope of this disclosure, is the literal and equivalent scope of the claims published in this application, taking the specific form published by those claims, including any subsequent amendments. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of this disclosure.

[0052] Additionally, spatially relative terms, such as “bottom” or “top,” may be used to describe the relationship of one element and / or feature to another, as illustrated in the figures. It should be understood that spatially relative terms are intended to cover different orientations of the device in use and / or operation than those depicted in the figures. For example, if the device in the figures is flipped, the element described as the “bottom” surface may then be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise) and may be interpreted accordingly by the spatially relative descriptors used herein.

[0053] As used herein, the terms “and,” “or,” and “and / or” can have a variety of meanings, which are also expected to depend at least in part on the context in which the terms are used. Generally, “or,” when used in a list of associations (such as A, B, or C), is intended to mean A, B, and C (used herein in an inclusive sense) and A, B, or C (used herein in an exclusive sense). Additionally, the term “one or more” as used herein can be used to describe any feature, structure, or property in the singular form, or can be used to describe some combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example and the claimed subject matter is not limited to this example. Furthermore, the term “at least one of…” when used in a list of associations (such as A, B, or C) can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0054] Throughout this specification, references to “an example,” “example,” “some examples,” or “exemplary embodiment” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the phrases “in an example,” “example,” “in some examples,” “in some embodiments,” or other similar phrases appearing throughout this specification do not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined into one or more examples and / or features.

[0055] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but rather includes all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A circuit comprising: A modulator circuit, the modulator circuit being referenced to a first ground and arranged to receive at least a first state identifier signal and a second state identifier signal, a pulse width modulation (PWM) signal and a first bit stream signal, and to generate a modulated signal in response; An isolation capacitor is coupled between the modulator circuit and the demodulator circuit, wherein the modulator circuit is arranged to transmit the modulated signal through the isolation capacitor to the demodulator circuit. as well as A clock generator circuit is arranged to generate a clock signal (CK0), wherein the PWM signal and the first bit stream signal are synchronized with CK0; and The demodulator circuit is referenced to a second ground and is arranged to receive the modulation signal and generate an output signal corresponding to the first identifier signal and the second identifier signal, the PWM signal and the first bit stream signal.

2. The circuit of claim 1, wherein the demodulator circuit is arranged to detect CK0 when a reset-set sequence is detected within a first time period T1 after the rising edge of the PWM.

3. The circuit according to claim 2, wherein the demodulator circuit is further arranged to set the first bit stream signal to 1 when a setting is detected during a second time period after CK0 is detected.

4. The circuit of claim 3, further comprising a second clock generator circuit arranged to generate a second clock signal.

5. The circuit of claim 4, wherein the demodulator circuit is further arranged to indicate that the second clock signal is active, and to indicate that the second status identifier signal is active when more than two consecutive set or two consecutive reset signals are detected.

6. The circuit of claim 5, wherein the modulator circuit is further arranged to receive a second bit stream signal.

7. The circuit of claim 6, wherein the second clock signal is mixed with the second state identifier signal and the third state identifier signal.

8. The circuit of claim 1, wherein the modulator circuit is disabled when the first state identifier signal is 1.

9. The circuit of claim 1, wherein the first status identifier signal corresponds to an isolated undervoltage lockout (UVLO) signal, and the second identifier signal corresponds to an isolated overcurrent status signal.

10. A circuit comprising: Multiple isolated detectors are arranged to detect the operating status of the system and generate multiple digital signals; A pulse width generation circuit, the pulse width generation circuit being arranged to generate a pulse width modulation (PWM) signal, and at least one bit stream generator circuit, the at least one bit stream generator circuit being arranged to generate at least a time-sensitive bit stream signal. as well as A modulator circuit is arranged to receive the PWM signal and the time-sensitive bitstream signal, and in response, generate a single modulated signal using a sequence of set and reset commands. The modulator circuit is further arranged to asynchronously modulate the plurality of digital signals onto the single modulated signal to generate an output modulated signal, and transmit the modulated output signal across an isolation capacitor to a demodulator circuit.

11. The circuit of claim 10, wherein the demodulator circuit is arranged to receive the modulated output signal and extract a reference clock from the modulated output signal.

12. The circuit of claim 11, wherein the demodulator circuit is arranged to regenerate the PWM signal, the time-sensitive bitstream signal, and the plurality of digital signals.

13. The circuit of claim 12, wherein the modulator circuit operates with reference to a first ground.

14. The circuit of claim 13, wherein the demodulator circuit operates with reference to a second location.

15. A method of operating a circuit, the method comprising: Provide a modulator circuit with reference to the first ground; The modulator circuit receives at least a first state identifier signal, a second state identifier signal, a pulse width modulation (PWM) signal, and a first bit stream signal. The modulator circuit generates the modulated signal; An isolation capacitor is provided between the modulator circuit and the demodulator circuit; as well as The modulated signal emitted by the modulator circuit passes through the isolation capacitor and reaches the demodulator circuit.

16. The method of claim 15, further comprising generating a clock signal (CK0) by a clock generator circuit.

17. The method of claim 16, further comprising synchronizing the PWM signal and the first bit stream signal with CK0.

18. The method of claim 17, further comprising receiving the modulated signal by the demodulator circuit.

19. The method of claim 18, further comprising generating an output signal corresponding to the first identifier signal and the second identifier signal, the PWM signal and the first bit stream signal by the demodulator circuit.

20. The method of claim 19, wherein the demodulator circuitry is referenced to a second ground.

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