FPGA-based multi-channel parallel data acquisition system and post-filtering processing method

Abstract

The invention relates to the technical improvement of digital signal processing and data acquisition, in particular to a multi-channel parallel data acquisition system based on an FPGA (Field Programmable Gate Array) and a post-filtering processing method, which can realize high-precision and multi-channel AD (Analog to Digital) data acquisition and real-time digital filtering based on the FPGA, and is mainly used for processing multi-channel differential analog signals. The system is used for high-speed synchronous acquisition, high-precision quantization and real-time filtering processing of intermediate-frequency signals, and comprises a front-end conditioning board, an ADC conversion module and a rear-stage FIR band-pass filter which are in communication connection in sequence. The system comprises an ADC conversion module, and further comprises an FPGA main control chip, an analog signal input interface of the ADC conversion module is provided with an RC low-pass filter, the ADC conversion module adopts three LTC2325-16 chips to work synchronously, a CNV pin of each LTC2325-16 chip is used for converting a starting signal, the FPGA adopts a state machine design to provide an accurate SPI acquisition control time sequence, and the FPGA main control chip is connected with the FPGA main control chip. According to the FPGA-based data acquisition and processing scheme, high-speed synchronous acquisition of multiple paths of differential signals, low-delay, flexible and configurable real-time filtering, high resource utilization rate and controllable cost can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical improvement of digital signal processing and data acquisition, in particular to a multi-channel parallel data acquisition system based on FPGA and a post-filtering processing method. BACKGROUND

[0002] With the rapid development of digital processing technology and integrated circuit technology, data acquisition has been applied to many disciplines today, especially in the field of communication and radar. The requirements for data acquisition technology are becoming higher and higher, and there are higher requirements for many technical indicators in AD acquisition, such as higher sampling rate, resolution, and larger input bandwidth. Therefore, the acquisition, analysis and processing of high-frequency and large-bandwidth signals have become a problem in today's acquisition technology.

[0003] In the existing multi-channel data acquisition system, the traditional technical scheme has the following shortcomings: Efficiency problem of multi-channel acquisition scheme: Many systems use a multi-channel selector to cooperate with a single ADC in a serial acquisition architecture. Although this scheme reduces the hardware complexity, the sampling rate is low, the data update period is proportional to the increase in the number of channels, the real-time performance is poor, the performance of high-performance ADC chips cannot be fully utilized, and it is difficult to meet the demand of multi-channel synchronous sampling. Each time only single-channel AD conversion can be performed, and after the conversion of the current channel is completed, the conversion of the next channel or the acquisition and transmission of data cannot be performed simultaneously, which causes the problem of low conversion efficiency. If an ADC is provided for each channel, the hardware cost, PCB layout area and system complexity will be significantly increased.

[0004] The traditional AD conversion chip also has the disadvantages of multiple control signals and complex control timing.

[0005] Software filtering scheme based on general-purpose processor: The data acquired by the ADC is transmitted to the host computer or DSP for software filtering (such as MATLAB algorithm). This scheme has flexible filtering algorithm, but the processing speed is limited by the serial execution capability of the processor, it is difficult to meet the real-time processing requirements of high-frequency signals, the system delay is large, and the complex filtering algorithm will occupy a large amount of CPU resources, affecting the overall response speed of the system.

[0006] System integration and flexibility: The traditional acquisition system with single-chip microcomputer or CPU as the core has relatively independent data acquisition, storage, processing and communication function modules, which often need additional logic chips (such as CPLD) for arbitration and coordination, increasing the system complexity and having potential risks that the CPU is in the interrupt state for a long time, affecting the real-time performance. In addition, the sampling rate, trigger condition, filtering parameters and other parameters of the system often lack flexible configurability. SUMMARY

[0007] Based on the above problems existing in the prior art, the application provides a multi-channel parallel data acquisition system based on FPGA and a post-filtering processing method, which can realize high-precision, multi-channel AD data acquisition and real-time digital filtering based on FPGA, and is mainly used for high-speed synchronous acquisition, high-precision quantization and real-time filtering processing of multi-channel differential analog signals, especially intermediate frequency signals.

[0008] The technical scheme adopted by the application to solve the technical problems is: a multi-channel parallel data acquisition system based on FPGA, comprising a front-end conditioning board, an ADC conversion module and a post-stage FIR band-pass filter, the front-end conditioning board, the ADC conversion module and the post-stage FIR band-pass filter are sequentially and communicatively connected, further comprising an FPGA master control chip, an RC low-pass filter is arranged on an analog signal input interface of the ADC conversion module, the ADC conversion module adopts synchronous work of three LTC2325-16 chips, a CNV pin of each LTC2325-16 chip is used for conversion of a start signal and a precise SPI acquisition control timing is provided by a state machine design of the FPGA, a SCK pin is used for a serial data clock and is generated and output to the ADC chip by the FPGA; an SDO pin is used for ADC serial conversion result data output; and a CLKOUT pin is used for a skew matching clock output by the ADC chip and is used for latching SDO output at a receiving end.

[0009] As a preferred, the LTC2325-16 chip further comprises an NC pin, a DNC pin, an AINI pin, an EF pin, an SDR# / DDR pin, a CMOS# / LVDS pin, a GND pin, a VDD pin, an OVDD pin, a CNV# pin and a CLKOUTEN# pin, wherein the NC pin and the DNC pin are both suspended, the GND pin, the SDR# / DDR pin, the CMOS# / LVDS pin and the CLKOUTEN# pin are all grounded, the AINI pin is divided into four paths, and an RC low-pass filter is arranged on each path, and the REF path comprises REF, REFOUT1, REFOUT2, REFOUT3 and REFOUT4, which are all grounded through capacitors.

[0010] As a preferred, the FPGA master control chip comprises an SPI interface, a state machine controller, an ADC data shift register, a data buffer and a FIR band-pass filter which are sequentially connected, the state machine controller is used for generating a precise timing to control the LTC2325-16 ADC chip, and the states of the state machine controller include IDLE (idle), ACQUIRE (waiting for acquisition), CONVERT (starting conversion) and STORE_DATA (storing data).

[0011] The technical solution adopted by this application to solve its technical problem is: a post-filtering processing method for a multi-channel parallel data acquisition system based on FPGA. After the multi-channel analog signals pass through the front-end conditioning circuit, they are sent to the ADC conversion module. Parallel data acquisition is adopted: the multi-channel differential analog signals are synchronously converted into digital signals by each ADC chip in the ADC conversion module. The FPGA generates precise and synchronous acquisition control timing for each ADC channel. After the digital signals enter the FPGA, they are preprocessed by shift registers to perform parallel data alignment and latching. The process is controlled by the state machine inside the FPGA through timing. The ADC data read by the FPGA through data preprocessing and buffering is shifted and then stored in a dedicated high-speed cache FIFO within the FPGA. The data in the buffer is continuously fed into a configurable FIR filter implemented in FPGA for bandpass filtering. The filter coefficients are designed and preloaded by MATLAB.

[0012] The beneficial effects of the present invention are: the FPGA-based multi-channel parallel data acquisition system and post-filtering method of the present invention provide an FPGA-based data acquisition and processing solution that can achieve high-speed synchronous acquisition of multiple differential signals, low latency and flexible configurable real-time filtering, high resource utilization and controllable cost. Attached Figure Description

[0013] Figure 1 This is an overall block diagram of the multi-channel parallel data acquisition and post-filtering processing system of the present invention; Figure 2 This is a schematic diagram of a single ADC conversion module of the present invention; Figure 3 This is the front-end circuit of the ADC chip of the present invention; Figure 4 This is a flowchart of the FPGA internal process of the present invention; Figure 5 This is the timing diagram of the LTC2325-16 of the present invention; Figure 6 This is a design diagram of the bandpass filter coefficients of the present invention; Figure 7 Observation chart of raw data for AD channel 1 Figure 8 Timing observation diagram of ADC drive; Figure 9 This is a comparison chart of the data before and after filtering. Detailed Implementation

[0014] The FPGA-based multi-channel parallel data acquisition system and post-filtering method of the present invention can realize high-speed synchronous acquisition of multiple differential signals, low latency and flexible configurable real-time filtering, with high resource utilization and controllable cost.

[0015] The continuous development of high-speed data acquisition is driving the advancement of digital receiving technology. Higher sampling rates require subsequent signal processing units to have higher real-time performance. Commonly used acquisition and processing chips are Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). However, due to their superior parallelism, computing power, and ultra-high throughput, FPGAs have become the preferred processing devices for high-speed acquisition. This design uses an FPGA as the signal processing device for acquisition to implement multi-channel signal preprocessing, which has the advantages of strong computing power and high real-time performance.

[0016] High sampling rate and high parallelism: By adopting an architecture of multiple high-performance ADCs (LTC2325-16) working in parallel and leveraging the parallel data processing advantages of FPGA, this invention can design independent parallel control timing for multiple ADCs, realize true synchronous acquisition of 12 differential signals, avoid the inter-channel delay caused by traditional multiplexers, maximize the performance of high-speed ADC chips, and avoid the rate bottleneck caused by traditional MCU serial acquisition.

[0017] Optimized system control and reliability: The FPGA program is written using a state machine, which optimizes the system timing control. The state machine can clearly and reliably describe the timing relationships of processes such as ADC sampling control and data latching, ensuring that each operation step is performed under precise clock control, thereby improving the stability and reliability of the system.

[0018] Exceptional real-time performance and low latency: By directly calling the FIR IP core within the FPGA for digital filtering, the filtering logic is tightly integrated with the data acquisition process, achieving hardware-level pipelined processing. This processing method has extremely low latency, meeting the demands of applications with stringent real-time requirements, and is far superior to software filtering solutions running on the CPU.

[0019] Flexible configurable filtering: By pre-generating filter coefficients (MATLAB generates .coe files) and loading them into the FIR IP core, the system's filtering characteristics (such as center frequency and bandwidth) are easily reconfigured. This allows the system to adapt to different application requirements without changing the hardware, thus improving its flexibility and versatility.

[0020] High precision and high reliability: The use of the LTC2325-16 16-bit high-precision ADC chip, combined with differential input, effectively suppresses common-mode noise, improving the signal-to-noise ratio (SNR) of signal acquisition and the system's anti-interference capability. The logic processing within the FPGA is also more deterministic and stable compared to software processing.

[0021] The main research content of this invention is the system design of multi-channel parallel data acquisition and post-filtering processing based on FPGA. The core principle of this system is to use FPGA to build a highly parallel hardware processing pipeline to complete the entire process from multi-channel differential analog signal input to filtered digital signal output. The system workflow is as follows: Figure 1 As shown.

[0022] Signal conditioning and conversion: After passing through the front-end conditioning circuit, multiple analog signals are sent to the high-performance differential ADC chip; Parallel data acquisition: Multiple differential analog signals are synchronously converted into digital signals by multiple ADCs. The FPGA internally generates precise and synchronous acquisition control timing (SPI interface timing) for each ADC channel. After the digital signals enter the FPGA, they undergo preprocessing such as shift registers for parallel data alignment and latching. The entire process is precisely controlled by the FPGA's internal state machine to ensure correct timing.

[0023] Data preprocessing and caching: The ADC data read is shifted and stored in the FPGA and then stored in a dedicated high-speed cache FIFO.

[0024] Real-time digital filtering: Data from the buffer is continuously fed into a configurable FIR filter (FIR IP core) implemented on the FPGA for bandpass filtering (8-10kHz). The filter coefficients are designed and preloaded using MATLAB.

[0025] The entire data flow runs in a pipelined manner inside the FPGA, enabling parallel execution of acquisition, buffering, and filtering, thus ensuring low latency and high throughput of the system.

[0026] (1) ADC Conversion Module: The AD chip used is the LTC2325-16, which can simultaneously acquire and convert four analog signals. Using multiple LTC2325-16 chips can acquire and convert multiple signals, effectively improving the AD conversion efficiency. The LTC2325-16 can also output four data conversion results simultaneously. Combined with the FPGA's internal RAM, it can realize the buffering and parallel reading of conversion results from multiple channels. The schematic diagram of the ADC conversion module is shown below. Figure 2 As shown.

[0027] The AD conversion unit uses three LTC2325-16 chips working simultaneously. This chip is a 16-bit successive approximation (SAR) analog-to-digital converter chip produced by Analog Devices (ADI), with a maximum sampling rate of 5 Msps.

[0028] (2) Analog signal input interface: As a fully differential input ADC, the LTC2325-16 must first ensure that the input signal of the analog-to-digital converter is a differential signal. Therefore, the front-end design of this high-speed ADC should be as follows: Figure 3The circuit shown.

[0029] This circuit uses RA1 and RA2 to form a voltage divider network, which distributes the analog single-ended signal output from the conditioning board evenly, thus generating differential signals of equal magnitude and opposite polarity at the output. Simultaneously, the capacitors and resistors together form an RC low-pass filter to attenuate high-frequency noise and unwanted signal components, thereby improving the signal-to-noise ratio.

[0030] (3) FPGA main control chip: As the core of system control and processing, this system selects the XC7Z020CLG400-2 chip from Xilinx's Zynq-7000 series. This chip has sufficient logic resources, block RAM and DSP slice that can efficiently implement multiplier accumulation operation.

[0031] (4) Hardware connection between FPGA and ADC chip: LTC2325-16 adopts SPI interface; CNV: conversion start signal, controlled by FPGA; SCK: serial data clock, generated by FPGA and output to ADC chip; SDO: ADC serial conversion result data output; CLKOUT: skew matching clock output by ADC chip, used to latch SDO output at the receiving end.

[0032] The core of this invention is the digital logic design within the FPGA, and its internal implementation flowchart is as follows: Figure 4 As shown, it mainly includes the following modules: ADC Interface Control State Machine: This module generates precise timing to control the LTC2325-16 ADC. The states of this state machine include IDLE, ACQUIRE, CONVERT, and STORE_DATA. Refer to the LTC2325-16 timing diagram for internal logic principles. Figure 5 As shown.

[0033] It can be seen that the key to the design lies in the calculation of timing parameters. To achieve a sampling rate of up to 5Msps, the high-level time of CNV must be compressed as much as possible. Here, we set the high-level time to 30ns, so the conversion time is 170ns. In the program, the state machine uses a 200MHz clock to precisely control the ADC timing. We define two parameter variables, cnv_h and cnv_l, and use parametric design to control the high and low levels of CNV.

[0034] Next, a variable `bit_count` is set up for counting. In ACQUIRE state, `bit_count` is compared with the value of `cnv_h`, and the CNV signal is pulled high when the condition is met. In CONVERT state, `bit_count` is compared with the value of `cnv_l`, and the CNV signal is pulled low when the condition is met, while the serial-to-parallel data is stored.

[0035] Additionally, in CONVERT state, the SCK signal is inverted with each rising edge of a 200MHz clock cycle until bit_count reaches 32. The resulting SCK signal is 100MHz.

[0036] Data Shift and Synchronization Registers: The serial data read needs to be shifted and stored within the FPGA to form correct parallel data. First, a 16-bit register variable SDR needs to be defined to store temporary values ​​during serial-to-parallel conversion operations.

[0037] For high-throughput ADCs, using CLKOUT to capture the SDO output can relax the timing requirements of the receiver. Therefore, we do not use SCK to latch the acquired data, but directly perform SDO shift register on the rising edge of CLKOUT. After 16 CLKOUT clock cycles, the value of SDR is the digital value corresponding to each sampling point.

[0038] Data buffer: It uses the Block Memory resources inside the FPGA to generate an asynchronous FIFO. Its main function is to balance the burstiness of the data flow, so that the subsequent filtering modules can continuously acquire data.

[0039] Configurable FIR filter IP core: This design uses MATLAB's FDA tool to calculate the FIR filter coefficients that meet the performance requirements, such as... Figure 6 As shown. Export the designed coefficients as a .coe file, and then import this file into the FIR Compiler IP core in the FPGA development environment (Vivado).

[0040] This FIR bandpass filter allows signals in the frequency range of 8-12kHz to pass through, with a stopband attenuation of -40dB and a sampling frequency of 1MHz. It can effectively filter out various high-frequency noises and signals that are crosstalked into the acquisition board by the conditioning circuit.

[0041] Furthermore, when floating-point coefficients are converted to fixed-point numbers, normalization is typically performed, which results in an inherent gain of less than 1, causing attenuation of the filtered signal amplitude. Therefore, an additional gain compensation module is added after filtering to ensure that the signal amplitude remains consistent before and after filtering.

[0042] ILA Verification Scheme Design: In the actual verification of this invention, the integrated logic analyzer built into the Vivado development environment is used to capture and observe the signals inside the FPGA in real time. The ILA IP core sampling clock is 200MHz, and the following two sets of probe signals are mainly configured: (1) AD raw data observation point: connected to the output of the ADC data interface control state machine, used to capture the 16-bit parallel raw data after conversion by LTC2325-16. This observation point is used to verify the correctness of the ADC drive timing, the accuracy of data synchronization, and the quality of the raw signal.

[0043] By testing the output signal of a 100mV, 10kHz sine wave input to a conditioning board, the raw data of AD channel 1 captured by ila is as follows: Figure 7 As shown, the original signal frequency is 10kHz, which matches the input signal frequency, but it contains out-of-band noise and is of poor quality. The ADC drive timing observation diagram is shown below. Figure 8 As shown, it can be observed that the ADC driving logic strictly follows the timing specifications of the LTC2325-16 chip, achieving error-free data acquisition.

[0044] (2) Filtered data observation point: Connected to the data output port of the FIR filter IP core, used to capture the data after 8-10kHz bandpass filtering. This observation point is used to visually evaluate the performance of the filter, including the retention of in-band signals and the suppression of out-of-band noise.

[0045] The comparison graph of the filtered data and the original signal before filtering is shown below. Figure 9 As shown, fir_out is the filtered data, and fir_GC is the data after gain compensation. The amplitude of fir_GC is basically the same as the original data. At the same time, it can be intuitively observed that the interference components in the signal are significantly attenuated, the waveform is smoother, and the filtering delay is low, about 5us.

[0046] The above embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

Claims

1. A multi-channel parallel data acquisition system based on FPGA, comprising a front-end conditioning board, an ADC conversion module, and a post-stage FIR bandpass filter, wherein the front-end conditioning board, the ADC conversion module, and the post-stage FIR bandpass filter are sequentially and communicatively connected, characterized in that, It also includes an RC low-pass filter on the analog signal input interface of the FPGA main control chip and the ADC conversion module. The ADC conversion module uses three LTC2325-16 chips to work synchronously. The CNV pin of each LTC2325-16 chip is used to convert the start signal and the FPGA uses a state machine design to provide accurate SPI acquisition control timing. The SCK pin is used for the serial data clock and is generated by the FPGA and output to the ADC chip. The SDO pin is used for the ADC serial conversion result data output. The CLKOUT pin is used for the skew matching clock of the ADC chip output and is used to latch the SDO output at the receiving end.

2. The FPGA-based multi-channel parallel data acquisition system as described in claim 1, characterized in that, The LTC2325-16 chip also includes NC pin, DNC pin, AINI pin, EF pin, SDR# / DDR pin, CMOS# / LVDS pin, GND pin, VDD pin, OVDD pin, CNV# pin, and CLKOUTEN# pin. Among them, the NC pin and DNC pin are floating, while the GND pin, SDR# / DDR pin, CMOS# / LVDS pin, and CLKOUTEN# pin are grounded. The AINI pin is divided into four paths, each with an RC low-pass filter. The REF path, including REF, REFOUT1, REFOUT2, REFOUT3, and REFOUT4, is grounded through a capacitor.

3. The FPGA-based multi-channel parallel data acquisition system as described in claim 1, characterized in that, The FPGA main control chip includes an SPI interface, a state machine controller, an ADC data shift register, a data buffer, and an FIR bandpass filter connected in sequence. The state machine controller is used to generate precise timing to control the LTC2325-16 ADC chip. The states of the state machine controller include IDLE, ACQUIRE, CONVERT, and STORE_DATA.

4. A post-filtering method for a multi-channel parallel data acquisition system based on FPGA, wherein multiple analog signals are sent to an ADC conversion module after passing through a front-end conditioning circuit; characterized in that, Parallel data acquisition is adopted: multiple differential analog signals are synchronously converted into digital signals by the individual ADC chips in the ADC conversion module. The FPGA generates precise and synchronous acquisition control timing for each ADC channel. After the digital signal enters the FPGA, it undergoes preprocessing by shift registers to align and latch the parallel data. The process is controlled by the state machine inside the FPGA through timing. The ADC data read by the FPGA through data preprocessing and buffering is shifted and then stored in a dedicated high-speed cache FIFO within the FPGA. The data in the buffer is continuously fed into a configurable FIR filter implemented in FPGA for bandpass filtering. The filter coefficients are designed and preloaded by MATLAB.

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