Time delay testing device and method for optical fiber channel
By complementing the design of the BeiDou/GPS time synchronization module and the temperature-controlled crystal oscillator module and collaborating with the SOC processing module, the automation and accuracy of fiber optic channel delay testing have been achieved. This solves the problems of insufficient testing complexity and accuracy in existing technologies, adapts to the mobile testing needs of different substations, and improves the reliability and efficiency of power grid operation.
Patent Information
- Application Number
- CN202511706638.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-20
- Publication Date
- 2026-02-10
AI Technical Summary
Existing technologies for longitudinal protection fiber optic channel delay testing suffer from cumbersome operation, poor compatibility, insufficient measurement accuracy, and inadequate adaptability. They cannot meet the requirements for microsecond-level delay testing and lack a clock guarantee mechanism in case of BeiDou/GPS signal loss, leading to easy interruption of the testing process and decreased data reliability.
The system adopts a complementary design of Beidou/GPS time synchronization module and temperature-controlled crystal oscillator module, combined with the division of labor and cooperation of SOC processing module, to realize the automation of the test process. Fiber optic channel delay test is performed through handheld device to ensure that the delay test accuracy is improved to the micrometer level, which is suitable for mobile test scenarios in different substations.
It improves the accuracy and efficiency of delay testing for longitudinal protection fiber optic channels, reduces manual operation, ensures the reliability and accuracy of test results, and supports the safe and stable operation of the power grid.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of power automation testing, and in particular to a time delay testing device and testing method for a fiber channel. BACKGROUND
[0002] With the development of power systems in the direction of high voltage, large capacity and long distance, the transmission time delay stability of the pilot protection fiber channel as the core communication carrier for fast removal of line faults directly determines the action reliability of the pilot protection device.
[0003] The current power industry mainly relies on two ways for time delay testing of the pilot protection fiber channel: one is to use a general communication tester, which needs to additionally configure a special interface module and protocol analysis software suitable for the power system, and the operation process is complicated and has poor compatibility; the other is to rely on manual on-site test environment construction, and manually record the signal transmission time through an oscilloscope, a stopwatch and other tools, which not only has low efficiency, but also is prone to measurement accuracy deficiency (error is mostly in the order of milliseconds) due to human operation errors and unsynchronized time at both ends, and cannot meet the needs of the pilot protection device for microsecond level time delay testing.
[0004] In addition, most of the existing test tools are fixed equipment, which are difficult to adapt to mobile testing scenarios in different substations, and lack of clock protection mechanism when the Beidou / GPS signal is lost, which leads to interruption of the testing process and reduction of data reliability, and cannot effectively support the safe and stable operation of the power grid. SUMMARY
[0005] The present application provides a time delay testing device and testing method for a fiber channel, which ensures the accuracy of time mark recording by complementary design of a Beidou / GPS time synchronization module and a constant temperature crystal oscillator module, and improves the time delay testing accuracy to the microsecond level; the SOC processing module realizes automation of the testing process through division of labor and cooperation of the PL side and the double ARM processor, and does not need manual intervention for signal transmission and data calculation, thereby solving the problems of insufficient testing accuracy, complicated operation and low efficiency of the existing testing methods.
[0006] The present application is implemented by the following technical solutions:
[0007] In a first aspect, the present application provides a time delay testing device for a fiber channel, which comprises a handheld casing and an internal hardware system, and the internal hardware system comprises:
[0008] a time synchronization module for receiving Beidou or GPS satellite navigation signals and providing a clock synchronization signal for the device;
[0009] a constant temperature crystal oscillator module for providing a local clock signal for the device when the time synchronization module loses the Beidou or GPS satellite navigation signals;
[0010] An optical fiber interface module is configured to connect an optical fiber channel to be tested, and transmit a time delay test signal to the optical fiber channel or receive the time delay test signal from the optical fiber channel.
[0011] The SOC processing module includes a PL side and a PS side, the PS side is integrated with a first ARM processor and a second ARM processor, the PL side is provided with programmable logic resources, and the PL side and the PS side are interconnected through an AXI high-speed bus.
[0012] The PL side is configured to communicate with the optical fiber interface module, to realize encoding transmission and receiving decoding of the time delay test signal, and mark time stamps at a transmission completion time and a receiving completion time.
[0013] The first ARM processor runs a clock control algorithm and a test flow control algorithm, to synchronize a local time according to a signal of the time module or the constant temperature crystal oscillator module, and control the PL side to initiate the time delay test; and the second ARM processor runs a man-machine interaction program, to receive a test instruction and feed back a test result.
[0014] Further, the optical fiber channel to be tested is a longitudinal protection optical fiber channel.
[0015] The optical fiber interface module adopts a standard longitudinal protection optical fiber 2M interface, connects the optical fiber channel to be tested through an optical fiber 2M communication port of an optical-electric conversion multiplexing interface device matched with the longitudinal protection device.
[0016] Further, the SOC processing module adopts ZYNQ-7000 as a core chip, adopts an asymmetric AMP operation mode, and the first ARM processor and the second ARM processor independently run different operating systems or bare machine application programs.
[0017] Further, the device further includes a touch liquid crystal screen module, to display a man-machine interaction interface and a test result.
[0018] Further, the PL side includes an encoding transmission module, a decoding receiving module, a time stamp module and a control module.
[0019] The encoding transmission module is connected with a signal transmitting port of the optical fiber interface module, to perform encoding processing and transmitting processing of the time delay test signal.
[0020] The decoding receiving module is connected with a signal receiving port of the optical fiber interface module, to perform receiving processing and decoding processing of the time delay test signal.
[0021] The timestamp module is connected with the encoding sending module, the decoding receiving module and the control module respectively, and is used for marking a sending timestamp at a time when the encoding sending module completes sending of the delay test signal, and marking a receiving timestamp at a time when the decoding receiving module completes receiving of the delay test signal, and sending to the control module;
[0022] The control module communicates with the first ARM processor through the AXI interconnection module, receives a test instruction issued by the first ARM processor, and controls the encoding sending module, the decoding receiving module and the timestamp module to complete a test process.
[0023] Further, the first ARM processor is further used for receiving a test result returned by the control module, and writing the test result into a shared address.
[0024] The second ARM processor is further used for reading the test result in the shared address, and counting the test result and generating a test report.
[0025] Further, the optical fiber interface module comprises filter capacitors C1-C8, patch resistors R1-R3, patch inductors L1-L2 and an optical fiber interface integrated module F1.
[0026] The filter capacitors C1-C4 and the patch inductor L1 constitute a first π-type filter circuit, an output of which is connected with a VccR pin of the optical fiber interface integrated module F1, and is used for power filtering on a receiving side of the F1.
[0027] The filter capacitors C5-C8 and the patch inductor L2 constitute a second π-type filter circuit, an output of which is connected with a VccT pin of the optical fiber interface integrated module F1, and is used for power filtering on a sending side of the F1.
[0028] One side of the patch resistors R1, R2 and R3 is connected with a VCC3V3 power supply, and the other side is connected with an SCL pin, a fourth pin (LOS / RSSI / SD pin) and an SDA pin of the optical fiber interface integrated module F1 respectively, and is used for voltage pull-up.
[0029] The SCL pin and the SDA pin of the optical fiber interface integrated module F1 constitute an I2C communication mode, and are connected with the SOC processing module, and the fourth pin (LOS / RSSI / SD pin) of the optical fiber interface integrated module F1 is used for detecting whether external optical fiber line connection is normal.
[0030] Further, the device further comprises a power supply module, which is used for supplying power for the internal hardware system.
[0031] In a second aspect of the present application, a time delay test method of an optical fiber channel is provided, comprising the following steps:
[0032] S1, respectively deploying a device as claimed in any one of claims 1-8 on both sides of the fiber channel to be tested, powering on the devices on both sides, starting the SOC processing module of the device, initializing and loading the underlying driver, and running the man-machine interaction program;
[0033] S2, waiting for the devices on both sides to complete synchronization through the respective time synchronization modules;
[0034] S3, configuring the devices on both sides with the relevant parameters of the fiber channel to be tested;
[0035] S4, taking one of the devices as the sending side device, controlling the sending side device to initiate the test process, outputting a first optical digital measurement message, sending it to the receiving side device through the fiber channel to be tested, and recording a first sending time T0, the receiving side device recording a first receiving time T1 after receiving the first optical digital measurement message, then initiating the test process, outputting a second optical digital measurement message to the sending side device, and recording a second sending time T2, the sending side device recording a second receiving time T3 after receiving the second optical digital measurement message, completing a time delay test process;
[0036] S5, the devices on both sides respectively process and calculate the recorded time stamps to obtain the sending time delay, receiving time delay and time delay difference value of the fiber channel to be tested, and generate a test report after the set test is completed.
[0037] Further, the sending time delay AT1=T1-T0, the receiving time delay AT2=T3-T2, and the time delay difference AT=AT1-AT2.
[0038] Compared with the prior art, the present application has the following advantages and beneficial effects:
[0039] The handheld shell design can be repeatedly used for testing the time delay of the pilot protection optical fiber channel in different substations, so as to complete the test of the time delay difference with as few manual interventions as possible;
[0040] The test device adopts a general optical fiber interface for pilot protection, can seamlessly access the optical fiber 2M communication port of the optical-electric conversion multiplexing interface device matched with the pilot protection device, and can also simulate the sending of communication messages by the line protection device to automatically and completely test the time delay difference of the entire optical fiber link;
[0041] The Beidou / GPS satellite navigation system is used as a time reference to ensure the time consistency of the test devices at the two station ends of the same fiber channel to be tested, and the real-time performance of the built-in software measurement algorithm and FPGA logic programming, so that the time delay difference of the channel can be accurately tested, which is convenient for acceptance personnel and maintenance personnel to find problems and shorten the problem solving period. BRIEF DESCRIPTION OF DRAWINGS
[0042] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:
[0043] Figure 1 is a schematic diagram of the internal hardware system structure of a time delay test device according to an embodiment of the present application;
[0044] Figure 2 is a schematic diagram of the application scenario of a time delay test device according to an embodiment of the present application;
[0045] Figure 3 is a schematic diagram of the overall handheld casing of a time delay test device according to an embodiment of the present application;
[0046] Figure 4 is a schematic diagram of the internal structure of a ZYNQSOC processing module according to an embodiment of the present application;
[0047] Figure 5 is a schematic diagram of the circuit principle of a 2M optical fiber interface according to an embodiment of the present application;
[0048] Figure 6 is a schematic diagram of a time delay test method according to an embodiment of the present application. DETAILED DESCRIPTION
[0049] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will further describe the present application in combination with the embodiments and drawings, the exemplary embodiments of the present application and the description thereof are only used to explain the present application, and should not be considered as a limitation to the present application.
[0050] It should be noted that the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above drawings are intended to cover the non-exclusive inclusion, for example, a process, method, system, product or device containing a series of steps or units does not have to be limited to or inherent to other steps or units.
[0051] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the present application. As used in this description, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments belong. The terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0052] Embodiments of the present application provide a kind of optical fiber channel delay test device, it is suitable for transmission delay test of longitudinal protection optical fiber channel in power system, can greatly reduce the complexity of longitudinal protection optical fiber channel delay test, improve work efficiency, reduce the time and cost of manual operation, improve the accuracy and reliability of test result, reduce the economic loss caused by line longitudinal protection misoperation or refusal of operation due to optical fiber channel transmission delay anomaly, to more effectively support power grid safe, stable operation.
[0053] The delay test device of the present application can be configured as a handheld electronic device, including a handheld housing and an internal hardware system. Referring to Figure 1 As shown, the internal hardware system is mainly composed of a time module 101, a constant temperature crystal oscillator module 102, an optical fiber interface module 103 and a SOC processing module 104.
[0054] The time module 101 uses a high-precision time chip, receives Beidou or GPS satellite navigation signals through an antenna, and provides a clock synchronization signal for the device. The time module can have an accuracy of up to 50ns, effectively providing accurate time protection for the delay test device.
[0055] The constant temperature crystal oscillator module 102 is used to provide a local clock signal for the delay test device when the time module loses the Beidou or GPS satellite navigation signal.
[0056] The delay test device is connected to the optical fiber channel to be tested through the optical fiber interface module 103 (including the receiving and transmitting interfaces), so as to send delay test signals to the optical fiber channel to be tested or receive delay test signals from the optical fiber channel through the optical fiber interface module.
[0057] As Figure 2An application diagram of the time delay testing device is shown. During testing, one testing device is arranged at each end of the optical fiber channel to be tested. A signal is transmitted through one end and received through the other end. The transmission time delay can be calculated according to the transmission and reception time. It can be understood that the testing object of the device can be a longitudinal protection optical fiber channel or other optical fiber channels. The optical fiber interface module is replaced with an interface matched with the type of optical fiber to be tested, and a matching test signal is configured. Then, the device can be connected to the optical fiber to be tested and complete the time delay test.
[0058] When the time delay testing device is applied to the testing of a longitudinal protection optical fiber channel, the optical fiber interface module adopts a standard longitudinal protection optical fiber 2M interface. The optical fiber 2M communication port of the optical-electric conversion multiplexing interface device matched with the longitudinal protection device is accessed to realize the connection with the optical fiber channel to be tested.
[0059] The SOC processing module 104 is a control center for realizing automatic testing and is electrically connected with the time module 101, the constant temperature crystal oscillator module 102 and the optical fiber interface module 103. The SOC processing module 104 is composed of a core processing chip and a PL side and a PS side. The PS side is integrated with a dual-core ARM processor: a first ARM processor (ARM1) and a second ARM processor (ARM2), which are hereinafter referred to as ARM1 and ARM2. The PL side has rich programmable logic resources. The PL side and the PS side are interconnected through an AXI high-speed bus to realize high-bandwidth and low-delay information interaction, so as to realize different functions by means of the respective advantages of the FPGA and the ARM.
[0060] The PL side realizes the encoding and sending of the time delay testing signal and the decoding of the received code and the time marking at the time of completing the sending and the time of completing the receiving based on VHDL hardware coding. That is, the time delay testing signal is encoded, sent to one end of the optical fiber channel to be tested through the optical fiber interface module, and the time stamp is marked at the time of completing the sending action. When the encoded time delay testing signal is received from one end of the optical fiber channel to be tested, the time stamp is marked at the time of completing the receiving action.
[0061] The PL side receives the testing instruction issued by the PS side through the AXI high-speed bus, completes the testing process according to the configured time delay testing program, obtains the testing result data (such as the time stamp), and sends the testing result data to the PS side through the AXI high-speed bus.
[0062] The dual-core ARM processor of the PS side adopts an asymmetric AMP running mode. In the asymmetric AMP running mode, the two cores can independently run different operating systems or bare machine application programs. The data interaction is realized through an agreed shared address.
[0063] The ARM1 on the PS side runs clock control algorithm and test flow control algorithm, which is used to synchronize the local time according to the signal of the time module 101 or the constant temperature crystal oscillator module 102, issue test instruction to control the PL side to initiate the time delay test flow, receive the test result data fed back by the PL side, and store the test result data in the shared address agreed by the ARM1. The second ARM processor runs the man-machine interaction program, which is used to receive the test instruction of the user and forward the test instruction to the ARM1, and extract the test result data from the shared address agreed by the ARM1 and feed back the test result to the user.
[0064] Further, the time delay test device further comprises a touch liquid crystal screen module. As shown in Figure 3 The touch liquid crystal screen module comprises a touch liquid crystal display screen 1 arranged on one side of the casing and connected with the SOC processing module 104 inside, and the user realizes man-machine interaction with the internal hardware system through the touch liquid crystal display screen.
[0065] The ARM2 on the PS side runs the embedded Linux system and the man-machine interface software, and displays the man-machine interface and the test result on the touch liquid crystal display screen. The ARM1 runs the bare machine application program, realizes the clock control algorithm and the test flow control algorithm, and controls the various components of the internal hardware system to orderly complete the time delay difference measurement flow.
[0066] Specifically, the ARM1 realizes synchronization of the local time of the test device by receiving the time synchronization information output by the time synchronization module, and realizes the integrity test of the time delay difference value of the optical fiber channel by controlling the time delay difference value measurement task module written based on the VHDL hardware programming language on the PL side, and writes the test return result into the shared address agreed between the dual-core ARMs. The ARM2 reads the time delay test result written by the ARM1 in the shared address and displays the time delay test result on the man-machine interface. After the set test is completed, the ARM2 will automatically count the test result and generate a test report, which is convenient for the on-site operation and maintenance personnel to check and accept.
[0067] Further, the touch liquid crystal screen adopts an industrial-grade 7-inch high-resolution display screen, which is convenient for displaying the operation interface and the test result of the time delay test in high definition. At the same time, the liquid crystal screen adopts a common USB communication protocol to be connected with the ARM2, which reduces the development difficulty of the developers.
[0068] Further, the time delay test device further comprises a power module for supplying power to each part of the internal hardware system.
[0069] Further, in combination with Figure 3 The handheld casing part further comprises a power interface 2, a power switch 3, a power indicator 4, a USB interface 5, a Beidou / GPS antenna interface 6, an Ethernet port 7, an Ethernet port 8, an optical fiber interface sending port 9, and an optical fiber interface receiving port 10 and other matching components.
[0070] In an embodiment, the SOC processing module adopts ZYNQ-7000 as a core chip, and an internal structure of a ZYNQ SOC processing module is as shown in Figure 4 An encoding and sending module F2M_TX, a decoding and receiving module F2M_RX, a time stamp module TimeStamp and a control module F2M_CTRL are designed at the PL end in the ZYNQ SOC host.
[0071] The encoding and sending module F2M_TX is connected with a signal sending port of the fiber interface module, and is used for encoding processing and sending processing of the delay test signal; the decoding and receiving module F2M_RX is connected with a signal receiving port of the fiber interface module, and is used for receiving processing and decoding processing of the delay test signal; the time stamp module TimeStamp is connected with the encoding and sending module F2M_TX, the decoding and receiving module F2M_RX and the control module F2M_CTRL respectively, and is used for marking a sending time stamp at a moment when the encoding and sending module F2M_TX completes sending of the delay test signal, and marking a receiving time stamp at a moment when the decoding and receiving module F2M_RX completes receiving of the delay test signal, and sending to the control module F2M_CTRL.
[0072] The control module F2M_CTRL communicates with the PS side ARM1 through an AXI interconnection module AXI_Interconnect, is used for receiving a test instruction issued by the ARM1, and coordinates to control the encoding and sending module F2M_TX, the decoding and receiving module F2M_RX and the time stamp module TimeStamp to complete a test flow. The AXI Interconnect is used as an interconnection hub to complete signal transmission between the PL side module and the PS side ARM1, and jointly constructs a module connection architecture in the PL.
[0073] The specific connection relationship of each module is as follows:
[0074] The TX output port of the F2M_TX module is connected with a 2M optical port signal sending port, and the F2M_TX_done output port is connected with an input port of the TimeStamp module;
[0075] The RX input port of the F2M_RX module is connected with a 2M optical port signal receiving port, the F2M_RX_done output port is connected with an input port of the TimeStamp module, and the F2M_RX_message output port is connected with an input port of the F2M_CTRL module;
[0076] The output ports tx_ts and rx_ts of the TimeStamp module are connected with input ports of the F2M_CTRL module respectively;
[0077] F2M_CTRL module: its CTRL_TX_start port is connected with the input port of F2M_TX module; F2M_CTRL module realizes signal interaction with ARM1 on PS side through AXI_Interconnect.
[0078] The accompanying drawings are incorporated in and constitute a part of this specification and will be understood by those skilled in the art to explain the principles of the application and the actual implementation. Figure 4 The test flow specifically executed by the PS side and the PL side includes:
[0079] S1, ARM2 receives the test instruction of the user through human-computer interaction (touch liquid crystal screen), and writes the decoded instruction into the specified address area of OCM shared memory;
[0080] S2, ARM1 polls the new instruction in OCM shared memory, analyzes the new instruction, generates the control instruction recognizable by the PL side, and sends the command to F2M_CTRL module on the PL side through AXI_Interconnect interconnection module;
[0081] S3, after receiving the instruction sent by ARM1, F2M_CTRL module on the PL side triggers CTRL_TX_start signal to start F2M_TX module to send the preset optical port encoding signal; after the sending is completed, F2M_TX module generates F2M_TX_done completion signal, and triggers TimeStamp module to record the sending timestamp tx_ts;
[0082] S4, F2M_RX module on the PL side receives 2M optical port signal and analyzes it, extracts the valid data frame F2M_RX_message; after the analysis is completed, F2M_RX_done signal is generated, TimeStamp module is triggered to record the receiving timestamp rx_ts; at the same time, F2M_RX_message received is sent to F2M_CTRL module;
[0083] S5, after receiving F2M_RX_message, rx_ts and tx_ts information, F2M_CTRL module integrates them to generate IRQ interrupt signal to inform ARM1 to read the results.
[0084] S6, ARM1 responds to IRQ interrupt, reads F2M_RX_message, rx_ts and tx_ts data in F2M_CTRL module through AXIInterconnect interconnection module;
[0085] S7, after processing F2M_RX_message, rx_ts and tx_ts information, ARM1 sends them to the specified address area of OCM shared memory; ARM2 reads the result data in OCM shared memory through polling mode, and formats the result to output to the touch screen display.
[0086] Referring to Figure 5 , which shows a 2M fiber interface circuit schematic design of the application. The 2M fiber interface circuit mainly includes filter capacitors C1-C8, chip resistors R1-R3, chip inductors L1-L2, and a fiber interface integrated module F1. The filter capacitors C1-C4 and the chip inductor L1 constitute a first π-type filter circuit, the output of which is connected to the 5th pin (VccR) of F1, for power filtering for the receiving side of F1; the filter capacitors C5-C8 and the chip inductor L2 constitute a second π-type filter circuit, the output of which is connected to the 6th pin (VccT) of F1, for power filtering for the transmitting side of F1.
[0087] One side of the chip resistors R1, R2, and R3 is connected to the VCC3V3 power supply, and the other side is respectively connected to the 3rd pin (SCL), the 7th pin (SDA), and the 4th pin (LOS / RSSI / SD) of F1, for realizing voltage pull-up.
[0088] Among them, the 3rd pin (SCL) and the 7th pin (SDA) of F1 constitute an I2C communication mode and are connected to the SOC processing module, and the 4th pin (LOS / RSSI / SD) of F1 is used for detecting whether the external fiber line connection is normal.
[0089] The embodiment of the application also provides a time delay test method of a fiber channel, applied to the time delay test device. As Figure 6 shown, one time delay test device is respectively arranged at each of the transformer substation 1 and the transformer substation 2. T0 is a start time mark when the test device of the transformer substation 1 sends a test message, T1 is a receiving time mark when the test device of the transformer substation 2 receives the test message sent by the test device of the transformer substation 1, T2 is a sending time mark when the test device of the transformer substation 2 sends a response message, and T3 is a receiving time mark when the test device of the transformer substation 1 receives the response message sent by the test device of the transformer substation 2. The test method is specifically as follows:
[0090] S1, a high-performance fiber channel test system is built: one test device is respectively arranged on both sides of the fiber channel to be tested, the devices on both sides are powered on, the SOC processing module of the device is started, the bottom layer driver is initialized and loaded, the man-machine interaction program is automatically run, and the man-machine interaction interface is displayed through the liquid crystal screen connected to the PS side;
[0091] S2, the devices on both sides complete synchronization based on the Beidou / GPS time service system through the respective time synchronization modules;
[0092] S3, according to the model of the equipment to be tested on site, the related parameters of the equipment to be tested are configured for the devices on both sides;
[0093] S4, take one side (substation 1) device as the transmitting side device, control the transmitting side device to initiate the test process, output the first optical digital measurement message, send it to the receiving side (substation 2) device through the optical fiber channel to be tested, and record the first transmission time stamp T0. After receiving the first optical digital measurement message, the receiving side device records the first reception time stamp T1, and then initiates the test process, outputs the second optical digital measurement message to the transmitting side device, and records the second transmission time stamp T2. After receiving the second optical digital measurement message, the transmitting side device records the second reception time stamp T3, and completes one delay test process;
[0094] S5, the two devices process and calculate the recorded timestamps to obtain the transmit delay, receive delay and delay difference of the fiber optic channel under test. After the set test is completed, a test report is generated.
[0095] The testing device processes and calculates the received time stamps T0, T1, T2, and T3, where ΔT1 = T1 - T0 represents the transmit delay of the longitudinal protection fiber optic channel delay test, and ΔT2 = T3 - T2 represents the receive delay of the longitudinal protection fiber optic channel delay test. After calculating the individual delays of the transmit and receive channels, the difference between the transmit and receive delays of the longitudinal protection fiber optic channel is calculated by performing the calculation ΔT = ΔT1 - ΔT2. After the set test is completed, the testing device will automatically generate a test report for acceptance by on-site maintenance personnel.
[0096] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A delay testing device for fiber optic channels, characterized in that, The device includes a handheld casing and an internal hardware system, the internal hardware system comprising: The time synchronization module is used to receive BeiDou or GPS satellite navigation signals and provide clock synchronization signals for the device; A temperature-controlled crystal oscillator module is used to provide a local clock signal to the device when the time synchronization module loses the BeiDou or GPS satellite navigation signal; The fiber optic interface module is used to connect to the fiber optic channel to be tested, so as to send a delay test signal to the fiber optic channel or receive a delay test signal from the fiber optic channel. The SOC processing module includes a PL side and a PS side. The PS side integrates a first ARM processor and a second ARM processor. The PL side has programmable logic resources, and the PL side and the PS side are interconnected through an AXI high-speed bus. The PL side is configured to communicate with the optical fiber interface module to encode, transmit, receive, and decode the delay test signal, and to mark timestamps at the time of transmission completion and the time of reception completion. The first ARM processor runs a clock control algorithm and a test process control algorithm to synchronize the local time according to the signal from the time synchronization module or the thermostatic crystal oscillator module, and to control the PL side to initiate a time delay test; the second ARM processor runs a human-machine interaction program to receive test instructions and provide feedback on test results.
2. The delay testing apparatus for fiber optic channels according to claim 1, characterized in that, The fiber optic channel to be tested is a longitudinally protected fiber optic channel; The fiber optic interface module adopts a standard longitudinal protection fiber optic 2M interface. It connects to the fiber optic 2M communication port of the optoelectronic conversion multiplexing interface device that is matched with the longitudinal protection device to achieve the connection with the fiber optic channel to be tested.
3. The delay testing apparatus for fiber optic channels according to claim 1, characterized in that, The SOC processing module uses ZYNQ-7000 as the core chip and adopts an asymmetric AMP operating mode. The first ARM processor and the second ARM processor run different operating systems or bare-metal applications independently.
4. The delay testing apparatus for fiber optic channels according to claim 1, characterized in that, The device also includes a touch LCD module for displaying the human-computer interaction interface and test results.
5. The delay testing apparatus for fiber optic channels according to claim 1, characterized in that, The PL side includes an encoding and transmitting module, a decoding and receiving module, a timestamp module, and a control module; The encoding and transmitting module is connected to the signal transmission port of the optical fiber interface module and is used for encoding and transmitting the delay test signal. The decoding and receiving module is connected to the receiving signal port of the optical fiber interface module and is used for receiving, processing and decoding the time delay test signal. The timestamp module is connected to the encoding and transmitting module, the decoding and receiving module, and the control module, respectively, and is used to mark the transmission timestamp when the encoding and transmitting module completes the transmission of the delay test signal, and to mark the reception timestamp when the decoding and receiving module completes the reception of the delay test signal, and send it to the control module. The control module communicates with the first ARM processor through the AXI interconnect module to receive test instructions issued by the first ARM processor and control the encoding sending module, decoding receiving module and timestamp module to complete the test process.
6. The delay testing apparatus for fiber optic channels according to claim 5, characterized in that, The first ARM processor is also used to receive the test results returned by the control module and write the test results into an agreed shared address; The second ARM processor is also used to read the test results within the shared address, and to statistically analyze the test results and generate a test report.
7. The delay testing apparatus for fiber optic channels according to claim 1, characterized in that, The fiber optic interface module includes filter capacitors C1-C8, surface mount resistors R1-R3, surface mount inductors L1-L2, and fiber optic interface integrated module F1; The filter capacitors C1-C4 and the surface mount inductor L1 form the first π-type filter circuit, and its output is connected to the VccR pin of the fiber optic interface integrated module F1 to perform power filtering for the receiving side of F1. The filter capacitors C5-C8 and the surface mount inductor L2 form a second π-type filter circuit, the output of which is connected to the VccT pin of the fiber optic interface integrated module F1 for power filtering on the transmitting side of F1. One side of the surface mount resistors R1, R2, and R3 is connected to the VCC3V3 power supply, and the other side is connected to the SCL pin, pin 4 (LOS / RSSI / SD pin), and SDA pin of the fiber optic interface integrated module F1, respectively, to achieve voltage pull-up. The SCL and SDA pins of the fiber optic interface integration module F1 form an I2C communication mode and are connected to the SOC processing module. Pin 4 (LOS / RSSI / SD pin) of the fiber optic interface integration module F1 is used to detect whether the external fiber optic cable connection is normal.
8. The delay testing apparatus for fiber optic channels according to claim 1, characterized in that, The device also includes a power module for supplying power to the internal hardware system.
9. A method for testing the delay of an optical fiber channel, characterized in that, Includes the following steps: S1, Deploy a device as described in any one of claims 1-8 on both sides of the fiber optic channel to be tested, power on both devices, start the SOC processing module of the device, initialize and load the underlying driver, and run the human-machine interaction program; S2, wait for the devices on both sides to complete time synchronization through their respective time synchronization modules; S3, Configure the relevant parameters of the optical fiber channel to be tested on both sides of the device; S4, one of the devices is used as the transmitting device. The transmitting device is controlled to initiate a test process, output a first optical digital measurement message, and send it to the receiving device through the optical fiber channel under test. The first transmission time stamp T0 is recorded. After receiving the first optical digital measurement message, the receiving device records the first reception time stamp T1. Then, the test process is initiated, and a second optical digital measurement message is output to the transmitting device. The second transmission time stamp T2 is recorded. After receiving the second optical digital measurement message, the transmitting device records the second reception time stamp T3, thus completing one delay test process. S5, the two devices process and calculate the recorded timestamps to obtain the transmit delay, receive delay and delay difference of the fiber optic channel under test. After the set test is completed, a test report is generated.
10. The delay testing method for an optical fiber channel according to claim 9, characterized in that, Transmit delay ΔT1=T1-T0, receive delay ΔT2=T3-T2, delay difference ΔT=ΔT1-ΔT2.