Method and device for constructing cloud computing trusted execution environment of FPGA (Field Programmable Gate Array) intelligent network card

Abstract

The invention provides a cloud computing trusted execution environment construction method of an FPGA intelligent network card, which comprises the following steps: encrypting a bit stream by using a user private key to obtain a user network function bit stream, and sending a challenge to a security management software module of the FPGA intelligent network card by a host application; after the security management software module receives the challenge, the public key share is calculated, key data containing the guide mirror image hash value, the challenge and the public key share are signed by using a temporary private key, and a signature is generated; verifying the correctness of the signature by using the temporary public key, and if the verification is passed, determining that the software and hardware environment of the intelligent network card is credible; the host application generates a random number, calculates a public key share of the random number and sends the public key share to the security management software module; the host application and security management software module calculates a session key according to a key exchange protocol; the host application securely transmits the encrypted user network function bit stream to the security management software module.

Description

Technical Field

[0001] This invention relates to the field of hardware security technology in cloud computing infrastructure, and particularly to a method, apparatus, electronic device, computer-readable storage medium, and computer program product for constructing a cloud computing trusted execution environment for an FPGA smart network interface card, which provides data security and privacy protection when deploying user network functions on an FPGA smart network interface card. Background Technology

[0002] In modern data centers, the growth rate of network bandwidth has far outpaced the performance growth rate of host CPUs. To bridge this gap, offloading network functions (such as firewalls and load balancing) from the host CPU to smart network interface cards (NICs) has become a mainstream technological trend. Among these, FPGA-based smart NICs are widely used to achieve efficient network function offloading due to their hardware-level programmability, high performance, and customizability. Against this backdrop, cloud service providers (CSPs) are increasingly allowing cloud users to directly deploy their custom network functions on FPGA smart NICs, providing users with unprecedented flexibility and performance. FPGA smart NICs refer to those NICs that not only possess basic network connectivity functions but also integrate FPGA computing units, enabling them to offload and execute network I / O-intensive tasks originally handled by the host CPU. Examples include the AMD Alveo™ SN1000 SmartNIC Accelerator Card and the Intel FPGA SmartNIC N6000.

[0003] The typical architecture of FPGA smart network interface cards (NICs) follows a "shell-role" model. The "shell," controlled and managed by the cloud service provider, serves as the infrastructure layer and includes basic logic such as packet management, PCIe Direct Memory Access (DMA), memory controllers, and internal interconnects. The "core," deployed by the user, is the hardware logic that implements their specific network functions. Cloud service providers can dynamically load or update the user's "core" without interrupting the operation of the "shell" through partial FPGA reconfiguration technology.

[0004] However, this offloading mode introduces significant security challenges. Since users do not trust cloud service providers, but the cloud service providers have complete control over the privileged hardware (the "shell" of the FPGA) and the upper-layer privileged software stack of the smart network interface card, an inherent trust asymmetry exists. The "shell" controlled by the cloud service provider can access and monitor all input / output (I / O) of the user's "core," meaning that sensitive user data (e.g., the content of data packets flowing through network functions) could be stolen or tampered with by malicious or curious cloud service providers.

[0005] To address trust issues in cloud computing scenarios, the industry has proposed Trusted Execution Environment (TEE) technology. TEE utilizes hardware isolation mechanisms to create a secure area that protects the confidentiality and integrity of code and data, shielding them from attacks by privileged software. Currently, various TEE solutions exist, which can be broadly categorized as follows:

[0006] CPU-based TEEs: such as Intel SGX technology, which creates a secure "enclave" on the main CPU to protect applications running on the host.

[0007] For TEEs of smart network cards, such as S-NICs, this solution is designed to protect the software network functions running on the System-on-Chip (SoC) CPU of the smart network card.

[0008] General-purpose FPGA TEEs: such as SGX-FPGA and the state-of-the-art ShEF solution. These technologies are designed to provide security for traditional CPU-FPGA co-computing models, where the ShEF solution uses a "ShEF Shield" module to encrypt and authenticate all I / O of the accelerator core, and is managed by a "ShEF Security Kernel" running on the SoC CPU core.

[0009] These existing technologies together form the current security technology foundation for performing sensitive computing tasks in untrusted environments.

[0010] While existing technologies offer a range of solutions for ensuring computing security, they all have significant limitations and drawbacks in the specific scenario of protecting user-defined hardware network functions on FPGA smart network cards, failing to provide complete and effective security guarantees. Specific problems are as follows:

[0011] The protection boundary of the host CPU TEE is ineffective: The security boundary of a host CPU-based TEE (such as Intel SGX) is limited to the host CPU and its memory. When network functions are offloaded to the FPGA on the smart NIC for execution, the computation process occurs entirely outside the security boundary of the CPU TEE. Therefore, this type of technology cannot provide any protection for data processing on the smart NIC and is completely ineffective in preventing threats from cloud service providers.

[0012] Existing TEEs for smart network interface cards (NICs) are not suitable for specific application scenarios: S-NIC is currently the only known TEE solution specifically designed for smart NICs. However, its design goal is to protect software-based network functions running on the smart NIC's SoC CPU, and its security mechanism relies on CPU memory access control. For hardware network functions implemented as hardware circuits in FPGAs, whose data paths are directly connected to the "shell" controlled by the cloud service provider, the S-NIC's protection model is completely inapplicable.

[0013] General-purpose FPGA TEEs have key flaws and cannot be directly applied to smart network interface cards (NICs): Taking ShEF, the most advanced general-purpose FPGA TEE solution currently available, as an example, it exposes the following three core problems when applied to smart NIC scenarios:

[0014] Lack of protection for packet I / O: ShEF's design primarily focuses on protecting the interaction between the FPGA core and memory, but completely neglects the protection of network packet I / O. For network functions, packets are the core object of processing, and their I / O path is the primary attack surface for data leakage. ShEF's "shield" module does not cover this critical path, resulting in sensitive data remaining fully visible to the cloud service provider's "shell" when entering and leaving the user's "core," posing a significant security vulnerability.

[0015] Wasteful and inefficient use of computing resources: The ShEF solution requires deploying its "security kernel" on a dedicated SoC CPU core to isolate it from cloud service provider software. In the resource-intensive cloud infrastructure, permanently occupying a general-purpose CPU core for a security function is a huge waste of valuable computing resources, reducing the overall resource utilization and economic efficiency of smart NICs.

[0016] Complex interface and poor usability: ShEF's "Shield" module provides users with a complex, low-level memory-mapped interface. This requires network function designers to have in-depth hardware interface knowledge and invest a lot of effort in adaptation, greatly increasing the development threshold and integration difficulty, which is not conducive to the widespread application and promotion of this technology.

[0017] In conclusion, existing technologies, whether in terms of protection boundaries, applicable scenarios, or specific functional implementation, cannot provide a secure, efficient, and easy-to-use protection solution for hardware network functions running on FPGA smart network cards in untrusted cloud environments. Summary of the Invention

[0018] This invention aims to address the problem of lacking effective technical means to ensure the confidentiality and integrity of network functions and the data they process when users deploy their custom hardware network functions on the FPGA smart network cards of cloud service providers in untrusted cloud environments.

[0019] This invention aims to overcome the following shortcomings in existing technologies: 1) The protection scope of the host CPU TEE cannot cover external smart network cards; 2) Existing smart network card TEEs are not suitable for hardware-based network functions; 3) General-purpose FPGA TEE solutions suffer from key problems such as not protecting network packet I / O, wasting computing resources, and having complex and difficult-to-use interfaces. This invention is dedicated to providing a secure, efficient, and easily integrated end-to-end trusted execution environment solution.

[0020] Specifically, addressing the shortcomings of existing technologies, such as Figure 5 As shown, this invention proposes a method for constructing a cloud computing trusted execution environment for an FPGA smart network interface card, including:

[0021] The initial step involves encrypting the bitstream of the network function of the file to be encrypted and the cryptographic metadata used to configure the hardware security protection unit using the user's private key to obtain the encrypted user network function bitstream, which is then uploaded to the host application. The host application runs on the host CPU and is used to initiate requests and manage processes, while the FPGA smart network card is used to execute the network function bitstream.

[0022] In the startup step, the host application sends challenge c to the security management software module of the FPGA smart network card to initiate the authentication process;

[0023] In the authentication process, after receiving the challenge c, the security management software module generates a random number a to calculate the Diffie-Hellman public key share g^a mod p. It then uses a temporary private key to sign the key data containing the boot image hash, challenge c, and public key share g^a mod p, generating a signature s. The key data and signature s, along with the device certificate and temporary public key, are sent back to the host as a response.

[0024] In the response steps, the host application verifies whether the device certificate is issued by a trusted smart network interface card (NIC) device vendor, verifies the validity of the temporary public key using the device public key, and verifies the correctness of the signature s using the temporary public key. If all verifications pass, the hardware and software environment of the smart NIC is trusted.

[0025] In the channel construction step, the host application generates a random number b, calculates its public key share g^b mod p, and sends it to the security management software module; the host application and the security management software module calculate the shared symmetric session key Kcom = g^(ab) mod p according to the key exchange protocol.

[0026] In the transmission step, the host application securely transmits the encrypted user network function bit stream to the security management software module. The security management software module decrypts the bit stream within the Trusted Execution Environment (TEE) and loads the decryption result into a designated area of ​​the FPGA smart network card.

[0027] The method for constructing a cloud computing trusted execution environment for the FPGA smart network card, wherein the FPGA smart network card has a data plane security hardware module between the user network function module and the external environment controlled by the cloud service provider.

[0028] This data plane security hardware module is used to perform encrypted authentication on all I / O channels between the user's network functions and the external environment;

[0029] This data plane security hardware module provides an AXI-Stream streaming interface for data-intensive I / O;

[0030] The network data packets transmitted in this I / O channel are processed using the AXI-Stream interface;

[0031] To enable DMA read and write operations, this data plane security hardware module provides a front-end interface consisting of multiple AXI-Stream channels; the back-end of this data plane security hardware module is responsible for converting streaming operations into AXI Memory-Mapped signals required for communication with the PCIe bridge or memory controller.

[0032] To ensure integrity, this data plane security hardware module uses message authentication codes to protect register values; to keep the register address mapping unchanged, the MAC of one register value is stored in another register address.

[0033] The data plane security hardware module verifies the complete MAC address upon receipt. If the verification is successful, the decrypted value is written into the register of the user's network function.

[0034] The data plane security hardware module reads plaintext values ​​from the user's network functions, encrypts them in real time, calculates the MAC address, and then responds to the host application.

[0035] The data plane security hardware module features an AES-GCM cryptographic engine to provide encryption and authentication functions; it employs fully pipelined AES-GCM for host memory DMA access, local memory access, and network packet transmission and reception in this I / O channel; and it uses lightweight AES-GCM for register access in this I / O channel.

[0036] The cloud computing trusted execution environment construction method for the FPGA smart network card includes a FIFO buffer queue with a streaming interface between the network packet protection module, the user network function module, and the memory access protection module.

[0037] When the first data packet is processed by the network packet protection module and written to the FIFO buffer queue, the network packet protection module becomes idle; at this time, the second data packet enters the network packet protection module to begin decryption and authentication.

[0038] The method for constructing a cloud computing trusted execution environment for the FPGA smart network card, wherein the root of trust for the FPGA smart network card is established on the device key burned into the electronic fuse of the FPGA chip by the smart network card device manufacturer during the manufacturing stage, and the FPGA smart network card executes a two-phase secure boot process when it powers on:

[0039] Phase 1: The integrity of the boot image provided by the equipment vendor is verified by the secure boot module embedded in the FPGA chip; the boot image contains the bootloader, TEE firmware, and an operating system loaded with the security management software module.

[0040] The second stage: Part i of the boot image is decrypted and authenticated by the operation key contained in Part i-1; while Part I is directly decrypted by the hardware secure boot module using the root key.

[0041] The cloud computing trusted execution environment construction method for the FPGA smart network card, wherein the security management software module is a background daemon running in the SoC CPU TEE of the FPGA smart network card; by running in the SoC CPU TEE, the operation and data of the security management software module are protected by hardware-level isolation.

[0042] To support authentication throughout the entire lifecycle, a permanent device asymmetric key pair is embedded in the module during boot image generation.

[0043] The method for constructing a cloud computing trusted execution environment for the FPGA smart network card includes the following secure transmission methods: the host application uses a symmetric session key Kcom to re-encrypt the encrypted user network function bit stream, or uses Kcom to establish a secure communication channel and transmits the encrypted user network function bit stream through the secure communication channel.

[0044] like Figure 6 As shown, this invention also proposes a cloud computing trusted execution environment construction device for FPGA smart network interface cards, including:

[0045] The initial module encrypts the bitstream of the network function of the file to be encrypted and the cryptographic metadata used to configure the hardware security protection unit using the user's private key to obtain the encrypted user network function bitstream, and uploads it to the host application. The host application runs on the host CPU and is used to initiate requests and manage processes, while the FPGA smart network card is used to execute the network function bitstream.

[0046] The startup module sends a challenge c to the security management software module of the FPGA smart network card to initiate the authentication process;

[0047] Upon receiving the challenge c, the authentication module and security management software module generate a random number a to calculate the Diffie-Hellman public key share g^a mod p. They then use a temporary private key to sign the key data containing the boot image hash, challenge c, and public key share g^a mod p, generating a signature s. The key data and signature s, along with the device certificate and temporary public key, are sent back to the host as a response.

[0048] The response module verifies whether the device certificate is issued by a trusted smart network interface card (NIC) device vendor, verifies the validity of the temporary public key using the device's public key, and verifies the correctness of the signature s using the temporary public key. If all verifications pass, the hardware and software environment of the smart NIC is trusted.

[0049] The channel construction module generates a random number b, calculates its public key share g^b mod p, and sends it to the security management software module. The host application and the security management software module calculate the shared symmetric session key Kcom = g^(ab) mod p according to the key exchange protocol.

[0050] The transmission module securely transmits the encrypted user network function bitstream to the security management software module. The security management software module decrypts the bitstream within a Trusted Execution Environment (TEE) and loads the decryption result into a designated area of ​​the FPGA smart network card.

[0051] The aforementioned FPGA smart network card cloud computing trusted execution environment construction device, wherein the FPGA smart network card has a data plane security hardware module between the user network function module and the external environment controlled by the cloud service provider;

[0052] This data plane security hardware module is used to perform encrypted authentication on all I / O channels between the user's network functions and the external environment;

[0053] This data plane security hardware module provides an AXI-Stream streaming interface for data-intensive I / O;

[0054] The network data packets transmitted in this I / O channel are processed using the AXI-Stream interface;

[0055] To enable DMA read and write operations, this data plane security hardware module provides a front-end interface consisting of multiple AXI-Stream channels; the back-end of this data plane security hardware module is responsible for converting streaming operations into AXI Memory-Mapped signals required for communication with the PCIe bridge or memory controller.

[0056] To ensure integrity, the data plane security hardware module uses message authentication codes to protect register values; to keep the register address mapping unchanged, the MAC of a register value is stored in another register address.

[0057] The data plane security hardware module verifies the complete MAC address upon receipt. If the verification is successful, the decrypted value is written into the register of the user's network function.

[0058] The data plane security hardware module reads plaintext values ​​from the user's network functions, encrypts them in real time, calculates the MAC address, and then responds to the host application.

[0059] The data plane security hardware module features an AES-GCM cryptographic engine to provide encryption and authentication functions; it employs fully pipelined AES-GCM for host memory DMA access, local memory access, and network packet transmission and reception in this I / O channel; and it uses lightweight AES-GCM for register access in this I / O channel.

[0060] The cloud computing trusted execution environment construction device for the FPGA smart network card includes a FIFO buffer queue with a streaming interface between the network data packet protection module, the user network function module, and the memory access protection module.

[0061] When the first data packet is processed by the network packet protection module and written to the FIFO buffer queue, the network packet protection module becomes idle; at this time, the second data packet enters the network packet protection module to begin decryption and authentication.

[0062] The aforementioned FPGA smart network card cloud computing trusted execution environment construction device, wherein the FPGA smart network card's root of trust is established on the device key burned into the electronic fuse of the FPGA chip by the smart network card device manufacturer during the manufacturing stage, and when the FPGA smart network card powers on, it executes a two-phase secure boot process:

[0063] Phase 1: The integrity of the boot image provided by the equipment vendor is verified by the secure boot module embedded in the FPGA chip; the boot image contains the bootloader, TEE firmware, and an operating system loaded with the security management software module.

[0064] The second stage: Part i of the boot image is decrypted and authenticated by the operation key contained in Part i-1; while Part I is directly decrypted by the hardware secure boot module using the root key.

[0065] The aforementioned cloud computing trusted execution environment construction device for FPGA smart network card, wherein the security management software module is a background daemon running in the SoC CPU TEE of the FPGA smart network card; by running in the SoC CPU TEE, the operation and data of the security management software module are protected by hardware-level isolation.

[0066] To support authentication throughout the entire lifecycle, a permanent device asymmetric key pair is embedded in the module during boot image generation.

[0067] The cloud computing trusted execution environment construction device for the FPGA smart network card includes the following secure transmission methods: the host application uses the symmetric session key Kcom to re-encrypt the encrypted user network function bit stream, or uses Kcom to establish a secure communication channel and transmits the encrypted user network function bit stream through the secure communication channel.

[0068] The present invention also proposes an electronic device, including the aforementioned FPGA smart network card cloud computing trusted execution environment construction device, the electronic device being connected to an information display device, the information display device being used to display the decryption result with user-set display parameters, attributes or through an artificial intelligence model.

[0069] The present invention also proposes a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the cloud computing trusted execution environment construction method for the FPGA smart network card.

[0070] The present invention also proposes a computer program product, including a computer program, wherein when the computer program is executed by a processor, it implements the steps of the cloud computing trusted execution environment construction method of the FPGA smart network card.

[0071] As can be seen from the above solutions, this invention provides a full lifecycle security protection scheme for the hardware network functions on FPGA smart network cards. Compared with the prior art, this invention has the following significant advantages:

[0072] 1. Comprehensive security: For the first time, it achieves end-to-end, all-around protection for control paths (secure boot, authentication, loading) and all data path I / O (especially network packets), solving the core problem of insufficient protection scope in existing solutions.

[0073] 2. High resource efficiency: It innovatively utilizes the TEE built into the SoC, avoiding the huge resource waste caused by physically exclusive CPU cores, and meets the high-density and high-efficiency deployment requirements of cloud data centers.

[0074] 3. High performance: Through microarchitectural optimizations such as overlapping execution pipelines, the impact of security mechanisms on data processing performance is minimized, while retaining the high throughput advantage brought by FPGA offloading.

[0075] 4. Easy to use: It provides a high-level abstract streaming interface, which greatly simplifies the user's hardware design, lowers the technical application threshold, and helps the widespread promotion and adoption of this security solution.

[0076] In summary, this invention enables cloud users to securely offload their core and sensitive network functions to a shared FPGA smart NIC without having to trust the cloud service provider. Attached Figure Description

[0077] Figure 1 This is a schematic diagram of a hardware and software co-working smart network interface card (TEE) architecture proposed in this invention.

[0078] Figure 2 This is a structural diagram of the data plane security hardware module proposed in this invention;

[0079] Figure 3 This is a diagram of the inter-module structure (data packet receiving direction) for overlapping execution proposed in this invention.

[0080] Figure 4 This is a schematic diagram of the overlapping execution module-level pipeline proposed in this invention;

[0081] Figure 5 This is a flowchart of the method of the present invention;

[0082] Figure 6 This is a block diagram of the device of the present invention;

[0083] Figure 7 This is a schematic diagram of the structure of the first electronic device of the present invention;

[0084] Figure 8 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0085] Figure 9 This is a schematic diagram of the structure of the second electronic device of the present invention.

[0086] Figure label:

[0087] A - First electronic device;

[0088] A device for constructing a cloud computing trusted execution environment using B-FPGA smart network interface cards;

[0089] C-Data acquisition equipment;

[0090] D-Information display device;

[0091] 1000 - Second electronic device;

[0092] Ⅰ-Computational Unit;

[0093] II-ROM;

[0094] III-RAM;

[0095] N-bus;

[0096] V-Interface;

[0097] VI - Input Unit;

[0098] VII - Output Unit;

[0099] VIII - Storage medium;

[0100] IX - Communication Unit. Detailed Implementation

[0101] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0102] Without further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] The processor described in this invention is the control center of an electronic device. It can be a single processor or a collective term for multiple processing elements. For example, it can be one or more central processing units (CPUs), application-specific integrated circuits (ASICs), or one or more integrated circuits configured to implement embodiments of this invention, such as one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs).

[0104] Alternatively, the processor can perform various functions of the electronic device by running or executing software programs stored in memory and by calling data stored in memory.

[0105] In a specific implementation, as one example, the processor may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" can refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions). Electronic devices may include servers, desktop computers, laptops, smartphones, tablets, embedded computers, etc., where the embedded computer includes vehicles and robots, etc.

[0106] The memory is used to store the software program that executes the solution of the present invention, and the execution is controlled by the processor. For specific implementation methods, please refer to the above method embodiments, which will not be repeated here.

[0107] It should be noted that the structure of the electronic device shown in the accompanying drawings of this invention does not constitute a limitation thereof. The actual knowledge structure recognition device may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0108] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0109] It should also be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0110] In this invention, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be a single item or multiple items.

[0111] It should also be understood that, in various embodiments of the present invention, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0112] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0113] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0115] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0116] The concept of this invention stems from addressing the core challenge of existing technologies failing to effectively protect the hardware network functions of FPGA smart network cards. The research and development process primarily overcame the following key technical difficulties:

[0117] The first technical challenge of this invention is how to establish a root of trust and a secure control plane on the smart network interface card (NIC). Existing solutions (such as ShEF) achieve this through physical isolation, i.e., by exclusively using a single SoC CPU core to run its secure kernel. While this method achieves isolation, it incurs huge resource overhead and does not meet the high-density, high-efficiency requirements of cloud environments. To address this problem, the technical breakthrough of this invention lies in the fact that FPGA smart NICs (such as the AMD SN1000) have widely integrated multi-core SoCs supporting CPU TEEs (such as ARM TrustZone). Therefore, this invention innovatively proposes to utilize the TEE provided by the SoC CPU itself on the FPGA smart NIC, rather than exclusively using a physical core, to construct a secure management software module for the FPGA smart NIC TEE. The technical challenge lies in designing a complete secure boot chain, starting from the root key (Root of Trust) fixed by the FPGA chip manufacturer, verifying the bootloader and firmware level by level, and finally securely loading and running the secure management software module in the SoC CPU TEE. At the same time, a rigorous remote authentication protocol needs to be designed so that remote users can establish a trust relationship and secure communication channel with the security management unit running in the SoC CPU TEE across untrusted network and host environments.

[0118] The second technical challenge lies in constructing a comprehensive and efficient data plane protection mechanism. The biggest drawback of existing general-purpose FPGA TEE solutions (such as ShefF) is the neglect of protection for network packet I / O on smart NICs, which is fatal for network functionality. The goal of this invention is to design a data plane security hardware module capable of providing seamless protection for all interactions between the user's "core" and the cloud service provider's "shell." The technical challenge lies in designing a unified and efficient encryption and authentication mechanism for four completely different I / O paths: register access, DMA, local memory access, and network packets. Simply encrypting all data would introduce significant performance latency, negating the advantages of FPGA acceleration.

[0119] The third technical challenge is how to achieve strong security while ensuring high performance and ease of use. Simply adding security features would make the hardware design extremely complex and degrade performance. The key to overcoming this challenge in this invention lies in designing a user-friendly streaming interface for data-intensive I / O (network packets, memory access), encapsulating complex underlying bus protocols (such as the AXI memory mapping interface), greatly simplifying the user's development work. More importantly, to hide the latency caused by encryption operations, this invention designs an "overlapping execution" hardware pipeline architecture. By introducing a First-in-First-out (FIFO) buffer between the data plane security hardware module and the user network functions, the encryption processing of the subsequent data packet can overlap with the network function processing of the previous data packet, thereby effectively utilizing packet-level parallelism and maintaining extremely high processing throughput without sacrificing security. This series of micro-architectural optimizations is the core of this invention's balance of security, performance, and ease of use.

[0120] To make the above-mentioned features and effects of the present invention clearer and easier to understand, specific embodiments are described below in conjunction with the accompanying drawings. This specification discloses one or more embodiments incorporating the features of the present invention. The disclosed embodiments are merely illustrative. The scope of protection of the present invention is not limited to the disclosed embodiments, but is defined by the appended claims.

[0121] This invention proposes a hardware and software co-working smart network interface card (NIC) TEE architecture, which includes a security management software module running in the smart NIC SoCCPU TEE, and a data plane security hardware module deployed in FPGA logic to protect all I / O of the user's network function hardware logic.

[0122] Figure 1 This invention demonstrates a hardware-software co-operational smart network interface card (NIC) TEE architecture. The proposed TEE architecture utilizes the CPU TEE (such as ARM TrustZone) built into the FPGA smart NIC SoC chip to run the security management software module. This achieves security protection for critical control path operations such as authentication, key management, and FPGA bitstream loading, without requiring a dedicated physical CPU core, thus significantly saving valuable computing resources. Simultaneously, the data plane security hardware module integrated within the FPGA uses AES-GCM authentication and encryption to prevent cloud service provider-controlled "shells" from stealing or tampering with the user's network function I / O data. This hardware-software co-operational architecture achieves comprehensive and deep protection for both control and data paths.

[0123] The FPGA smart network interface card (NIC) trust root proposed in this invention is established on the device key programmed into the electronic fuse (eFuse) of the FPGA chip by the smart NIC device manufacturer during the manufacturing stage. When the smart NIC powers on, a two-phase secure boot process is executed:

[0124] Phase 1: Fixed read-only memory (ROM) code is executed by a secure boot module embedded within the chip (such as the Platform Management Unit (PMU) and Configuration and Security Unit (CSU) integrated on an AMD MPSoC FPGA). These modules verify the integrity of the boot image provided by the device vendor step by step. This boot image contains the bootloader, TEE firmware, and an operating system loaded with the security management software module described in this invention. Cloud service providers cannot tamper with this boot image.

[0125] The second stage involves each part of the boot image being decrypted and authenticated one by one before loading. To prevent device key leakage, this invention employs a rolling key mechanism: the i-th part of the boot image is decrypted and authenticated by the operation key contained in the (i-1)-th part. The first part, however, is directly decrypted by the hardware secure boot module using the root key. This chained verification process ensures that only verified boot images can be loaded and ultimately securely boot the "security management software module" in the SoC CPU TEE.

[0126] The security management software module proposed in this invention is a background daemon running in a SoC CPU TEE (e.g., an OP-TEE based on ARM TrustZone technology). Its core responsibilities include: responding to remote authentication requests, securely loading the cloud service provider's "shell" and the user's network function bitstream into the FPGA, and clearing the bitstream according to user requests.

[0127] Security Isolation: By running in the SoC CPU TEE, the critical operations (such as processing plaintext bit streams and managing keys) and sensitive data of the security management software module are protected by hardware-level isolation, freeing it from interference and snooping by CSP software running in the same CPU's normal environment.

[0128] Key Management: To support authentication throughout the entire lifecycle, a permanent device asymmetric key pair is embedded in the security management software module during boot image generation. To mitigate the risk of runtime key leakage, the module generates a temporary, one-time authentication key pair after secure boot for subsequent authentication processes. One of the core uses of the permanent device asymmetric key pair is to securely generate temporary authentication key pairs for subsequent runtime use. After the device securely boots and enters the running state, the security management software module uses the private key of this permanent key to digitally sign a random number or specific derived data. This signature result, processed by a specific algorithm, can derive or generate a new, one-time temporary authentication key pair.

[0129] To enable remote users to establish trust with the security management software module on the smart network interface card (NIC) and securely load its network functions, this invention designs the following authentication and key negotiation process:

[0130] Step 1: User Uploads Encrypted File. The user first encrypts the bitstream of their network function and cryptographic metadata (such as AES-GCM keys and initialization vectors) used to configure the hardware security protection unit, using a user-private key (Khost). The encrypted file is uploaded to a host application located on a cloud server (host) via an untrusted channel provided by the cloud service provider. The host application, part of the cloud platform management software, is responsible for interacting with the user and initiating management requests (such as loading functions) to the smart network interface card on behalf of the user. The Khost key is protected by the host-side virtual machine-level CPUTEE.

[0131] In the application scenario of this invention, the core of the encrypted file uploaded by the user is the "network function bitstream." This is a configuration file generated during the FPGA design process using a hardware description language (such as Verilog / VHDL) after synthesis, placement, and routing. It is typically a file with a .bit or .bin extension. This file contains all the configuration information for implementing specific hardware logic circuits (i.e., "network functions") within the FPGA. For example, a user might want to deploy a custom firewall rule engine or a proprietary load balancing algorithm on a smart network interface card (NIC). They first need to design the corresponding hardware logic and then generate a firewall bitstream file based on that logic. To protect their intellectual property and functional security, they need to encrypt this firewall bitstream file before uploading it.

[0132] The host side refers to the cloud server side that runs the host application, as opposed to the smart network interface card (NIC) side. The host side is not the user end. The specific relationship between the user end, cloud, and NIC side is as follows: User end: The user operates from their own office or data center. Cloud (host): The data center server of the cloud service provider, on which the "host application" runs. NIC side: The FPGA smart network interface card plugged into the cloud server.

[0133] Step Two: The host application initiates a challenge. The host application sends a challenge 'c' to the security management software module on the smart network interface card (NIC) to initiate the authentication process. In cryptography, the "Challenge-Response" protocol is a standard authentication mechanism. Using a "challenge" (a random number 'c') instead of a regular "initiation request" is to prevent replay attacks. If an attacker intercepts a valid response and retransmits it during the next authentication attempt, the authenticator will reject the response because challenge 'c' has expired or is different.

[0134] Step 3: The module generates the authentication response. Upon receiving the challenge c, the security management software module generates a random number a, calculates a Diffie-Hellman public key share g^a mod p, and then uses a temporary authentication private key to sign the authentication information containing the boot image hash, challenge c, and public key share g^a mod p, generating a signature s. Subsequently, this authentication information and signature s, along with the device certificate and temporary public key, are sent back to the host as a response.

[0135] The temporary authentication private key (and its corresponding public key) is temporarily generated by the security management software module on the smart network interface card (NIC) at the start of this authentication session based on the aforementioned permanent device asymmetric key. It is a one-time event, used only for the current session, and destroyed after the session ends. This provides "forward security."

[0136] Device certificates are issued by the smart network interface card (NIC) manufacturer before the device leaves the factory. They are linked to the device's permanent public key and identity information, serving as the device's "identity card" in the digital world.

[0137] The temporary public key is generated together with the temporary private key. The temporary authentication private key and the temporary authentication public key are an asymmetric key pair, which are generated simultaneously when the security management software module generates random numbers.

[0138] Step 4: Host Application Verifies Response. The host application first verifies whether the device certificate was issued by a trusted smart network interface card (NIC) vendor, then uses the device's public key to verify the validity of the temporary public key, and finally uses the temporary public key to verify the correctness of the signature 's'. Successful verification proves that the smart NIC's hardware and software environment is trustworthy.

[0139] The device public key originates from the device certificate. In step three, the security management software module sends the "device certificate" along with the response. This certificate contains the device public key, which has been digitally signed by a Certificate Authority (CA, i.e., the smart network interface card (NIC) manufacturer).

[0140] Step 5: Both parties establish a secure communication channel over the existing communication link using the shared session key Kcom. The host application generates another random number b, calculates its public key share g^b mod p, and sends it to the security management software module. Both parties calculate the shared symmetric session key Kcom = g^(ab) mod p according to the Diffie-Hellman key exchange protocol.

[0141] In this diagram, the up arrow ^ represents exponentiation, and mod represents modulo. Obtaining the shared key itself does not directly "obtain" a physical channel, but rather the ability to establish "security" on that channel. Once both parties have negotiated the Kcom, they can overlay a "security layer" consisting of encryption and authentication on top of the existing, insecure physical channel. This "security layer" gives the channel the characteristics of confidentiality (preventing eavesdropping) and integrity (preventing tampering).

[0142] Step Six: Secure Transmission and Loading of Bitstream. Using the secure channel established in the previous step, the host application securely transmits the encrypted user network function bitstream to the security management software module. The module decrypts the bitstream within the TEE and loads it into a designated area of ​​the FPGA. Simultaneously, other remote users can also interact with the host application through a similar secure channel to obtain the cryptographic metadata required for network function safety communication.

[0143] The encrypted user network function bitstream is not runtime-generated network communication data. It refers to the FPGA configuration file (i.e., the bitstream file itself) encrypted by the user terminal using its private key Khost in step one. This encrypted file, after being uploaded from the user terminal, is temporarily stored in the cloud host application. In step six, the host application needs to transmit this pre-existing, statically encrypted file to the network card.

[0144] The secure transmission described in step six uses the symmetric session key Kcom generated in step five through Diffie-Hellman key negotiation. Specifically, the cloud host application uses Kcom to re-encrypt the bitstream file that has already been encrypted with Khost. Alternatively, more commonly, Kcom is used to establish a secure communication channel (such as a TLS record encryption layer), through which the Khost-encrypted file is transmitted. This ensures that the file is not eavesdropped on or tampered with during transmission from the host to the network card.

[0145] This invention also proposes a data plane security hardware module. This module provides comprehensive encryption and authentication for all four types of I / O channels between the user network function and the external environment (i.e., the "shell" controlled by the cloud service provider), including register access, host memory DMA access, local memory access, and network packet transmission and reception. Simultaneously, the proposed data plane security hardware module provides a high-level abstract streaming interface for data-intensive I / O, freeing developers from complex underlying bus protocols and significantly reducing the barrier to entry and workload for developing secure network functions. Here, the user network function is not an abstract concept but refers to the concrete hardware circuitry implemented on FPGA logic resources. When the user-designed bitstream is loaded into a designated area of ​​the FPGA by the security management software module, the designated area becomes a network function accelerator (e.g., a hardware firewall) running at the hardware level. This hardware circuitry is the entity of the "user network function." The "external environment" (i.e., the "shell" of the cloud service provider) refers to the hardware logic implemented in other areas of the FPGA, controlled by the cloud service provider, and used for basic resource management and scheduling.

[0146] Technical Effects: The data plane security hardware module of this invention is a hardware module deployed in FPGA logic, serving as a mandatory access control point between user network functions and the untrusted cloud service provider "shell". Its core function is to perform real-time, transparent encryption authentication on all data entering and leaving the user network function, ensuring that the user network function always processes only plaintext data, while any data flowing through the cloud service provider "shell" is encrypted. Specifically, this data plane security hardware module protects four types of I / O channels in the following ways and has the following characteristics:

[0147] User-friendly streaming interface design: To simplify user development, this module provides a high-level AXI-Stream streaming interface for data-intensive I / O, rather than a complex AXI Memory-Mapped interface.

[0148] Network packets: Incoming and outgoing network packets are processed using the standard AXI-Stream interface, which conforms to the natural pattern of data flow processing in FPGA.

[0149] Host and Local Memory Access: To enable DMA read and write operations, this module provides a front-end interface consisting of multiple AXI-Stream channels (e.g., three read channels for address handshake, data transfer, and three write channels for response). Users only need to handle simple "valid-ready" handshakes and data transfers, without needing to worry about the complex underlying bus protocol details such as burst transfer control and address alignment. The back-end of this module is responsible for translating these simple streaming operations into the complex AXI Memory-Mapped signals required for communication with the PCIe bridge or memory controller.

[0150] Secure register access:

[0151] For slow register configuration, this module provides an industry-standard AXI-Lite interface.

[0152] To ensure integrity, a Message Authentication Code (MAC) is used to protect register values. To maintain the register address mapping, the MAC of a register value is stored in another register address.

[0153] Write operation: The host application needs to follow a specific sequence: first write the encrypted register value, then write its corresponding MAC address. This module verifies the received MAC address; only after successful verification does it write the decrypted value to the user's network function registers.

[0154] Read operations: The host application needs to initiate multiple reads. The first read retrieves the encrypted value, and subsequent reads retrieve the MAC address. This module reads the plaintext value from the user's network function, encrypts it in real time, calculates the MAC address, and then sends a response to the host.

[0155] High-performance AES-GCM cryptographic engine:

[0156] At the core of the module is a 128-bit key AES-GCM cryptographic engine that provides encryption and authentication functions.

[0157] For the three high-throughput channels of network packets, host memory, and local memory, a fully pipelined AES-GCM implementation is adopted, which can process a 128-bit data block in one clock cycle. It is sufficient to support line-rate processing of 25Gbps at a typical FPGA frequency of 250MHz and can be expanded to higher bandwidth.

[0158] For 32-bit register accesses with less demanding performance requirements, a lightweight AES-GCM implementation is used (e.g., processing a 128-bit data block every ten clock cycles) to significantly save FPGA logic resources. This design allows users to flexibly customize it according to performance and resource needs.

[0159] This invention employs an inter-module pipeline mechanism with overlapping execution to process multiple consecutive data packets, thereby reducing the performance overhead of data authentication and encryption on user network functions.

[0160] Technical Effects: To maintain the high-performance advantage of FPGA smart network cards offloading network functions, this invention must minimize the latency caused by cryptographic operations. The core idea is to utilize packet-level parallelism to design an overlapping data processing pipeline. This invention is the first to systematically integrate these components into a complete, hardware-based, high-performance architecture, solving the "data plane security" problem of FPGA smart network cards. For example, regarding the protection of register read and write data integrity, this invention defines a read and write operation sequence operating on the protected registers, without the need to introduce additional MAC storage registers. For example, for the same security algorithm (AES-GCM), this invention innovatively implements two hardware implementations with different performance levels within the same module: (1) Fully pipelined engine: used for high-throughput channels such as network and memory, ensuring line-speed performance. (2) Lightweight iterative engine: used for register access, greatly saving FPGA resources. For example, to reduce the computational overhead of AES-GCM, this invention proposes an inter-module pipeline mechanism.

[0161] This invention also proposes a decoupling mechanism: as shown in the appendix. Figure 3 As shown, FIFO buffer queues with streaming interfaces are inserted as a decoupling mechanism between the main modules in the data processing path, such as the network packet protection module, the user network function module, and the memory access protection module. The network packet protection module and the memory access protection module belong to the data plane security hardware modules. The network packet protection module is responsible for handling the data flow between the network function module and the physical network interface (e.g., MAC / PHY). The memory access protection module is responsible for handling the data flow between the network function module and host memory (via the PCIe bus) and onboard local memory (such as the DDR controller). The user network function module is user-defined hardware logic (such as firewalls and load balancers), which is securely "wrapped" inside the data plane security hardware modules.

[0162] Performance improvement example (taking receiving data packets as an example), as shown in the attached image. Figure 4 :

[0163] Non-overlapping execution (serial processing): The first data packet must complete the following three steps sequentially: 1) decryption and authentication in the network packet protection module; 2) processing in the user network function; 3) encryption and authentication of the processing result in the memory access protection module, ready to be written to memory. During this period, the second data packet must wait until the first data packet is completely processed before it can enter the first module. This leads to severe pipeline idle time and performance bottlenecks.

[0164] An overlapping execution data processing pipeline is employed: when the first data packet completes processing in the network packet protection module and is written to the next FIFO, that module immediately becomes idle. At this point, the second data packet can immediately enter the network packet protection module to begin decryption and authentication, without waiting for the first data packet to complete all subsequent steps. In this way, multiple data packets can be in different stages of pipeline processing simultaneously, effectively hiding the processing latency of individual modules (especially the time-consuming AES-GCM encryption / decryption module), greatly improving overall throughput and reducing end-to-end latency.

[0165] The following are system embodiments corresponding to the above method embodiments. This embodiment can be implemented in conjunction with the above embodiments. The relevant technical details mentioned in the above embodiments are still valid in this embodiment, and will not be repeated here to reduce repetition. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiments.

[0166] like Figure 6 As shown, this invention also proposes a cloud computing trusted execution environment construction device for FPGA smart network interface cards, including:

[0167] The initial module encrypts the bitstream of the network function of the file to be encrypted and the cryptographic metadata used to configure the hardware security protection unit using the user's private key to obtain the encrypted user network function bitstream, and uploads it to the host application. The host application runs on the host CPU and is used to initiate requests and manage processes, while the FPGA smart network card is used to execute the network function bitstream.

[0168] The startup module sends a challenge c to the security management software module of the FPGA smart network card to initiate the authentication process;

[0169] Upon receiving the challenge c, the authentication module and security management software module generate a random number a to calculate the Diffie-Hellman public key share g^a mod p. They then use a temporary private key to sign the key data containing the boot image hash, challenge c, and public key share g^a mod p, generating a signature s. The key data and signature s, along with the device certificate and temporary public key, are sent back to the host as a response.

[0170] The response module verifies whether the device certificate is issued by a trusted smart network interface card (NIC) device vendor, verifies the validity of the temporary public key using the device's public key, and verifies the correctness of the signature s using the temporary public key. If all verifications pass, the hardware and software environment of the smart NIC is trusted.

[0171] The channel construction module generates a random number b, calculates its public key share g^b mod p, and sends it to the security management software module. The host application and the security management software module calculate the shared symmetric session key Kcom = g^(ab) mod p according to the key exchange protocol.

[0172] The transmission module securely transmits the encrypted user network function bitstream to the security management software module. The security management software module decrypts the bitstream within a Trusted Execution Environment (TEE) and loads the decryption result into a designated area of ​​the FPGA smart network card.

[0173] The aforementioned FPGA smart network card cloud computing trusted execution environment construction device, wherein the FPGA smart network card has a data plane security hardware module between the user network function module and the external environment controlled by the cloud service provider;

[0174] This data plane security hardware module is used to perform encrypted authentication on all I / O channels between the user's network functions and the external environment;

[0175] This data plane security hardware module provides an AXI-Stream streaming interface for data-intensive I / O;

[0176] The network data packets transmitted in this I / O channel are processed using the AXI-Stream interface;

[0177] To enable DMA read and write operations, this data plane security hardware module provides a front-end interface consisting of multiple AXI-Stream channels; the back-end of this data plane security hardware module is responsible for converting streaming operations into AXI Memory-Mapped signals required for communication with the PCIe bridge or memory controller.

[0178] To ensure integrity, the data plane security hardware module uses message authentication codes to protect register values; to keep the register address mapping unchanged, the MAC of a register value is stored in another register address.

[0179] The data plane security hardware module verifies the complete MAC address upon receipt. If the verification is successful, the decrypted value is written into the register of the user's network function.

[0180] The data plane security hardware module reads plaintext values ​​from the user's network functions, encrypts them in real time, calculates the MAC address, and then responds to the host application.

[0181] The data plane security hardware module features an AES-GCM cryptographic engine to provide encryption and authentication functions; it employs fully pipelined AES-GCM for host memory DMA access, local memory access, and network packet transmission and reception in this I / O channel; and it uses lightweight AES-GCM for register access in this I / O channel.

[0182] The cloud computing trusted execution environment construction device for the FPGA smart network card includes a FIFO buffer queue with a streaming interface between the network data packet protection module, the user network function module, and the memory access protection module.

[0183] When the first data packet is processed by the network packet protection module and written to the FIFO buffer queue, the network packet protection module becomes idle; at this time, the second data packet enters the network packet protection module to begin decryption and authentication.

[0184] The aforementioned FPGA smart network card cloud computing trusted execution environment construction device, wherein the FPGA smart network card's root of trust is established on the device key burned into the electronic fuse of the FPGA chip by the smart network card device manufacturer during the manufacturing stage, and when the FPGA smart network card powers on, it executes a two-phase secure boot process:

[0185] Phase 1: The integrity of the boot image provided by the equipment vendor is verified by the secure boot module embedded in the FPGA chip; the boot image contains the bootloader, TEE firmware, and an operating system loaded with the security management software module.

[0186] The second stage: Part i of the boot image is decrypted and authenticated by the operation key contained in Part i-1; while Part I is directly decrypted by the hardware secure boot module using the root key.

[0187] The aforementioned cloud computing trusted execution environment construction device for FPGA smart network card, wherein the security management software module is a background daemon running in the SoC CPU TEE of the FPGA smart network card; by running in the SoC CPU TEE, the operation and data of the security management software module are protected by hardware-level isolation.

[0188] To support authentication throughout the entire lifecycle, a permanent device asymmetric key pair is embedded in the module during boot image generation.

[0189] The cloud computing trusted execution environment construction device for the FPGA smart network card includes the following secure transmission methods: the host application uses the symmetric session key Kcom to re-encrypt the encrypted user network function bit stream, or uses Kcom to establish a secure communication channel and transmits the encrypted user network function bit stream through the secure communication channel.

[0190] like Figure 7 As shown, in another embodiment of the present invention, a first electronic device A is also proposed, which includes a cloud computing trusted execution environment construction device B for an FPGA smart network card.

[0191] like Figure 8 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to acquire the video to be identified and classified, such as the sorting video described in the embodiment of the present invention. The information display device D is used to display the video classification results obtained by the present invention.

[0192] The information display device D can process and organize the data output by the first electronic device A based on an information display mechanism to improve the readability of the data. This information display mechanism can be manually preset, for example, visualizing the data output by the first electronic device A. It can present the user with the specified key information based on user-defined display parameters and / or attributes, such as the data range and font, color, and scrolling options. Users can access this information more quickly without needing to navigate to secondary pages or scroll through pages, saving them time and effort. Alternatively, the information display mechanism can be an artificial intelligence (AI) display model that learns the user's key information interests based on past usage habits, such as viewing time, click count, and edit count, and automatically presents rich and necessary key information.

[0193] The present invention also provides a computer program product, which includes a computer program that can be stored on a readable storage medium. When the computer program is executed by a processor, the computer can execute the cloud computing trusted execution environment construction method for FPGA smart network cards provided by the above methods.

[0194] In another embodiment of the present invention, a storage medium VIII is provided for storing a computer program that executes a cloud computing trusted execution environment construction method for the FPGA smart network card. It should be understood that the storage medium in the embodiments of the present invention can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0195] Figure 9 A schematic block diagram of a second electronic device 1000 that can be used to implement embodiments of the present invention is shown. The second electronic device 1000 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein. The second electronic device 1000 may be the same as or different from the first electronic device A.

[0196] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from storage medium VIII into random access memory (RAM) III. The RAM III may also store various programs and data required for the operation of the device 1000. The computing unit I, ROM II, and RAM III are interconnected via bus IV. An input / output (I / O) interface V is also connected to bus IV.

[0197] Multiple components in the second electronic device 1000 are connected to I / O interface V, including: input unit VI, such as a keyboard, mouse, etc.; output unit VII, such as various types of displays, speakers, etc.; storage medium VIII, such as a disk, optical disk, etc.; and communication unit IX, such as a network card, modem, wireless transceiver, etc. Communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0198] The computing unit I can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit I performs the various methods and processes described above, such as method steps S1-S6. For example, in some embodiments, the methods can be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage medium VIII. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by computing unit I, one or more steps of the methods described above can be performed. Alternatively, in other embodiments, computing unit I can be configured to perform methods by any other suitable means (e.g., by means of firmware).

[0199] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A method for constructing a cloud computing trusted execution environment for an FPGA smart network interface card, characterized in that, include: The initial step involves encrypting the bitstream of the network function of the file to be encrypted and the cryptographic metadata used to configure the hardware security protection unit using the user's private key to obtain the encrypted user network function bitstream, which is then uploaded to the host application. The host application runs on the host CPU and is used to initiate requests and manage processes, while the FPGA smart network card is used to execute the network function bitstream. In the startup step, the host application sends challenge c to the security management software module of the FPGA smart network card to initiate the authentication process; In the authentication process, after receiving the challenge c, the security management software module generates a random number a to calculate the Diffie-Hellman public key share g^a mod p. It then uses a temporary private key to sign the key data containing the bootstrap image hash, the challenge c, and the public key share g^a mod p, generating a signature s. The key data and signature, along with the device certificate and temporary public key, are sent back to the host as a response. In the response steps, the host application verifies whether the device certificate is issued by a trusted smart network interface card (NIC) device vendor, verifies the validity of the temporary public key using the device public key, and verifies the correctness of the signature s using the temporary public key. If all verifications pass, the hardware and software environment of the smart NIC is trusted. In the channel construction step, the host application generates a random number b, calculates its public key share g^b mod p, and sends it to the security management software module; the host application and the security management software module calculate the shared symmetric session key Kcom = g^(ab) mod p according to the key exchange protocol. In the transmission step, the host application securely transmits the encrypted user network function bit stream to the security management software module. The security management software module decrypts the bit stream within the Trusted Execution Environment (TEE) and loads the decryption result into a designated area of ​​the FPGA smart network card.

2. The method for constructing a cloud computing trusted execution environment for an FPGA smart network card as described in claim 1, characterized in that, The FPGA smart network card has a data plane security hardware module between the user network function module and the external environment controlled by the cloud service provider. This data plane security hardware module is used to perform encrypted authentication on all I / O channels between the user's network functions and the external environment; This data plane security hardware module provides an AXI-Stream streaming interface for data-intensive I / O; The network data packets transmitted in this I / O channel are processed using the AXI-Stream interface; To enable DMA read and write operations, this data plane security hardware module provides a front-end interface consisting of multiple AXI-Stream channels; the back-end of this data plane security hardware module is responsible for converting streaming operations into AXI Memory-Mapped signals required for communication with the PCIe bridge or memory controller. To ensure integrity, this data plane security hardware module uses message authentication codes to protect register values; to keep the register address mapping unchanged, the MAC of one register value is stored in another register address. The data plane security hardware module verifies the complete MAC address upon receipt. If the verification is successful, the decrypted value is written into the register of the user's network function. The data plane security hardware module reads plaintext values ​​from the user's network functions, encrypts them in real time, calculates the MAC address, and then responds to the host application. The data plane security hardware module features an AES-GCM cryptographic engine to provide encryption and authentication functions; it employs fully pipelined AES-GCM for host memory DMA access, local memory access, and network packet transmission and reception in this I / O channel; and it uses lightweight AES-GCM for register access in this I / O channel.

3. The method for constructing a cloud computing trusted execution environment for an FPGA smart network card as described in claim 2, characterized in that, There is a FIFO buffer queue with a streaming interface between the network packet protection module, the user network function module, and the memory access protection module. When the first data packet is processed by the network packet protection module and written to the FIFO buffer queue, the network packet protection module becomes idle; at this time, the second data packet enters the network packet protection module to begin decryption and authentication.

4. The method for constructing a cloud computing trusted execution environment for an FPGA smart network card as described in claim 1, characterized in that, The root of trust for this FPGA smart network interface card is established on the device key burned into the electronic fuse of the FPGA chip by the smart network interface card manufacturer during the manufacturing stage. When the FPGA smart network interface card is powered on, it executes a two-phase secure boot process: Phase 1: The integrity of the boot image provided by the equipment vendor is verified by the secure boot module embedded in the FPGA chip; The boot image contains a bootloader, TEE firmware, and an operating system loaded with the security management software module; The second stage: Part i of the boot image is decrypted and authenticated by the operation key contained in Part i-1; while Part I is directly decrypted by the hardware secure boot module using the root key.

5. The method for constructing a cloud computing trusted execution environment for an FPGA smart network card as described in claim 1, characterized in that, This security management software module is a background daemon running in the SoC CPU TEE of the FPGA smart network card; by running in the SoC CPU TEE, the operation and data of this security management software module are protected by hardware-level isolation. To support authentication throughout the entire lifecycle, a permanent device asymmetric key pair is embedded in the module during boot image generation.

6. The method for constructing a cloud computing trusted execution environment for an FPGA smart network card as described in claim 1, characterized in that, The secure transmission includes: the host application re-encrypting the encrypted user network function bitstream using the symmetric session key Kcom, or establishing a secure communication channel using Kcom and transmitting the encrypted user network function bitstream through the secure communication channel.

7. A device for constructing a cloud computing trusted execution environment for an FPGA smart network interface card, characterized in that, include: The initial module encrypts the bitstream of the network function of the file to be encrypted and the cryptographic metadata used to configure the hardware security protection unit using the user's private key to obtain the encrypted user network function bitstream, and uploads it to the host application. The host application runs on the host CPU and is used to initiate requests and manage processes, while the FPGA smart network card is used to execute the network function bitstream. The startup module sends a challenge c to the security management software module of the FPGA smart network card to initiate the authentication process; Upon receiving the challenge c, the authentication module and the security management software module generate a random number a to calculate the Diffie-Hellman public key share g^a mod p. They then use a temporary private key to sign the key data containing the bootstrap image hash, the challenge c, and the public key share g^a mod p, generating a signature s. The key data and signature, along with the device certificate and temporary public key, are sent back to the host as a response. The response module verifies whether the device certificate is issued by a trusted smart network interface card (NIC) device vendor, verifies the validity of the temporary public key using the device's public key, and verifies the correctness of the signature s using the temporary public key. If all verifications pass, the hardware and software environment of the smart NIC is trusted. The channel construction module generates a random number b, calculates its public key share g^b mod p, and sends it to the security management software module. The host application and the security management software module calculate the shared symmetric session key Kcom = g^(ab) mod p according to the key exchange protocol. The transmission module securely transmits the encrypted user network function bitstream to the security management software module. The security management software module decrypts the bitstream within a Trusted Execution Environment (TEE) and loads the decryption result into a designated area of ​​the FPGA smart network card.

8. An electronic device, characterized in that, The device includes a cloud computing trusted execution environment construction apparatus for an FPGA smart network card as described in claim 7. The electronic device may be connected to an information display device, which is used to display the decryption result using user-set display parameters, attributes, or through an artificial intelligence model.

9. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the cloud computing trusted execution environment construction method for any FPGA smart network card according to claims 1-6.

10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the cloud computing trusted execution environment construction method for any of the FPGA smart network cards described in claims 1-6.

Images