Simulation test method, system, equipment and product of Ethernet physical layer circuit

Abstract

The invention is applicable to the field of circuit testing, and provides a simulation testing method, system, equipment and product for an Ethernet physical layer circuit, and the method comprises the steps: respectively obtaining a reference signal generated based on a set Ethernet signal frame structure and an attenuation signal after the reference signal is transmitted through an Ethernet physical layer entity circuit and a set network cable; converting the attenuation signal into a simulation test signal which can be processed by an Ethernet physical layer circuit to be tested in the simulation environment; inputting the reference signal into a medium independent interface sending direction of the Ethernet physical layer circuit, and inputting the simulation test signal into a physical medium related interface receiving end of the Ethernet physical layer circuit; operating the Ethernet physical layer circuit to obtain a test response signal output in the receiving direction of a medium independent interface of the Ethernet physical layer circuit; and comparing the reference signal with the test response signal, and determining the signal transmission quality of the Ethernet physical layer circuit. According to the scheme, scientific and objective simulation testing can be carried out on the Ethernet physical layer circuit.

Description

Technical Field

[0001] This application belongs to the field of circuit testing, and in particular relates to a simulation testing method, system, equipment and product for Ethernet physical layer circuits. Background Technology

[0002] Ethernet physical layer (PHY) circuits enable bidirectional conversion between digital signals at the Media Access Control (MAC) layer and analog signals in the physical medium, ensuring reliable data transmission and reception over the physical medium (such as twisted-pair cables). The design of Ethernet PHY circuits addresses the issue of MAC layer digital interfaces not being able to directly connect to the physical medium; therefore, the Ethernet PHY circuit is closely related to signal transmission quality. To guarantee signal transmission quality, the designed Ethernet PHY circuit must be simulated and tested beforehand. However, existing simulation tests are typically based on idealized assumptions, leading to discrepancies between design verification results and actual application performance, thus failing to provide a scientifically objective simulation test for the Ethernet PHY circuit. Summary of the Invention

[0003] This application provides simulation testing methods, systems, devices, and products for Ethernet physical layer circuits to address the problem in the prior art that it failed to perform scientific and objective simulation testing of Ethernet PHY circuits.

[0004] The first aspect of this application provides a simulation and testing method for Ethernet physical layer circuits, including: The reference signal generated based on the set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through the Ethernet physical layer physical circuit and the set network cable are respectively acquired. The attenuated signal is converted into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment. The reference signal is input to the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and the simulation test signal is input to the receiver of the physical medium-dependent interface of the Ethernet physical layer circuit. Run the Ethernet physical layer circuit to obtain the test response signal output from the media-independent interface of the Ethernet physical layer circuit in the receive direction; By comparing the reference signal and the test response signal, the signal transmission quality of the Ethernet physical layer circuit is determined.

[0005] A second aspect of this application provides a simulation and testing system for Ethernet physical layer circuits, comprising: The acquisition module is used to acquire the reference signal generated based on the set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through the Ethernet physical layer physical circuit and the set network cable, respectively. The conversion module is used to convert the attenuated signal into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment. The signal input module is used to input the reference signal into the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and to input the simulation test signal into the receiving end of the physical medium-dependent interface of the Ethernet physical layer circuit. The test module is used to run the Ethernet physical layer circuit and obtain the test response signal output from the medium-independent interface of the Ethernet physical layer circuit in the receive direction. The comparison and determination module is used to compare the reference signal and the test response signal to determine the signal transmission quality of the Ethernet physical layer circuit.

[0006] A third aspect of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described in the first aspect.

[0007] A fourth aspect of this application provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0008] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0009] As can be seen from the above, this application obtains a reference signal generated based on a set Ethernet signal frame structure and an attenuated signal after the reference signal is transmitted through an Ethernet physical layer physical circuit and a set network cable. The simulation environment contains the Ethernet physical layer circuit to be tested. After converting the attenuated signal into a simulation test signal that the Ethernet physical layer circuit can process, the reference signal is injected into the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and the simulation test signal is injected into the receiver of the physical medium-dependent interface of the Ethernet physical layer, thus constructing a realistic signal transmission scenario in the simulation environment. Subsequently, the Ethernet physical layer circuit is run, and the test response signal output from the receiving direction of the medium-independent interface of the Ethernet physical layer circuit is obtained. By comparing the reference signal and the test response signal, the signal transmission quality of the Ethernet physical layer circuit is determined. That is, the signal transmission quality of the Ethernet physical layer circuit is scientifically quantified under a real signal transmission scenario, solving the problem that existing technologies rely on ideal models and fail to conduct scientific and objective simulation tests on Ethernet physical layer circuits. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a simulation test method for an Ethernet physical layer circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of a signal waveform provided in an embodiment of this application; Figure 3 This is a structural diagram of a simulation and testing system for Ethernet physical layer circuits provided in an embodiment of this application; Figure 4 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0013] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0014] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0016] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0017] In specific implementations, the terminals described in the embodiments of this application include, but are not limited to, other portable devices such as mobile phones, laptop computers, or tablet computers with touch-sensitive surfaces (e.g., touchscreen displays and / or touchpads). It should also be understood that in some embodiments, the device is not a portable communication device, but a desktop computer with touch-sensitive surfaces (e.g., touchscreen displays and / or touchpads).

[0018] The following discussion describes terminals that include displays and touch-sensitive surfaces. However, it should be understood that terminals may include one or more other physical user interface devices such as physical keyboards, mice, and / or joysticks.

[0019] The terminal supports a variety of applications, such as one or more of the following: drawing applications, presentation applications, word processing applications, website creation applications, disc burning applications, spreadsheet applications, game applications, telephone applications, video conferencing applications, email applications, instant messaging applications, exercise support applications, photo management applications, digital camera applications, digital camcorder applications, web browsing applications, digital music player applications, and / or digital video player applications.

[0020] Various applications that can run on a terminal can use at least one common physical user interface device, such as a touch-sensitive surface. One or more functions of the touch-sensitive surface and the corresponding information displayed on the terminal can be adjusted and / or changed between and / or within applications. In this way, the terminal's common physical architecture (e.g., the touch-sensitive surface) can support various applications with user interfaces that are intuitive and transparent to the user.

[0021] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0022] Ethernet ports, also known as Physical Medium Dependent Interfaces (MDI), are Ethernet physical layer interfaces that support standard physical media such as 10BASE-T (10 Megabits per second Baseband Twisted-pair Ethernet) and 100BASE-TX (100 Megabits per second Baseband Twisted-pair Extended). These physical media differ in their specific implementations of Ethernet physical layer circuits. For example, 10BASE-T uses Manchester encoding and decoding based on the Physical Layer Signaling (PLS) sublayer, while 100BASE-TX uses 4B / 5B encoding and decoding based on the Physical Coding Sublayer (PCS) and the Physical Medium Dependent (PMD) sublayer. However, when electrical signals are transmitted through these network cables of a certain length, signal attenuation will inevitably occur. The longer the network cable, the greater the possibility of signal attenuation and distortion.

[0023] In practical applications, one of the core functions of Ethernet physical layer circuits is to process attenuated signals received via physical medium-related interfaces and accurately recover the original data from them using internal circuitry such as analog-to-digital converters (ADCs), equalizers, and clock data recovery units. Since Ethernet physical layer circuits must process attenuated signals received via physical medium-related interfaces, simulation testing of their ability to recover real-world attenuated signals is crucial. This performance is verified through the signal transmission quality of the Ethernet physical layer circuit.

[0024] However, traditional simulation tests, such as mixed-signal simulation tests and loopback tests, are conducted in ideal environments and do not take into account the signal attenuation factors that occur when the signal is transmitted through the network cable. They fail to conduct scientific and objective simulation tests on the Ethernet physical layer circuit and thus fail to obtain scientific and objective results on signal transmission quality.

[0025] To address the aforementioned issues, this application proposes a simulation testing method, system, device, and product for Ethernet physical layer circuits, enabling scientific and objective simulation testing of Ethernet physical layer circuits and accurately evaluating the signal transmission quality of the circuits in real transmission environments.

[0026] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0027] See Figure 1 , Figure 1 This is a flowchart illustrating a simulation and testing method for an Ethernet physical layer circuit provided in an embodiment of this application. Figure 1 As shown, a simulation and testing method for Ethernet physical layer circuits includes the following steps: Step 101: Obtain the reference signal generated based on the set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through the Ethernet physical layer physical circuit and the set network cable.

[0028] Setting the Ethernet signal frame structure refers to a predefined data frame format that conforms to the Ethernet protocol standard, used to generate reference signals.

[0029] A reference signal is a digital signal generated based on a defined Ethernet frame structure and used as a test stimulus source. It is an ideal signal that has not undergone transmission impairment. Reference signals are digital signals.

[0030] Ethernet physical layer physical circuits refer to circuits that are packaged as Ethernet physical layer physical chips and used in production for processing the transmission and reception of signals in the real world.

[0031] A set-length network cable refers to a physical network cable with a set length, such as a 50m physical twisted-pair cable, used to generate attenuated signals.

[0032] Attenuated signal refers to the analog signal measured after the reference signal has been transmitted through the Ethernet physical layer physical circuit and the specified network cable.

[0033] The simulation tests acquire the signals required for the simulation, including the original, undamaged reference signal and the attenuated signal after the reference signal has been degraded through a real physical channel. The reference signal is used for signal comparison and circuit state simulation. The attenuated signal provides the input signal for subsequent simulation tests that closely resembles the actual application scenario, overcoming the limitations of ideal signals in traditional simulation tests.

[0034] In some embodiments, the reference signal includes a first reference signal and a second reference signal. The steps of acquiring the reference signal generated based on a set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through an Ethernet physical layer physical circuit and a set network cable include: controlling an Ethernet verification IP core inside the simulation environment to generate the first reference signal based on the set Ethernet signal frame structure; and controlling an Ethernet tester outside the simulation environment to generate the second reference signal based on the set Ethernet signal frame structure; inputting the second reference signal into the Ethernet physical layer physical circuit to obtain an initial signal output by the Ethernet physical layer physical circuit; transmitting the initial signal along the set network cable and performing signal acquisition at the end of the set network cable to obtain the attenuated signal.

[0035] In some embodiments, the simulation environment is an Electronic Design Automation (EDA) simulation environment, which performs simulation testing of the Ethernet physical layer circuit through EDA simulation. The simulation environment refers to a verification platform equipped with the Ethernet physical layer circuit under test.

[0036] The simulation environment also includes an Ethernet Verification IP (VIP) core, which contains components such as a sequence, a driver, and a monitor. The sequence generates a first reference signal based on the defined Ethernet frame structure, the driver inputs this first reference signal into the Ethernet physical layer circuit under test, and the monitor captures the test response signal output by the Ethernet physical layer circuit.

[0037] The Ethernet tester is a dedicated hardware device that can generate a second reference signal.

[0038] The initial signal refers to the signal output from the physical medium-related interface of the Ethernet physical layer physical circuit after processing the second reference signal, which has not yet been transmitted through the physical network cable.

[0039] In some embodiments, script functions control the Ethernet verification IP core inside the simulation environment and the Ethernet tester outside the simulation environment to generate a reference signal based on a set Ethernet signal frame structure, ensuring the consistency of the reference signal and ensuring the comparability of data in subsequent comparison processes.

[0040] Under the constraints of the Ethernet signal frame structure, the Ethernet verification IP core and the Ethernet tester generate reference signals with the same frame structure, resulting in a first reference signal generated by the Ethernet verification IP core and a second reference signal generated by the Ethernet tester. The first and second reference signals are signals with the same frame structure generated by different signal generation devices inside and outside the simulation environment. Although their generation locations and devices differ, their frame structure composition is identical.

[0041] The first reference signal is the reference signal for signal comparison.

[0042] A second reference signal is input to the Ethernet physical layer physical circuit to obtain the initial signal output by the circuit after encoding and driving operations. This initial signal is then fed into a designated network cable. An oscilloscope, such as one with a 10GHz sampling rate, is used to acquire the signal at the end of the cable to obtain the attenuated signal. High-quality attenuated signals were obtained using professional instruments and actual chips, improving the reliability of the simulation test.

[0043] In some embodiments, taking 100BASE-TX network cable transmission as an example, the transmitting end (which can be represented as TX) of the MAC interface of the Ethernet physical layer physical circuit receives the reference signal (which can be represented as TXD) generated by the Ethernet tester. After processing by the digital unit, analog unit and other units inside the physical circuit, the test material, i.e. the initial signal, is output through the MDI transmitting end. The initial signal is then fed into a set network cable of length such as 20m, 50m or 100m for transmission, and an oscilloscope is used to capture the attenuation signal at the end of the set network cable.

[0044] Step 102: Convert the attenuated signal into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment.

[0045] In some embodiments, the Ethernet physical layer circuit under test is typically a circuit in the design verification phase, or it may be a circuit that has been put into production and requires signal transmission quality testing. Ethernet physical layer circuits are usually designed as chips, and accordingly, the Ethernet physical layer circuit under test is referred to as a device under test (DUT).

[0046] The simulation test signal is a signal that has been format converted and can be directly accessed by the Ethernet physical layer circuit under test in the simulation environment. The simulation test signal is a discrete timing differential voltage signal.

[0047] The acquired attenuated signal is format-converted so that it can be used by the Ethernet physical layer circuit, driving the Ethernet physical layer circuit to perform simulation tests using real signals.

[0048] In some embodiments, converting the attenuation signal into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment includes: converting the attenuation signal into a comma-separated value format data file, the data file containing the simulation test signal.

[0049] Comma-Separated Values ​​(CSV) is a plain text format that uses commas to separate different values, with each line representing a data record.

[0050] The attenuation signal acquired by the oscilloscope is converted into a common data file format that can be used by the Ethernet physical layer circuit in the simulation environment, such as a CSV data file. This CSV data file contains multiple voltage sample values ​​arranged in chronological order, which together constitute the simulation test signal.

[0051] Format conversion bridges the gap between real physical measurement data and the simulation environment. By using simple, universal, and easy-to-process data formats, measured signals can be efficiently imported into the simulation environment.

[0052] Step 103: Input the reference signal into the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and input the simulation test signal into the receiver of the physical medium-dependent interface of the Ethernet physical layer circuit.

[0053] The Media Independent Interface (MII) is a standard interface between the Ethernet MAC layer and the PHY layer, and its transmission direction is the channel through which the MAC layer sends data to the PHY layer.

[0054] The Physical Medium Dependent Interface (PDI) receiver is the port where the Ethernet physical layer circuit connects to the physical medium (such as a network cable). A PDI receiver can be represented as an MDI RX. An MDI receiver is typically a differential pair port, including a positive and a negative MDI receiver terminal, used to receive the differential signal, the simulation test signal.

[0055] By injecting reference signals and simulation test signals into different interfaces of the Ethernet physical layer circuit under test, the two signal inputs of the Ethernet physical layer circuit in actual operation are accurately reproduced, thus constructing a realistic circuit state for subsequent circuit simulation testing.

[0056] In some embodiments, inputting the reference signal into the medium-independent interface transmission direction of the Ethernet physical layer circuit includes: converting the first reference signal into parallel data conforming to the timing standard of the medium-independent interface transmission direction through the Ethernet authentication IP core; and inputting the parallel data and its corresponding transmission clock signal into the medium-independent interface transmission direction of the Ethernet physical layer circuit.

[0057] Timing standards define the relative timing relationships between data, clock, and control signals in the interface specifications of media-independent interfaces such as Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII).

[0058] Parallel data refers to data transmitted synchronously through multiple signal lines on a medium-independent interface. For example, the TXD[3:0] bus in RGMII uses dual-edge sampling technology, which transmits the lower 4 bits (TXD[3:0]) on the rising edge and the higher 4 bits (TXD[3:0]) on the falling edge to achieve 8-bit transmission in a single clock cycle.

[0059] In some embodiments, in a simulation environment, the Ethernet verification IP core imports the reference signal, i.e., the first reference signal it generates itself, into the transmission direction channel of the medium-independent interface of the Ethernet physical layer circuit according to the timing specification of the medium-independent interface, thereby constructing a real interference scenario and verifying the function of the transmission direction channel.

[0060] In some embodiments, the simulation test signal is a discrete-time differential voltage signal, which includes a differential positive voltage component and a differential negative voltage component. The step of inputting the simulation test signal into the physical medium-dependent interface receiver of the Ethernet physical layer circuit includes: inputting the differential positive voltage component into the positive terminal of the physical medium-dependent interface receiver and inputting the differential negative voltage component into the negative terminal of the physical medium-dependent interface receiver according to a set synchronization timing.

[0061] Discrete-time differential voltage signals are multiple pairs of voltage values ​​obtained by sampling in time sequence. Each pair of values ​​represents the positive and negative components of a differential voltage signal, namely, the differential positive voltage component and the differential negative voltage component.

[0062] In some embodiments, the simulation test signals are CSV format data files, and Verification Logic (Verilog) script functions are used to read and process the CSV format data files containing the simulation test signals.

[0063] The CSV format data file contains the differential positive voltage component to be input to the positive terminal (MDI_RX_P) of the physical medium-dependent interface receiver and the differential negative voltage component to be input to the negative terminal (MDI_RX_N) of the physical medium-dependent interface receiver.

[0064] In each simulation clock cycle (e.g., a 40ns clock cycle in the 100M mode of the RGMII interface), the voltage values ​​in the CSV format data file are imported into the MDI receiver of the Ethernet physical layer circuit. Specifically, the differential positive voltage component that constitutes a pair of voltage values ​​is imported into the positive terminal of the MDI receiver, and the differential negative voltage component is imported into the negative terminal of the MDI receiver, thus providing a real analog input signal for the Ethernet physical layer circuit.

[0065] Among them, timing synchronization constraints ensure that signals can be received by the Ethernet physical layer circuit in the correct timing, avoiding simulation failures caused by interface timing errors and ensuring the effectiveness of the test.

[0066] In some embodiments, a script function is used to precisely import signal data contained in a CSV format data file into the Ethernet physical layer circuit within the simulation environment, simulating a real signal transmission scenario. This operation includes opening the file, reading and assigning data, and closing the file.

[0067] In some embodiments, a 10GHz simulated clock is generated to provide a timing reference for subsequent synchronous file read operations, as shown in the example code below: reg clk_10GHz; initial begin. clk_10GHz = 0; forever #0.1nsclk_10GHz= ~clk_10GHz; end.

[0068] In some embodiments, the CSV format data file includes an MDI_P.csv file and an MDI_N.csv file. The $fopen function is used to open the MDI_P.csv file and the MDI_N.csv file storing the differential signals in read-only mode, and the file is checked to see if it has been opened successfully.

[0069] In some embodiments, the example code for opening the MDI_P.csv file is shown below: integer file_data_p; initial begin. file_data_p=$fopen(" / mnt / msnashome / SM88E1111 / front / sim_dig / out / real_data_txt / 20m_copper_data / MDI_P.csv","r"); / / Open the MDI_P.csv file using the $fopen function and name it file_data_p; if(file_data_p); $display("file_p opening succeed!"); else begin; / / Check if MDI_P.csv is opened normally; $display("file_p opening fail!"); $finish; end; end.

[0070] In some embodiments, the example code for opening the MDI_N.csv file is shown below: integer file_data_n; initial begin; file_data_n=$fopen(" / mnt / msnashome / SM88E1111 / front / sim_dig / out / real_data_txt / 20m_copper_data / MDI_N.csv","r"); / / Open the MDI_N.csv file using the $fopen function and name it file_data_n; if(file_data_n); $display("file_n opening succeed!"); else begin; / / Check if MDI_N.csv is opened normally; $display("file_n opening fail!"); $finish; end end.

[0071] In some embodiments, under clock rising edge synchronization control, the $fscanf function is used to read real data from the file line by line, and the read values ​​are assigned to the real_data_p register and the real_data_n register respectively. At the same time, the reading information and real-time simulation time are printed for debugging.

[0072] In some embodiments, sample code for reading and printing the MDI_P.csv file is shown below: real real_sample_p; / / Define parameters; real real_data_p; / / Define parameters; always@(posedge clk_10GHz) begin; / / Clock rising edge; if($fscanf(file_data_p,"%f",real_sample_p)) begin; / / Read the values ​​of file_data_p line by line using the $fscanf function and assign them to real_sample_p; $display("file_p reading succeed!"); / / Prints "file_p reading succeeded"; real_data_p = real_sample_p; / / Assign the value of real_sample_p to real_data_p; $display("%t",$realtime); / / Print the time; $display("real_data_p=%f\n",real_data_p); / / Prints the value of real_data_p; end else begin $display("file_p reading fail!!"); / / If a reading error occurs, real_data_p is 0; real_data_p = 0; $finish; end end.

[0073] In some embodiments, sample code for reading and printing the MDI_N.csv file is shown below: real real_sample_n; / / Define parameters; real real_data_n; / / Define parameters; always@(posedge clk_10GHz) begin; / / Clock rising edge; if($fscanf(file_data_n,"%f",real_sample_n)) begin; / / Read the values ​​of file_data_n line by line using the $fscanf function and assign them to real_sample_n; $display("file_n reading succeed!"); / / Prints "file_n reading succeeded!"; real_data_n = real_sample_n; / / Assign the value of real_sample_n to real_data_n; $display("%t",$realtime); / / Print the time; $display("real_data_n=%f\n",real_data_n); / / Prints the value of real_data_p; end else begin $display("file_n reading fail!!"); / / If a reading error occurs, real_data_n is 0; real_data_n = 0; $finish; end end.

[0074] In some embodiments, register values ​​are continuously assigned to the differential signal receiver of the MDI interface using the assign statement, as shown in the example code below: assign MDI_R_P_b = real_data_p; / / Assign the read real_data_p to MDI_R_P_b; assign MDI_R_N_b = real_data_n; / / Assign the read real_data_n to MDI_R_N_b.

[0075] In some embodiments, after a predetermined number of rows have been read (250,000 rows in this example), the $fclose function is used to close the two opened data files and release resources. Example code is shown below: parameter LINE_NUM = 250000; / / The file contains a total of 250,000 lines; integer line_num = 0; always@(posedge clk_10GHz) begin; line_num++; if(line_num==LINE_NUM) begin; / / Read from line 1 to line 250,000, and close the file after reading; $fclose(file_data_p); $fclose(file_data_n); end end.

[0076] Simulated test signals are injected into the receiver through the physical medium-related interface of the Ethernet physical layer circuit. These simulated test signals exhibit various losses and interferences present in real network cable transmission, thus providing a higher reliability of the signal transmission quality obtained from the test.

[0077] Step 104: Run the Ethernet physical layer circuit to obtain the test response signal output from the medium-independent interface of the Ethernet physical layer circuit in the receive direction.

[0078] The media-independent interface is the interface through which the PHY layer outputs recovered data to the MAC layer.

[0079] The test response signal is a digital signal output from the media-independent interface of the Ethernet physical layer circuit after processing the injected simulation test signal. This signal represents the processing result of the Ethernet physical layer circuit on the damaged input signal.

[0080] In some embodiments, the Ethernet physical layer circuit is driven to perform simulation processing based on the input signal, and the signal processing is performed by units such as analog front-end, analog-to-digital converter, and equalizer, and the directional output test response signal is received through a medium-independent interface.

[0081] In some embodiments, the test response signal is captured by the monitor component in the Ethernet verification IP core within the simulation environment, and the output response of the Ethernet physical layer circuit under the excitation of a real damage signal is obtained. This test response signal is a direct basis for evaluating the signal transmission performance of the Ethernet physical layer circuit.

[0082] Step 105: Compare the reference signal and the test response signal to determine the signal transmission quality of the Ethernet physical layer circuit.

[0083] Signal transmission quality is a metric for quantitatively evaluating the signal transmission performance of Ethernet physical layer circuits.

[0084] In some embodiments, by comparing the reference signal and the test response signal, the bit error rate, packet loss rate, signal margin, and other indicators between the reference signal and the test response signal are determined, and then the signal transmission quality of the Ethernet physical layer circuit is evaluated by threshold determination.

[0085] This application provides a quantitative and objective evaluation method to accurately measure the performance of Ethernet physical layer circuits in response to real-world damaged signals, significantly improving the reliability of test results. By judging the quality of signal transmission, the merits of circuit design can be determined, preventing the production of substandard Ethernet physical layer circuits and reducing the cost losses associated with their production. Simultaneously, it encourages engineers to optimize circuit designs in a timely manner.

[0086] In some embodiments, determining the signal transmission quality of the Ethernet physical layer circuit by comparing the reference signal and the test response signal includes: performing a bit-by-bit comparison of the first Ethernet data frame corresponding to the reference signal and the second Ethernet data frame corresponding to the test response signal; and determining the signal transmission quality of the Ethernet physical layer circuit based on the bit error rate obtained from the comparison.

[0087] Bit-by-bit alignment refers to comparing each bit of two data sequences one by one.

[0088] The bit error rate is the ratio of the number of erroneous bits to the total number of transmitted bits.

[0089] In some embodiments, the first Ethernet data frame is represented as TXD and the second Ethernet data frame is represented as RXD. By comparing TXD and RXD, it is determined whether a transmission error has occurred in the data frame, and the signal reception, identification and processing capabilities of the analog-to-digital converter, digital echo cancellation, near-end crosstalk and other units of the Ethernet physical layer circuit are evaluated.

[0090] In some embodiments, an Ethernet verification IP core is used to compare signals and determine signal transmission quality.

[0091] In some embodiments, the Ethernet authentication IP core performs a bit-by-bit data comparison based on a first reference signal and a test response signal. The number of mismatched bits is counted, and the bit error rate is calculated.

[0092] In some embodiments, the Ethernet authentication IP core further includes a scoreboard component that subscribes to signals from the authentication IP core monitor and the Ethernet physical layer circuit monitor to obtain a first reference signal and a test response signal. The scoreboard strips and unpacks the payload portions of the first reference signal (first Ethernet data frame) and the test response signal (second Ethernet data frame), then performs a bit-by-bit comparison, counts the number of erroneous bits, and calculates the bit error rate.

[0093] Bit error rate (BER) is used to measure whether the test response signal and the reference signal data are consistent. Consistent data indicates that the Ethernet physical layer circuit has a strong ability to identify and recover the signal, and that there is no severe attenuation or distortion after transmission. Inconsistent data indicates that the Ethernet physical layer circuit has a poor ability to identify and process such signals.

[0094] If the compared Ethernet data frames are completely identical, with no errors or losses (i.e., the bit error rate is 0), it indicates that the Ethernet physical layer circuit being tested has strong signal reception and processing capabilities and excellent signal transmission quality.

[0095] The bit error rate (BER) is used as a performance quantification metric to determine the signal transmission quality of Ethernet physical layer circuits. A lower BER indicates a stronger ability to receive and process damaged signals, resulting in higher signal transmission quality. In other words, the BER clearly reflects the signal transmission quality of Ethernet physical layer circuits.

[0096] In some embodiments, a variety of different network cable lengths are selected to obtain a variety of attenuation signals with different attenuation levels; determining the signal transmission quality of the Ethernet physical layer circuit based on the bit error rate obtained by comparison includes: determining the signal transmission quality of the Ethernet physical layer circuit under the attenuation signals with different attenuation levels according to the bit error rate and different network cable lengths.

[0097] Various attenuated signals of different degrees are introduced by network cables of different lengths, resulting in signals with varying degrees of degradation. The longer the network cable, the greater the attenuation.

[0098] In some embodiments, different lengths of network cables of the same specification, such as 20 meters, 50 meters, and 100 meters, are used to perform the signal acquisition step in step 101, obtaining various attenuated signals with different attenuation levels. These attenuated signals are then converted into their signal formats, and the converted signals are sequentially input as simulation test signals to the physical medium-dependent interface receiver of the Ethernet physical layer circuit. Test response signals are captured, and the bit error rate is calculated to determine the signal transmission quality of the Ethernet physical layer circuit under attenuated signals of different attenuation levels.

[0099] In some embodiments, a curve showing the relationship between bit error rate and cable length is plotted to determine the signal recovery capability of the Ethernet physical layer circuit, providing a comprehensive understanding of the performance of the Ethernet physical layer circuit in different application scenarios (such as short-distance interconnection and long-distance cabling), which greatly improves the sufficiency of simulation testing.

[0100] like Figure 2 As shown, Figure 2This is a schematic diagram of a signal waveform provided in an embodiment of this application. The diagram includes partial waveforms of four signals, from top to bottom: a reference signal waveform, a test response signal waveform, an initial signal waveform before attenuation, and a simulation test signal waveform. Collecting signal waveform data provides input data support for circuit simulation testing and simultaneously enables signal comparison and analysis. Figure 2 The reference signal waveform and the test response signal waveform were found to be basically consistent, indicating that the signal transmission quality of the tested Ethernet physical layer circuit is high, that is, its ability to recover attenuated signals is strong.

[0101] This application overcomes the shortcomings of traditional circuit simulation testing that does not consider the transmission attenuation of network cables, and provides a more realistic test feedback for the design of Ethernet physical layer circuits, greatly improving the accuracy and design quality of Ethernet physical layer circuits.

[0102] In this embodiment, a reference signal generated based on a set Ethernet signal frame structure and an attenuated signal after the reference signal is transmitted through an Ethernet physical layer physical circuit and a set network cable are obtained. The simulation environment contains the Ethernet physical layer circuit to be tested. After converting the attenuated signal into a simulation test signal that the Ethernet physical layer circuit can process, the reference signal is injected into the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and the simulation test signal is simultaneously injected into the receiver of the physical medium-dependent interface of the Ethernet physical layer, thus constructing a realistic signal transmission scenario in the simulation environment. Subsequently, the Ethernet physical layer circuit is run, and the test response signal output from the receiving direction of the medium-independent interface of the Ethernet physical layer circuit is obtained. By comparing the reference signal and the test response signal, the signal transmission quality of the Ethernet physical layer circuit is determined. This scientifically quantifies the signal transmission quality of the Ethernet physical layer circuit under a real signal transmission scenario, solving the problem that existing technologies rely on ideal models and fail to conduct scientific and objective simulation tests of Ethernet physical layer circuits.

[0103] See Figure 3 , Figure 3 This is a structural diagram of a simulation test system for an Ethernet physical layer circuit provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0104] The simulation and testing system 300 for the Ethernet physical layer circuit includes: an acquisition module 301, a conversion module 302, a signal input module 303, a test running module 304, and a comparison and determination module 305.

[0105] The acquisition module 301 is used to acquire the reference signal generated based on the set Ethernet signal frame structure and the attenuation signal of the reference signal after transmission through the Ethernet physical layer physical circuit and the set network cable.

[0106] The conversion module 302 is used to convert the attenuated signal into a simulation test signal that can be processed by the Ethernet physical layer circuit to be tested inside the simulation environment.

[0107] The signal input module 303 is used to input the reference signal into the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and to input the simulation test signal into the receiving end of the physical medium-dependent interface of the Ethernet physical layer circuit.

[0108] The test module 304 is used to run the Ethernet physical layer circuit and obtain the test response signal output from the medium-independent interface of the Ethernet physical layer circuit in the receive direction.

[0109] The comparison and determination module 305 is used to compare the reference signal and the test response signal to determine the signal transmission quality of the Ethernet physical layer circuit.

[0110] In some embodiments, the reference signal includes a first reference signal and a second reference signal, and the acquisition module is specifically used for: The Ethernet verification IP core within the simulation environment is controlled to generate the first reference signal based on the defined Ethernet signal frame structure; and, The Ethernet tester outside the control simulation environment generates the second reference signal based on the set Ethernet signal frame structure; The second reference signal is input into the Ethernet physical layer physical circuit to obtain the initial signal output by the Ethernet physical layer physical circuit. The initial signal is transmitted along a designated network cable, and the signal is acquired at the end of the designated network cable to obtain the attenuated signal.

[0111] In some embodiments, the signal input module is used for: The Ethernet verification IP core converts the first reference signal into parallel data that conforms to the timing standard of the medium-independent interface transmission direction; The parallel data and its corresponding transmission clock signal are input into the medium-independent interface of the Ethernet physical layer circuit in the transmission direction.

[0112] In some embodiments, the simulation test signal is a discrete-time differential voltage signal, which includes a differential positive voltage component and a differential negative voltage component. The signal input module is used for: According to the set synchronization timing, the differential positive voltage component is input to the positive terminal of the physical medium related interface receiver, and the differential negative voltage component is input to the negative terminal of the physical medium related interface receiver.

[0113] In some embodiments, the conversion module is specifically used for: The attenuation signal is converted into a comma-separated value format data file, which contains the simulation test signal.

[0114] In some embodiments, the comparison and determination module is specifically used for: The first Ethernet data frame corresponding to the reference signal and the second Ethernet data frame corresponding to the test response signal are compared bit by bit. Based on the bit error rate obtained from the comparison, the signal transmission quality of the Ethernet physical layer circuit is determined.

[0115] In some embodiments, the acquisition module is further configured to: By selecting various network cables of different lengths, attenuation signals with different attenuation levels are obtained accordingly. Accordingly, the comparison and determination module is also used for: Based on the bit error rate and different cable lengths, the signal transmission quality of the Ethernet physical layer circuit under attenuated signals with various attenuation levels is determined.

[0116] The Ethernet physical layer circuit simulation and testing system provided in this application embodiment can implement each process of the above-described Ethernet physical layer circuit simulation and testing method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0117] Figure 4 This is a structural diagram of an electronic device provided in an embodiment of this application. As shown in the figure, the electronic device 4 of this embodiment includes: at least one processor 40 ( Figure 4 (Only one is shown in the diagram), memory 41, and computer program 42 stored in said memory 41 and executable on said at least one processor 40, which, when executed, implements the steps in any of the above method embodiments.

[0118] The electronic device 4 can be a desktop computer, laptop, handheld computer, or cloud server, etc. The electronic device 4 may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art will understand that... Figure 4 This is merely an example of electronic device 4 and does not constitute a limitation on electronic device 4. It may include more or fewer components than shown, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0119] The processor 40 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0120] The memory 41 can be an internal storage unit of the electronic device 4, such as a hard disk or memory. The memory 41 can also be an external storage device of the electronic device 4, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 41 can include both internal and external storage units of the electronic device 4. The memory 41 is used to store the computer program and other programs and data required by the electronic device. The memory 41 can also be used to temporarily store data that has been output or will be output.

[0121] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the system can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0122] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0123] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0124] In the embodiments provided in this application, it should be understood that the disclosed systems / electronic devices and methods can be implemented in other ways. For example, the system / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of systems or units may be electrical, mechanical, or other forms.

[0125] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0126] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0127] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0128] The processes in the above-described embodiments can be implemented by a computer program product. When the computer program product is run on an electronic device, the electronic device executes the steps in the above-described method embodiments.

[0129] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A simulation and testing method for Ethernet physical layer circuits, characterized in that, include: The reference signal generated based on the set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through the Ethernet physical layer physical circuit and the set network cable are respectively acquired. The attenuated signal is converted into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment. The reference signal is input to the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and the simulation test signal is input to the receiver of the physical medium-dependent interface of the Ethernet physical layer circuit. Run the Ethernet physical layer circuit to obtain the test response signal output from the media-independent interface of the Ethernet physical layer circuit in the receive direction; By comparing the reference signal and the test response signal, the signal transmission quality of the Ethernet physical layer circuit is determined.

2. The method according to claim 1, characterized in that, The reference signal includes a first reference signal and a second reference signal. The steps of acquiring the reference signal generated based on a set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through the Ethernet physical layer physical circuit and a set network cable include: The Ethernet verification IP core within the simulation environment is controlled to generate the first reference signal based on the defined Ethernet signal frame structure; and, The Ethernet tester outside the control simulation environment generates the second reference signal based on the set Ethernet signal frame structure; The second reference signal is input into the Ethernet physical layer physical circuit to obtain the initial signal output by the Ethernet physical layer physical circuit. The initial signal is transmitted along a designated network cable, and the signal is acquired at the end of the designated network cable to obtain the attenuated signal.

3. The method according to claim 2, characterized in that, The transmission direction of inputting the reference signal into the medium-independent interface of the Ethernet physical layer circuit includes: The Ethernet verification IP core converts the first reference signal into parallel data that conforms to the timing standard of the medium-independent interface transmission direction; The parallel data and its corresponding transmission clock signal are input into the medium-independent interface of the Ethernet physical layer circuit in the transmission direction.

4. The method according to claim 1, characterized in that, The simulated test signal is a discrete-time differential voltage signal, which includes a differential positive voltage component and a differential negative voltage component. Inputting the simulated test signal into the physical medium-dependent interface receiver of the Ethernet physical layer circuit includes: According to the set synchronization timing, the differential positive voltage component is input to the positive terminal of the physical medium related interface receiver, and the differential negative voltage component is input to the negative terminal of the physical medium related interface receiver.

5. The method according to claim 1, characterized in that, The step of converting the attenuated signal into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment includes: The attenuation signal is converted into a comma-separated value format data file, which contains the simulation test signal.

6. The method according to claim 1, characterized in that, The comparison of the reference signal and the test response signal to determine the signal transmission quality of the Ethernet physical layer circuit includes: The first Ethernet data frame corresponding to the reference signal and the second Ethernet data frame corresponding to the test response signal are compared bit by bit. Based on the bit error rate obtained from the comparison, the signal transmission quality of the Ethernet physical layer circuit is determined.

7. The method according to claim 6, characterized in that, The method further includes: By selecting various network cables of different lengths, attenuation signals with different attenuation levels are obtained accordingly. Determining the signal transmission quality of the Ethernet physical layer circuit based on the bit error rate obtained from the comparison includes: Based on the bit error rate and different cable lengths, the signal transmission quality of the Ethernet physical layer circuit under attenuated signals with various attenuation levels is determined.

8. A simulation and testing system for Ethernet physical layer circuits, characterized in that, include: The acquisition module is used to acquire the reference signal generated based on the set Ethernet signal frame structure and the attenuated signal of the reference signal after transmission through the Ethernet physical layer physical circuit and the set network cable, respectively. The conversion module is used to convert the attenuated signal into a simulation test signal that can be processed by the Ethernet physical layer circuit under test within the simulation environment. The signal input module is used to input the reference signal into the transmission direction of the medium-independent interface of the Ethernet physical layer circuit, and to input the simulation test signal into the receiving end of the physical medium-dependent interface of the Ethernet physical layer circuit. The test module is used to run the Ethernet physical layer circuit and obtain the test response signal output from the medium-independent interface of the Ethernet physical layer circuit in the receive direction. The comparison and determination module is used to compare the reference signal and the test response signal to determine the signal transmission quality of the Ethernet physical layer circuit.

9. An electronic device, characterized in that, The electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the electronic device performs the method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, Includes a computer program, which, when run, causes the method as described in any one of claims 1 to 7 to be performed.

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