Method, device and equipment for realizing real-time output of data and storage medium

Abstract

The invention discloses a method, device and equipment for realizing real-time output of data and a storage medium, and relates to the technical field of communication, the method comprises the following steps: obtaining test sequence data of external control equipment, the data is composed of a plurality of states including voltage, current and time, and the data is received through a serial or IC interface; processing the test sequence data in the t period to obtain a communication data frame in the (t + 1) period, specifically, generating standard format test sequence data in combination with the initialized communication protocol stack, calculating the load in the (t + 1) period according to the test sequence data, and filling the load in a corresponding field; and outputting the communication data frame when the (t + 1) th period is reached. The data frame is stored in a cache region, and when the storage capacity reaches a capacity threshold value, part of output data is removed; and monitoring the residual space of the cache region, and if the residual space is smaller than a threshold value, pausing to receive new data and sending an alarm signal. The method can meet the real-time output requirement of the high-frame-rate data and guarantee the transmission stability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and in particular to a method and device for realizing real-time output of data, equipment and a storage medium. BACKGROUND

[0002] With the continuous advancement of smart grid construction, the automation level of substations continues to improve. As an international unified standard for communication between intelligent electronic devices, IEC61850 protocol has become the core technical support for data transmission in power systems. In the IEC61850 protocol system, the station control layer mainly relies on the Ethernet MMS protocol to realize monitoring and control functions, while the process layer takes the GOOSE (Generic Object Oriented Substation Event) and SV (Sampled Value) protocols as the key, and needs to rely on optical fiber communication to meet the transmission requirements of high speed, real-time and high reliability. In particular, in the scenarios of relay protection testing, intelligent electronic device verification and process layer communication of smart substations, the SV protocol explicitly requires that the device stably outputs 4000 frames of data per second, which puts high requirements on the computing performance, data transmission stability and real-time performance of the communication module.

[0003] To meet the stringent requirements of GOOSE and SV protocols in IEC61850 protocol, the mainstream solution in the current industry generally uses FPGA (Field Programmable Gate Array) as the core processing unit to build a relay protection testing module and an optical transceiver device. FPGA, with its powerful parallel processing capability, has become the preferred solution for implementing GOOSE / SV protocols in the early stage of smart grid construction.

[0004] However, the existing technical solutions are difficult to achieve real-time output of data while meeting the requirement of low cost. SUMMARY

[0005] The present application provides a method, device, equipment and storage medium for realizing real-time output of data, which can achieve real-time output of data while meeting the requirement of low cost.

[0006] To achieve the above purpose, the present application adopts the following technical solutions: In a first aspect, the present application provides a method for realizing real-time output of data, comprising: obtaining test sequence data of an external control device; processing the test sequence data at the tth cycle to obtain a communication data frame of the t+1th cycle; outputting the communication data frame of the t+1th cycle when the t+1th cycle is reached.

[0007] Optionally, the processing of the test sequence data to obtain the communication data frame of the t+1th cycle comprises: Based on the test sequence data and the initialized communication protocol stack, test sequence data with a standard format is generated; Based on the test sequence data in the standard format, the communication data frame of the (t+1)th cycle is obtained.

[0008] Optionally, obtaining the communication data frame of the (t+1)th period based on the test sequence data in the standard format includes:

[0009] in, This represents the communication data frame in the (t+1)th cycle. Indicates the conversion coefficient of the merged unit. Indicates the transformation ratio of the mutual inductor. This represents the first test sequence data in standard format. The voltage amplitude of phase A in each state; This represents the first test sequence data in standard format. Phase angle of phase A voltage in each state, This represents the first test sequence data in standard format. The start time of each state. This indicates the output time corresponding to the (t+1)th cycle; The payload of the (t+1)th cycle is filled into the field corresponding to the test sequence data in the standard format to obtain the communication data frame of the (t+1)th cycle.

[0010] Optionally, acquiring the test sequence data of the external control device includes: The test sequence data is received from an external control device via a serial interface or an I²C interface. The test sequence data consists of multiple states, each of which includes voltage, current, and time.

[0011] Optionally, the method further includes: The communication data frame of the (t+1)th cycle is stored in the buffer. When the amount of data stored in the buffer reaches the capacity threshold, some of the output buffer data is cleared.

[0012] Optionally, the method further includes: Monitor the remaining storage space of the cache area; If the remaining storage space is less than the space threshold, the reception of new test sequence data will be suspended, and a cache status alarm signal will be sent to the external control device.

[0013] Secondly, this application provides an apparatus for realizing real-time data output, comprising: The acquisition module is used to acquire test sequence data from external control devices; The data processing module is used to process the test sequence data in the t-th period to obtain the communication data frame in the (t+1)-th period. The output module is used to output the communication data frame of the (t+1)th cycle when the (t+1)th cycle is reached.

[0014] Thirdly, this application provides a computing device, including a memory and a processor; The memory stores one or more computer programs, the one or more computer programs including instructions; when the instructions are executed by the processor, the computing device performs the method as described in any one of the first aspects.

[0015] Fourthly, this application provides a computer-readable storage medium for storing a computer program for performing the method as described in any one of the first aspects.

[0016] As can be seen from the above technical solution, this application has at least the following beneficial effects: In this application, by preprocessing the test sequence data in the t-th cycle and generating the communication data frame in the (t+1)-th cycle, the pre-generated data frame is directly output when the (t+1)-th cycle is reached, which greatly shortens the response time of the data output, effectively ensures the real-time performance of the data output, and can meet the stringent requirements of the SV protocol in the IEC61850 protocol for stable output of 4000 frames of data per second.

[0017] Meanwhile, through standardized protocol stack processing and formulaic instantaneous value calculation, the communication data frames are ensured to conform to the format specifications of the GOOSE / SV protocol, adapting to the communication requirements of the power system process layer. With the flexible data acquisition methods of serial interface or I²C interface, dynamic management of buffer and alarm mechanism, the stability of data transmission and scenario adaptability are improved while reducing hardware costs (without relying on the high parallel hardware logic of FPGA). It solves the multiple limitations of existing solutions in real-time performance, reliability and cost control, and can be widely used in power scenarios such as relay protection testing and intelligent electronic equipment verification, as well as extended industrial fields.

[0018] It should be understood that the descriptions of technical features, technical solutions, beneficial effects, or similar language in this application do not imply that all features and advantages can be achieved in any single embodiment. Rather, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution, or beneficial effect is included in at least one embodiment. Therefore, the descriptions of technical features, technical solutions, or beneficial effects in this specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions, and beneficial effects described in this embodiment can be combined in any suitable manner. Those skilled in the art will understand that embodiments can be implemented without one or more specific technical features, technical solutions, or beneficial effects of a particular embodiment. In other embodiments, additional technical features and beneficial effects may be identified in specific embodiments that do not embody all embodiments. Attached Figure Description

[0019] Figure 1 A flowchart illustrating a method for real-time data output provided in this application embodiment; Figure 2 A schematic diagram of a device for real-time data output provided in an embodiment of this application; Figure 3 This is a schematic diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0020] The terms "first," "second," and "third," etc., used in this application specification and accompanying drawings are used to distinguish different objects, not to limit a specific order.

[0021] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0022] To ensure clarity and conciseness in the description of the following embodiments, a brief introduction to the related technologies is given first: The Ethernet-based substation communication network and system protocol IEC61850 refers to the internationally unified standard for communication between intelligent electronic devices (such as relay protection devices and smart meters in substations). It is divided into a three-layer architecture: station control layer, bay layer, and process layer. Among them, the process layer mainly relies on the GOOSE substation event protocol and the SV sample value transmission protocol for general objects to realize data transmission. It is a key technical specification to ensure real-time monitoring and protection of the power system.

[0023] The GOOSE protocol refers to the event transmission protocol of the process layer of the IEC61850 protocol. It is mainly used to transmit control signals with high real-time requirements, such as switch status and trip commands, and needs to meet the millisecond-level response requirement.

[0024] The SV protocol refers to the sampling data transmission protocol of the process layer of the IEC61850 protocol. It is used to transmit the sampled values ​​of analog quantities such as current and voltage to relay protection equipment in real time. In scenarios such as relay protection testing and process layer communication in smart substations, it is clearly required to output 4,000 frames of data per second stably, which places extremely high demands on the real-time performance and stability of data transmission.

[0025] Existing FPGA-based IEC61850 protocol data transmission solutions are difficult to reliably achieve high frame rate real-time data output that meets the requirements of the SV protocol, and have significant shortcomings in cost control and scenario adaptability. They cannot meet the needs of smart grids and extended industrial fields (such as rail transit automation and smart manufacturing) for low latency, high reliability, and low cost communication.

[0026] The problem arises for the following reasons: The technical root cause of insufficient real-time performance lies in the fact that although FPGAs possess parallel processing capabilities, existing solutions employ serial logic for real-time computation and instant output. Within each data output cycle, the data frame for the current cycle must be calculated before the output operation is completed. However, the SV protocol requires 4000 frames of data per second (i.e., each output cycle is only 250μs). The real-time computation process is prone to accumulated latency, leading to data frame loss or output stuttering, which fails to meet the protocol's stringent real-time requirements.

[0027] The objective limitations of high cost and development threshold are that the hardware cost of FPGA chips is 5-10 times that of general-purpose processors with the same function (such as MCUs), and they need to be developed using hardware description languages ​​such as Verilog / VHDL. The learning cycle for R&D personnel is long and the professional threshold is high, resulting in high overall R&D costs for equipment. This is not conducive to the participation of small and medium-sized manufacturers in technology promotion, and it is also unable to adapt to the needs of large-scale industry applications.

[0028] The design flaw of poor scenario adaptability is that once the hardware logic of the FPGA is solidified, if it is necessary to adjust the test parameters (such as modifying the voltage and current amplitude, switching the communication protocol version) or adapt to new scenarios (such as signal transmission of wind power generation equipment), the hardware logic and PCB layout must be redesigned. It cannot be quickly iterated and adjusted through software, resulting in insufficient flexibility and scalability.

[0029] The management loophole for data transmission stability lies in the fact that the existing solution lacks an efficient cache management mechanism. The cache area adopts a fixed capacity design, neither monitoring the remaining storage space in real time nor having the logic to dynamically clean up the output data. When the data transmission load is high, cache overflow or data overwriting errors are likely to occur, which will further lead to data transmission interruption and affect communication reliability.

[0030] In view of this, embodiments of this application provide a method for real-time data output, which can be executed by a processing device. The processing device can be a terminal or a server. Terminals include, but are not limited to, smartphones, tablets, laptops, personal digital assistants, or smart wearable devices. The server can be a cloud server, such as a central server in a central cloud computing cluster or an edge server in an edge cloud computing cluster. Alternatively, the server can be a server in a local data center. A local data center refers to a data center directly controlled by the user.

[0031] To address the issues of insufficient real-time performance, high cost, and poor flexibility in existing FPGA-based solutions for high frame rate real-time data output, this application proposes a collaborative method of pre-computation, caching, and periodic output. By pre-computing and caching the data frame of the next cycle in the current cycle, and directly reading and outputting the cached data when a cycle interruption is triggered, the latency caused by real-time computation is completely eliminated.

[0032] At the same time, by combining standardized protocol stack processing, dynamic cache management and flexible interface design, it can achieve highly reliable real-time data transmission that meets the requirements of IEC61850 protocol (especially SV protocol 4000 frames per second) on low-cost hardware (such as MCU), taking into account real-time performance, stability and scenario adaptability.

[0033] To make the technical solution of this application clearer and easier to understand, the following describes a method for real-time data output provided by an embodiment of this application, in conjunction with the accompanying drawings. Figure 1 As shown, this figure is a flowchart of a method for real-time data output provided in an embodiment of this application. The method includes: S201. The processing device acquires the test sequence data of the external control device.

[0034] In this application, the processing device specifically refers to the core hardware carrier that enables high frame rate real-time data output. Specifically, it is an IEC61850 protocol optical transceiver module integrating an MCU (microcontroller unit) main controller, an Ethernet PHY module, a photoelectric conversion module, and various interfaces (Serial, I²C, USB, etc.). The processing device's functions include receiving external data, performing data processing (such as protocol parsing and forward computation), buffering data, and periodically outputting data frames that conform to the protocol requirements. It is a key device for replacing traditional FPGA solutions and achieving low-cost, high-reliability data transmission.

[0035] External control equipment refers to upstream devices that provide test task instructions and basic data to processing equipment. In power system scenarios, these typically include relay protection testers and smart substation monitoring hosts; in industrial applications (such as rail transit and smart manufacturing), they can be industrial controllers and test terminals. The role of external control equipment is to generate and distribute test sequence data containing specific parameters based on actual testing or communication needs, guiding the processing equipment to output data frames that meet the scenario requirements.

[0036] Test sequence data is a set of basic data generated by external control equipment to guide the processing equipment in generating communication data frames. This test sequence data uses states as the basic unit, with each state containing three sets of parameters: voltage parameters (such as voltage amplitude and phase angle of phases A / B / C), current parameters (such as current amplitude and phase angle of phases A / B / C), and time parameters (such as the duration of the state). The overall format is typically [state 1 (voltage 1, current 1, time 1), state 2 (voltage 2, current 2, time 2), ..., state n (voltage n, current n, time n)]. It is the core basis for the processing equipment to generate data frames conforming to the IEC 61850 protocol.

[0037] The processing device receives the test sequence data from an external control device via a serial interface or an I²C interface. The test sequence data consists of multiple states, each of which includes voltage, current, and time.

[0038] The processing device establishes a stable communication connection with the external control device through its own serial interface or I²C interface. The external control device generates test sequence data containing multiple voltage-current-time states according to actual needs such as relay protection testing and intelligent electronic device verification, and sends the test sequence data to the processing device through the aforementioned serial interface or I²C interface. After receiving the test sequence data, the processing device will first perform integrity verification, such as verifying whether the data format conforms to the [state 1, state 2, ...] specification and whether the parameters are within a reasonable range.

[0039] If the test sequence data is normal, it is stored in the internal parameter cache to provide basic data for subsequent steps such as generating data frame sequences and forward calculation of the next cycle data.

[0040] If the test sequence data has format errors or abnormal parameters, the abnormal data is discarded directly, and a data error signal is fed back to the external control device through the interface to ensure the accuracy of subsequent data processing.

[0041] This application allows the processing device to clearly define specific output tasks (such as the required voltage and current amplitudes and duration) by acquiring test sequence data. This lays the data foundation for generating high-frame-rate real-time data frames according to the IEC61850 protocol. It is also a key solution to the poor scenario adaptability of traditional FPGA solutions: the processing device can adjust the output logic through software by simply sending different test sequence data from an external control device, without modifying the hardware, thus greatly improving flexibility.

[0042] S202. During the t-th cycle, the processing device processes the test sequence data to obtain the communication data frame for the (t+1)-th cycle.

[0043] The period refers to the fixed time interval between the output data frames of the processing device. In this application, it corresponds to the interrupt period of the timer, such as 1 / 4000 second, or 250μs. Each period corresponds to the output rhythm of one frame of data and is the time base for realizing high frame rate real-time output.

[0044] A communication data frame is a data unit that conforms to the GOOSE and SV protocol format specifications in the IEC 61850 protocol. It contains a frame header (protocol identifier, length, etc.), payload (such as instantaneous voltage and current values), check bits, etc. It can be directly parsed by downstream equipment (such as relay protection devices) and is the smallest unit of data transmission.

[0045] When the processing device is in the t-th cycle, i.e., the time window in which it is currently outputting the t-th frame of data, it will not wait for the t-th frame to finish outputting before processing the next frame. Instead, it will utilize the idle computing power of the current cycle to start processing the (t+1)-th frame of data in advance. This parallel processing logic completely avoids the latency accumulation caused by the real-time calculation and instant output links in traditional solutions, and is the core design to ensure the real-time performance of high frame rates (such as 4000 frames per second).

[0046] Specifically, firstly, the processing device generates test sequence data in a standard format based on the test sequence data and the initialized communication protocol stack.

[0047] The initialized communication protocol stack is a pre-configured IEC61850 protocol software module in the processing device, which includes the SV protocol stack and the GOOSE protocol stack. Its initialization content includes setting the sampling rate of data frames (such as 4000 frames per second for the SV protocol), frame header identifiers (such as the APPID of the GOOSE frame), data structures (such as the ASDU format of the SV frame and the dataset definition of the GOOSE frame), etc., to ensure that the generated data frames conform to the protocol specifications and can be parsed by downstream devices.

[0048] Standard format test sequence data is intermediate data that conforms to the IEC61850 protocol data structure after the original test sequence data is processed by the protocol stack. Its format is consistent with the subsequently generated communication data frames, including field definitions of voltage and current parameters, unit conversion rules, state switching identifiers, etc. It is a bridge connecting the original data and the final communication data frame.

[0049] The processing device invokes the initialized communication protocol stack to standardize the raw test sequence data sent by the external control device. The raw test sequence data contains voltage, current, and time parameters for each state, but does not carry the structured information required by the protocol. The processing device maps these parameters to preset data fields through the protocol stack, such as specifying the data type, length, and unit conversion rules corresponding to the voltage amplitude, and adding state association identifiers (such as the time range label of the state to which the parameter belongs). Finally, it generates standard format test sequence data that conforms to the IEC61850 protocol data structure, providing a unified format benchmark for the subsequent generation of communication data frames.

[0050] Then, the processing device obtains the communication data frame of the (t+1)th cycle based on the test sequence data in the standard format.

[0051] The processing equipment performs real-time calculations of the load data based on standard format test sequence data, expressed as:

[0052] in, This represents the load in the (t+1)th cycle. Indicates the conversion coefficient of the merged unit. Indicates the transformation ratio of the mutual inductor. This represents the first test sequence data in standard format. The voltage amplitude of phase A in each state; This represents the first test sequence data in standard format. Phase angle of phase A voltage in each state, This represents the first test sequence data in standard format. The start time of each state. This represents the output time corresponding to the (t+1)th cycle.

[0053] Next, the payload of the (t+1)th cycle is filled into the field corresponding to the test sequence data in the standard format to obtain the communication data frame of the (t+1)th cycle.

[0054] After calculating the load (such as the instantaneous values ​​of voltage and current in each phase) for the (t+1)th cycle, the processing equipment fills in these real-time calculated loads according to the preset field rules in the standard format test sequence data, i.e., the structured data positions defined by the IEC 61850 protocol. For example, the instantaneous voltage value of phase A is filled into the corresponding data field, the instantaneous current value of phase B is filled into its dedicated field, and so on. Through this precise matching of data and fields, the standard format test sequence data, which originally only contained a basic parameter framework, is given specific real-time values ​​and is finally integrated into a complete communication data frame for the (t+1)th cycle that conforms to the protocol specifications. This process ensures the structural integrity and protocol compatibility of the data frame, laying the foundation for stable output in the (t+1)th cycle.

[0055] S203. When the processing device reaches the (t+1)th cycle, it outputs the communication data frame of the (t+1)th cycle.

[0056] When the timer of the processing device triggers the interrupt signal of the (t+1)th cycle, that is, when the preset (t+1)th output time point is reached, the processing device no longer needs to perform data calculation or format conversion. Instead, it directly reads the communication data frame of the (t+1)th cycle that has been pre-generated in the (t)th cycle from the buffer, converts it into an optical signal through the photoelectric conversion module, and transmits it to downstream devices through the optical fiber link. For example, downstream devices can be relay protection devices or intelligent electronic devices.

[0057] The key to this process lies in timely output: relying on the accurate periodic control of the timer, it is ensured that each frame of data is output strictly in accordance with the time interval required by the IEC61850 protocol (especially the SV protocol) (such as a 250μs interval corresponding to 4000 frames per second), avoiding data disorder caused by time deviation; at the same time, since the data frames are pre-buried, the output operation only needs to complete the reading and transmission, compressing the response time to the microsecond level, completely eliminating the latency that may be introduced by real-time computing, thereby ensuring the real-time performance and stability of data transmission in high frame rate scenarios.

[0058] The communication data frame of the (t+1)th cycle is stored in the buffer. When the amount of data stored in the buffer reaches the capacity threshold, some of the output buffer data is cleared.

[0059] After generating the communication data frame for the (t+1)th cycle in the (t)th cycle, the processing device stores the data frame in a preset buffer, temporarily holding it to await the output command in the (t+1)th cycle. The buffer capacity is preset, for example, it can store 10 or 20 frames of data. When the number of stored data frames reaches this capacity threshold, the processing device automatically triggers a cleanup mechanism, prioritizing the clearing of historical data frames that have already been output from the buffer, i.e., data that has been transmitted to downstream devices in previous cycles, to free up storage space to accommodate newly generated data frames for subsequent cycles, such as data frames for the (t+2)th and (t+3)th cycles.

[0060] This method dynamically recycles cache space to avoid the problem of new data not being able to be stored due to cache overflow, while preventing expired historical data from occupying resources. It ensures that the cache always reserves enough space for the new data frames to be output, thereby guaranteeing the continuity and stability of high frame rate data transmission. It is especially suitable for the caching requirements of high-frequency output scenarios of 4000 frames per second in the SV protocol.

[0061] The method also includes: The processing device monitors the remaining storage space in the buffer; if the remaining storage space is less than the space threshold, it suspends the reception of new test sequence data and sends a buffer status alarm signal to the external control device.

[0062] The processing device monitors the remaining storage space in the buffer in real time, i.e., the capacity currently available to store new data frames, and compares it with a preset space threshold (such as 20% of the total buffer capacity). When the remaining storage space is detected to be less than this space threshold, it means that the buffer is about to reach its storage limit. If new test sequence data sent by the external control device continues to be received, it may cause subsequent data frames to fail to be stored in the buffer, thus triggering an output interruption.

[0063] At this point, the processing device will immediately perform two operations: First, the reception of new test sequence data is suspended to prevent the buffer from overflowing due to continuous writing; second, a buffer status alarm signal, such as a fault code or status message in a specific format, is sent to the external control device through the communication interface to indicate that the upstream device is currently experiencing a shortage of buffer resources.

[0064] This method prevents data loss caused by buffer overflow through early warning and flow control, while allowing external control devices to adjust the data delivery rhythm in a timely manner, such as pausing transmission or reducing the amount of data, thus ensuring the stability of the entire data transmission link. Especially in high frame rate (such as 4000 frames per second) scenarios, it can effectively avoid the risk of communication interruption caused by improper buffer management.

[0065] Based on the above description, this application has the following beneficial effects: In this application, by preprocessing the test sequence data in the t-th cycle and generating the communication data frame in the (t+1)-th cycle, the pre-generated data frame is directly output when the (t+1)-th cycle is reached, which greatly shortens the response time of the data output, effectively ensures the real-time performance of the data output, and can meet the stringent requirements of the SV protocol in the IEC61850 protocol for stable output of 4000 frames of data per second.

[0066] Meanwhile, through standardized protocol stack processing and formulaic instantaneous value calculation, the communication data frames are ensured to conform to the format specifications of the GOOSE / SV protocol, adapting to the communication requirements of the power system process layer. With the flexible data acquisition methods of serial interface or I²C interface, dynamic management of buffer and alarm mechanism, the stability of data transmission and scenario adaptability are improved while reducing hardware costs (without relying on the high parallel hardware logic of FPGA). It solves the multiple limitations of existing solutions in real-time performance, reliability and cost control, and can be widely used in power scenarios such as relay protection testing and intelligent electronic equipment verification, as well as extended industrial fields.

[0067] The above text combined Figure 1 The method for real-time data output provided in the embodiments of this application has been described in detail. The apparatus and device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0068] like Figure 2 As shown in the figure, this is a schematic diagram of a device for realizing real-time data output according to an embodiment of this application. The device includes: The acquisition module 301 is used to acquire test sequence data from external control devices; The data processing module 302 is used to process the test sequence data in the t-th period to obtain the communication data frame in the (t+1)-th period. The output module 303 is used to output the communication data frame of the (t+1)th cycle when the (t+1)th cycle is reached.

[0069] Optionally, the data processing module 302 is specifically used to generate test sequence data with a standard format based on the test sequence data and the initialized communication protocol stack; Based on the test sequence data in the standard format, the communication data frame for the (t+1)th period is obtained, including:

[0070] in, This represents the load in the (t+1)th cycle. Indicates the conversion coefficient of the merged unit. Indicates the transformation ratio of the mutual inductor. This represents the first test sequence data in standard format. The voltage amplitude of phase A in each state; This represents the first test sequence data in standard format. Phase angle of phase A voltage in each state, This represents the first test sequence data in standard format. The start time of each state. This indicates the output time corresponding to the (t+1)th cycle; The payload of the (t+1)th cycle is filled into the field corresponding to the test sequence data in the standard format to obtain the communication data frame of the (t+1)th cycle.

[0071] Optionally, the acquisition module 301 is specifically used to receive the test sequence data from an external control device via a serial interface or an I²C interface, wherein the test sequence data consists of multiple states, each state including voltage, current and time.

[0072] Optionally, the data processing module 302 is further configured to store the communication data frame of the (t+1)th cycle into a buffer, and when the amount of data stored in the buffer reaches a capacity threshold, clear some of the output buffer data.

[0073] Optionally, the data processing module 302 is also used to monitor the remaining storage space of the cache area; If the remaining storage space is less than the space threshold, the reception of new test sequence data will be suspended, and a cache status alarm signal will be sent to the external control device.

[0074] The apparatus for real-time data output according to the embodiments of this application can correspond to the execution of the method described in the embodiments of this application, and the other operations and / or functions of each module / unit of the apparatus for real-time data output are respectively for implementing Figure 1 For the sake of brevity, the corresponding processes of each method in the illustrated embodiments will not be described in detail here.

[0075] This application also provides a computing device. For example... Figure 3 As shown in the figure, this is a schematic diagram of a computing device provided in an embodiment of this application. The computing device 700 includes a bus 701, a processor 702, a communication interface 703, and a memory 704. The processor 702, the memory 704, and the communication interface 703 communicate with each other via the bus 701.

[0076] The 701 bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 3 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0077] The processor 702 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0078] The communication interface 703 is used for communication with external devices.

[0079] Memory 704 may include volatile memory, such as random access memory (RAM). Memory 704 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0080] The memory 704 stores executable code, and the processor 702 executes the executable code to perform the aforementioned method for implementing real-time data output.

[0081] Specifically, in achieving Figure 2 In the case of the illustrated embodiment, and Figure 2 When the modules or units of the device for real-time data output described in the embodiments are implemented by software, the execution... Figure 2 The software or program code required for the functions of each module / unit can be partially or wholly stored in the memory 704. The processor 702 executes the program code corresponding to each unit stored in the memory 704, and executes the aforementioned method for implementing real-time data output.

[0082] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute the above-described method for real-time data output.

[0083] This application also provides a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application are generated.

[0084] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0085] When the computer program product is executed by a computer, the computer executes any of the aforementioned methods for achieving real-time data output. The computer program product can be a software installation package; when any of the aforementioned methods for achieving real-time data output is required, the computer program product can be downloaded and executed on the computer.

[0086] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application.

Claims

1. A method for achieving real-time data output, characterized in that, The method includes: Acquire test sequence data from external control devices; In the t-th period, the test sequence data is processed to obtain the communication data frame in the (t+1)-th period; When the (t+1)th cycle is reached, the communication data frame of the (t+1)th cycle is output.

2. The method according to claim 1, characterized in that, The process of processing the test sequence data to obtain the communication data frame of the (t+1)th period includes: Based on the test sequence data and the initialized communication protocol stack, test sequence data with a standard format is generated; Based on the test sequence data in the standard format, the communication data frame of the (t+1)th cycle is obtained.

3. The method according to claim 2, characterized in that, The step of obtaining the communication data frame for the (t+1)th period based on the test sequence data in the standard format includes: in, This represents the load in the (t+1)th cycle. Indicates the conversion coefficient of the merged unit. Indicates the transformation ratio of the mutual inductor. This represents the first test sequence data in standard format. The voltage amplitude of phase A in each state; This represents the first test sequence data in standard format. Phase angle of phase A voltage in each state, This represents the first test sequence data in standard format. The start time of each state This indicates the output time corresponding to the (t+1)th cycle; The payload of the (t+1)th cycle is filled into the field corresponding to the test sequence data in the standard format to obtain the communication data frame of the (t+1)th cycle.

4. The method according to claim 1, characterized in that, The acquisition of test sequence data from external control devices includes: The test sequence data is received from an external control device via a serial interface or an I²C interface. The test sequence data consists of multiple states, each of which includes voltage, current, and time.

5. The method according to claim 1, characterized in that, The method further includes: The communication data frame of the (t+1)th cycle is stored in the buffer. When the amount of data stored in the buffer reaches the capacity threshold, some of the output buffer data is cleared.

6. The method according to claim 4, characterized in that, The method also includes: Monitor the remaining storage space of the cache area; If the remaining storage space is less than the space threshold, the reception of new test sequence data will be suspended, and a cache status alarm signal will be sent to the external control device.

7. A device for realizing real-time data output, characterized in that, The device includes: The acquisition module is used to acquire test sequence data from external control devices; The data processing module is used to process the test sequence data in the t-th period to obtain the communication data frame in the (t+1)-th period. The output module is used to output the communication data frame of the (t+1)th cycle when the (t+1)th cycle is reached.

8. The apparatus according to claim 6, wherein the data processing module is specifically configured to generate test sequence data with a standard format based on the test sequence data and the initialized communication protocol stack; and to obtain a communication data frame for the (t+1)th cycle based on the test sequence data with the standard format.

9. A computing device, characterized in that, Including memory and processor; The memory stores one or more computer programs, the one or more computer programs including instructions; when the instructions are executed by the processor, the computing device performs the method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program for performing the method as described in any one of claims 1 to 6.

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