Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a method for manufacturing the semiconductor device. A method for manufacturing a semiconductor device includes forming a mold stack over a substrate, the mold stack including a mold layer and a lower support layer; forming a lower electrode having a lower portion and an upper portion in the molded stack; exposing the lower electrode by recessing an upper surface of the molded stack; forming a trimming portion by trimming the exposed upper portion of the lower electrode; forming a pyrolysis layer surrounding the lower side surface of the trimming part; forming a supporting body lining layer on the pyrolysis layer and the trimming part; forming a horizontal level gap by removing the pyrolysis layer; forming an upper support body layer on the support body lining layer; forming a support body hole by etching the upper support body layer and the support body lining layer; and exposing an outer wall of a lower portion of the lower electrode by removing the molding layer through the support hole and the horizontal level gap.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0104512, filed on August 6, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor device and a method for manufacturing the semiconductor device, and more specifically, to a semiconductor device including a capacitor and a method for manufacturing the semiconductor device. Background Technology

[0004] Recently, with the increasing aspect ratio of capacitors, supports are being used to prevent capacitor collapse. However, the problem lies in the increased manufacturing complexity due to the difference in etching selectivity between the molding layer and the support, as well as the increased height that may result from the application of supports. Summary of the Invention

[0005] The embodiments of this disclosure are intended to reduce the manufacturing difficulty of capacitors with higher aspect ratios, increased capacitance, and higher structural stability.

[0006] The embodiments of this disclosure aim to form capacitors with a high aspect ratio and improved capacitance and structural stability by applying an upper support after forming the lower electrode.

[0007] Specifically, pyrolytic polymers can be used to manufacture the upper support.

[0008] According to embodiments of this disclosure, a method for manufacturing a semiconductor device includes: forming a molding stack on a substrate, the molding stack including a plurality of molding layers and a lower support layer; forming a plurality of lower electrodes having lower portions and upper portions in the molding stack; exposing the upper portions of the lower electrodes by recessing the upper surface of the molding stack; forming a trimmed portion by trimming the exposed upper portions of the lower electrodes; forming a pyrolysis layer surrounding a lower side surface of the trimmed portion; forming a support inner liner on the pyrolysis layer and the trimmed portion; forming a horizontal hierarchical gap exposing the outer wall of the trimmed portion by removing the pyrolysis layer; forming an upper support layer on the support inner liner; forming a support via exposing the horizontal hierarchical gap by etching the upper support layer and the support inner liner; and exposing the outer wall of the lower portion of the lower electrodes by removing the molding layer through the support via and the horizontal hierarchical gap.

[0009] According to another embodiment of the disclosure, a semiconductor device includes: an array of lower electrodes, each lower electrode including a first pillar portion and a second pillar portion disposed above the first pillar portion and having a line width narrower than the first pillar portion; a lower support body adapted to support an outer wall of the first pillar portion of the lower electrode; an upper support body adapted to support an upper portion and an outer wall of the second pillar portion of the lower electrode; a dielectric layer adapted to cover the lower electrode, the lower support body, and the upper support body; and an upper electrode above the dielectric layer.

[0010] According to another embodiment of the disclosure, a semiconductor device includes: an array of lower electrodes, each lower electrode including a first pillar portion and a second pillar portion disposed above the first pillar portion and having a line width narrower than the first pillar portion; a lower support body adapted to support an outer wall of the first pillar portion of the lower electrode; an upper support body adapted to support an upper portion and an outer wall of the second pillar portion of the lower electrode; a dielectric layer adapted to cover the lower electrode, the lower support body, and the upper support body; and an upper electrode above the dielectric layer.

[0011] According to another embodiment of the disclosure, a semiconductor device includes: an array of lower electrodes, each lower electrode including a first pillar portion and a second pillar portion disposed above the first pillar portion and having a line width narrower than the first pillar portion; a lower support body adapted to support an outer wall of the first pillar portion of the lower electrode; an upper support body adapted to support an upper portion and an outer wall of the second pillar portion of the lower electrode; and a support body liner between the upper support body and the second pillar portion.

[0012] According to another embodiment of the disclosure, a semiconductor device includes: an array of lower electrodes, each lower electrode including a first pillar portion and a second pillar portion disposed above the first pillar portion and having a line width narrower than the first pillar portion; a lower support body adapted to support an outer wall of the first pillar portion of the lower electrode; an upper support body adapted to support an upper portion and an outer wall of the second pillar portion of the lower electrode; and a support body liner between the upper support body and the second pillar portion.

[0013] These and other features and advantages of embodiments of the present application will be better understood by persons of ordinary skill in the art upon reading the following detailed description of embodiments of the present application in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the disclosure.

[0015] Figures 2A-2P is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure will be described below in greater detail with reference to the accompanying drawings. Embodiments can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various drawings and embodiments of the present disclosure.

[0017] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0018] The accompanying drawings are not necessarily drawn to scale, and in some instances the dimensions can be exaggerated for the sake of clarity. When a first layer is referred to as being "on" or "under" a second layer, it can mean that the first layer is directly formed on the second layer, or a third layer can exist between the first layer and the second layer.

[0019] Features described with reference to one embodiment can also be combined with features of another embodiment.

[0020] Figure 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0021] Referring to Figure 1 , the semiconductor device can include a capacitor CAP disposed over a substrate 101 including a lower structure LB.

[0022] The lower structure LB can include a gate structure BG disposed in the substrate 101 and a bit line BL and a storage node contact 113 disposed over the substrate 101.

[0023] The substrate 101 can be a material suitable for a semiconductor process. The substrate 101 can include a semiconductor substrate. The substrate 101 can be formed of a silicon-containing material. The substrate 101 can include silicon, single crystalline silicon, polysilicon, amorphous silicon, silicon germanium, single crystalline silicon germanium, polysilicon germanium, carbon-doped silicon, combinations thereof, or multiple layers thereof. The substrate 101 can also include other semiconductor materials such as germanium. The substrate 101 can include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The substrate 101 can include an SOI (silicon on insulator) substrate.

[0024] An isolation layer 102 and an active region 103 can be formed on the substrate 101. Multiple active regions 103 can be defined by the isolation layer 102.

[0025] The gate structure BG can be disposed in the substrate 101. The gate structure BG can include a buried gate structure disposed at a level lower than an upper surface of the substrate 101. Although not shown, the gate structure BG can include a gate electrode and a gate insulating layer.Figure 1 The buried gate structure disposed at a level lower than the upper surface of the substrate 101 is illustrated, but the technical concept and scope of the present disclosure are not limited thereto, and can be applied to all gate structures including a recessed gate, a fin gate, a planar gate, etc.

[0026] The gate structure BG can include a stack structure of the gate electrode 105 and a gate capping layer 106 gap-filled to the gate trench 104. A gate dielectric layer can be interposed between the gate trench 104 and the stack structure of the gate electrode 105 and the gate capping layer 106.

[0027] Specifically, the gate trench 104 can be formed in the substrate 101. A bottom surface of the gate trench 104 can be disposed at a level higher than a bottom surface of the isolation layer 102. The gate trench 104 can have a shallower depth than the isolation layer 102. According to another embodiment of the present disclosure, a bottom portion of the gate trench 104 can have a curvature. According to another embodiment of the present disclosure, the isolation layer 102 in a direction in which the gate trench 104 extends can be etched to a predetermined depth to form a fin in the active region 103.

[0028] The gate electrode 105 can fill a portion of the gate trench 104. The gate capping layer 106 can fill a remaining portion of the gate trench 104 above the gate electrode 105. An upper surface of the gate capping layer 106 can be disposed at the same level as an upper surface of the substrate 101.

[0029] The first impurity region 107 and the second impurity region 108 can be formed in the substrate 101. The first impurity region 107 and the second impurity region 108 can be referred to as "first and second source / drain regions," respectively. The first impurity region 107 and the second impurity region 108 can be spaced apart from each other by the gate trench 104. As a result, the gate electrode 105 and the first and second impurity regions 107 and 108 can form a unit transistor. The unit transistor can improve a short channel effect by increasing a channel length through formation of the gate electrode 105 in the buried gate structure.

[0030] An interlayer dielectric layer 112 can be disposed on the substrate 101. For example, the interlayer dielectric layer 112 can include at least one of silicon nitride, silicon oxide, and silicon oxynitride. According to another embodiment of the present disclosure, the interlayer dielectric layer 112 can include an empty space.

[0031] A bit line structure BL and a storage node contact 113 can be disposed in the interlayer dielectric layer 112. The bit line structure BL can be formed to be coupled to the first source / drain region 107 located between the gate structures BG.

[0032] Storage node contact 113 can penetrate interlayer dielectric layer 112. A first end of storage node contact 113 can contact substrate 101, and a second end of storage node contact 113 can contact lower electrode 150. Storage node contact 113 can be coupled to a second source / drain region 108 of substrate 101. Storage node contact 113 and lower electrode 150 can be at least partially stacked on top of each other.

[0033] Etch stop pattern 120 may be disposed on the lower structure LB. Etch stop pattern 120 may include a dielectric material. For example, etch stop pattern 120 may include silicon nitride, however, the technical concept and scope of this disclosure are not limited thereto.

[0034] The lower electrode 150 may be disposed on the lower structure LB. The lower electrode 150 may penetrate the etch stop pattern 120. Each lower electrode 150 may be electrically connected to the substrate 101 via a storage node contact 113 formed in the lower structure LB. The lower electrode 150 may have a high aspect ratio. Here, aspect ratio may refer to the ratio of height to width. According to embodiments of the present disclosure, a high aspect ratio may refer to an aspect ratio of about 10:1 or greater. The height of the lower electrode 150 may be approximately Or larger. For example, each lower electrode 150 may be cylindrical. According to another embodiment of the present disclosure, each lower electrode 150 may be cylindrical or pylinder-shaped, wherein a first lower electrode having a cylindrical shape and a second lower electrode that gap-fills the first lower electrode are combined.

[0035] Each lower electrode 150 may include a conductive material. For example, each lower electrode 150 may include cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), gold (Pt), ruthenium (Ru), iridium (Ir), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), or combinations thereof. According to embodiments of the present disclosure, each lower electrode 150 may be formed of titanium nitride. According to another embodiment of the present disclosure, the lower electrode 150 may include a stacked structure of TiSiN / TiN.

[0036] According to another embodiment of this disclosure, each lower electrode 150 may include a stacked structure having a cylindrical titanium nitride and a gap-filled interior of titanium nitride silicon.

[0037] Each lower electrode 150 may include a trimming portion 150P. The trimming portion 150P may be referred to as the "upper portion". The lower electrode 150 excluding the trimming portion 150P may be referred to as the non-trimmed portion. The non-trimmed portion may be referred to as the "lower portion". The non-trimmed portion of the lower electrode 150 may be referred to as the "first pillar portion", while the trimming portion 150P of the lower electrode may be referred to as the "second pillar portion".

[0038] According to an embodiment, the trimmed portion 150P may have a uniform linewidth at both the top and bottom. The trimmed portion 150P may have a side surface perpendicular to the surface of the substrate 101. The untrimmed portion may have a linewidth that decreases from top to bottom. The untrimmed portion may have a side surface with a negative slope.

[0039] The trimmed section 150P can refer to an area with a narrower linewidth than the untrimmed section due to the trimming process. The sidewalls of the trimmed section 150P can be continuous with the untrimmed section to form an integral structure.

[0040] Due to the linewidth difference between the trimmed portion 150P and the untrimmed portion, the upper surface (e.g., top surface) of the untrimmed portion exposed in a direction parallel to the surface of the substrate 101 can be referred to as a "shoulder portion 150S". The shoulder portion 150S can have a shape that surrounds the trimmed portion 150P in a plane. The connection portion located between the shoulder portion 150S and the trimmed portion 150P can be rounded. The linewidth of the shoulder portion 150S can be inversely proportional to the linewidth of the trimmed portion 150P. For example, as the linewidth of the trimmed portion 150P narrows, the linewidth of the shoulder portion 150S can increase.

[0041] As the linewidth of the trimmed portion 150P narrows, the volume of the upper support USP disposed between the trimmed portions 150P can be increased, thereby increasing the supporting force of the support. For example, as the linewidth of the trimmed portion 150P narrows, the linewidth of the shoulder portion 150S can be increased, which ultimately increases the contact area between the dielectric layer 151 and the lower electrode 150 and increases the capacitance.

[0042] The lower support 140 and the upper support USP can be disposed on the substrate 101. The lower support 140 and the upper support USP can be spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101. The number of lower supports 140 can be increased or decreased as needed. When multiple lower supports are included, each lower support 140 can be arranged to be spaced apart from each other by a predetermined distance in a direction perpendicular to the surface of the substrate 101.

[0043] A lower support 140 may be disposed between the lower electrodes 150. Specifically, the lower support 140 may be disposed between the non-adjustable portions of the lower electrodes 150. The lower support 140 may contact the side of the non-adjustable portion of each lower electrode 150 and may surround the side of the non-adjustable portion of each lower electrode 150. The lower support 140 may physically support the lower electrodes 150. The lower support 140 may contact the sidewall of an adjacent lower electrode 150. The upper support USP may be thicker than the lower support 140.

[0044] The lower support 140 may include a dielectric material. For example, the lower support 140 may include silicon nitride or silicon carbonitride; however, the technical concept and scope of this disclosure are not limited thereto.

[0045] The upper support USP can be formed in multiple layers. The upper support USP can be disposed between adjacent lower electrodes 150 and on top of the lower electrodes 150. Specifically, according to embodiments of this disclosure, the upper support USP can be disposed between and on top of the lower electrode trimming portions 150P. The upper support USP can cover a portion of the side surface of each lower electrode trimming portion 150P. In a direction perpendicular to the surface of the substrate 101, the bottom surface of the upper support USP can be spaced apart from the non-trimmed portion of the lower electrode 150 by a predetermined distance. The bottom surface of the upper support USP can be disposed at a level higher than the upper surface of the non-trimmed portion of the lower electrode 150 (i.e., the shoulder portion 150S of the lower electrode).

[0046] The upper support USP may include a stacked structure of a support liner 141, a first upper support 142, and a second upper support 143. The support liner 141 may cover a portion of the upper surface and side surface of each lower electrode trimming portion 150P. The support liner 141 may have an inner liner shape that uniformly covers a portion of the upper surface and side surface of each lower electrode trimming portion 150P.

[0047] A first upper support 142 can be disposed on the inner liner 141 of the support. The thickness of the first upper support 142 can be greater than the thickness of the trimmed portion 150P of the lower electrode covered by the inner liner 141 of the support. Therefore, the upper surface of the first upper support 142 can be planarized. A second upper support 143 can be disposed on the first upper support 142.

[0048] The inner liner 141, the first upper support 142, and the second upper support 143 may comprise the same dielectric material. For example, the inner liner 141, the first upper support 142, and the second upper support 143 may comprise silicon nitride or silicon carbonitride; however, the technical concept and scope of this disclosure are not limited thereto. According to another embodiment of this disclosure, the inner liner 141, the first upper support 142, and the second upper support 143 may also comprise a dielectric material selected from the group consisting of SiOC, SiBN, SiBCN, SiCN, SiON, SiN, Si, and doped SiN. According to another embodiment of this disclosure, the inner liner 141, the first upper support 142, and the second upper support 143 may comprise different dielectric materials.

[0049] The dielectric layer 151 can uniformly cover the outer wall of the lower electrode 150, the surface of the lower support 140, and the surface of the upper support USP. The dielectric layer 151 can cover the outer wall of each lower electrode 150, a portion of the sidewall of the lower electrode trimming portion 150P, and the lower electrode shoulder portion 150S. According to embodiments of this disclosure, the area of ​​the dielectric layer 151 can be increased proportionally to the linewidth of the lower electrode shoulder portion 150S, thereby increasing the capacitance.

[0050] The dielectric layer 151 may comprise a high-k material having a dielectric constant higher than that of silicon oxide. High-k materials may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of this disclosure, the dielectric layer 151 may be formed of a composite layer comprising two or more layers of the aforementioned high-k materials. According to embodiments of this disclosure, the dielectric layer 151 may be formed of a zirconium oxide-based material, exhibiting excellent leakage current characteristics while sufficiently reducing the equivalent oxide thickness (EOT). For example, dielectric layer 151 may include one of the following: ZAZ (ZrO2 / Al2O3 / ZrO2), TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2), TZAZT (TiO2 / ZrO2 / Al2O3 / ZrO2 / TiO2), ZAZT (ZrO2 / Al2O3 / ZrO2 / TiO2), TZ (TiO2 / ZrO2), and ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2). In dielectric layer stacks such as TZAZ, TZAZT, ZAZT, TZ, and ZAZAT, Ta2O5 may be used instead of TiO2. Dielectric layer 151 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes with excellent step coverage.

[0051] An upper electrode 152 may be formed on the dielectric layer 151. The upper electrode 152 may include a metal-based material. For example, the upper electrode 152 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum nitride (MoN), titanium silicon nitride (TiSiN), or combinations thereof. The upper electrode 152 may be formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or an atomic layer deposition (ALD) process. According to embodiments of this disclosure, the upper electrode 152 may include titanium nitride (ALD-TiN) formed by an atomic layer deposition process.

[0052] According to another embodiment of this disclosure, the upper electrode 152 may have a multilayer structure. The upper electrode 152 can be formed by sequentially stacking a lower metal layer, a silicon-germanium layer, and an upper metal layer. The lower and upper metal layers may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or combinations thereof. For example, the lower metal layer may be titanium nitride, and the upper metal layer may be a WN / W layer in which tungsten nitride and tungsten are stacked. The silicon-germanium layer may be doped with boron.

[0053] Figures 2A-2P This is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 2A-2P It shows the manufacturing process. Figure 1 A process cross-sectional view of the method for developing semiconductor devices.

[0054] refer to Figure 2A A lower structure 12 can be formed on the substrate 11. The substrate 11 and the lower structure 12 can include components that are compatible with... Figure 1 The lower structure LB (including substrate 101) shown has the same structure. The lower structure 12 may include structures disposed on... Figure 1 The substrate 101 shown includes the gate structure BG, the bit line BL, the storage node contact 113, and the interlayer dielectric layer 112 disposed on the substrate 101.

[0055] Substrate 11 can be a material suitable for semiconductor processes. Substrate 11 may include a semiconductor substrate. Substrate 11 may be formed of a silicon-containing material. Substrate 11 may include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. Substrate 11 may also include other semiconductor materials, such as germanium. Substrate 11 may also include a group III / V semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 11 may include an SOI (silicon-on-insulator) substrate.

[0056] A molded stack MS can be formed on the lower structure 12. The molded stack MS may include multiple molding layers 14A and 16A and a lower support layer 15A. According to embodiments of the present disclosure, the molded stack MS may include a stacked structure of an etch stop layer 13A, a first molding layer 14A, a lower support layer 15A, and a second molding layer 16A.

[0057] When forming storage node vias, the etch stop layer 13A can serve as an etch endpoint. The etch stop layer 13A may include a material with etch selectivity relative to the first molding layer 14A. The etch stop layer 13A may include a dielectric material. For example, the etch stop layer 13A may include silicon nitride. The etch stop layer 13A can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) processes. The etch stop layer 13A can also use plasma to enhance the deposition effect. That is, the etch stop layer 13A can be formed using methods such as PECVD or PEALD.

[0058] The first molding layer 14A, the lower support layer 15A, and the second molding layer 16A can be used to provide openings for forming the lower electrode. According to another embodiment of this disclosure, the number of molding layers and the number of support layers can be increased or decreased as needed, such as the height of the storage node holes.

[0059] The first molding layer 14A and the second molding layer 16A may include a dielectric material. For example, each molding layer in the first molding layer 14A and the second molding layer 16A may include BSG (borosilicate glass), PSG (phossphosilicate glass), BPSG (borophosphosilicate glass), or TEOS (tetraethyl orthosilte). Each molding layer in the first molding layer 14A and the second molding layer 16A may be a single layer. According to another embodiment of the present disclosure, each molding layer in the first molding layer 14A and the second molding layer 16A may be a multilayer structure with at least two or more layers. For example, BPSG and TEOS may be stacked. According to another embodiment of the present disclosure, each molding layer in the first molding layer 14A and the second molding layer 16A may include an undoped silicon layer or an amorphous silicon layer.

[0060] The lower support layer 15A may include a material that is etch-selective relative to the first molding layer 14A and the second molding layer 16A. The thickness of the lower support layer 15A may be thinner than the thickness of each of the first molding layers 14A and the second molding layer 16A. The difficulty of the etching process can be reduced depending on the thickness of the lower support layer 15A and the thickness of the upper support layer to be formed by subsequent processes. For example, as the thickness of the lower support layer 15A decreases, the difficulty of the etching process can be reduced. The lower support layer 15A may include a nitrogen-containing material. For example, the lower support layer 15A may include silicon nitride or silicon carbonitride; however, the technical concept and scope of this disclosure are not limited thereto.

[0061] refer to Figure 2B An opening 17 can be formed. Multiple openings 17 spaced apart from each other in a horizontal direction parallel to the top surface of the substrate 11 can be formed. The characteristics of an opening 17 will be described with reference to a single opening. Thus, an opening 17 can expose a portion of the lower structure 12 by penetrating the molded stack MS. The molded stack MS in which the opening 17 is formed may include a stacked structure of an etch stop pattern 13, a first molded pattern 14, a lower support 15, and a second molded pattern 16. The opening 17 can provide an area for forming the lower electrode, and the opening 17 may be referred to as a "storage node via". The opening 17 may have a negative slope, where the linewidth narrows as the opening approaches the substrate (i.e., as the opening approaches the substrate).

[0062] To form the opening 17, a mask pattern can first be formed on the second molding layer 16A (see...). Figure 2A Subsequently, the second molding layer 16A can be sequentially etched using a mask pattern as an etch stop layer (see...).Figure 2A ), lower support layer 15A (see Figure 2A ) and the first molding layer 14A (see Figure 2A Subsequently, the etch stop layer 13A (see...) can be etched. Figure 2A The etching process is performed to form an opening 17 that exposes the lower structure 12. The lower structure 12 exposed by the opening 17 can be... Figure 1 The storage node contact 113 is shown.

[0063] Opening 17 may have a high aspect ratio. Aspect ratio can refer to the ratio of height to width. According to embodiments of this disclosure, a high aspect ratio may refer to an aspect ratio of at least about 10:1 or greater.

[0064] According to an embodiment, the opening 17 can be formed by etching the first molding layer 14A, the second molding layer 16A, and the lower support layer 15A. As a comparative example, when the upper support layer is formed beforehand on the second molding layer 16A, the etching height can be increased. When the etching height is increased, the etching process margin may decrease, and therefore, opening defects in the opening 17 may occur, or bending may occur in the opening 17.

[0065] However, according to the embodiment, since the upper support layer is not applied to the upper part of the second molding layer 16A when forming the opening 17, the etching burden can be reduced when forming the opening 17, and thus, opening defects or bending phenomena of the opening 17 can be prevented.

[0066] refer to Figure 2C A lower electrode material layer 18A can be formed in the opening 17.

[0067] The lower electrode material layer 18A may include a metal, a metal nitride, or a combination thereof. For example, the lower electrode material layer 18A may include at least one of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum titanium nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or a combination thereof. According to embodiments of this disclosure, the lower electrode material layer 18A may include titanium nitride (TiN). The lower electrode material layer 18A may include titanium nitride (ALD-TiN) formed by atomic layer deposition (ALD) process; however, the technical concept and scope of this disclosure are not limited thereto. According to another embodiment of this disclosure, the lower electrode material layer 18A may include a TiSiN / TiN stacked structure.

[0068] The lower electrode material layer 18A can be electrically connected to the substrate 11 through the lower structure 12. The lower electrode material layer 18A can be... Figure 1The storage node contact 113 shown is electrically connected to the substrate 11.

[0069] refer to Figure 2D Multiple lower electrodes 18 can be formed. The lower electrodes 18 can be disposed in the opening 17. The lower electrodes 18 can be formed by an isolation process.

[0070] The isolation process can be performed using a polishing process. For example, the polishing process may include a chemical mechanical polishing (CMP) process or an etching-back process. The lower electrode material layer 18A above the second molding pattern 16 can be completely etched using the isolation process (see [link to isolation process]). Figure 2C Therefore, the upper surface of the lower electrode 18 can be positioned at the same level as the upper surface of the second molded pattern 16.

[0071] refer to Figure 2E The second molded pattern 16 can be etched to a predetermined height h1 to expose the upper portion 18T of the lower electrode.

[0072] The second molded pattern 16 can be etched using an oxide etching process.

[0073] refer to Figure 2F By etching and adjusting the second molding pattern 16, the lower electrode adjustment portion 18P separated by the recess R formed between the lower electrode adjustment portions 18P can be formed.

[0074] The upper portion 18T, exposed by etching the second molded pattern 16 through the lower electrode (see... Figure 2E A trimming process is performed to form the trimmed portion 18P of the lower electrode. The remaining lower electrode 18 that has not undergone the trimming process may be referred to as the "lower portion of the lower electrode" or the "untrimmed portion". The linewidth of each trimmed portion 18P may be at least narrower than the linewidth of the uppermost portion of the untrimmed portion. The linewidth of each trimmed portion 18P may be adjusted to the minimum linewidth within a range that does not result in bending. The linewidth of each trimmed portion 18P may be narrower than the linewidth of the lower surface of the untrimmed portion; however, the technical concept and scope of this disclosure are not limited thereto.

[0075] The adjustment portion 18P can be positioned at a level higher than the upper surface of the second molded pattern 16. The height of the adjustment portion 18P can be adjusted to... Figure 2E The height h1 of the recessed portion of the second molded pattern 16. That is, the height of the trimmed portion 18P can be defined as "h1", which is the etching height of the second molded pattern 16. Each trimmed portion in the trimmed portion 18P can be continuous with the corresponding non-trimmed portion in the non-trimmed portion to form an integral structure.

[0076] Because the linewidth of each trimmed portion 18P becomes narrower than the linewidth of the uppermost part of the non-trimmed portion, the upper surface of the non-trimmed portion can be partially exposed. In the following text, the exposed upper surface of each non-trimmed portion may be referred to as "shoulder portion 18S". The portion where the trimmed portion 18P and shoulder portion 18S are coupled may be rounded. The linewidth of shoulder portion 18S can be adjusted according to the linewidth of trimmed portion 18P. The linewidth of shoulder portion 18S can be inversely proportional to the linewidth of trimmed portion 18P. That is, as the linewidth of trimmed portion 18P decreases, the linewidth of shoulder portion 18S can increase.

[0077] refer to Figure 2G A pyrolytic layer 19 can be formed to surround the sides of the trimmed portion 18P. The pyrolytic layer 19 can be gap-filled between the trimmed portions 18P on the second molding pattern 16. The pyrolytic layer 19 can be formed at a height such that a portion of the upper surface and side surface of the trimmed portion 18P is exposed.

[0078] The pyrolytic layer 19 may comprise a material that decomposes at or above 500°C. The pyrolytic layer 19 can be formed between the trimmed portions 18P without voids by a deposition process and a reflow process. For example, after the pyrolytic layer 19 is formed on the second molding pattern 16 and the trimmed portions 18P, a reflow process can be performed so that the gaps in the pyrolytic layer 19 fill the spaces between the lower electrode trimmed portions 18P without voids. According to another embodiment of this disclosure, the reflow process can be omitted when the pyrolytic layer 19 can be deposited without voids.

[0079] The pyrolysis layer 19 may include a polymer, i.e., a high molecular weight material. The pyrolysis layer 19 may be deposited at a temperature of about 100°C to 150°C. The reflow process of the pyrolysis layer 19 may be performed at a temperature of about 180°C to 220°C; however, the technical concept and scope of the present invention are not limited thereto.

[0080] The pyrolysis layer 19 can be adjusted to fill the gaps between the trimming portions 18P with a thickness of h2. Therefore, a portion of the upper surface and side surface of the trimming portions 18P can be exposed on the pyrolysis layer 19.

[0081] refer to Figure 2H The inner liner 20A of the support can be conformally formed on the pyrolysis layer 19 and the trimming portion 18P.

[0082] The inner liner 20A of the support can be formed at a temperature lower than the temperature at which the pyrolysis layer 19 is decomposed. According to embodiments of the present disclosure, the inner liner 20A of the support can be formed at a temperature of at least about 50°C or lower to prevent potential loss due to heat; however, the technical concept and scope of the present disclosure are not limited thereto.

[0083] The inner liner 20A of the support can cover the upper portion of the pyrolysis layer 19 and the upper portion and exposed sides of the trimmed portion 18P. The inner liner 20A of the support can be an inner liner shape that uniformly covers the contour of the upper portion of the entire structure. The thickness of the inner liner 20A of the support can be thinner than the thickness of each of the pyrolysis layer 19 and the lower support 15.

[0084] The substrate liner 20A may include a dielectric material that is etch-selective relative to the pyrolysis layer 19 and the lower electrode 18. For example, the substrate liner 20A may include silicon nitride or silicon carbonitride.

[0085] refer to Figure 2I Heat treatment can be performed. Therefore, the pyrolysis layer 19 may be decomposed and volatilized. For example, heat treatment can be performed at a temperature of at least about 500°C or higher. According to an embodiment, heat treatment can be performed at a temperature of about 500°C to 550°C.

[0086] refer to Figure 2J A horizontal hierarchical gap 19S can be formed between the inner lining 20A of the support body and the second molded pattern 16. The horizontal hierarchical gap 19S can be formed by... Figure 2I The result of heat treatment to remove the pyrolysis layer 19 is shown.

[0087] The inner lining 20A and the unadjusted portion of the support can be spaced apart from each other by a horizontal hierarchical gap 19S. Furthermore, the horizontal hierarchical gap 19S can expose a portion of the sidewall of each of the adjusting portion 18P and the shoulder portion 18S.

[0088] refer to Figure 2K A first upper support layer 21A and a second upper support layer 22A may be sequentially formed on the inner liner layer 20A of the support. The first upper support layer 21A and the second upper support layer 22A may include materials with etching selectivity relative to the first molding pattern 14 and the second molding pattern 16. The first upper support layer 21A and the second upper support layer 22A may include dielectric materials. For example, the first upper support layer 21A and the second upper support layer 22A may include silicon nitride or silicon carbonitride; however, the technical concept and scope of this disclosure are not limited thereto.

[0089] A first upper support layer 21A may be formed on top of the inner liner 20A of the support body. The first upper support layer 21A may be formed to have a thickness sufficient to fill the gaps between the trimming portions 18P. The thickness of the first upper support layer 21A may be greater than the thickness of the trimming portions 18P covered by the inner liner 20A of the support body. The first upper support layer 21A may also be formed between the trimming portions 18P and in the region overlapping with the upper portion of the trimming portions 18P.

[0090] A second upper support layer 22A may be formed on top of the first upper support layer 21A. The first upper support layer 21A and the second upper support layer 22A may be formed of the same material. According to another embodiment of this disclosure, the first upper support layer 21A and the second upper support layer 22A may be formed of different materials.

[0091] According to the embodiments, refer to Figure 2F By forming a trimmed portion 18P whose linewidth is narrowed due to the trimming process, the area (or volume) of the first upper support layer 21A that fills the gap between the lower electrodes 18 can be increased. Therefore, the supporting force of the support can be increased.

[0092] refer to Figure 2L An upper support USP including an upper support hole 23 can be formed. The upper support hole 23 can be formed by a series of processes including: forming a mask pattern over the second upper support layer 22A, and then using the mask pattern as an etching barrier layer to... Figure 2K The second upper support layer 22A, the first upper support layer 21A, and the inner liner layer 20A of the support layer are sequentially etched.

[0093] When the upper support hole 23 is formed, the exposed portion of the second molded pattern 16 may be lost; however, the technical concept and scope of this disclosure are not limited thereto.

[0094] The upper support hole 23 can be formed in a circular, elliptical, or polygonal shape. The upper support hole 23 can be disposed between the lower electrodes 18. According to embodiments of this disclosure, adjacent lower electrodes 18 can share a single upper support hole 23.

[0095] According to embodiments of this disclosure, reference is made to Figure 2F By forming the trimming portions 18P, the process difficulty of forming the upper support hole 23 can be reduced. That is, due to the trimming process, the gap between the trimming portions 18P is widened, thus reducing the patterning and etching difficulty of the mask process used to form the upper support hole 23.

[0096] The horizontal hierarchical gap 19S and the second molded pattern 16 can be exposed through the upper support hole 23.

[0097] refer to Figure 2M The second molded pattern 16 can be removed (see...) Figure 2L ).

[0098] The second molded pattern 16 can be removed by a wet leaching process. The wet chemical used to remove the second molded pattern 16 can be supplied through the upper support hole 23. The wet chemical may include a wet chemical for removing oxides. For example, one or more chemicals such as HF, NH4F / NH4OH, H2O2, HCl, HNO3, H2SO4, etc., can be used as the wet chemical.

[0099] When the second molding pattern 16 is removed, the upper support USP, which has etching selectivity relative to wet chemicals, may remain intact instead of being removed. When the second molding pattern 16 is removed, a second molding gap 16M may be formed that exposes a portion of the outer wall of the lower electrode 18.

[0100] Since the surface oxide layer of the lower electrode 18 is removed during the wet leaching process, the linewidth of the lower electrode 18 can be reduced.

[0101] refer to Figure 2N A lower support hole 15H can be formed. The lower support hole 15H can be formed to facilitate the removal of the first molding pattern 14. The opening area of ​​the lower support hole 15H can be the same as the cross-sectional area of ​​the upper support hole 23. The lower support hole 15H can be formed by etching the lower support 15 exposed by the second molding gap 16M.

[0102] refer to Figure 2O The first molded pattern 14 can be removed (see...) Figure 2N ).

[0103] The first molded pattern 14 can be removed by a wet leaching process. The wet chemical used to remove the first molded pattern 14 can be supplied through the lower support hole 15H. The wet chemical may include wet chemicals suitable for removing oxides, such as, for example, HF, NH4F / NH4OH, H2O2, HCl, HNO3, H2SO4, etc.

[0104] When the second molding pattern 16 is removed, the lower support 15 and the upper support USP, which have etching selectivity relative to wet chemicals, may not be removed and can remain essentially unchanged. When the first molding pattern 14 is removed, a first molding gap 14M can be formed to expose the outer wall of the lower electrode 18.

[0105] Since the surface oxide layer of the lower electrode 18 is removed during the wet leaching process, the linewidth of the lower electrode 18 can be reduced.

[0106] The outer wall of the lower electrode 18 can be exposed through the first molding gap 14M, the second molding gap 16M, and the horizontal layer gap 19S. Except for the area overlapping with the lower support 15 and the upper support USP, all outer walls of the lower electrode 18 can be exposed. The lower electrode 18 can be supported by the lower support 15 and the upper support USP, thus improving the structural stability of the lower electrode 18 and preventing its collapse. Furthermore, according to the embodiment, since trimmed portions 18P with reduced linewidths are formed on the lower electrode through a trimming process, the volume of the upper support USP disposed between the trimmed portions 18P can be increased. Therefore, the supporting force of the support can be increased.

[0107] refer to Figure 2P A dielectric layer 24 can be formed on the lower electrode 18, the lower support 15, and the upper support USP. A portion of the dielectric layer 24 can cover the etch stop pattern 13. The dielectric layer 24 can uniformly cover the outer wall of the lower electrode 18, the surface of the lower support 15, and the surface of the upper support USP. The dielectric layer 24 can cover the outer wall of the lower electrode 18, a portion of the sidewall of the trim portion 18P, and the shoulder portion 18S. Therefore, the area of ​​the dielectric layer 24 can be increased proportionally to the linewidth of the shoulder portion 18S, thereby increasing the capacitance.

[0108] The dielectric layer 24 may comprise a high-k material having a higher dielectric constant than silicon oxide. High-k materials may include zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of this disclosure, the dielectric layer 24 may be formed of a composite layer comprising two or more layers of the aforementioned high-k materials. According to embodiments of this disclosure, the dielectric layer 24 may be formed of a zirconium oxide-based material having excellent leakage current characteristics while sufficiently reducing the equivalent oxide thickness (EOT). For example, dielectric layer 24 may include one of the following: ZAZ (ZrO2 / Al2O3 / ZrO2), TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2), TZAZT (TiO2 / ZrO2 / Al2O3 / ZrO2 / TiO2), ZAZT (ZrO2 / Al2O3 / ZrO2 / TiO2), TZ (TiO2 / ZrO2), and ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2). In dielectric layer stacks such as TZAZ, TZAZT, ZAZT, TZ, and ZAZAT, Ta2O5 may be used instead of TiO2. Dielectric layer 24 may be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes with excellent step coverage.

[0109] An upper electrode 25 may be formed on the dielectric layer 24. The upper electrode 25 may comprise a metal-based material. For example, the upper electrode 25 may comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum nitride (MoN), titanium silicon nitride (TiSiN), or combinations thereof. The upper electrode 25 may be formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or an atomic layer deposition (ALD) process. According to one embodiment of this disclosure, the upper electrode 25 may comprise titanium nitride (ALD-TiN) formed by an atomic layer deposition process.

[0110] According to another embodiment of this disclosure, the upper electrode 25 may have a multilayer structure. The upper electrode 25 can be formed by sequentially stacking a lower metal layer, a silicon-germanium layer, and an upper metal layer. The lower and upper metal layers may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or combinations thereof. For example, the lower metal layer may be titanium nitride, and the upper metal layer may be a WN / W layer in which tungsten nitride and tungsten are stacked. The silicon-germanium layer may be doped with boron. To form the upper electrode 25, processes for depositing an upper electrode layer (not shown) and for patterning the upper electrode can be performed.

[0111] According to embodiments of this disclosure, capacitance can be increased by applying pyrolytic polymers.

[0112] According to embodiments of this disclosure, by applying an upper support after forming the lower electrode, the process complexity can be reduced and the reliability of the semiconductor can be increased.

[0113] While embodiments of this disclosure have been described with reference to specific embodiments, various other changes and modifications can be made by those skilled in the art without departing from the technical concept and scope of this disclosure as defined by the appended claims. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A molded stack is formed on a substrate, the molded stack comprising a plurality of molded layers and an underlying support layer; Multiple lower electrodes having lower and upper portions are formed in the molding stack; The upper portion of the lower electrode is exposed by recessing the upper surface of the molded stack; The trimmed portion is formed by trimming the exposed upper portion of the lower electrode; A pyrolysis layer is formed surrounding the lower side of the adjusted portion; A support inner liner is formed on the pyrolysis layer and the trimmed portion; By removing the pyrolysis layer, a horizontal hierarchical gap is formed that exposes the outer wall of the trimmed portion; An upper support layer is formed on top of the inner liner of the support body; Support holes that expose the horizontal hierarchical gaps are formed by etching the upper support layer and the inner liner of the support layer. as well as The outer wall of the lower portion of the lower electrode is exposed by removing the molding layer through the support hole and the horizontal hierarchical gap.

2. The method as described in claim 1, wherein, The steps for forming the pyrolysis layer include: A pyrolysis layer is deposited on the molded stack and the trimmed portion; and Perform the reflow process.

3. The method as described in claim 1, wherein, The pyrolysis layer comprises a polymer material that pyrolyzes at a temperature of at least about 500°C or higher.

4. The method of claim 2, wherein, The deposition of the pyrolysis layer is performed at a temperature of approximately 100°C to 150°C.

5. The method of claim 2, wherein, The reflux process is performed at a temperature of approximately 180°C to 220°C.

6. The method of claim 1, wherein, The removal of the pyrolysis layer is performed by heat treatment.

7. The method of claim 6, wherein, The heat treatment is performed at a temperature of approximately 500°C to 550°C.

8. The method of claim 1, wherein, The step of forming the molded stack includes sequentially forming a first molding layer, a lower support layer, and a second molding layer on the substrate.

9. The method of claim 1, wherein, The steps for forming the lower electrode include: An opening is formed by etching the molded stack to expose a portion of the substrate; A lower electrode material layer is formed to fill the gaps in the opening; and An isolation process is performed on the lower electrode material layer.

10. The method of claim 8, wherein, The step of exposing the outer wall of the lower portion of the lower electrode by removing the molding layer through the support hole and the horizontal hierarchical gap includes: Remove the second molding layer; The lower support layer is etched to form the lower support hole; and Remove the first molding layer.

11. The method of claim 10, wherein, The removal of the second molding layer and the removal of the first molding layer are performed by a wet leaching process.

12. The method of claim 1, further comprising: After exposing the outer wall of the lower portion of the lower electrode, A dielectric layer is formed along the outer wall of the lower electrode; as well as An upper electrode is formed on the dielectric layer.

13. A semiconductor device, comprising: The lower electrode array, each lower electrode includes a first pillar portion and a second pillar portion, the second pillar portion being disposed above the first pillar portion and having a linewidth narrower than the first pillar portion; A lower support body, the lower support body being adapted to support the outer wall of the first column portion of the lower electrode; An upper support body, the upper support body being adapted to support the upper portion and outer wall of the second column portion of the lower electrode; A dielectric layer adapted to cover the lower electrode, the lower support, and the upper support; as well as The upper electrode is located above the dielectric layer.

14. The semiconductor device of claim 13, wherein, The first pillar portion and the second pillar portion of each lower electrode are continuous to form an integral structure.

15. The semiconductor device of claim 13, wherein, The bottom surface of the upper support is spaced apart from the upper surface of the first column portion.

16. The semiconductor device of claim 13, wherein, The upper support includes: A support liner adapted to cover a portion of the upper surface and sidewall of the second column portion of the lower electrode; A first upper support body, the first upper support body being adapted to fill the gaps between the second column portions above the support liner; and The second upper support is located above the first upper support.

17. The semiconductor device of claim 13, wherein, The lower support and the upper support are silicon nitride or silicon carbonitride.

18. The semiconductor device of claim 13, wherein, The thickness of the lower support is thinner than the thickness of the upper support.

19. A method for manufacturing a semiconductor device, the method comprising: A molded stack is formed on a substrate, the molded stack including a lower support layer; The lower electrode is formed in the molded stack; This exposes the upper portion of the lower electrode; The exposed upper portion of the lower electrode is trimmed to form a trimmed portion of the lower electrode, which is exposed on the molded stack. The lower side of the trimmed portion is surrounded by a pyrolysis layer; A support inner liner is formed to surround the top surface of the trimmed portion of the lower electrode and the pyrolysis layer; as well as An upper support layer is formed on top of the inner liner of the support body.

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