Semiconductor device and preparation method thereof
By achieving source and drain isolation in group III nitride HEMT devices through a closed-gate structure, the problem of increased cost and risk due to additional processes in existing technologies is solved, enabling low-cost and high-reliability device fabrication.
Patent Information
- Application Number
- CN202411088769.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-08
- Publication Date
- 2026-02-10
AI Technical Summary
Existing group III nitride HEMT devices require additional dry etching or ion implantation processes during fabrication, which increases process costs and reduces yield and reliability, and poses risks of metal interconnect breakage and local electric field concentration.
A closed-gate structure is used to isolate the source and drain during gate fabrication. The gate switches to isolate the source under the off-bias voltage and turn on under the on-bias voltage through the switching effect of the gate.
No additional etching or ion implantation processes are required, reducing manufacturing costs, improving product yield and reliability, and avoiding the risks of metal breakage and electric field concentration.
Smart Images
Figure CN121510620A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a novel group III nitride semiconductor device and its fabrication method, and particularly to a novel group III nitride semiconductor device and its fabrication method that can achieve source-drain controllable pinch-off without special active region design or isolation process, belonging to the field of semiconductor electronic devices. Background Technology
[0002] Group III nitride semiconductors are known as third-generation semiconductors, possessing advantages such as large bandgap, good chemical stability, and high breakdown voltage. Moreover, high electron mobility transistors (HEMTs) composed of heterostructures such as AlGaN / GaN have the advantages of high electron concentration and mobility, exhibiting excellent performance in high frequency, high voltage withstand, and low on-resistance. They can be used as core devices in various power conversion systems and have broad prospects in power supply applications such as consumer electronics, 5G base stations, and servers.
[0003] Typically, the epitaxial growth of GaN-based materials involves atomically flattening, resulting in a two-dimensional electron gas (2DEG) induced by the AlGaN / GaN heterostructure, which exists and is uniformly distributed throughout the entire wafer surface. To achieve independent operation of the device and isolation between the source and drain electrodes, the 2DEG in other regions needs to be eliminated during device fabrication to form a high-resistivity state, thereby isolating the active region of the device. Within the active region, the source and drain are isolated by a gate, enabling controllable conduction from the drain to the source.
[0004] In conventional semiconductor device fabrication, the active region is typically protected by a photoresist mask. Then, the lattice structure of the unprotected region is disrupted through methods such as dry etching or ion implantation, causing the 2DEG to disappear and forming a high-resistivity state. (See appendix for details.) Figures 1-3 .
[0005] The structure of a conventional group III nitride HEMT device is shown in the attached figure. Figure 1 As shown, a group III nitride HEMT device includes a group III nitride HEMT epitaxial structure and a gate 106A, a source 107A, and a drain 108A. The group III nitride HEMT epitaxial structure includes a transition layer 102, a high-resistivity breakdown layer 103, a conductive channel layer 104, and a barrier layer 105 sequentially stacked on a substrate 101. The group III nitride HEMT epitaxial structure has an active region 109 isolated and fabricated using a dry etching process. The planar structure of the device is often shown in the attached figure. Figure 2a , Figure 2b As shown, the device also includes a gate lead / pad 106B, a source lead / pad 107B, and a drain lead / pad 108B. The active region 109 contains the gate 106A, the source 107A, and the drain 108A simultaneously.
[0006] In addition, the structure of another traditional group III nitride HEMT device is shown in the attached figure. Figure 3 As shown, the group III nitride HEMT device includes a group III nitride HEMT epitaxial structure and a gate 206A, a source 207A, and a drain 208A. The group III nitride HEMT epitaxial structure includes a transition layer 202, a high-resistivity breakdown layer 203, a conductive channel layer 204, and a barrier layer 205 sequentially stacked on a substrate 201. The group III nitride HEMT epitaxial structure has an active region 209 fabricated using an ion implantation process.
[0007] Existing active region isolation techniques for group III nitride-enhanced HEMTs mostly involve dry etching of the barrier layer or ion implantation to destroy the 2DEG, which have significant shortcomings compared to the proposed solution:
[0008] First, the aforementioned existing technologies require an additional dry etching equipment or ion implantation process. The addition of a process inevitably leads to a greater investment of resources, such as specialized equipment and manpower, thereby increasing process costs. At the same time, a longer process means a decrease in yield, which will further increase manufacturing costs.
[0009] Secondly, the active region prepared by the existing dry etching technology is a mesa structure (see attached image). Figure 1 109 in section 2, appendix Figure 3 In the 209), there is a step between the active region and the isolation region, which increases the process difficulty of other processes in the device fabrication process. For example, there are problems such as the risk of breakage of metal interconnects and local electric field concentration, which in turn leads to negative effects such as reduced device processing yield, reduced lifespan and reliability.
[0010] Third, the existing ion implantation methods for preparing active regions have high requirements for ion concentration and depth. Inappropriate processes can easily lead to problems such as excessive leakage current and poor reliability in the off-state of the device. At the same time, the ion implantation process has extremely high requirements for photoresist removal technology. If the photoresist is not cleaned properly, it will bring about a number of other related problems, such as dielectric deposition voids and metal deposition defects. Summary of the Invention
[0011] The main objective of this invention is to provide a semiconductor device and its fabrication method. The device isolates the source and drain by using an in-plane gate structure that surrounds the source and / or drain. This closed-gate structure achieves complete isolation between the source and drain when a gate-off bias voltage is applied, and enables conduction between the source and drain when a gate-on bias voltage is applied. This invention cleverly utilizes the switching isolation effect of the gate, achieving complete isolation of the source and drain electrodes within a uniformly distributed 2DEG wafer surface without etching or ion implantation processes. This ultimately results in a low-cost, high-reliability HEMT device, overcoming the shortcomings of existing technologies.
[0012] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0013] A first aspect of the present invention provides a semiconductor device including an epitaxial structure and a source, a drain, and a gate matched with the epitaxial structure. The epitaxial structure includes a heterostructure having a carrier channel. The source and the drain are electrically connected through the carrier channel. The gate is a closed ring structure. The source and / or the drain are independently surrounded by the gate. The source and the drain are isolated by the gate. When a turn-off bias voltage is applied to the gate, the source and the drain are electrically isolated. When a turn-on bias voltage is applied to the gate, the source and the drain are electrically connected.
[0014] A second aspect of this invention discloses a method for fabricating a semiconductor device, comprising fabricating an epitaxial structure and a source, drain, and gate electrode matched with the epitaxial structure, wherein the epitaxial structure includes a heterostructure, a carrier channel is formed within the heterostructure, the source and the drain are electrically connected via the carrier channel, and the method for fabricating the semiconductor device further comprises:
[0015] A gate with a closed ring structure is fabricated, and the source and / or the drain are independently surrounded by the gate, with the source and the drain isolated by the gate; when a turn-off bias voltage is applied to the gate, the source and the drain are electrically isolated, and when a turn-on bias voltage is applied to the gate, the source and the drain are electrically connected.
[0016] Compared with the prior art, the advantages of the present invention include:
[0017] 1) The closed gate structure used in this invention can completely isolate the source and drain at the same time as the gate is fabricated, without the need for additional dry etching or ion implantation processes to isolate the active region structure. Compared with the traditional HEMT device fabrication method, the process of this invention is shorter, without the need for additional etching equipment or ion implantation equipment, and the manufacturing cost is lower.
[0018] 2) Compared with the traditional technique of etching mesa to prepare active regions, the closed gate structure used in this invention does not have the risk of metal breakage or local electric field concentration caused by steps during the source, drain and gate interconnection process, and the prepared products have higher yield and reliability.
[0019] 3) Compared with the traditional technology of ion implantation isolation method for preparing active regions, the present invention adopts a closed gate structure, which eliminates the risk of abnormally difficult removal due to photoresist and other mask deformation caused by ion implantation, and can greatly improve the yield and reliability of products. Attached Figure Description
[0020] Figure 1 This is a schematic cross-sectional view of a traditional group III nitride HEMT device structure;
[0021] Figure 2a , Figure 2b This is a schematic diagram of a traditional group III nitride HEMT structure.
[0022] Figure 3 This is a cross-sectional schematic diagram of another traditional group III nitride HEMT structure;
[0023] Figure 4 This is a schematic cross-sectional view of a group III nitride HEMT device provided in a typical embodiment of the present invention;
[0024] Figure 5a This is a planar schematic diagram of a group III nitride HEMT device provided in a typical embodiment of the present invention;
[0025] Figure 5b yes Figure 5a A schematic diagram of a local structure in the image;
[0026] Figure 6 This is a schematic diagram of the epitaxial structure of a group III nitride HEMT device provided in a typical embodiment of the present invention;
[0027] Figure 7 This is a schematic diagram of the epitaxial structure after removing the gate from the non-gate region;
[0028] Figure 8 This is a schematic diagram of the FET structure after the source and drain are formed in a typical embodiment of the present invention;
[0029] Figure 9 This is a schematic diagram of the structure of a group III nitride HEMT device forming a gate field plate in a typical embodiment of the present invention;
[0030] Figure 10This is a schematic diagram of the structure of a group III nitride HEMT device with a source field plate and source-drain interconnect metal in a typical embodiment of the present invention.
[0031] Figure 11 This is a schematic diagram of the structure of a group III nitride HEMT device after the formation of a protective layer in a typical embodiment of the present invention. Detailed Implementation
[0032] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.
[0033] The present invention employs a closed gate to surround the source and the source-related lead / bonding area, or a closed gate to surround the drain and the drain-related lead / bonding area, or a closed gate to simultaneously surround the source, drain and their related lead / bonding areas. This solution can achieve complete isolation between the source and drain in the off state within a single chip, while not affecting the conduction between the source and drain in the on state.
[0034] A first aspect of the present invention provides a semiconductor device including an epitaxial structure and a source, a drain, and a gate matched with the epitaxial structure. The epitaxial structure includes a heterostructure having a carrier channel. The source and the drain are electrically connected through the carrier channel. The gate is a closed ring structure. The source and / or the drain are independently surrounded by the gate. The source and the drain are isolated by the gate. When a turn-off bias voltage is applied to the gate, the source and the drain are electrically isolated. When a turn-on bias voltage is applied to the gate, the source and the drain are electrically connected.
[0035] In a more specific embodiment, the semiconductor device includes: a plurality of sources and / or a plurality of drains, wherein the plurality of sources are spaced apart and each of the plurality of sources is independently surrounded by a gate; and the plurality of drains are spaced apart and each of the plurality of sources is independently surrounded by a gate.
[0036] Furthermore, the plurality of sources and the plurality of drains are arranged alternately at intervals.
[0037] Furthermore, the width of the gate is 1nm-5000nm.
[0038] Furthermore, the spacing between different regions of the gate and the source and / or drain is equal.
[0039] Furthermore, the spacing between the gate and the drain is greater than the spacing between the gate and the source, so that the drain can withstand a higher off-state voltage without being rapidly broken down.
[0040] In a more specific embodiment, the semiconductor device further includes: a source lead / pad, a drain lead / pad, and a gate lead / pad, wherein the source lead / pad, the drain lead / pad, and the gate lead / pad are respectively electrically connected to the source, the drain, and the gate, and wherein the source lead / pad and / or the drain lead / pad are also independently surrounded by the gate.
[0041] In a more specific implementation, the semiconductor device further includes: a source field plate and a gate field plate, wherein the source field plate is electrically connected to the source and the gate field plate is electrically connected to the gate.
[0042] In a more specific embodiment, the semiconductor device further includes:
[0043] A first insulating dielectric layer covers the source, the drain, the gate, and the epitaxial structure, and the gate lead / pad is disposed on the first insulating dielectric layer and electrically connected to the gate;
[0044] A second insulating dielectric layer covers the gate lead / pad and the first insulating dielectric layer. The source lead / pad and the drain lead / pad are disposed on the second insulating dielectric layer and are electrically connected to the source and the drain, respectively.
[0045] A protective layer is disposed on the second insulating dielectric layer and covers the area not covered by the source lead / pad and the drain lead / pad.
[0046] Furthermore, the first insulating dielectric layer may be SiN. x The second insulating dielectric layer may be SiN, etc. x / SiO2 / SiN x The structure is a stacked structure, and the protective layer can be a SiO2 layer or the like.
[0047] Furthermore, the gate field plate is disposed between the first insulating dielectric layer and the second insulating dielectric layer, and the source field plate is disposed on the second insulating dielectric layer.
[0048] Furthermore, the gate includes various gate structures such as MIS / MOS gate, p-type gate, or ion-implanted gate.
[0049] Furthermore, the material of the heterostructure is a group III nitride; for example, the heterostructure can be an AlGaN / GaN heterostructure.
[0050] Furthermore, the semiconductor device includes a HEMT device, specifically, the HEMT device may be an enhancement-mode or depletion-mode device.
[0051] A second aspect of this invention discloses a method for fabricating a semiconductor device, comprising fabricating an epitaxial structure and a source, drain, and gate electrode matched with the epitaxial structure, wherein the epitaxial structure includes a heterostructure, a carrier channel is formed within the heterostructure, the source and the drain are electrically connected via the carrier channel, and the method for fabricating the semiconductor device further comprises:
[0052] A gate with a closed ring structure is fabricated, and the source and / or the drain are independently surrounded by the gate, with the source and the drain isolated by the gate; when a turn-off bias voltage is applied to the gate, the source and the drain are electrically isolated, and when a turn-on bias voltage is applied to the gate, the source and the drain are electrically connected.
[0053] In a more specific implementation scheme, the method for fabricating the semiconductor device specifically includes:
[0054] First, a gate with a closed ring structure is formed in the gate region of the heterostructure, the gate independently surrounding the source region and / or drain region in a plane;
[0055] A source electrode is formed in the source region of the heterostructure, and a drain electrode is formed in the drain region. The source electrode and the drain electrode are isolated by the gate electrode.
[0056] In a more specific embodiment, the method for fabricating the semiconductor device specifically includes: forming a plurality of source electrodes and / or a plurality of drain electrodes, wherein the plurality of source electrodes are spaced apart and each of the plurality of source electrodes is independently surrounded by the gate electrode; wherein the plurality of drain electrodes are spaced apart and each of the plurality of source electrodes is independently surrounded by the gate electrode.
[0057] Furthermore, the plurality of sources and the plurality of drains are arranged alternately at intervals.
[0058] Furthermore, the width of the gate is 1nm-5000nm.
[0059] Furthermore, the spacing between different regions of the gate and the source and / or drain is equal.
[0060] Furthermore, the distance between the gate and the drain is greater than the distance between the gate and the source.
[0061] In a more specific embodiment, the method for fabricating the semiconductor device further includes: fabricating source leads / pads, drain leads / pads, and gate leads / pads, wherein the source leads / pads, drain leads / pads, and gate leads / pads are electrically connected to the source, drain, and gate, respectively, wherein the source leads / pads and / or the drain leads / pads are also independently surrounded by the gate.
[0062] In a more specific implementation, the method for fabricating the semiconductor device further includes: fabricating a source field plate and a gate field plate, wherein the source field plate is electrically connected to the source and the gate field plate is electrically connected to the gate.
[0063] In a more specific implementation scheme, the method for fabricating the semiconductor device specifically includes:
[0064] A first insulating dielectric layer is formed, and the first insulating dielectric layer covers the source, the drain, the gate and the epitaxial structure. The gate lead / pad is formed on the first insulating dielectric layer and the gate lead / pad is electrically connected to the gate.
[0065] A second insulating dielectric layer is formed, and the second insulating dielectric layer covers the gate lead / pad and the first insulating dielectric layer. The source lead / pad and the drain lead / pad are formed on the second insulating dielectric layer, and the source lead / pad and the drain lead / pad are electrically connected to the source and the drain, respectively.
[0066] A protective layer is formed, and the protective layer covers a second insulating dielectric layer that is not covered by the source lead / pad or the drain lead / pad.
[0067] Furthermore, the gate includes various gate structures such as MIS / MOS gate, p-type gate, or ion-implanted gate.
[0068] Furthermore, the material of the heterostructure is a group III nitride; for example, the heterostructure can be an AlGaN / GaN heterostructure.
[0069] Furthermore, the semiconductor device includes a HEMT device, specifically, the HEMT device may be an enhancement-mode or depletion-mode device.
[0070] The following will provide a further explanation of the technical solution, its implementation process, and its principles, in conjunction with the accompanying drawings and specific implementation examples.
[0071] Please see Figure 4A group III nitride HEMT device includes: an HEMT epitaxial wafer (i.e., the aforementioned epitaxial structure) and a gate contact structure (which can be understood as a gate or a part of a gate) 306A, a source contact structure (which can be understood as a source or a part of a source) 307A, and a drain contact structure (which can be understood as a drain or a part of a drain) 308A. The HEMT epitaxial wafer includes a transition layer 302, a high-resistivity layer 303, a channel layer 304, and a barrier layer 305 sequentially stacked on a substrate 301. A two-dimensional electron gas is formed between the channel layer 304 and the barrier layer 305. The source contact structure 307A and the drain contact structure 308A are electrically connected through the two-dimensional electron gas. The gate contact structure 306A is disposed on the barrier layer 305.
[0072] Please refer to the following: Figure 5a , Figure 5b The group III nitride HEMT device also includes a source lead / pad 307B and a drain lead / pad 308B. The source lead / pad 307B and the drain lead / pad 308B are electrically connected to the source contact structure 307A and the drain contact structure 308A, respectively. The gate contact structure 306A is a closed ring structure that surrounds the source contact structure 307A and the source lead / pad 307B. Of course, the gate contact structure 306A can also surround the drain contact structure 308A and the drain lead / pad 308B.
[0073] It should be noted that this group III nitride HEMT device may also include more structures, such as a gate field plate and its dielectric, a source field plate and its dielectric, etc. Only the core technical part of the present invention is described here; the specific fabrication methods can be found in the various embodiments.
[0074] Example 1
[0075] A method for fabricating a GaN HEMT device includes the following steps:
[0076] 1) Using metal-organic vapor deposition (MOCVD), a 600 nm AlN / AlGaN transition layer structure 302 and a 4 μm C-doped Al2O3 layer were sequentially deposited on a Si<1 11> substrate 301. 0.07 Ga 0.93 High-resistivity layer 303, 300nm high-quality, low-electron-concentration unintentionally doped GaN channel layer 304, 15nm Al 0.25 Ga 0.75 The N-barrier layer has a Mg doping concentration of ~3x10⁻¹⁰ nm at 305 nm and 100 nm. 19 cm -3The p-GaN layer 306 is used to obtain an enhanced AlGaN / GaN heterostructure HEMT epitaxial wafer (hereinafter referred to as HEMT epitaxial wafer), such as... Figure 6 As shown, the unintentionally doped GaN channel layer 304 and Al 0.25 Ga 0.75 There is a 2DEG (two-dimensional electron gas) between the N-barrier layers 305.
[0077] 2) A photoresist is formed on the surface of the HEMT epitaxial wafer as a mask, and the wafer is placed in an inductively coupled plasma (ICP) etching apparatus. Low-speed etching and oxygen-containing self-terminating etching are used to remove the p-GaN layer 306 in the non-gate region to restore the 2DEG in that region as a conductive channel (e.g., ...). Figure 7 The remaining p-GaN layer 306 serves as the gate contact structure 306A, and the mask is removed.
[0078] It is important to note that in this process, the gate contact structure 306A formed by etching surrounds the entire drain region and drain lead / pad region in the plane, completely isolating it from the source region, as shown below. Figure 5a , Figure 5b As shown.
[0079] 3) A photoresist mask is formed on the surface of the HEMT epitaxial wafer to pattern the wafer, exposing the source and drain regions. The wafer is then placed in an inductively coupled plasma (ICP) etching apparatus to etch the source and drain regions until the 40nm unintentionally doped GaN channel layer 304 in that region is removed. Then, a 20nm Ti / 130nm Al / 50nm Ti / i / 50nm TiN stacked structure is deposited on the unintentionally doped GaN channel layer 304 exposed in the source and drain regions. After removing the mask and cleaning, the source contact structure 307A and drain contact structure 308A are obtained. Figure 8 As shown;
[0080] HEMT epitaxial wafers with active electrode contact structure 307A and drain electrode contact structure 308A are placed in a rapid annealing furnace and annealed at 500℃-600℃ for 120s-300s in a nitrogen atmosphere to form good ohmic contacts with 2DEG.
[0081] 4) The HEMT epitaxial wafer with active electrode contact structure 307A and drain electrode contact structure 308A is placed in a plasma-enhanced vapor deposition (PECVD) apparatus to deposit a SiN layer with a thickness of about 200nm on its surface. x Layer 310 employs a patterned photoresist mask, utilizing plasma to deposit SiN above the gate contact structure 306A. xLayer etching to create windows;
[0082] After cleaning to remove the photoresist mask, a 20nm Ti / 400nm Al / 50nm TiN stacked structure is deposited on the exposed gate contact structure 306A. This structure is then patterned and etched to remove the metal in the non-gate regions, yielding the interconnected gate interconnect structure 306B. The gate interconnect structure 306B is electrically connected to the gate contact structure 306A. Figure 9 As shown.
[0083] 5) After cleaning, continue to deposit SiN with a total thickness of 1500 nm in the PECVD equipment. x / SiO2 / SiN x After photolithography patterning, the SiN layer 311 is used to remove the SiN above the source contact structure 307A and drain contact structure 308A by plasma etching. x / SiO2 / SiN x Dielectric layer 311, and then a 4 μm Al layer is deposited on the exposed source contact structure 307A and drain contact structure 308A using magnetron sputtering equipment as the interconnect source interconnect structure 307B and drain interconnect structure 308B, such as Figure 10 As shown.
[0084] 6) A 2μm thick SiO2 layer is deposited as a protective layer 312. The protective layer 312 at the leads / pads (source interconnect structure 307B, drain interconnect structure 308B) is then removed to form a GaN HEMT device, such as... Figure 11 As shown.
[0085] The GaN HEMT device was subjected to off-state withstand voltage test. When the gate voltage was 0 V and 600 V, the leakage current was 10 nA / mm, and the hard breakdown voltage of the device reached 1150 V. The results show that the device has good turn-off performance and meets the actual requirements, which confirms that the present invention has the ability to turn off and isolate the source and drain.
[0086] Example 2
[0087] A method for fabricating a GaN HEMT device includes the following steps:
[0088] 1) Using metal-organic vapor deposition (MOCVD), a 600 nm AlN / AlGaN transition layer structure 302 and a 4 μm C-doped Al2O3 layer were sequentially deposited on a Si<1 11> substrate 301. 0.07 Ga 0.93 High-resistivity layer 303, 300nm high-quality, low-electron-concentration unintentionally doped GaN channel layer 304, 30nm Al 0.25 Ga 0.75An N-barrier layer of 305 was used to obtain a sheet resistance of 360 Ω / ◆ and a 2DEG concentration of 1×10⁻⁶. 13 cm -2 Depletion-type AlGaN / GaN heterostructure HEMT epitaxial wafers (hereinafter referred to as HEMT epitaxial wafers).
[0089] 2) A photoresist mask is formed on the surface of the HEMT epitaxial wafer, and then placed in a metal deposition apparatus such as magnetron sputtering to deposit a 20nm Ti / 200nm Al / 20nm Ti stacked structure. After removing the mask and cleaning, the gate contact structure 306A is obtained. The gate contact structure 306A surrounds all the drain regions and drain lead / pad regions in the plane, completely isolating them from the source regions, such as... Figure 5a , Figure 5b As shown.
[0090] 3) A photoresist mask is formed on the surface of the HEMT epitaxial wafer to pattern the wafer, exposing the source and drain regions. The wafer is then placed in an inductively coupled plasma (ICP) etching apparatus to etch the source and drain regions until the 40nm unintentionally doped GaN channel layer 304 in that region is removed. Then, a 20nm Ti / 130nm Al / 50nm Ti / 50nm TiN stacked structure is deposited on the exposed unintentionally doped GaN channel layer 304 in the source and drain regions. After removing the mask and cleaning, the source contact structure 307A and drain contact structure 308A are obtained. Figure 8 As shown
[0091] HEMT epitaxial wafers with active electrode contact structure 307A and drain electrode contact structure 308A are placed in a rapid annealing furnace and annealed at 500℃-600℃ for 120s-300s in a nitrogen atmosphere to form good ohmic contacts with 2DEG.
[0092] 4) The HEMT epitaxial wafer with active electrode contact structure 307A and drain electrode contact structure 308A is placed in a plasma-enhanced vapor deposition (PECVD) apparatus to deposit a SiN layer with a thickness of about 200nm on its surface. x Layer 310 employs a patterned photoresist mask, utilizing plasma to deposit SiN above the gate contact structure 306A. x Layer etching to create windows;
[0093] After cleaning to remove the photoresist mask, a 20nm Ti / 400nm Al / 50nm TiN stacked structure is deposited on the exposed gate contact structure 306A. This structure is then patterned and etched to remove the metal in the non-gate regions, yielding the interconnected gate interconnect structure 306B. The gate interconnect structure 306B is electrically connected to the gate contact structure 306A. Figure 9 As shown.
[0094] 5) After cleaning, continue to deposit SiN with a total thickness of 1500 nm in the PECVD equipment. x / SiO2 / SiN x After photolithography patterning, the SiN layer 311 is used to remove the SiN above the source contact structure 307A and drain contact structure 308A by plasma etching. x / SiO2 / SiN x Dielectric layer 311, and then a 4 μm Al layer is deposited on the exposed source contact structure 307A and drain contact structure 308A using magnetron sputtering equipment as the interconnect source interconnect structure 307B and drain interconnect structure 308B, such as Figure 10 As shown.
[0095] 6) A 2μm thick SiO2 layer is deposited as a protective layer 312. The protective layer 312 at the leads / pads (source interconnect structure 307B, drain interconnect structure 308B) is then removed to form a GaN HEMT device, such as... Figure 11 As shown.
[0096] The GaN HEMT device was subjected to a power-off breakdown voltage test. When the gate voltage was 0V and 600V, the leakage current was 50nA / mm, and the hard breakdown voltage of the device reached 1080V. The results show that the device has good turn-off performance and meets the actual requirements, which confirms that the present invention has the ability to turn off and isolate the source and drain.
[0097] The closed gate structure used in this invention can completely isolate the source and drain during gate fabrication, eliminating the need for additional dry etching or ion implantation processes to isolate the active region structure. Compared with traditional HEMT device fabrication methods, this invention has a shorter process, requires no additional etching or ion implantation equipment, and has lower manufacturing costs.
[0098] Compared to the traditional technique of etching mesa to prepare active regions, the closed gate structure used in this invention does not pose risks such as metal breakage or local electric field concentration caused by steps during the source, drain and gate interconnection process, resulting in products with higher yield and reliability.
[0099] Compared to the traditional technique of ion implantation isolation for fabricating active regions, the present invention uses a closed gate structure, which eliminates the risk of photoresist and other mask deformation caused by ion implantation, making removal extremely difficult and significantly improving product yield and reliability.
[0100] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A semiconductor device comprising an epitaxial structure and a source, a drain, and a gate matched with the epitaxial structure, the epitaxial structure comprising a heterostructure having a carrier channel, the source and the drain being electrically connected via the carrier channel, characterized in that: The gate is a closed ring structure, and the source and / or the drain are independently surrounded by the gate, with the source and the drain isolated by the gate; when a turn-off bias voltage is applied to the gate, the source and the drain are electrically isolated, and when a turn-on bias voltage is applied to the gate, the source and the drain are electrically connected.
2. The semiconductor device according to claim 1, characterized in that, include: Multiple sources and / or multiple drains, wherein the multiple sources are spaced apart and each of the multiple sources is independently surrounded by the gate; The plurality of drains are spaced apart, and the plurality of sources are each independently surrounded by the gate; Preferably, the plurality of sources and the plurality of drains are arranged alternately at intervals; Preferably, the width of the gate is 1nm-5000nm; Preferably, the spacing between different regions of the gate and the source and / or drain is equal; Preferably, the distance between the gate and the drain is greater than the distance between the gate and the source.
3. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: Source leads / pads, drain leads / pads, and gate leads / pads are provided, wherein the source leads / pads, drain leads / pads, and gate leads / pads are electrically connected to the source, drain, and gate, respectively, and wherein the source leads / pads and / or the drain leads / pads are also independently surrounded by the gate. And / or, the semiconductor device further includes: a source field plate and a gate field plate, wherein the source field plate is electrically connected to the source and the gate field plate is electrically connected to the gate.
4. The semiconductor device according to claim 3, characterized in that, Also includes: A first insulating dielectric layer covers the source, the drain, the gate, and the epitaxial structure, and the gate lead / pad is disposed on the first insulating dielectric layer and electrically connected to the gate; A second insulating dielectric layer covers the gate lead / pad and the first insulating dielectric layer. The source lead / pad and the drain lead / pad are disposed on the second insulating dielectric layer and are electrically connected to the source and the drain, respectively. A protective layer is disposed on the second insulating dielectric layer and covers the area not covered by the source lead / pad and the drain lead / pad; And / or, the gate field plate is disposed between the first insulating dielectric layer and the second insulating dielectric layer, and the source field plate is disposed on the second insulating dielectric layer.
5. The semiconductor device according to claim 1, characterized in that: The gate includes a MIS / MOS gate, a p-type gate, or an ion-implanted gate; And / or, the material of the heterostructure is a group III nitride; And / or, the semiconductor device includes a HEMT device.
6. A method for fabricating a semiconductor device, comprising fabricating an epitaxial structure and a source, drain, and gate matching the epitaxial structure, wherein the epitaxial structure includes a heterostructure, a carrier channel is formed within the heterostructure, and the source and the drain are electrically connected via the carrier channel, characterized in that, Also includes: A gate with a closed ring structure is fabricated, and the source and / or the drain are independently surrounded by the gate, with the source and the drain isolated by the gate; when a turn-off bias voltage is applied to the gate, the source and the drain are electrically isolated, and when a turn-on bias voltage is applied to the gate, the source and the drain are electrically connected.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Specifically, it includes: First, a gate with a closed ring structure is formed in the gate region of the heterostructure, the gate independently surrounding the source region and / or drain region in a plane; A source electrode is formed in the source region of the heterostructure, and a drain electrode is formed in the drain region. The source electrode and the drain electrode are isolated by the gate electrode.
8. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, Specifically, it includes: Multiple sources and / or multiple drains are fabricated, wherein the multiple sources are spaced apart and each of the multiple sources is independently surrounded by the gate; The plurality of drains are spaced apart, and the plurality of sources are each independently surrounded by the gate; Preferably, the plurality of sources and the plurality of drains are arranged alternately at intervals; Preferably, the width of the gate is 1nm-5000nm; Preferably, the spacing between different regions of the gate and the source and / or drain is equal; Preferably, the distance between the gate and the drain is greater than the distance between the gate and the source.
9. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, Also includes: Fabricate source leads / pads, drain leads / pads, and gate leads / pads, wherein the source leads / pads, drain leads / pads, and gate leads / pads are electrically connected to the source, drain, and gate, respectively, wherein the source leads / pads and / or the drain leads / pads are also independently surrounded by the gate; And / or, the method for fabricating the semiconductor device further includes: fabricating a source field plate and a gate field plate, wherein the source field plate is electrically connected to the source and the gate field plate is electrically connected to the gate; Preferably, the method for fabricating the semiconductor device specifically includes: A first insulating dielectric layer is formed, and the first insulating dielectric layer covers the source, the drain, the gate and the epitaxial structure. The gate lead / pad is formed on the first insulating dielectric layer and the gate lead / pad is electrically connected to the gate. A second insulating dielectric layer is formed, and the second insulating dielectric layer covers the gate lead / pad and the first insulating dielectric layer. The source lead / pad and the drain lead / pad are formed on the second insulating dielectric layer, and the source lead / pad and the drain lead / pad are electrically connected to the source and the drain, respectively. A protective layer is formed, and the protective layer covers a second insulating dielectric layer that is not covered by the source lead / pad or the drain lead / pad.
10. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that: The gate includes a MIS / MOS gate, a p-type gate, or an ion-implanted gate; And / or, the material of the heterostructure is a group III nitride; And / or, the semiconductor device includes a HEMT device.