Semiconductor device

Abstract

The purpose of the present disclosure is to provide a semiconductor device capable of reducing parasitic oscillation caused by inductance generated between semiconductor chips. The first gate pattern (4) and the first source pattern (6) are linearly formed parallel to each other along a first side of the insulating substrate (1). The second gate pattern (5) extends from a first side of the insulating substrate (1) to a second side facing the first side, and is formed in a quadrilateral shape in plan view. The drain pattern (8) is formed so as to surround at least three sides of the quadrangle of the second gate pattern (5). The second source pattern (7) is formed along a side of the insulating substrate (1) other than the first side so as to surround the drain pattern (8). The first semiconductor chip group (11) and the second semiconductor chip group (12) are disposed at positions adjacent to the second source pattern (7). The first semiconductor chip group (11), the second semiconductor chip group (12), and the second source pattern (7) are connected via a plurality of first gate conductive lines (23).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] For example, in the semiconductor device described in Patent Literature 1, the collector wiring on the ceramic substrate and the plurality of IGBT chips (corresponding to semiconductor chips) and the diode chips (corresponding to semiconductor chips) are joined to each other on the ceramic substrate by the lower sintering joining layer. Above the IGBT chips and the diode chips, different conductive members are connected by the upper sintering joining layer, the emitter wiring on the ceramic substrate, the emitter of the IGBT chips, and the anode of the diode chips are connected by the joining wires, and the IGBT chips and the emitter sensing wiring on the ceramic substrate are connected by different joining wires. The sintering joining layer is composed of the lower layer and the upper layer, and since they are separated from each other, a semiconductor device in which excessive stress is difficult to occur in the gate wiring portion and the characteristics are improved is realized. PRIOR ART DOCUMENTS PATENT LITERATURE

[0003] Patent Literature 1: Japanese Patent Laid-Open No. 2018-117054 SUMMARY PROBLEMS TO BE SOLVED BY THE INVENTION

[0004] In a semiconductor device in which the gate, the collector (or the drain), and the emitter (or the source) of the semiconductor chips are connected in parallel, sometimes a positive feedback circuit is formed by the parasitic capacitance and the floating inductance of the semiconductor chips, causing parasitic oscillation. Especially in the case where the source impedance is large, that is, in the case where the path of the source lead is long, parasitic oscillation occurs significantly.

[0005] In the semiconductor device described in Patent Literature 1, the emitter wiring on the ceramic substrate, the diode chips, and the IGBT chips are arranged in this order, and since the emitter wiring on the ceramic substrate is far from the IGBT chips, the path of the joining wire (corresponding to the source lead) connecting the emitter wiring on the ceramic substrate and the IGBT chips becomes long. Therefore, there is a problem that the inductance between the semiconductor chips deviates, and the possibility of causing parasitic oscillation between the semiconductor chips is high.

[0006] Therefore, an object of the present disclosure is to provide a semiconductor device capable of reducing parasitic oscillation caused by inductance generated between semiconductor chips. MEANS FOR SOLVING THE PROBLEMS

[0007] The semiconductor device according to the present disclosure includes an insulating substrate formed into a quadrangle in plan view and having a first gate pattern, a second gate pattern, a first source pattern, a second source pattern, and a drain pattern formed on an upper surface, and a first semiconductor chip group and a second semiconductor chip group mounted on the drain pattern, the first gate pattern and the first source pattern being formed in a linear shape in parallel with each other along a first side of the insulating substrate, the second gate pattern extending from the first side of the insulating substrate to a second side opposite to the first side and formed into a quadrangle in plan view, the drain pattern being formed so as to surround at least three sides of the quadrangle of the second gate pattern, the second source pattern being formed along a side other than the first side of the insulating substrate so as to surround the drain pattern, the first semiconductor chip group and the second semiconductor chip group being disposed at positions adjacent to the second source pattern, the first gate pattern and the second gate pattern being connected via a first gate lead wire, the second gate pattern and the first semiconductor chip group and the second semiconductor chip group being connected via a plurality of second gate lead wires, the first semiconductor chip group and the second semiconductor chip group and the second source pattern being connected via a plurality of first source lead wires, the first semiconductor chip group and the second semiconductor chip group being connected via a plurality of second source lead wires, the first semiconductor chip group and the second semiconductor chip group and the first source pattern being connected via a plurality of third source lead wires, the semiconductor chips included in the first semiconductor chip group and the second semiconductor chip group being connected via a plurality of fourth source lead wires, and a drain main terminal and a source main terminal being connected to the drain pattern and the second source pattern, respectively. Inventive Effects

[0008] According to the present disclosure, since the first semiconductor chip group and the second semiconductor chip group are disposed at positions adjacent to the second source pattern, the length of the plurality of first source lead wires connecting the first semiconductor chip group and the second semiconductor chip group and the second source pattern is shortened. With this configuration, the variation in inductance generated between the semiconductor chips included in the first semiconductor chip group and the second semiconductor chip group can be suppressed, and thus the parasitic oscillation caused by the inductance generated between the semiconductor chips can be mitigated. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view for explaining the overall configuration of the semiconductor device according to Embodiment 1. Figure 2 is a plan view of the insulating substrate included in the semiconductor device according to Embodiment 1. Figure 3 is an enlarged plan view of the first semiconductor chip group and the second semiconductor chip group mounted on the insulating substrate and the periphery thereof in Embodiment 1. Figure 4 This is a top view of an insulating substrate used to illustrate the positions of the first semiconductor chip group and the second semiconductor chip group, the length of the first source wire, and the length of the second source wire in Embodiment 1. Figure 5 This is a top view of the insulating substrate included in the semiconductor device according to Embodiment 2. Figure 6 This is a top view of the insulating substrate included in the semiconductor device according to Embodiment 3. Figure 7 This is a top view of the insulating substrate included in the semiconductor device according to Embodiment 4. Figure 8 This is a top view of the insulating substrate included in the semiconductor device according to Embodiment 5. Figure 9 This is a top view of the insulating substrate included in the semiconductor device according to Embodiment 6. Detailed Implementation

[0010] <Implementation Method 1> The following description uses the accompanying drawings to illustrate Embodiment 1. Figure 1 This is a schematic cross-sectional view used to illustrate the overall structure of the semiconductor device 100 according to Embodiment 1. Figure 2 This is a top view of the insulating substrate 1 included in the semiconductor device 100 according to Embodiment 1. Figure 3 This is an enlarged top view of the first semiconductor chip group 11 and the second semiconductor chip group 12 mounted on the insulating substrate 1 and their surroundings in Embodiment 1.

[0011] like Figure 1 As shown, the semiconductor device 100 includes an insulating substrate 1, a first semiconductor chipset 11, a second semiconductor chipset 12, a drain main terminal 31, a source main terminal 32, a housing 41, a sealing material 42, and a cover 43. Additionally, Figure 1 This is a schematic cross-sectional view shown to illustrate the overall structure of the semiconductor device 100, and does not correspond to... Figure 2 Top view.

[0012] like Figure 1 and Figure 2 As shown, the insulating substrate 1 is quadrilateral when viewed from above, and has a base plate 2, an insulating layer 3 formed on the base plate 2, and a circuit pattern formed on the insulating layer 3. Figure 2 As shown, the circuit pattern is formed of metals such as copper, including a first gate pattern 4, a second gate pattern 5, a first source pattern 6, a second source pattern 7, and a drain pattern 8.

[0013] The first gate pattern 4 and the first source pattern 6 are along the first edge of the insulating substrate 1.Figure 2 The lower and middle sides are parallel to each other, forming a straight line. From the first side of the insulating substrate 1 towards the second side opposite to the first side ( Figure 2 The first source pattern 6 and the first gate pattern 4 are sequentially arranged on the upper side of the middle.

[0014] The second gate pattern 5 extends from the first side to the second side of the insulating substrate 1, and is formed into an elongated quadrilateral when viewed from above. In addition, the second gate pattern 5 is disposed further to the second side than the first gate pattern 4.

[0015] The drain pattern 8 is formed in such a way that at least three sides of the quadrilateral surrounding the second gate pattern 5 are arranged. More specifically, the drain pattern 8 is formed in such a way that four sides of the quadrilateral surrounding the second gate pattern 5 are arranged.

[0016] The second source pattern 7 is formed along the edges of the insulating substrate 1, excluding the first edge, in a manner that surrounds the drain pattern 8. More specifically, the second source pattern 7 is formed along the second, third, and fourth edges of the insulating substrate 1 in a manner that surrounds the drain pattern 8. The first edge portion of the second source pattern 7 and the first edge portion of the drain pattern 8 face each other directly opposite the first gate pattern 4. Here, the third edge is the edge connecting the first edge and the second edge (…). Figure 2 The leftmost edge), the fourth edge is the edge opposite the third edge. Figure 2 (The right side of the middle).

[0017] like Figure 1 As shown, the first semiconductor chip set 11 and the second semiconductor chip set 12 are mounted on the drain pattern 8 via a bonding material 13 such as solder. More specifically, as Figure 2 and Figure 3 As shown, the first semiconductor chip group 11 and the second semiconductor chip group 12 are disposed on the drain pattern 8 at a position adjacent to the second source pattern 7. Furthermore, the first semiconductor chip group 11 and the second semiconductor chip group 12 are positioned opposite each other, sandwiching the second gate pattern 5. Specifically, the first semiconductor chip group 11 is disposed on the third side, and the second semiconductor chip group 12 is disposed on the fourth side.

[0018] Both the first semiconductor chip group 11 and the second semiconductor chip group 12 include multiple semiconductor chips. The semiconductor chips are formed from wide-bandgap semiconductors such as SiC, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Alternatively, the semiconductor chips may be IGBTs (Insulated Gate Bipolar Transistors) or RC-IGBTs (Reverse-Conducting IGBTs) formed within a semiconductor substrate, consisting of an IGBT and a return diode. like Figure 1 As shown, the housing 41, when viewed from above, is formed as a quadrilateral frame and is bonded to the periphery of the insulating substrate 1 with an adhesive (not shown). One end of the drain main terminal 31 and the source main terminal 32 are fixed to the housing 41. A sealing material 42 is filled inside the housing 41. The sealing material 42 seals the upper surface of the insulating substrate 1, as well as the first semiconductor chip assembly 11 and the second semiconductor chip assembly 12. The sealing material 42 is, for example, epoxy resin. A cover 43 covering the upper surface of the sealing material 42 is installed on the upper part of the housing 41.

[0020] Next, the connection between the first semiconductor chip group 11 and the second semiconductor chip group 12 and each circuit pattern will be explained.

[0021] like Figure 2 As shown, the first gate pattern 4 and the second gate pattern 5 are connected via the first gate wire 21. The second gate pattern 5 is connected to the first semiconductor chip group 11 and the second semiconductor chip group 12 via a plurality of second gate wires 22.

[0022] The first semiconductor chip group 11, the second semiconductor chip group 12, and the second source pattern 7 are connected via a plurality of first gate wires 23. The first semiconductor chip group 11 and the second semiconductor chip group 12 are connected in parallel via a plurality of second source wires 24. The first semiconductor chip group 11, the second semiconductor chip group 12, and the first source pattern 6 are connected via a plurality of third source wires 25. The semiconductor chips included in the first semiconductor chip group 11 and the second semiconductor chip group 12 are connected to each other via a plurality of fourth source wires 26.

[0023] In addition, the drain main terminal 31 and the source main terminal 32 are connected to the drain pattern 8 and the second source pattern 7 respectively by solder or other bonding materials (not shown) or wires (not shown).

[0024] Next, the positional relationship between the first semiconductor chip group 11 and the second semiconductor chip group 12 and the length of the source wires connected to them will be explained. Figure 4 This is a top view of an insulating substrate 1 used to illustrate the positions of the first semiconductor chip group 11 and the second semiconductor chip group 12, the length of the first source wire 23, and the length of the second source wire 24 in Embodiment 1.

[0025] like Figure 4 As shown, the semiconductor chips included in the first semiconductor chip group 11 and the semiconductor chips included in the second semiconductor chip group 12 have the same structure. The first semiconductor chip group 11 is configured with a 180° lateral rotation relative to the second semiconductor chip group 12. In other words, the first semiconductor chip group 11 is configured in a lateral opposite manner to the second semiconductor chip group 12. Moreover, the first semiconductor chip group 11 is offset from the second semiconductor chip group 12 by a length 'a' corresponding to 20% of the length of the third side in a direction parallel to the third side of the insulating substrate 1. Without offsetting the first semiconductor chip group 11 relative to the second semiconductor chip group 12, the length of the plurality of second source wires 24 becomes longer, but by offsetting the configuration, the plurality of second source wires 24 can be connected in the shortest possible way.

[0026] Furthermore, the length b of the plurality of first source wires 23 is the same, or the length is within ±3% considering manufacturing deviations. Similarly, the length c of the plurality of second source wires 24 is the same, or the length is within ±3% considering manufacturing deviations. As described above, in Embodiment 1, the semiconductor device 100 includes: an insulating substrate 1, which is quadrilateral in plan view and has a first gate pattern 4, a second gate pattern 5, a first source pattern 6, a second source pattern 7, and a drain pattern 8 formed on its upper surface; and a first semiconductor chip set 11 and a second semiconductor chip set 12 mounted on the drain pattern 8. The first gate pattern 4 and the first source pattern 6 are formed as straight lines parallel to each other along a first side of the insulating substrate 1. The second gate pattern 5 extends from the first side of the insulating substrate 1 toward a second side opposite to the first side and is formed as a quadrilateral in plan view. The drain pattern 8 is formed to surround at least three sides of the quadrilateral of the second gate pattern 5. The second source pattern 7 is formed to surround the drain pattern 8 along the sides of the insulating substrate 1 other than the first side. The first semiconductor chip set 11 and the second semiconductor chip set 12 are disposed adjacent to the second source pattern 7. The first gate pattern 4 and the second gate pattern 5 are connected via a first gate wire 21. The second gate pattern 5 and the first semiconductor chip group 11 and the second semiconductor chip group 12 are connected via a plurality of second gate wires 22. The first semiconductor chip group 11, the second semiconductor chip group 12 and the second source pattern 7 are connected via a plurality of first gate wires 23. The first semiconductor chip group 11 and the second semiconductor chip group 12 are connected via a plurality of second source wires 24. The first semiconductor chip group 11, the second semiconductor chip group 12 and the first source pattern 6 are connected via a plurality of third source wires 25. The semiconductor chips included in the first semiconductor chip group 11 and the second semiconductor chip group 12 are connected to each other via a plurality of fourth source wires 26. The drain main terminal 31 and the source main terminal 32 are respectively connected to the drain pattern 8 and the second source pattern 7.

[0028] More specifically, the drain pattern 8 is formed in such a way that it surrounds the quadrilateral of the second gate pattern 5. Therefore, since the first semiconductor chip group 11 and the second semiconductor chip group 12 are positioned adjacent to the second source pattern 7, the lengths of the plurality of first source wires 23 connecting the first semiconductor chip group 11, the second semiconductor chip group 12, and the second source pattern 7 are shortened. This structure can suppress the inductance deviation generated between the semiconductor chips included in the first semiconductor chip group 11 and the second semiconductor chip group 12, thus mitigating parasitic oscillations caused by the inductance generated between the semiconductor chips.

[0030] In addition, using multiple second gate wires 22 to connect the second gate pattern 5 to the first semiconductor chip group 11 and the second semiconductor chip group 12 via two second gate wires 22 is less susceptible to induction than using a single wire stitching method, thus improving the effectiveness as an oscillation countermeasure.

[0031] Furthermore, the first semiconductor chip group 11 is offset from the second semiconductor chip group 12 by a length corresponding to 20% of the length of the third side in a direction parallel to the third side connecting the first and second sides of the insulating substrate 1. Therefore, compared to the case where the first semiconductor chip group 11 is not offset from the second semiconductor chip group 12, the plurality of second source wires 24 can be shortened.

[0032] Furthermore, the lengths of the plurality of first source wires 23 are the same or include an error within ±3%. Similarly, the lengths of the plurality of second source wires 24 are the same or include an error within ±3%. Therefore, since the deviation of inductance generated between semiconductor chips can be further suppressed, parasitic oscillations caused by inductance generated between semiconductor chips can be further reduced. Furthermore, the semiconductor chips included in the first semiconductor chip group 11 and the second semiconductor chip group 12 are formed of wide-bandgap semiconductors. Since the semiconductor chips formed of wide-bandgap semiconductors are driven at high speeds, the inductance between the semiconductor chips is prone to deviation. However, with the structure of the semiconductor device 100 according to Embodiment 1, the inductance deviation can be suppressed, thus achieving excellent results in this case.

[0034] <Implementation Method 2> Next, implementation method 2 will be described. Figure 5 This is a top view of the insulating substrate 1 included in the semiconductor device 100 according to Embodiment 2. Furthermore, in Embodiment 2, structural elements identical to those described in Embodiment 1 are labeled with the same reference numerals and their descriptions are omitted.

[0035] like Figure 5 As shown, in Embodiment 2, the first gate pattern 4 and the second gate pattern 5 are formed as a single unit instead of the first gate wire 21. That is, the first gate wire 21 is not used. In addition, the drain pattern 8 is formed in such a way that it surrounds the four sides of the quadrilateral of the second gate pattern 5.

[0036] Therefore, in Embodiment 2, the same effects as in Embodiment 1 can be obtained. Furthermore, since the first gate wire 21 can be eliminated, it helps to reduce the manufacturing time in the semiconductor device 100 manufacturing process.

[0037] <Implementation Method 3> Next, implementation method 3 will be described. Figure 6 This is a top view of the insulating substrate 1 included in the semiconductor device 100 according to Embodiment 3. Furthermore, in Embodiment 3, structural elements identical to those described in Embodiments 1 and 2 are labeled with the same reference numerals and their descriptions are omitted.

[0038] like Figure 6 As shown, in Embodiment 3, the structure of Embodiment 1 is configured with two parallel rows. Specifically, when the second gate pattern 5 and the drain pattern 8 are configured as one block, the insulating substrate 1 has two blocks 51 and 52 formed adjacent to each other. The two blocks 51 and 52 are arranged side by side in a direction parallel to the first side. A first semiconductor chip set 11 and a second semiconductor chip set 12 are mounted on the two blocks 51 and 52. The second source pattern 7 is formed along the sides other than the first side in a manner that surrounds the two blocks 51 and 52, and extends to the region between the two blocks 51 and 52.

[0039] The portions of semiconductor chip groups 11 and 12 and the second source pattern 7 that are adjacent to the region on both sides of the region in the first semiconductor chip group 11 and the second semiconductor chip group 12, extending into the region, replace the plurality of first source wires 23 and are connected via a plurality of sixth source wires 28 and a plurality of fifth source wires 27, respectively. Therefore, the plurality of first source wires 23 connect the semiconductor chip groups 11 and 12 and the second source pattern 7 that are not adjacent to the region in the first semiconductor chip group 11 and the second semiconductor chip group 12. As described above, in Embodiment 3, not only can the same effect as in Embodiment 1 be obtained, but also a large capacity can be achieved.

[0041] <Implementation Method 4> Next, implementation method 4 will be described. Figure 7 This is a top view of the insulating substrate 1 included in the semiconductor device 100 according to Embodiment 4. Furthermore, in Embodiment 4, structural elements identical to those described in Embodiments 1-3 are labeled with the same reference numerals and their descriptions are omitted.

[0042] like Figure 7 As shown, in Embodiment 4, the two blocks 51 and 52 in Embodiment 3 are replaced with the structure of Embodiment 2. Specifically, in the two blocks 51 and 52, the first gate pattern 4 and the second gate pattern 5 are formed as a single unit, replacing the first gate wire 21. The drain pattern 8 is formed in such a way that it surrounds three sides of the quadrilateral of the second gate pattern 5.

[0043] Therefore, in Embodiment 4, the same effects as in Embodiment 3 can be obtained. Furthermore, since the first gate wire 21 can be eliminated, it helps to reduce the manufacturing time in the semiconductor device 100 manufacturing process.

[0044] <Implementation Method 5> Next, implementation method 5 will be described. Figure 8This is a top view of the insulating substrate 1 included in the semiconductor device 100 according to Embodiment 5. Furthermore, in Embodiment 5, structural elements identical to those described in Embodiments 1-4 are labeled with the same reference numerals and their descriptions are omitted.

[0045] like Figure 8 As shown, in embodiment 5, when the second gate pattern 5 and the drain pattern 8 are configured as a single block, the insulating substrate 1 has three first blocks 53, 54, and 55 formed adjacent to each other on the first side and three second blocks 56, 57, and 58 formed adjacent to each other on the second side. The three first blocks 53, 54, and 55 and the three second blocks 56, 57, and 58 are respectively face-to-face.

[0046] The first semiconductor chipset 11 is mounted on three first chips 53, 54, and 55, and the second semiconductor chipset 12 is mounted on three second chips 56, 57, and 58. Therefore, the first semiconductor chipset 11 and the second semiconductor chipset 12 are also face-to-face, and the first semiconductor chipset 11 and the second semiconductor chipset 12 facing each other are connected in series. The first drain main terminal 31a is connected to the three first blocks 53, 54, and 55. The second drain main terminal 31b and the second source main terminal 32b are connected to the three second blocks 56, 57, and 58, and the second drain main terminal 31b functions as the first source main terminal 32a.

[0048] As described above, a half-bridge circuit can be configured in Embodiment 5. Furthermore, by arranging the semiconductor devices 100 according to Embodiment 5 in parallel, it becomes easier to configure a multiphase inverter.

[0049] <Implementation Method 6> Next, implementation method 6 will be described. Figure 9 This is a top view of the insulating substrate 1 included in the semiconductor device 100 according to Embodiment 6. Furthermore, in Embodiment 6, structural elements identical to those described in Embodiments 1-5 are labeled with the same reference numerals and their descriptions are omitted.

[0050] like Figure 9 As shown, in embodiment 6, instead of the insulating layer 3, the insulating substrate 1 has a first ceramic substrate 3a and a second ceramic substrate 3b. In other words, the insulating layer 3 is divided into two ceramic substrates 3a and 3b.

[0051] Three first blocks 53, 54, and 55 and three second blocks 56, 57, and 58 are formed on a first ceramic substrate 3a and a second ceramic substrate 3b, respectively. The first ceramic substrate 3a and the second ceramic substrate 3b are connected by a plurality of first drain wires 35, a plurality of second drain wires 36, and a plurality of third drain wires 37.

[0052] As described above, in embodiment 6, since the insulating layer 3 of the insulating substrate 1 is divided into two ceramic substrates 3a and 3b, the power cycle life can be improved by enhancing the heat dissipation of the insulating substrate 1.

[0053] It is possible to freely combine various implementation methods, or appropriately modify or omit various implementation methods. The various methods disclosed herein are summarized and recorded below as appendices. (Note 1) A semiconductor device, comprising: An insulating substrate, which, when viewed from above, is quadrilateral and has a first gate pattern, a second gate pattern, a first source pattern, a second source pattern, and a drain pattern formed on its upper surface; and A first semiconductor chip set and a second semiconductor chip set mounted on the drain pattern. The first gate pattern and the first source pattern are arranged in a straight line parallel to each other along the first edge of the insulating substrate. The second gate pattern extends from the first side of the insulating substrate toward the second side opposite to the first side, forming a quadrilateral shape when viewed from above. The drain pattern is formed such that at least three sides of the quadrilateral surrounding the second gate pattern are arranged. The second source pattern is formed along the edges of the insulating substrate, excluding the first edge, in a manner that surrounds the drain pattern. The first semiconductor chip set and the second semiconductor chip set are configured adjacent to the second source pattern. The first gate pattern and the second gate pattern are connected via a first gate wire. The second gate pattern is connected to the first semiconductor chip set and the second semiconductor chip set via a plurality of second gate wires. The first semiconductor chip set, the second semiconductor chip set, and the second source pattern are connected via a plurality of first source wires. The first semiconductor chip set and the second semiconductor chip set are connected via multiple second source wires. The first semiconductor chip set, the second semiconductor chip set, and the first source pattern are connected via multiple third source wires. The semiconductor chips contained in the first semiconductor chipset and the second semiconductor chipset are connected to each other via multiple fourth source wires. The drain main terminal and the source main terminal are respectively connected to the drain pattern and the second source pattern. (Note 2) The semiconductor device as described in Note 1 The drain pattern is formed in such a way that it surrounds the four sides of the quadrilateral of the second gate pattern.

[0057] (Note 3) The semiconductor device as described in Note 1 Instead of the first gate wire, the first gate pattern and the second gate pattern are formed as a single unit. The drain pattern is formed in such a way that it surrounds three sides of the quadrilateral of the second gate pattern. (Note 4) The semiconductor device as described in any of Notes 1 to 3, The first semiconductor chip group is configured relative to the second semiconductor chip group by a length corresponding to 20% of the length of the third side in a direction parallel to the third side of the insulating substrate that connects the first side and the second side.

[0059] (Note 5) The semiconductor device as described in any of Notes 1 to 4, The lengths of the multiple first source conductors are the same or include an error within ±3%. (Note 6) The semiconductor device as described in any of Notes 1 to 5, The lengths of the multiple second source conductors are the same or include an error within ±3%. (Note 7) Semiconductor devices as described in Note 1 The second gate pattern and the drain pattern are treated as a single block. The insulating substrate has two blocks formed adjacent to each other. The second source pattern extends into the region between the two blocks. The portions of the semiconductor chip groups adjacent to the region on both sides in the first semiconductor chip group and the second semiconductor chip group, and the portions of the second source pattern extending toward the region, are respectively connected via a plurality of sixth source wires and a plurality of fifth source wires.

[0062] (Note 8) Semiconductor devices as described in Note 7 Instead of the first gate wire, the first gate pattern and the second gate pattern are formed as a single unit. The drain pattern is formed in such a way that it surrounds three sides of the quadrilateral of the second gate pattern.

[0063] (Note 9) Semiconductor devices as described in Note 1 The second gate pattern and the drain pattern are treated as a single block. The insulating substrate has three first blocks formed adjacent to each other on the first side and three second blocks formed adjacent to each other on the second side. The aforementioned first semiconductor chipset and second semiconductor chipset are respectively mounted on three of the first chipset and three of the second chipset. The drain main terminal includes a first drain main terminal and a second drain main terminal. The source main terminal includes a first source main terminal and a second source main terminal. The first drain main terminal is connected to three of the first blocks. The second drain main terminal and the second source main terminal, which serve as the first source main terminal, are connected to the three second blocks.

[0064] (Note 10) Semiconductor devices as described in Note 9 The insulating substrate includes a first ceramic substrate and a second ceramic substrate. The three first blocks and the three second blocks are respectively formed on the first ceramic substrate and the second ceramic substrate. The first ceramic substrate and the second ceramic substrate are connected by a first drain wire, a second drain wire and a third drain wire.

[0065] (Note 11) The semiconductor device as described in any of Notes 1 to 10, The semiconductor chips included in the first semiconductor chip group and the second semiconductor chip group are formed of wide-bandgap semiconductors. Label Explanation 1 Insulating substrate, 3a First ceramic substrate, 3b Second ceramic substrate, 4 First gate pattern, 5 Second gate pattern, 6 First source pattern, 7 Second source pattern, 8 Drain pattern, 11 First semiconductor chipset, 12 Second semiconductor chipset, 21 First gate wire, 22 Second gate wire, 23 First source wire, 24 Second source wire, 25 Third source wire, 26 Fourth source wire, 27 Fifth source wire, 28 Sixth source wire, 31 Drain main terminal, 31a First drain main terminal, 31b Second drain main terminal, 32 Source main terminal, 32a First source main terminal, 32b Second source main terminal, 35 First drain wire, 36 Second drain wire, 37 Third drain wire, 51, 52, 53, 54, 55 First block, 56, 57, 58 Second block.

Claims

1. A semiconductor device, characterized in that, include: An insulating substrate, which is quadrilateral when viewed from above and has a first gate pattern, a second gate pattern, a first source pattern, a second source pattern and a drain pattern formed on its upper surface; as well as A first semiconductor chip set and a second semiconductor chip set mounted on the drain pattern. The first gate pattern and the first source pattern are arranged in a straight line parallel to each other along the first edge of the insulating substrate. The second gate pattern extends from the first side of the insulating substrate toward the second side opposite to the first side, forming a quadrilateral shape when viewed from above. The drain pattern is formed such that at least three sides of the quadrilateral surrounding the second gate pattern are arranged. The second source pattern is formed along the edges of the insulating substrate, excluding the first edge, in a manner that surrounds the drain pattern. The first semiconductor chip group and the second semiconductor chip group are configured adjacent to the second source pattern. The first gate pattern and the second gate pattern are connected via a first gate wire. The second gate pattern and the first semiconductor chip assembly and the second semiconductor chip assembly are connected via a plurality of second gate wires. The first semiconductor chip group, the second semiconductor chip group, and the second source pattern are connected via a plurality of first source wires. The first semiconductor chip set and the second semiconductor chip set are connected via multiple second source wires. The first semiconductor chip group, the second semiconductor chip group, and the first source pattern are connected via a plurality of third source wires. The semiconductor chips contained in the first semiconductor chipset and the second semiconductor chipset are connected to each other via multiple fourth source wires. The drain main terminal and the source main terminal are respectively connected to the drain pattern and the second source pattern.

2. The semiconductor device as claimed in claim 1, characterized in that, The drain pattern is formed in such a way that it surrounds the four sides of the quadrilateral of the second gate pattern.

3. The semiconductor device as claimed in claim 1, characterized in that, Instead of the first gate wire, the first gate pattern and the second gate pattern are formed as a single unit. The drain pattern is formed in such a way that it surrounds three sides of the quadrilateral of the second gate pattern.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first semiconductor chip group is configured relative to the second semiconductor chip group by a length corresponding to 20% of the length of the third side in a direction parallel to the third side of the insulating substrate that connects the first side and the second side.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The lengths of the multiple first source conductors are the same or include an error within ±3%.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The lengths of the multiple second source conductors are the same or include an error within ±3%.

7. The semiconductor device as claimed in claim 1, characterized in that, The second gate pattern and the drain pattern are treated as a single block. The insulating substrate has two blocks formed adjacent to each other. The second source pattern extends into the region between the two blocks. The semiconductor chip groups in the first semiconductor chip group and the second semiconductor chip group that are adjacent to the region on both sides, and the portion of the second source pattern that extends toward the region, are respectively connected via a plurality of sixth source wires and a plurality of fifth source wires.

8. The semiconductor device as claimed in claim 7, characterized in that, Instead of the first gate wire, the first gate pattern and the second gate pattern are formed as a single unit. The drain pattern is formed in such a way that it surrounds three sides of the quadrilateral of the second gate pattern.

9. The semiconductor device as claimed in claim 1, characterized in that, The second gate pattern and the drain pattern are treated as a single block. The insulating substrate has three first blocks formed adjacent to each other on the first side and three second blocks formed adjacent to each other on the second side. The first semiconductor chipset and the second semiconductor chipset are respectively mounted on three of the first chipset and three of the second chipset. The drain main terminal includes a first drain main terminal and a second drain main terminal. The source main terminal includes a first source main terminal and a second source main terminal. The first drain main terminal is connected to three of the first blocks. The second drain main terminal and the second source main terminal, which serve as the first source main terminal, are connected to the three second blocks.

10. The semiconductor device as claimed in claim 9, characterized in that, The insulating substrate includes a first ceramic substrate and a second ceramic substrate. The three first blocks and the three second blocks are respectively formed on the first ceramic substrate and the second ceramic substrate. The first ceramic substrate and the second ceramic substrate are connected by a first drain wire, a second drain wire and a third drain wire.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The semiconductor chips included in the first semiconductor chip group and the second semiconductor chip group are formed of wide-bandgap semiconductors.

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